Memory device and operating method thereof

Abstract

A memory device includes: a memory array for storing a plurality of data in a plurality of memory cells; a plurality of read circuits for reading the data from the plurality of memory cells; and a plurality of input / output (I / O) terminals. A first multiplexer set is used to retrieve the plurality of data from the plurality of memory cells and transfer the data to the plurality of I / O terminals in a first data column order; and a second multiplexer set is used to retrieve the plurality of data from the plurality of memory cells and transfer the data to the plurality of I / O terminals in a second data row order transposed from the first data column order.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] A memory device can store information in memory, such as random-access memory (RAM). The memory device may include a compute-in-memory (CIM) system and method. This system and method can store information in memory (e.g., RAM) and perform computations within the memory device, a technique that contrasts with techniques that move data between a memory device and another device for various computational steps. Through CIM systems and methods, the speed at which stored data is accessed from a memory device is faster than the speed at which it is accessed from other memory devices. Furthermore, the stored data in the memory device can be analyzed more quickly, thereby enabling faster computation in artificial intelligence (AI) applications, such as applying memory devices to large language models (LLMs) and convolutional neural networks (CNNs). [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify one embodiment of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the description of a first feature being formed above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, an embodiment of this disclosure may reuse reference numerals and / or letters in various instances. Such reuse is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," "upper," "top," and "bottom" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] In conventional artificial intelligence applications, data is typically read from memory and rearranged before computations (such as matrix calculations) are performed. Sometimes, additional buffers are needed for these computations, such as dedicated buffers for performing row-wise and column-wise access, and multiple macros for rearranging the data. This negatively impacts energy efficiency, increasing power consumption and circuit latency, and increasing device size.

[0008] Embodiments of this disclosure provide a memory device having two operations for reading data stored in memory. In the first operation, data can be read from the memory device in a "normal" columnar order. In the second operation, data can be read from the memory device in a "transposed" rowar order. This allows the memory device to adapt to different matrix operations, such as those used in artificial intelligence applications.

[0009] This disclosure provides an apparatus. The apparatus includes a first multiplexer set and a second multiplexer set. The first multiplexer set retrieves multiple data from memory cells and transmits these data to multiple input / output (I / O) terminals in a first data column order. The second multiplexer set retrieves multiple data from memory cells and transmits these data to multiple I / O terminals in a second data row order transposed from the first data column order.

[0010] This disclosure provides a method for operating a memory device, the method comprising: storing a plurality of data in a plurality of memory cells of a memory array; reading the plurality of data from the memory cells through a plurality of read circuits; selecting a first multiplexer set or a second multiplexer set; if the first multiplexer set is selected, retrieving data from the plurality of memory cells and transmitting the data to a plurality of I / O terminals in a first data column order; if the second multiplexer set is selected, retrieving data from the plurality of memory cells and transmitting the data to the plurality of I / O terminals in a second data row order transposed from the first data column order.

[0011] The advantages of the embodiments described above in this disclosure include the ability to rearrange data through a memory device without the need for additional buffers or multiple macros. Furthermore, the embodiments described above in this disclosure also offer advantages such as reduced power consumption, reduced latency, and reduced memory device area or size.

[0012] Figure 1 is a schematic diagram of a memory device 20 for accessing data from a memory array 22 in columnar and rowar order according to an embodiment of this disclosure. In a first access operation, data can be read from the memory array 22 in a "normal" columnar order. In a second access operation, data can be read from the memory array 22 in a "transposed" rowar order. The memory device 20 may be an electronic device, one or more semiconductor devices, and / or one or more integrated circuit devices.

[0013] The memory device 20 includes a memory array 22 disposed above or on top of the memory device circuitry 24. In some embodiments, the memory device 20 may be a CIM device, which includes the memory device circuitry 24 for providing application functions such as large language model (LLM) applications and / or convolutional neural network (CNN) applications. In some embodiments, the memory device 20 includes a memory array 22, which is a back-end-of-line (BEOL) memory array disposed above the memory device circuitry 24, which serves as a front-end-of-line (FEOL) circuit. In other embodiments, the memory array 22 may be disposed in the same plane as the memory device circuitry 24 or below the plane of the memory device circuitry 24.

[0014] The memory array 22 may be a static random-access memory (SRAM) array. In other embodiments, the memory array 22 may be different types of memory arrays, such as a resistive random-access memory (RRAM) array, a magnetoresistive random-access memory (MRAM) array, or a phase-change memory (PCRAM) array. In other embodiments, the memory array 22 may be a dynamic random-access memory (DRAM) array.

[0015] The memory circuit 24 may include multiple word line drivers (WLDVs) 28, multiple column multiplexers and sense amplifiers (CMSAs) 30, multiple column select (CS) circuits 32, multiple read circuits 34, and multiple CIM circuits 36. The multiple WLDVs 28 and multiple CMSAs 30 are directly disposed below and electrically coupled to the SRAM memory array 26. The CS circuits 32, which include multiple column decoder circuits, and the read circuits 34 are both located between the coverage areas of the SRAM memory array 26 and are electrically coupled to the CMSAs 30. Each of the read circuits 34 includes multiple read ports electrically coupled to the CIM circuits 36, which receive data from the multiple read ports. In some embodiments, the read circuits 34 may include I / O terminals or connection ports, input multiplexers, and / or output multiplexers.

[0016] The circuitry included in the CIM circuit 36 ​​can be used to support applications, such as LLM applications and / or CNN applications. In some embodiments, the CIM circuit 36 ​​may include a weight buffer circuit 38 for providing accumulated results and a multiply-accumulate (MAC) circuit 40. In some embodiments, the CIM circuit 36 ​​performs LLM functions. In some embodiments, the CIM circuit 36 ​​performs CNN functions.

[0017] Figure 2 is a schematic diagram of an SRAM memory array 26 electrically coupled to a memory device circuit 24 according to an embodiment of this disclosure. The memory device circuit 24 includes a WLDV 28 and a CMSA 30 located directly below and electrically coupled to the SRAM memory array 26. Furthermore, the memory device circuit 24 includes a CS circuit 32 and a read circuit 34, both of which are electrically coupled to the CMSA 30 and located in the coverage area adjacent to the SRAM memory array 26. Additionally, the memory circuit 24 includes a CIM circuit 36, such as a weighted buffer circuit 38 and a MAC circuit 40.

[0018] During the read operation, WLDV 28 and CS circuit 32 provide multiple signals for reading the SRAM memory array 26. CMSA 30 selects multiple rows of multiple bit lines (BL) and multiple complementary bit lines (BLB) and senses voltages from memory cells in the SRAM memory array 26. Read circuit 34 obtains a voltage from CMSA 30, which corresponds to the voltage sensed from the memory cells in the SRAM memory array 26. Read circuit 34 outputs a voltage at a read port, which corresponds to the voltage read from CMSA 30. CIM circuit 36 ​​receives the output voltage from the read port and performs functions of memory device 20, such as functions for LLM applications and / or functions for CNN applications. In some embodiments, the read port provides an output voltage to an output multiplexer. In some embodiments, the read port provides an output voltage to an output multiplexer, which in turn provides a voltage to CIM circuit 36.

[0019] During the write operation, WLDV 28 and CS circuit 32 provide multiple signals for writing to the SRAM memory array 26. CMSA 30 receives input data (e.g., through an input multiplexer and I / O pins) that is being written to the SRAM memory array 26. In some embodiments, the input multiplexer and I / O pins may be part of the read circuit 34.

[0020] Figure 3 is a schematic diagram of a memory device 50 according to an embodiment of this disclosure, wherein the memory device 50 includes a control circuit 52, which is used to perform columnar data access operations and rowar data access operations on the memory array 54 in the memory device 50. In the first access operation, data can be read from the memory array 54 in a "normal" columnar order. In the second access operation, data can be read from the memory array 54 in a "transposed" rowar order. In some embodiments, the memory device 50 is similar to the memory device 20 of Figure 1. In some embodiments, the memory device 50 includes the CIM circuit 36 ​​shown in Figures 1 and 2, which is used to provide functionality for AI applications, such as LLM applications and / or CNN applications. In some embodiments, the memory array 54 may be a BEOL memory array and is disposed on the CIM circuit, which serves as a FEOL circuit.

[0021] Memory array 54 includes a plurality of memory cells storing data. Memory array 54 and a plurality of associated circuits may be connected between a power supply terminal receiving VDD voltage and a ground terminal. Column selection circuit 56 and row selection circuit 58 are connected to memory array 54 and are used to select memory cells in columns and rows of memory array 54 during read and write operations. In some embodiments, column selection circuit 56 includes WLDV 28, as shown in Figures 1 and 2. In some embodiments, row selection circuit 58 is similar to CS circuit 32 shown in Figures 1 and 2. In some embodiments, row selection circuit 58 includes one or more row decoder circuits 60 for selecting rows in "normal" column order of data and reading data in "transposed" row order of data.

[0022] Control circuitry 52 is connected to memory array 54, for example, to bit line BL and complementary bit line BLB, and is used to write data into memory array 54 and read data from memory array 54. Control circuitry 52 includes a first multiplexer set 62 and a second multiplexer set 66. The first multiplexer set 62 retrieves multiple data from memory array 54 and transmits the data to multiple I / O terminals 64 in a first data column order. In some embodiments, control circuitry 52 includes an input multiplexer 68 and / or an output multiplexer 70. In some embodiments, control circuitry 52 includes WLDV 28, CMSA 30, and read circuitry 34, as shown in Figures 1 and 2.

[0023] Figure 4 is a schematic diagram of an SRAM cell 80 used in the memory devices of Figures 1 and 3 according to an embodiment of this disclosure. The SRAM cell 80 is a six-transistor (6T) SRAM cell. In some embodiments, the SRAM cell 80 may be used in the memory device 20 of Figure 1. In some embodiments, the SRAM cell 80 may be used in the memory device 50 of Figure 3. In other embodiments, the SRAM cell 80 may contain more or fewer than six transistors, such as four, eight, or ten transistors.

[0024] The SRAM cell 80 includes two cross-coupled first inverters 82 and second inverters 84. The first inverter 82 includes a left upper pull-up transistor 86 and a left lower pull-down transistor 88, and the second inverter 84 includes a right upper pull-up transistor 90 and a right lower pull-down transistor 92. The SRAM cell 80 further includes a left transfer gate transistor 94 and a right transfer gate transistor 96.

[0025] Each of the first inverter 82 and the second inverter 84 is powered, wherein the first terminals of the upper left pull-up crystal 86 and the upper right pull-up crystal 90 are electrically coupled to the power supply VDD, while the first terminals of the lower left pull-down crystal 88 and the lower right pull-down crystal 92 are electrically coupled to the reference voltage VSS, which can be ground voltage. Node QB stores the complement of the value of node Q, so that if node Q is at a high potential, then node QB is at a low potential, and vice versa. Node QB can be read via the complementary bit line BLB and according to the left transmission gate crystal 94, wherein access to node QB can be controlled by the left transmission gate crystal 94.

[0026] The gate of the left transmission gate transistor 94 is coupled to the word line WL. The first source / drain (S / D) terminal of the left transmission gate transistor 94 is coupled to the complementary bit line BLB. The second S / D terminal of the left transmission gate transistor 94 is coupled to node QB, and also coupled to the second terminal of the left upper pull-up transistor 86 and the coupling point of the left lower pull-down transistor 88, and simultaneously coupled to the gates of the right upper pull-up transistor 90 and the right lower pull-down transistor 92.

[0027] The gate of the right transmission gate transistor 96 is coupled to the word line WL. The first S / D terminal of the right transmission gate transistor 96 is coupled to the bit line BL, while the second S / D terminal of the right transmission gate transistor 96 is coupled to the node QB, and is also coupled to the second terminal of the right upper pull-up transistor 90 and the coupling point of the right lower pull-up transistor 92, and is simultaneously coupled to the gates of the left upper pull-up transistor 86 and the left lower pull-up transistor 88.

[0028] Figure 5 is a schematic diagram of a control circuit 100 connected to a memory array 102 according to an embodiment of this disclosure. The control circuit 100 is used to perform columnar access operations and rowar access operations on data in the memory array 102. In a first access operation, data can be read from the memory array 102 in a "normal" columnar order. In a second access operation, data can be read from the memory array 102 in a "transposed" rowar order. In some embodiments, the control circuit 100 is similar to the control circuit 52 shown in Figure 3. In some embodiments, the memory array 102 is similar to the memory array 54 shown in Figure 3.

[0029] The memory array 102 includes a plurality of memory cells 104 storing data. The memory array 102 includes bit line pairs of bit lines BL and word lines WL for accessing the memory cells 104 in the memory array 102. Furthermore, column selection circuitry (e.g., column selection circuitry 56) and row selection circuitry (e.g., row selection circuitry 58) may be connected to the memory array 102 and used to select memory cells 104 in columns and rows of the memory array 102 during read and write operations. In some embodiments, the row selection circuitry includes one or more row decoder circuits (e.g., row decoder circuitry 60) for selecting rows in "normal" columnar order of data and reading data in "transposed" rowar order of data. In some embodiments, the memory cells 104 are SRAM cells. In some embodiments, the memory cells 104 are similar to the memory cell 80 of Figure 4.

[0030] The control circuit 100 is connected to the memory array 102 via bit pairs, such as bit lines BL and complementary bit lines BLB, and is used to write data into and read data from the memory array 102. The control circuit 100 includes a first multiplexer set 106a-106d, which retrieves data from the memory array 102 and transmits the data to multiple I / O terminals 108a-108d in a first data column order. The first multiplexer set 106a-106d is a 4-to-1 multiplexer, having 4 bit pairs of input terminals (e.g., 8 input terminals), 1 output terminal, and multiple control input terminals for selecting which input terminal data is provided to the multiplexer output terminal. The control circuit 100 includes a second set of multiplexers 110a-110d, which retrieves data from the memory array 102 and transmits the data to a plurality of I / O terminals 108a-108d in a second data row order transposed from the first data column order. Each of the second set of multiplexers 110a-110d is a 4-to-1 multiplexer, having four bit-line pairs of input terminals (e.g., eight input terminals), one output terminal, and a plurality of control input terminals for selecting which input terminal data is provided to the multiplexer output terminal. In some embodiments, the first set of multiplexers 106a-106d is similar to the first set of multiplexers 62 shown in Figure 3. In some embodiments, the second set of multiplexers 110a-110d is similar to the second set of multiplexers 66 shown in Figure 3. In some embodiments, the plurality of I / O terminals 108a-108d is similar to the plurality of I / O terminals 64 shown in Figure 3. In other embodiments, the first multiplexer sets 106a-106d each have more than four inputs (e.g., eight or sixteen) and one output. Furthermore, in other embodiments, the second multiplexer sets 110a-110d each have more than four inputs (e.g., eight or sixteen) and one output.

[0031] The control circuit 100 includes multiple input multiplexers 112a-112d that receive data and transmit the data to I / O terminals 108a-108d. Each of the multiple input multiplexers 112a-112d is a 4-to-1 multiplexer, having four input terminals, one output terminal, and multiple control input terminals for selecting which input data is provided to the multiplexer output terminal. Furthermore, the control circuit 100 includes output multiplexers 114a-114d that receive data from I / O terminals 108a-108d and output the data to other hardware components, such as hardware and / or memory devices external to the control circuit 100. Each of the output multiplexers 114a-114d is a 4-to-1 multiplexer, having four input terminals, one output terminal, and multiple control input terminals for selecting which input data is provided to the multiplexer output terminal. In some embodiments, the multiple input multiplexers 112a-112d are similar to the input multiplexer 68 shown in Figure 3. In some embodiments, the output multiplexers 114a-114d are similar to the output multiplexer 70 shown in Figure 3. In other embodiments, the multiple input multiplexers 112a-112d each have more than four inputs (e.g., eight or sixteen) and one output. Furthermore, in other embodiments, the output multiplexers 114a-114d each have more than four inputs (e.g., eight or sixteen) and one output. In other embodiments, the multiple input multiplexers 112a-112d and / or the output multiplexers 114a-114d are located outside the control circuit 100.

[0032] Figure 6 is a schematic diagram of multiplexers 106a, 106b, 110a, 110b and I / O terminals 108a, 108b according to an embodiment of this disclosure. Multiplexers 106a, 106b are examples in the first set of multiplexers 106a-106d, while multiplexers 110a and 110b are examples in the second set of multiplexers (multiplexers 110a-110d). The remaining multiplexers in the first and second sets will not be further described here.

[0033] Multiplexers 106a and 110a include PMOS transistor transmission gates 116a-116h. Each PMOS transistor transmission gate 116a-116h includes two PMOS transistors, the drains of which are connected to each other and the sources of which are connected to each other. One of the drain-connected or source-connected transistors is connected to a bit line BL or a complementary bit line BLB, while the other drain-connected or source-connected transistor is connected to a data line DL or a complementary data line DLB. In addition, one gate of the two PMOS transistors is connected to one of the normal row select lines RYN[3:0] of multiplexer 106a, and the other gate of the two PMOS transistors is connected to the transposed row select line RYT[3:0].

[0034] PMOS transistor transmission gates 116a, 116c, 116e, and 116g are connected to bit line BL, and PMOS transistor transmission gates 116b, 116d, 116f, and 116h are connected to complementary bit line BLB. Furthermore, PMOS transistor transmission gates 116a, 116c, 116e, and 116g are connected to multiple data lines DL, which are interconnected at the outputs of multiplexers 106a and 110a. PMOS transistor transmission gates 116b, 116d, 116f, and 116h are connected to multiple complementary data lines DLB, which are interconnected at the outputs of multiplexers 106a and 110a.

[0035] The normal row select line RYN[3:0] for multiplexer 106a is connected to the PMOS transistor of each of the PMOS transistor transmission gates 116a-116h. And, the transpose row select line RYT[3:0] for multiplexer 110a is connected to the other PMOS transistor in each of the PMOS transistor transmission gates 116a-116h.

[0036] The multiplexer 106a is connected to the normal row select line RYN[3:0] in the sequence [0,1,2,3]. The PMOS transistor transmission gate 116a is connected to the first address line 0 of the normal row select line RYN[3:0] for bit line BL and data line DL. The PMOS transistor transmission gate 116b is connected to the first address line 0 of the normal row select line RYN[3:0] for complementary bit line BLB and complementary data line DLB. The PMOS transistor transmission gate 116c is connected to the second address line 1 of the normal row select line RYN[3:0] for bit line BL and data line DL. The PMOS transistor transmission gate 116d is connected to the second address line 1 of the normal row select line RYN[3:0] for complementary bit line BLB and complementary data line DLB. PMOS transistor transmission gate 116e is connected to the third address line 2 of the normal row select line RYN[3:0] for bit line BL and data line DL. PMOS transistor transmission gate 116f is connected to the third address line 2 of the normal row select line RYN[3:0] for complementary bit line BLB and complementary data line DLB. PMOS transistor transmission gate 116g is connected to the fourth address line 3 of the normal row select line RYN[3:0] for bit line BL and data line DL. PMOS transistor transmission gate 116h is connected to the fourth address line 3 of the normal row select line RYN[3:0] for complementary bit line BLB and complementary data line DLB.

[0037] The multiplexer 110a is connected to the transposed row select line RYT[3:0] in the sequence [0,1,2,3]. The PMOS transistor transmission gate 116a is connected to the first address line 0 of the transposed row select line RYT[3:0] for bit line BL and data line DL. The PMOS transistor transmission gate 116b is connected to the first address line 0 of the transposed row select line RYT[3:0] for complementary bit line BLB and complementary data line DLB. The PMOS transistor transmission gate 116c is connected to the second address line 1 of the transposed row select line RYT[3:0] for bit line BL and data line DL. The PMOS transistor transmission gate 116d is connected to the second address line 1 of the transposed row select line RYT[3:0] for complementary bit line BLB and complementary data line DLB. PMOS transistor transmission gate 116e is connected to the third address line 2 of the transposed row select line RYT[3:0] for bit line BL and data line DL. PMOS transistor transmission gate 116f is connected to the third address line 2 of the transposed row select line RYT[3:0] for complementary bit line BLB and complementary data line DLB. PMOS transistor transmission gate 116g is connected to the fourth address line 3 of the transposed row select line RYT[3:0] for bit line BL and data line DL. PMOS transistor transmission gate 116h is connected to the fourth address line 3 of the transposed row select line RYT[3:0] for complementary bit line BLB and complementary data line DLB.

[0038] Multiplexers 106b and 110b include PMOS transistor transmission gates 118a-118h. Each PMOS transistor transmission gate 118a-118h includes two PMOS transistors, the drains of which are connected to each other and the sources of which are connected to each other. One of the drain connection or source connection is connected to a bit line BL or a complementary bit line BLB, while the other drain connection or source connection is connected to a data line DL or a complementary data line DLB. In addition, one gate of the two PMOS transistors is connected to one of the normal row select lines RYN[3:0] of multiplexer 106b, and the other gate of the two PMOS transistors is connected to the transposed row select line RYT[3:0].

[0039] PMOS transistor transmission gates 118a, 118c, 118e, and 118g are connected to bit line BL, and PMOS transistor transmission gates 118b, 118d, 118f, and 118h are connected to complementary bit line BLB. Furthermore, PMOS transistor transmission gates 118a, 118c, 118e, and 118g are connected to multiple data lines DL, which are interconnected at the outputs of multiplexers 106b and 110b. PMOS transistor transmission gates 118b, 118d, 118f, and 118h are connected to multiple complementary data lines DLB, which are interconnected at the outputs of multiplexers 106b and 110b.

[0040] The normal row select line RYN[3:0] for multiplexer 106b is connected to the PMOS transistor of each of the PMOS transistor transmission gates 118a-118h. Furthermore, the transpose row select line RYT[3:0] for multiplexer 110b is connected to the other PMOS transistor of each of the PMOS transistor transmission gates 118a-118h.

[0041] The multiplexer 106b is connected to the normal row select line RYN[3:0] in the sequence [0,1,2,3]. The PMOS transistor transmission gate 118a is connected to the first address line 0 of the normal row select line RYN[3:0] for bit line BL and data line DL. The PMOS transistor transmission gate 118b is connected to the first address line 0 of the normal row select line RYN[3:0] for complementary bit line BLB and complementary data line DLB. The PMOS transistor transmission gate 118c is connected to the second address line 1 of the normal row select line RYN[3:0] for bit line BL and data line DL. The PMOS transistor transmission gate 118d is connected to the second address line 1 of the normal row select line RYN[3:0] for complementary bit line BLB and complementary data line DLB. PMOS transistor transmission gate 118e is connected to the third address line 2 of the normal row select line RYN[3:0] for bit line BL and data line DL. PMOS transistor transmission gate 118f is connected to the third address line 2 of the normal row select line RYN[3:0] for complementary bit line BLB and complementary data line DLB. PMOS transistor transmission gate 118g is connected to the fourth address line 3 of the normal row select line RYN[3:0] for bit line BL and data line DL. PMOS transistor transmission gate 118h is connected to the fourth address line 3 of the normal row select line RYN[3:0] for complementary bit line BLB and complementary data line DLB.

[0042] The multiplexer 110b is connected to the transposed row select line RYT[3:0] in the sequence [1,0,3,2]. The PMOS transistor transmission gate 118a is connected to the second address line 1 of the transposed row select line RYT[3:0] for bit line BL and data line DL. The PMOS transistor transmission gate 118b is connected to the second address line 1 of the transposed row select line RYT[3:0] for complementary bit line BLB and complementary data line DLB. The PMOS transistor transmission gate 118c is connected to the first address line 0 of the transposed row select line RYT[3:0] for bit line BL and data line DL. The PMOS transistor transmission gate 118d is connected to the first address line 0 of the transposed row select line RYT[3:0] for complementary bit line BLB and complementary data line DLB. PMOS transistor transmission gate 118e is connected to the fourth address line 3 of the transposed row select line RYT[3:0] for bit line BL and data line DL. PMOS transistor transmission gate 118f is connected to the fourth address line 3 of the transposed row select line RYT[3:0] for complementary bit line BLB and complementary data line DLB. PMOS transistor transmission gate 118g is connected to the third address line 2 of the transposed row select line RYT[3:0] for bit line BL and data line DL. PMOS transistor transmission gate 118h is connected to the third address line 2 of the transposed row select line RYT[3:0] for complementary bit line BLB and complementary data line DLB.

[0043] Referring to Figures 5 and 6, each of the first multiplexer sets 106a-106d is connected to the normal row selection line RYN[3:0] in the order of [0,1,2,3]. Multiplexer 110a is connected to the transposed row selection line RYT[3:0] in the sequence [0,1,2,3]; multiplexer 110b is connected to the transposed row selection line RYT[3:0] in the sequence [1,0,3,2]; multiplexer 110c is connected to the transposed row selection line RYT[3:0] in the sequence [2,3,0,1]; and multiplexer 110d is connected to the transposed row selection line RYT[3:0] in the sequence [3,2,1,0]. In some embodiments, the row selection circuit 58 provides multiple selection signals to the normal row selection line RYN[3:0] and the transposed row selection line RYT[3:0]. In some embodiments, the decoder circuit 60 may select whether to activate the normal line selection line RYN[3:0] or the transposed line selection line RYT[3:0].

[0044] Figure 7 is a schematic diagram of a control circuit 100 performing a write operation on a memory array 102 according to an embodiment of this disclosure. The memory array 102 includes a plurality of memory cells 104 arranged in columns along the x-axis 120 and rows along the y-axis 122. Column selection circuits (e.g., column selection circuit 56) and row selection circuits (e.g., row selection circuit 58) decode addresses and select the column and row of the memory cell to be written. In some embodiments, the row selection circuit includes one or more row decoder circuits (e.g., row decoder circuit 60) for selecting the input terminals of a plurality of input multiplexers 112a-112d to write data into the memory array 102.

[0045] The control circuit 100 includes multiple input multiplexers 112a-112d that receive data and transmit the data to I / O terminals 108a-108d. Each of the multiple input multiplexers 112a-112d is a 4-to-1 multiplexer, having four input terminals, one output terminal, and a control input terminal (not shown) for selecting which input data is provided to the multiplexer output terminal. In some embodiments, the multiple input multiplexers 112a-112d are similar to the input multiplexer 68 shown in Figure 3. In other embodiments, each of the multiple input multiplexers 112a-112d has more than four input terminals (e.g., eight or sixteen) and one additional output terminal.

[0046] In order to write data into the memory array 102, the data is transmitted to external data input terminals ext-D[0], ext-D[1], ext-D[2], and ext-D[3], and connected to internal data input terminals int-D[0], int-D[1], int-D[2], and int-D[3] and multiple I / O terminals 108a-108d respectively through one of the multiple input multiplexers 112a-112d. Each of the four input terminals of each of the multiple input multiplexers 112a-112d can receive data. Input multiplexer 112a receives external input data ext-D[0,1,2,3], input multiplexer 112b receives external input data ext-D[1,0,3,2], input multiplexer 112c receives external input data ext-D[2,3,0,1], and input multiplexer 112d receives external input data ext-D[3,2,1,0].

[0047] The data written to the memory array 102 is provided from the outside, such as from another device or user. Figure 8 is a schematic diagram of an external data mapping table 132 for data written to the memory array 102 according to an embodiment of this disclosure.

[0048] During a write operation, the column selection circuit can select a column, for example, column x = 0; and either the row selection circuit or the row decoder circuit can select a row, for example, row y = 0, 1, 2, or 3. The selected row y = 0, 1, 2, or 3 can select one of the four input terminals on each of the multiple input multiplexers 112a-112d, which can be provided to the output terminal of the multiplexer. The input terminals of each of the multiple input multiplexers 112a-112d can be selected in sequence [0, 1, 2, 3], and all input multiplexers 112a-112d receive the same row selection signal.

[0049] Referring to Figures 7 and 8, when the xy address of memory array 102 is located at column x=0 and row y=0, data 00 is provided to the external data input terminal ext-D[0] and written to memory cell 124a through input multiplexer 112a and I / O terminal 108a; data 01 is provided to the external data input terminal ext-D[1] and written to memory cell 124b through input multiplexer 112b and I / O terminal 108b; data 02 is provided to the external data input terminal ext-D[2] and written to memory cell 124c through input multiplexer 112c and I / O terminal 108c; and data 03 is provided to the external data input terminal ext-D[3] and written to memory cell 124d through input multiplexer 112d and I / O terminal 108d.

[0050] When the xy address of memory array 102 is located at column x=0 and row y=1, data 11 is provided to external data input terminal ext-D[0] and written to memory cell 126a through input multiplexer 112a and I / O terminal 108a; data 10 is provided to external data input terminal ext-D[1] and written to memory cell 126b through input multiplexer 112b and I / O terminal 108b; data 13 is provided to external data input terminal ext-D[2] and written to memory cell 126c through input multiplexer 112c and I / O terminal 108c; and data 12 is provided to external data input terminal ext-D[3] and written to memory cell 126d through input multiplexer 112d and I / O terminal 108d.

[0051] When the xy address of memory array 102 is located at column x=0 and row y=2, data 22 is provided to external data input terminal ext-D[0] and written to memory cell 128a through input multiplexer 112a and I / O terminal 108a; data 23 is provided to external data input terminal ext-D[1] and written to memory cell 128b through input multiplexer 112b and I / O terminal 108b; data 20 is provided to external data input terminal ext-D[2] and written to memory cell 128c through input multiplexer 112c and I / O terminal 108c; and data 21 is provided to external data input terminal ext-D[3] and written to memory cell 128d through input multiplexer 112d and I / O terminal 108d.

[0052] When the xy address of memory array 102 is located at column x=0 and row y=3, data 33 is provided to the external data input terminal ext-D[0] and written to memory cell 130a through input multiplexer 112a and I / O terminal 108a; data 32 is provided to the external data input terminal ext-D[1] and written to memory cell 130b through input multiplexer 112b and I / O terminal 108b; data 31 is provided to the external data input terminal ext-D[2] and written to memory cell 130c through input multiplexer 112c and I / O terminal 108c; and data 21 is provided to the external data input terminal ext-D[3] and written to memory cell 130d through input multiplexer 112d and I / O terminal 108d. The above operations can be repeated for any number of rows and columns, for example, column x=1 and rows y=0, 1, 2 and 3.

[0053] Figure 9 is a schematic diagram of a control circuit 100 performing a "normal" columnar access operation on a memory array 102 according to an embodiment of this disclosure. The "normal" columnar access operation reads data from the memory array 102 in the form of data columns, as shown in the external data mapping table 132 of Figure 8.

[0054] The memory array 102 includes a plurality of memory cells 104 arranged in columns along the x-axis 120 and rows along the y-axis 122. Column selection circuitry (e.g., column selection circuitry 56) and row selection circuitry (e.g., row selection circuitry 58) decode the address and select the column and row of the memory cell to be read. In some embodiments, the row selection circuitry includes one or more row decoder circuits (e.g., row decoder circuitry 60) for selecting the inputs of the first multiplexer sets 106a-106d and the inputs of the plurality of output multiplexers 114a-114d to read data from the memory array 102.

[0055] The control circuit 100 includes a first multiplexer set 106a-106d, which receives data from the memory array 102 and transmits the data to a plurality of I / O terminals 108a-108d. Each of the first multiplexer sets 106a-106d is a 4-to-1 multiplexer, having four inputs, one output, and a control input (not shown) for selecting which input data is provided to the multiplexer output. The inputs of each of the first multiplexer sets 106a-106d can be selected sequentially [0, 1, 2, 3]. In some embodiments, the first multiplexer sets 106a-106d are similar to the first multiplexer set 62 shown in Figure 3. In other embodiments, each of the first multiplexer sets 106a-106d has more than four inputs (e.g., eight or sixteen) and one additional output.

[0056] The control circuit 100 further includes multiple output multiplexers 114a-114d that receive data from multiple I / O terminals 108a-108d and an internal output terminal int-Q. The multiple output multiplexers 114a-114d transmit data to an external output terminal ext-Q. Each of the output multiplexers 114a-114d is a 4-to-1 multiplexer, having four inputs, one output, and a control input (not shown) for selecting which input data is provided to the multiplexer output. The inputs of each of the multiple multiplexers 114a-114d can be selected sequentially [0, 1, 2, 3]. In some embodiments, the multiple output multiplexers 114a-114d are similar to the output multiplexer 70 shown in Figure 3. In other embodiments, each of the multiple output multiplexers 114a-114d has more than four inputs (e.g., eight or sixteen) and one additional output.

[0057] In order to read data from memory array 102, the first multiplexer set 106a-106d receives data from memory array 102 and transmits the data to multiple I / O terminals 108a-108d and internal output terminals int-Q[0], int-Q[1], int-Q[2] and int-Q[3]. Next, the data is transmitted to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and ext-Q[3] through multiple output multiplexers 114a-114d. Output multiplexer 114a receives internal output data int-Q[0,1,2,3], output multiplexer 114b receives internal output data int-Q[1,0,3,2], output multiplexer 114c receives internal output data int-Q[2,3,0,1], and output multiplexer 114d receives internal output data int-Q[3,2,1,0]. The data received at the external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and ext-Q[3] are mapped to columns of the external data mapping table 132, and one column is mapped at a time.

[0058] In a read operation, the column selection circuit selects a column (e.g., column x=0), and either the row selection circuit or the row decoder circuit selects a row (e.g., row y=0, 1, 2, or 3). The selected row y=0, 1, 2, or 3 can be selected from one of the four inputs of each of the first multiplexer sets 106a-106d and / or one of the four inputs of each of the multiple output multiplexers 114a-114d. The inputs of each of the first multiplexer sets 106a-106d can be selected in the order [0, 1, 2, 3], and the inputs of each of the multiple output multiplexers 114a-114d are selected in the order [0, 1]. In some embodiments, the first multiplexer sets 106a-106d all receive the same row selection signal. In some embodiments, the multiple output multiplexers 114a-114d all receive the same row selection signal. In some embodiments, the first multiplexer set 106a-106d and the plurality of output multiplexers 114a-114d all receive the same row selection signal. In some embodiments, the first multiplexer set 106a-106d and the plurality of output multiplexers 114a-114d receive different row selection signals at different times.

[0059] Referring to Figures 8 and 9, when the xy address of memory array 102 is located at column x=0 and row y=0, data 00 is read from memory cell 124a, received from multiplexer 106a, and transmitted to I / O terminal 108a (I / O[0]) and internal output terminal int-Q[0]. Data 00 is further received by output multiplexer 114a and transmitted to external output terminal ext-Q[0]. Data 01 is read from memory cell 124b, received from multiplexer 106b, and transmitted to I / O terminal 108b (I / O[1]) and internal output terminal int-Q[1]. Data 01 is further received by output multiplexer 114b and transmitted to external output terminal ext-Q[1]. Data 02 is read from memory unit 124c, received from multiplexer 106c, and transmitted to I / O terminal 108c (I / O[2]) and internal output terminal int-Q[2]. Data 02 is further received by output multiplexer 114c and transmitted to external output terminal ext-Q[2]. Data 03 is read from memory unit 124d, received from multiplexer 106d, and transmitted to I / O terminal 108d (I / O[3]) and internal output terminal int-Q[3]. Data 03 is further received by output multiplexer 114d and transmitted to external output terminal ext-Q[3]. Data received at external output terminals ext-Q[0], ext-Q[1], ext-Q[2], and ext-Q[3] are mapped to the first column of external data mapping table 132.

[0060] When the xy address of memory array 102 is located at column x=0 and row y=1, data 11 is read from memory cell 126a, received from multiplexer 106a, and transmitted to I / O terminal 108a (I / O[0]) and internal output terminal int-Q[0]. Data 11 is further received by output multiplexer 114a and transmitted to external output terminal ext-Q[0]. Data 10 is read from memory cell 126b, received from multiplexer 106b, and transmitted to I / O terminal 108b (I / O[1]) and internal output terminal int-Q[1]. Data 10 is further received by output multiplexer 114b and transmitted to external output terminal ext-Q[1]. Data 13 is read from memory cell 126c, received from multiplexer 106c, and transmitted to I / O terminal 108c (I / O[2]) and internal output terminal int-Q[2]. Data 13 is further received by output multiplexer 114c and transmitted to external output terminal ext-Q[2]. Data 12 is read from memory cell 126d, received from multiplexer 106d, and transmitted to I / O terminal 108d (I / O[3]) and internal output terminal int-Q[3]. Data 12 is further received by output multiplexer 114d and transmitted to external output terminal ext-Q[3]. Data received at external output terminals ext-Q[0], ext-Q[1], ext-Q[2], and ext-Q[3] are mapped to the second column of external data mapping table 132.

[0061] When the xy address of memory array 102 is located at column x=0 and row y=2, data 22 is read from memory cell 128a, received from multiplexer 106a, and transmitted to I / O terminal 108a (I / O[0]) and internal output terminal int-Q[0]. Data 22 is further received by output multiplexer 114a and transmitted to external output terminal ext-Q[0]. Data 23 is read from memory cell 128b, received from multiplexer 106b, and transmitted to I / O terminal 108b (I / O[1]) and internal output terminal int-Q[1]. Data 23 is further received by output multiplexer 114b and transmitted to external output terminal ext-Q[1]. Data 20 is read from memory cell 128c, received from multiplexer 106c, and transmitted to I / O terminal 108c (I / O[2]) and internal output terminal int-Q[2]. Data 20 is further received by output multiplexer 114c and transmitted to external output terminal ext-Q[2]. Data 21 is read from memory cell 128d, received from multiplexer 106d, and transmitted to I / O terminal 108d (I / O[3]) and internal output terminal int-Q[3]. Data 21 is further received by output multiplexer 114d and transmitted to external output terminal ext-Q[3]. Data received at external output terminals ext-Q[0], ext-Q[1], ext-Q[2], and ext-Q[3] are mapped to the third column of external data mapping table 132.

[0062] When the xy address of memory array 102 is located at column x=0 and row y=3, data 33 is read from memory cell 130a, received from multiplexer 106a, and transmitted to I / O terminal 108a (I / O[0]) and internal output terminal int-Q[0]. Data 33 is further received by output multiplexer 114a and transmitted to external output terminal ext-Q[0]. Data 32 is read from memory cell 130b, received from multiplexer 106b, and transmitted to I / O terminal 108b (I / O[1]) and internal output terminal int-Q[1]. Data 32 is further received by output multiplexer 114b and transmitted to external output terminal ext-Q[1]. Data 31 is read from memory cell 130c, received from multiplexer 106c, and transmitted to I / O terminal 108c (I / O[2]) and internal output terminal int-Q[2]. Data 31 is further received by output multiplexer 114c and transmitted to external output terminal ext-Q[2]. Data 30 is read from memory cell 130d, received from multiplexer 106d, and transmitted to I / O terminal 108d (I / O[3]) and internal output terminal int-Q[3]. Data 30 is further received by output multiplexer 114d and transmitted to external output terminal ext-Q[3]. Data received at external output terminals ext-Q[0], ext-Q[1], ext-Q[2], and ext-Q[3] are mapped to the fourth column of external data mapping table 132.

[0063] This operation can be repeated for any number of columns and rows, for example, column x = 1 and rows y = 0, 1, 2 and 3.

[0064] Figure 10 is a schematic diagram of a control circuit 100 performing a "transpose" row access operation on a memory array 102 according to an embodiment of this disclosure, and Figure 11 is a schematic diagram of an external data mapping table 140 for reading data from the memory array 102 according to an embodiment of this disclosure. The "transpose" row access operation reads data from the memory array 102 in the form of data columns, as shown in the external data mapping table 140 of Figure 11.

[0065] The memory array 102 includes a plurality of memory cells 104 arranged in columns along the x-axis 120 and rows along the y-axis 122. Column selection circuitry (e.g., column selection circuitry 56) and row selection circuitry (e.g., row selection circuitry 58) decode the address and select the column and row of the memory cell to be written. In some embodiments, the row selection circuitry includes one or more row decoder circuitry (e.g., row decoder circuitry 60) for selecting the inputs of the second multiplexer set 110a-110d and the inputs of the plurality of output multiplexers 114a-114d, and for reading data from the memory array 102.

[0066] The control circuit 100 includes a second multiplexer set 110a-110d, which receives data from the memory array 102 and transmits the data to multiple I / O terminals 108a-108d. Each of the second multiplexer sets 110a-110d is a 4-to-1 multiplexer, having 4 input terminals, 1 output terminal, and a control input terminal (not shown) for selecting which input data is provided to the multiplexer output terminal. The input terminals of multiplexer 110a can be selected sequentially [0, 1, 2, 3], the input terminals of multiplexer 110b can be selected sequentially [1, 0, 3, 2], the input terminals of multiplexer 110c can be selected sequentially [2, 3, 0, 1], and the input terminals of multiplexer 110d can be selected sequentially [3, 2, 1, 0]. In some embodiments, the second multiplexer sets 110a-110d are similar to the second multiplexer set 66 shown in Figure 3. In other embodiments, the second multiplexer sets 110a-110d each have more than four inputs (e.g., eight or sixteen) and one output.

[0067] The control circuit 100 further includes multiple output multiplexers 114a-114d that receive data from multiple I / O terminals 108a-108d and an internal output terminal int-Q. The multiple output multiplexers 114a-114d transmit data to an external output terminal ext-Q. Each of the output multiplexers 114a-114d is a 4-to-1 multiplexer, having four inputs, one output, and a control input (not shown) for selecting which input data is provided to the multiplexer output. The inputs of each of the multiple multiplexers 114a-114d can be selected sequentially [0, 1, 2, 3]. In some embodiments, the multiple output multiplexers 114a-114d are similar to the output multiplexer 70 shown in Figure 3. In other embodiments, each of the multiple output multiplexers 114a-114d has more than four inputs (e.g., eight or sixteen) and one additional output.

[0068] In order to read data from memory array 102, the second multiplexer set 110a-110d receives data from memory array 102 and transmits the data to multiple I / O terminals 108a-108d and internal output terminals int-Q[0], int-Q[1], int-Q[2] and int-Q[3]. Next, the data is transmitted to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and ext-Q[3] through multiple output multiplexers 114a-114d. Output multiplexer 114a receives internal output data int-Q[0,1,2,3], output multiplexer 114b receives internal output data int-Q[1,0,3,2], output multiplexer 114c receives internal output data int-Q[2,3,0,1], and output multiplexer 114d receives internal output data int-Q[3,2,1,0]. The data received at the external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and ext-Q[3] are mapped to rows of the external data mapping table 140, and one row is mapped at a time.

[0069] In the read operation, the column selection circuit selects a column (e.g., column x=0), and either the row selection circuit or the row decoder circuit selects a row (e.g., row y=0, 1, 2, or 3). The selected row y=0, 1, 2, or 3 can select one of the four inputs of each of the second multiplexer sets 110a-110d and / or one of the four inputs of each of the multiple output multiplexers 114a-114d. The inputs of multiplexer 110a can be selected in the order [0, 1, 2, 3], the inputs of multiplexer 110b can be selected in the order [1, 0, 3, 2], the inputs of multiplexer 110c can be selected in the order [2, 3, 0, 1], and the inputs of multiplexer 110d can be selected in the order [3, 2, 1, 0]. Additionally, the inputs of each of the multiple output multiplexers 114a-114d can be selected sequentially [0, 1, 2, 3]. In some embodiments, the second multiplexer set 110a-110d all receive the same row selection signal. In some embodiments, the multiple output multiplexers 114a-114d receive the same row selection signal. In some embodiments, the second multiplexer set 110a-110d and the multiple output multiplexers 114a-114d all receive the same column selection signal. In some embodiments, the second multiplexer set 110a-110d and the multiple output multiplexers 114a-114d receive different row selection signals at different times.

[0070] Referring to Figures 10 and 11, when the xy address of memory array 102 is located at column x=0 and row y=0, data 00 is read from memory cell 124a, received from multiplexer 110a, and transmitted to I / O terminal 108a (I / O[0]) and internal output terminal int-Q[0]. Data 00 is further received by output multiplexer 114a and transmitted to external output terminal ext-Q[0], and corresponds to the first column of external data mapping table 140 in Figure 11. Data 10 is read from memory cell 126b, received from multiplexer 110b, and transmitted to I / O terminal 108b (I / O[1]) and internal output terminal int-Q[1]. Data 10 is further received by output multiplexer 114b and transmitted to external output terminal ext-Q[1], and corresponds to the first column of external data mapping table 140 in Figure 11. Data 20 is read from memory cell 128c, received from multiplexer 110c, and transmitted to I / O terminal 108c (I / O[2]) and internal output terminal int-Q[2]. Data 20 is further received by output multiplexer 114c, transmitted to external output terminal ext-Q[2], and corresponds to the first column of external data mapping table 140 in Figure 11. Data 30 is read from memory cell 130d, received from multiplexer 110d, and transmitted to I / O terminal 108d (I / O[3]) and internal output terminal int-Q[3]. Data 30 is further received by output multiplexer 114d, transmitted to external output terminal ext-Q[3], and corresponds to the first column of external data mapping table 140 in Figure 11. Therefore, data can be transposed from memory array 102 to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and the first column of data in external data mapping table 140.

[0071] When the xy address of memory array 102 is located at column x=0 and row y=1, data 11 is read from memory cell 126a, received from multiplexer 110a, and transmitted to I / O terminal 108a (I / O[0]) and internal output terminal int-Q[0]. Data 11 is further received by output multiplexer 114a and transmitted to external output terminal ext-Q[0], and corresponds to the second column of external data mapping table 140 in Figure 11. Data 01 is read from memory cell 124b, received from multiplexer 110b, and transmitted to I / O terminal 108b (I / O[1]) and internal output terminal int-Q[1]. Data 01 is further received by output multiplexer 114b and transmitted to external output terminal ext-Q[1], and corresponds to the second column of external data mapping table 140 in Figure 11. Data 31 is read from memory cell 130c, received from multiplexer 110c, and transmitted to I / O terminal 108c (I / O[2]) and internal output terminal int-Q[2]. Data 31 is further received by output multiplexer 114c, transmitted to external output terminal ext-Q[2], and corresponds to the second column of external data mapping table 140 in Figure 11. Data 21 is read from memory cell 128d, received from multiplexer 110d, and transmitted to I / O terminal 108d (I / O[3]) and internal output terminal int-Q[3]. Data 21 is further received by output multiplexer 114d, transmitted to external output terminal ext-Q[3], and corresponds to the second column of external data mapping table 140 in Figure 11. Therefore, data can be transposed from memory array 102 to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and the second column of data in external data mapping table 140.

[0072] When the xy address of memory array 102 is located at column x=0 and row y=2, data 22 is read from memory cell 128a, received from multiplexer 110a, and transmitted to I / O terminal 108a (I / O[0]) and internal output terminal int-Q[0]. Data 22 is further received by output multiplexer 114a and transmitted to external output terminal ext-Q[0], and corresponds to the third column of external data mapping table 140 in Figure 11. Data 32 is read from memory cell 130b, received from multiplexer 110b, and transmitted to I / O terminal 108b (I / O[1]) and internal output terminal int-Q[1]. Data 32 is further received by output multiplexer 114b and transmitted to external output terminal ext-Q[1], and corresponds to the third column of external data mapping table 140 in Figure 11. Data 02 is read from memory unit 124c, received from multiplexer 110c, and transmitted to I / O terminal 108c (I / O[2]) and internal output terminal int-Q[2]. Data 02 is further received by output multiplexer 114c, transmitted to external output terminal ext-Q[2], and corresponds to the third column of external data mapping table 140 in Figure 11. Data 12 is read from memory unit 126d, received from multiplexer 110d, and transmitted to I / O terminal 108d (I / O[3]) and internal output terminal int-Q[3]. Data 12 is further received by output multiplexer 114d, transmitted to external output terminal ext-Q[3], and corresponds to the third column of external data mapping table 140 in Figure 11. Therefore, data can be transposed from memory array 102 to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and the third column of data in external data mapping table 140.

[0073] When the xy address of memory array 102 is located at column x=0 and row y=3, data 33 is read from memory cell 130a, received from multiplexer 110a, and transmitted to I / O terminal 108a (I / O[0]) and internal output terminal int-Q[0]. Data 33 is further received by output multiplexer 114a and transmitted to external output terminal ext-Q[0], and corresponds to the fourth column of external data mapping table 140 in Figure 11. Data 23 is read from memory cell 128b, received from multiplexer 110b, and transmitted to I / O terminal 108b (I / O[1]) and internal output terminal int-Q[1]. Data 23 is further received by output multiplexer 114b and transmitted to external output terminal ext-Q[1], and corresponds to the fourth column of external data mapping table 140 in Figure 11. Data 13 is read from memory cell 126c, received from multiplexer 110c, and transmitted to I / O terminal 108c (I / O[2]) and internal output terminal int-Q[2]. Data 13 is further received by output multiplexer 114c, transmitted to external output terminal ext-Q[2], and corresponds to the fourth column of external data mapping table 140 in Figure 11. Data 03 is read from memory cell 124d, received from multiplexer 110d, and transmitted to I / O terminal 108d (I / O[3]) and internal output terminal int-Q[3]. Data 03 is further received by output multiplexer 114d, transmitted to external output terminal ext-Q[3], and corresponds to the fourth column of external data mapping table 140 in Figure 11. Therefore, data can be transposed from memory array 102 to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and the fourth column of data in external data mapping table 140.

[0074] This operation can be repeated for any number of columns and rows, for example, column x = 1 and rows y = 0, 1, 2 and 3.

[0075] Figure 12 is a schematic diagram of a control circuit 150 connected to a memory array 152 comprising a first memory bank (bank 0) 154 and a second memory bank (bank 1) 156, according to an embodiment of this disclosure. Furthermore, the control circuit 150 is used to read data from each of the first memory bank 154 and the second memory bank 156 in columnar access operations and row-level access operations. In the first access operation, data can be read from each of the first memory bank 154 and the second memory bank 156 in a "normal" columnar order. In the second access operation, data can be read from each of the first memory bank 154 and the second memory bank 156 in a "transposed" row-level order. In some embodiments, the control circuit 150 is similar to the control circuit 52 shown in Figure 3. In some embodiments, the memory array 152 is similar to the memory array 54 shown in Figure 3.

[0076] The first memory bank 154 contains a first memory cell set 158 ​​for storing data, while the second memory bank 156 contains a second memory cell set 160 for storing data. The first memory cell set 158 ​​is arranged in columns along the x-axis 162 and rows along the y-axis 164 in the first memory bank 154. The second memory cell set 160 is arranged in columns along the x-axis 166 and rows along the y-axis 168 in the second memory bank 156. Each of the first memory bank 154 and the second memory bank 156 includes bit line pairs of bit lines BL and BLB and word lines WL for accessing the first memory cell set 158 ​​and the second memory cell set 160 in the memory array 152.

[0077] Column selection circuitry (e.g., column selection circuitry 56) and row selection circuitry (e.g., row selection circuitry 58) may be connected to memory array 152 and used to select first memory bank 154 and second memory bank 156, as well as first memory cell set 158 ​​and second memory cell set 160, during read and write operations. In some embodiments, the row selection circuitry includes memory selection circuitry for selecting first memory bank 154 or second memory bank 156. In some embodiments, the row selection circuitry includes one or more row decoder circuits (e.g., row decoder circuitry 60) for selecting rows in "normal" columnar order of data and reading data in "transposed" rowar order of data. In some embodiments, first memory cell set 158 ​​and second memory cell set 160 may be SRAM cells. In some embodiments, first memory cell set 158 ​​and second memory cell set 160 are similar to memory cell 80 of Figure 4.

[0078] . The control circuit 150 is connected to the memory array 152 via the bit line pairs of bit lines BL and BLB, and is used to write data to each of the first memory bank 154 and the second memory bank 156 and to read data from each of the first memory bank 154 and the second memory bank 156 of the memory array 152.

[0079] The control circuit 150 includes a first multiplexer set 170a-170d, which retrieves data from a first memory bank 154 and transmits the data to multiple I / O terminals 172a-172d in a first data column order. Each of the first multiplexer sets 170a-170d is a 4-to-1 multiplexer, having four bit-line pairs of input terminals (e.g., eight input terminals), one output terminal, and multiple control input terminals for selecting which input data is provided to the multiplexer output terminal. The input terminals of each of the first multiplexer sets 170a-170d can be selected sequentially [0, 1, 2, 3]. The control circuit 150 further includes a second set of multiplexers 174a-174d, which retrieves data from the first memory bank 154 and transmits the data to a plurality of I / O terminals 172a-172d in a second data row order transposed from the first data column order. Each of the second set of multiplexers 174a-174d is a 4-to-1 multiplexer, having four bit-line pairs of input terminals (e.g., eight input terminals), one output terminal, and a plurality of control input terminals for selecting which input data is provided to the multiplexer output terminal. In some embodiments, the first set of multiplexers 170a-170d is similar to the first set of multiplexers 62 shown in Figure 3. In some embodiments, the second set of multiplexers 174a-174d is similar to the second set of multiplexers 66 shown in Figure 3. In some embodiments, the plurality of I / O terminals 172a-172d is similar to the plurality of I / O terminals 64 shown in Figure 3. In other embodiments, the first multiplexer sets 170a-170d each have more than four inputs (e.g., eight or sixteen) and one output. Furthermore, in other embodiments, the second plurality of multiplexers 174a-174d each have more than four inputs (e.g., eight or sixteen) and one output.

[0080] The control circuit 150 further includes a third multiplexer set 176a-176d, which retrieves data from the second memory bank 156 and transmits the data to multiple I / O terminals 172a-172d in the first data column sequence. Each of the third multiplexer sets 176a-176d is a 4-to-1 multiplexer, having four bit-line pairs of input terminals (e.g., eight input terminals), one output terminal, and multiple control input terminals for selecting which input data is provided to the multiplexer output terminal. The input terminals of each of the third multiplexer sets 176a-176d can be selected sequentially [0, 1, 2, 3]. Control circuitry 150 includes a fourth set of multiplexers 178a-178d, which retrieves data from a second memory bank 156 and transmits the data to multiple I / O terminals 172a-172d in a second data row order transposed from the first data column order. Each of the fourth multiplexers 178a-178d is a 4-to-1 multiplexer, having four bit-line pairs of inputs (e.g., eight inputs), one output, and multiple control inputs for selecting which input data is provided to the multiplexer output. In some embodiments, a third set of multiplexers 176a-176d is similar to the first set of multiplexers 62 shown in Figure 3. In some embodiments, a fourth set of multiplexers 178a-178d is similar to the second set of multiplexers 66 shown in Figure 3. In other embodiments, the third set of multiplexers 176a-176d has more than four inputs (e.g., eight or sixteen) and one output. Furthermore, in other embodiments, the fourth multiplexer set 178a-178d has more than 4 inputs (e.g., 8 or 16) and one output.

[0081] The control circuit 150 includes multiple input multiplexers 180a-180d, which receive data and transmit the data to multiple I / O terminals 172a-172d. Each of the multiple input multiplexers 180a-180d is a 4-to-1 multiplexer, having four input terminals, one output terminal, and a control input terminal for selecting which input data is provided to the multiplexer output terminal. The input terminals of each of the multiple input multiplexers 180a-180d can be selected sequentially [0,1,2,3]. Furthermore, the control circuit 150 includes multiple output multiplexers 182a-182d, which receive data from the multiple I / O terminals 172a-172d and the internal output terminal int-Q, and transmit the data to the external output terminal ext-Q and hardware external to the control circuit 150 and / or the memory device. Each of the multiple output multiplexers 182a-182d is a 4-to-1 multiplexer, having four inputs, one output, and a control input for selecting which input data is provided to the multiplexer output. The inputs of each of the multiple output multiplexers 182a-182d can be selected sequentially [0, 1, 2, 3]. In some embodiments, the multiple input multiplexers 180a-180d are similar to the input multiplexer 68 shown in Figure 3. In some embodiments, the multiple output multiplexers 182a-182d are similar to the output multiplexer 70 shown in Figure 3. In other embodiments, each of the multiple input multiplexers 180a-180d has more than four inputs (e.g., eight or sixteen) and one additional output. Furthermore, in other embodiments, each of the multiple output multiplexers 182a-182d has more than four inputs (e.g., eight or sixteen) and one additional output. In other embodiments, multiple input multiplexers 180a-180d and / or multiple output multiplexers 182a-182d are disposed outside the control circuit 150.

[0082] During a write operation, column selection circuitry (e.g., column selection circuitry 56) and row selection circuitry (e.g., row selection circuitry 58) decode the address and select one of the first memory bank 154 and the second memory bank 156 to be written, as well as the column and row of the first memory cell set 158 ​​and the second memory cell set 160. In some embodiments, the row selection circuitry includes one or more row decoder circuits (e.g., row decoder circuitry 60) for selecting the inputs of a plurality of input multiplexers 180a-180d to write data to the memory array 152.

[0083] In order to write data into one of the first memory bank 154 and the second memory bank 156, the data is transferred to each of the external data input terminals ext-D[0], ext-D[1], ext-D[2] and ext-D[3], and connected to the internal data input terminals int-D[0], int-D[1], int-D[2] and int-D[3] and the multiple I / O terminals 172a-172d respectively through one of the corresponding terminals of the multiple input multiplexers 180a-180d. Each of the four input terminals of each of the multiple input multiplexers 180a-180d can receive data. Input multiplexer 180a receives external input data ext-D[0,1,2,3], input multiplexer 180b receives external input data ext-D[1,0,3,2], input multiplexer 180c receives external input data ext-D[2,3,0,1], and input multiplexer 180d receives external input data ext-D[3,2,1,0]. Data written to memory array 152 is provided externally, such as from another device or from a user.

[0084] During a write operation, the column selection circuit can select one of the first memory bank 154 and the second memory bank 156, and a column, for example, column x=0; and one of the row selection circuits or the row decoder circuit selects a row, for example, row y = 0, 1, 2, or 3. The selected row y = 0, 1, 2, or 3 can select one of the four input terminals on each of the multiplexers 180a-180d, which can be provided to the output terminal of the multiplexer. The input terminals of each of the multiplexers 180a-180d can be selected in sequence [0, 1, 2, 3], and all input multiplexers 180a-180d receive the same row selection signal. Data is written to the first memory cell set 158 ​​and the second memory cell set 160 of the selected first memory bank 154 and the second memory bank 156.

[0085] For example, when the first memory bank 154 is selected, the xy address is located in column x = 0 and row y = 0, data 00 is provided to the external data input terminal ext-D[0] and written to memory cell 184a through input multiplexer 180a and I / O terminal 172a; data 01 is provided to the external data input terminal ext-D[1] and written to memory cell 184b through input multiplexer 180b and I / O terminal 172b; data 02 is provided to the external data input terminal ext-D[2] and written to memory cell 184c through input multiplexer 180c and I / O terminal 172c; and data 03 is provided to the external data input terminal ext-D[3] and written to memory cell 184d through input multiplexer 180d and I / O terminal 172d. This operation can continue for columns x=0 and the remaining rows y=1, 2, and 3 of the first memory bank 154, as well as for any number of columns and rows (e.g., column x = 1, row y = 0, 1, 2, and 3). Furthermore, the second memory bank 156 can be written to in the same manner. In some embodiments, the first memory bank 154 and the second memory bank 156 are written to in a manner similar to the memory array 102 shown in Figure 7.

[0086] When the control circuit 150 performs a "normal" columnar access operation on the memory array 152, data can be read from the memory array 152 through the columnar data. Column selection circuits (e.g., column selection circuit 56) and row selection circuits (e.g., row selection circuit 58) decode the address and select one of the first memory bank 154 and the second memory bank 156 to be read, as well as the column and row of the first memory cell set 158 ​​and the second memory cell set 160. In some embodiments, the row selection circuit includes one or more row decoder circuits (e.g., row decoder circuit 60) for selecting the input terminals of the first multiplexer sets 170a-170d of the first memory bank 154, the input terminals of the third multiplexer sets 176a-176d of the second memory bank 156, and the input terminals of the multiplexer output multiplexers 182a-182d to read data from the memory array 152.

[0087] In order to read data from the first memory bank 154 during "normal" columnar access operations, the first multiplexer set 170a-170d receives data from the first memory bank 154 and transmits the data to multiple I / O terminals 172a-172d and internal output terminals int-Q[0], int-Q[1], int-Q[2] and int-Q[3]. Next, the data is transmitted to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and ext-Q[3] through multiple output multiplexers 182a-182d. Output multiplexer 182a receives internal output data int-Q[0,1,2,3], output multiplexer 182b receives internal output data int-Q[1,0,3,2], output multiplexer 182c receives internal output data int-Q[2,3,0,1], and output multiplexer 182d receives internal output data int-Q[3,2,1,0]. The data received at the external output terminals ext-Q[0], ext-Q[1], ext-Q[2], and ext-Q[3] are mapped to columns of the external data mapping table, one column at a time.

[0088] In order to read data from the second memory bank 156 during "normal" columnar access operations, the third multiplexer set 176a-176d receives data from the second memory bank 156 and transmits the data to multiple I / O terminals 172a-172d and internal output terminals int-Q[0], int-Q[1], int-Q[2] and int-Q[3]. Next, the data is transmitted to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and ext-Q[3] through multiple output multiplexers 182a-182d. Output multiplexer 182a receives internal output data int-Q[4,5,6,7], output multiplexer 182b receives internal output data int-Q[5,4,7,6], output multiplexer 182c receives internal output data int-Q[6,7,4,5], and output multiplexer 182d receives internal output data int-Q[7,6,5,4]. The data received at the external output terminals ext-Q[0], ext-Q[1], ext-Q[2], and ext-Q[3] are mapped to columns of the external data mapping table, and one column is mapped at a time.

[0089] During a "normal" columnar access operation, the column selection circuit selects one of the first memory bank 154 and the second memory bank 156, as well as a column (e.g., column x=0), and one of the row selection circuits or the row decoder selects a row (e.g., row y=0, 1, 2, or 3). The selected row y=0, 1, 2, or 3 can be selected from one of the four inputs of each of the first multiplexer sets 170a-170d or one of the four inputs of each of the third multiplexer sets 176a-176d, and one of the four inputs of each of the multiple output multiplexers 182a-182d. The input terminals of each of the first multiplexer sets 170a-170d can be selected sequentially [0,1,2,3], the input terminals of each of the third multiplexer sets 176a-176d can be selected sequentially [0,1,2,3], and the input terminals of each of the plurality of output multiplexer sets 182a-182d can be selected sequentially [0,1,2,3]. In some embodiments, the first multiplexer sets 170a-170d all receive the same row selection signal. In some embodiments, the third multiplexer sets 176a-176d all receive the same row selection signal. In some embodiments, the plurality of output multiplexers 182a-182d all receive the same row selection signal. In some embodiments, the first multiplexer sets 170a-170d and the plurality of output multiplexers 182a-182d receive the same row selection signal. In some embodiments, all third multiplexers 176a-176d and all output multiplexers 182a-182d receive the same column selection signal. In some embodiments, the first multiplexer set 170a-170d, the third multiplexer set 176a-176d, and the output multiplexers 182a-182d receive different row selection signals at different times.

[0090] For example, during a "normal" columnar access operation, the first memory bank 154 is selected, the xy address is located at column x = 0 and row y = 0, data 00 is read from memory cell 184a, received from multiplexer 170a, and transmitted to I / O terminal 172a (I / O[0]) and internal output terminal int-Q[0]. Data 00 is further received by output multiplexer 182a and transmitted to external output terminal ext-Q[0]. Data 01 is read from memory cell 184b, received from multiplexer 170b, and transmitted to I / O terminal 172b (I / O[1]) and internal output terminal int-Q[1]. Data 01 is further received by output multiplexer 182b and transmitted to external output terminal ext-Q[1]. Data 02 is read from memory unit 184c, received from multiplexer 170c, and transmitted to I / O terminal 172c (I / O[2]) and internal output terminal int-Q[2]. Data 02 is further received by output multiplexer 182c and transmitted to external output terminal ext-Q[2]. Data 03 is read from memory unit 184d, received from multiplexer 170d, and transmitted to I / O terminal 172d (I / O[3]) and internal output terminal int-Q[3]. Data 03 is further received from output multiplexer 182d and transmitted to external output terminal ext-Q[3]. Data received at external output terminals ext-Q[0], ext-Q[1], ext-Q[2], and ext-Q[3] are mapped to the first column of the external data mapping table.

[0091] This operation can continue for column x = 0 and the remaining rows y = 1, 2, and 3 of the first memory bank 154, as well as for any number of columns and rows (e.g., column x = 1 and row y = 0, 1, 2, and 3). Furthermore, in a "normal" columnar access operation, the second memory bank 156 is read out in the same manner, but the second memory bank 156 and the third multiplexer sets 176a-176d are selected. In some embodiments, the first memory bank 154 and the second memory bank 156 are read out in a "normal" columnar access operation, similar to the memory array 102 shown in Figure 9.

[0092] Figure 13 is a schematic diagram of an external data mapping table 186 for data read from the first memory bank 154 and the second memory bank 156 through a "transpose" row access operation according to an embodiment of this disclosure.

[0093] Referring to Figures 12 and 13, when the control circuit 150 performs a "transpose" columnar access operation on the memory array 152, data can be read from the memory array 152 in row-wise order. Column selection circuits (e.g., column selection circuit 56) and row selection circuits (e.g., row selection circuit 58) decode the address and select one of the first memory bank 154 and the second memory bank 156 to be read, as well as the column and row of the first memory cell set 158 ​​and the second memory cell set 160. In some embodiments, the row selection circuit includes one or more row decoder circuits (e.g., row decoder circuit 60) for selecting the input terminals of the second multiplexer set 174a-174d of the first memory bank 154, the input terminals of the fourth multiplexer set 178a-178d of the second memory bank 156, and the input terminals of the multiplexer output multiplexers 182a-182d to read data from the memory array 152.

[0094] For the first memory bank 154, the control circuit 150 includes a second multiplexer set 174a-174d, which receives data from the first memory bank 154 and transmits the data to multiple I / O terminals 172a-172d. Each of the second multiplexer sets 174a-174d is a 4-to-1 multiplexer, having 4 input terminals, 1 output terminal, and a control input terminal (not shown) for selecting which input data is provided to the multiplexer output terminal. The input terminals of multiplexer 174a can be selected sequentially in the order [0, 1, 2, 3], the input terminals of multiplexer 174b can be selected sequentially in the order [1, 0, 3, 2], the input terminals of multiplexer 174c can be selected sequentially in the order [2, 3, 0, 1], and the input terminals of multiplexer 174d can be selected sequentially in the order [3, 2, 1, 0]. In some embodiments, the second multiplexer sets 174a-174d are similar to the second multiplexer set 66 shown in Figure 3. In other embodiments, the second multiplexer sets 174a-174d each have more than four inputs (e.g., eight or sixteen) and one output.

[0095] For the second memory bank 156, the control circuit 150 includes a fourth multiplexer set 178a-178d, which receives data from the second memory bank 156 and transmits the data to multiple I / O terminals 172a-172d. Each of the fourth multiplexer sets 178a-178d is a 4-to-1 multiplexer, having 4 input terminals, 1 output terminal, and a control input terminal (not shown) for selecting which input data is provided to the multiplexer output terminal. The input terminals of multiplexer 178a can be selected sequentially [4,5,6,7], the input terminals of multiplexer 178b can be selected sequentially [5,4,7,6], the input terminals of multiplexer 178c can be selected sequentially [6,7,4,5], and the input terminals of multiplexer 178d can be selected sequentially [7,6,5,4]. In some embodiments, the fourth multiplexer sets 178a-178d are similar to the second multiplexer set 66 shown in Figure 3. In other embodiments, the fourth multiplexer sets 178a-178d each have more than four inputs (e.g., eight or sixteen) and one output.

[0096] The control circuit 150 further includes a plurality of output multiplexers 182a-182d, which receive data from a plurality of I / O terminals 172a-172d and an internal output terminal int-Q. The plurality of output multiplexers 182a-182d transmit data to an external output terminal ext-Q. Each of the plurality of output multiplexers 182a-182d is a 4-to-1 multiplexer, having 4 input terminals, 1 output terminal, and a control input terminal (not shown) for selecting which input terminal data is provided to the multiplexer output terminal. The input terminals of each of the plurality of output multiplexers 182a-182d can be selected in sequence [0, 1, 2, 3]. In some embodiments, the plurality of output multiplexers 182a-182d are similar to the output multiplexer 70 shown in Figure 3. In other embodiments, the multiple output multiplexers 182a-182d each have more than four inputs (e.g., eight or sixteen) and one output.

[0097] In order to read data from the first memory bank 154 during the "transpose" row access operation, the second multiplexer set 174a-174d receives data from the first memory bank 154 and transmits the data to multiple I / O terminals 172a-172d and internal output terminals int-Q[0], int-Q[1], int-Q[2] and int-Q[3]. Next, the data is transmitted to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and ext-Q[3] through multiple output multiplexers 182a-182d. Output multiplexer 182a receives internal output data int-Q[0,1,2,3], output multiplexer 182b receives internal output data int-Q[1,0,3,2], output multiplexer 182c receives internal output data int-Q[2,3,0,1], and output multiplexer 182d receives internal output data int-Q[3,2,1,0]. The data received at the external output terminals ext-Q[0], ext-Q[1], ext-Q[2], and ext-Q[3] are mapped to rows in the external data mapping table 186, one row at a time.

[0098] In order to read data from the second memory bank 156 during the "transpose" row access operation, the fourth multiplexer set 178a-178d receives data from the second memory bank 156 and transmits the data to multiple I / O terminals 172a-172d and internal output terminals int-Q[0], int-Q[1], int-Q[2] and int-Q[3]. Next, the data is transmitted to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and ext-Q[3] through multiple output multiplexers 182a-182d. Output multiplexer 182a receives internal output data int-Q[4,5,6,7], output multiplexer 182b receives internal output data int-Q[5,4,7,6], output multiplexer 182c receives internal output data int-Q[6,7,4,5], and output multiplexer 182d receives internal output data int-Q[7,6,5,4]. The data received at the external output terminals ext-Q[0], ext-Q[1], ext-Q[2], and ext-Q[3] are mapped to rows in the external data mapping table 186, one row at a time.

[0099] During a "transpose" row access operation, the column selection circuit selects one of the first memory bank 154 and the second memory bank 156, as well as a column (e.g., column x = 0), and one of the row selection circuits or the row decoder selects a row (e.g., row y = 0, 1, 2, or 3). If the first memory bank 154 is selected, the selected row y = 0, 1, 2, or 3 can be selected from one of the four inputs of each of the second multiplexer sets 174a-174d or one of the four inputs of each of the second multiplexer sets 174a-174d. The input terminals of multiplexer 174a can be selected sequentially [0, 1, 2, 3], the input terminals of multiplexer 174b can be selected sequentially [1, 0, 3, 2], the input terminals of multiplexer 174c can be selected sequentially [2, 3, 0, 1], and the input terminals of multiplexer 174d can be selected sequentially [3, 2, 1, 0]. Additionally, the input terminals of each of the multiple output multiplexers 182a-182d can be selected sequentially [0, 1, 2, 3].

[0100] If the second memory bank 156 is selected, the selected row of y = 0, 1, 2, or 3 selects one of the four input terminals of each of the fourth multiplexer sets 178a-178d. The input terminals of multiplexer 178a can be selected in the order [4, 5, 6, 7], the input terminals of multiplexer 178b can be selected in the order [5, 4, 7, 6], the input terminals of multiplexer 178c can be selected in the order [6, 7, 4, 5], and the input terminals of multiplexer 178d can be selected in the order [7, 6, 5, 4]. In addition, the input terminals of each of the multiple output multiplexers 182a-182d can be selected in the order [0, 1, 2, 3].

[0101] In some embodiments, the second multiplexer sets 174a-174d all receive the same row selection signal. In some embodiments, the fourth multiplexer sets 178a-178d all receive the same row selection signal. In some embodiments, multiple output multiplexers 182a-182d all receive the same row selection signal. In some embodiments, the second multiplexer sets 174a-174d and multiple output multiplexers 182a-182d all receive the same row selection signal. In some embodiments, the fourth multiplexer sets 178a-178d and multiple output multiplexers 182a-182d all receive the same row selection signal. In some embodiments, the second multiplexer sets 174a-174d, the fourth multiplexer sets 178a-178d, and the multiple output multiplexers 182a-182d receive different row selection signals at different times.

[0102] For example, referring to Figures 12 and 13, during a "transpose" row access operation, the first memory bank 154 is selected, the xy address is located at column x = 0 and row y = 0, data 00 is read from memory cell 184a, received from multiplexer 174a, and transmitted to I / O terminal 172a (I / O[0]) and internal output terminal int-Q[0]. Data 00 is further received by output multiplexer 182a and transmitted to external output terminal ext-Q[0], and corresponds to the first row of external data mapping table 186 in Figure 13. Data 10 is read from memory cell 188b, received from multiplexer 174b, and transmitted to I / O terminal 172b (I / O[1]) and internal output terminal int-Q[1]. Data 10 is further received by output multiplexer 182b and transmitted to external output terminal ext-Q[1], and corresponds to the first row of external data mapping table 186 in Figure 13. Data 20 is read from memory unit 190c, received from multiplexer 174c, and transmitted to I / O terminal 172c (I / O[2]) and internal output terminal int-Q[2]. Data 20 is further received by output multiplexer 182c and transmitted to external output terminal ext-Q[2], and corresponds to the first row of external data mapping table 186 in Figure 13. Data 30 is read from memory unit 190d, received from multiplexer 174d, and transmitted to I / O terminal 172d (I / O[3]) and internal output terminal int-Q[3]. Data 30 is further received by output multiplexer 182d and transmitted to external output terminal ext-Q[3], and corresponds to the first row of external data mapping table 186 in Figure 13. Therefore, data can be transposed from the first memory bank 154 to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and the first row of data in external data mapping table 186.

[0103] This operation can continue for column x=0 and the remaining rows y=1, 2, and 3 of the first memory bank 154, as well as for any number of columns and rows (e.g., column x=1, row y=0, 1, 2, and 3). Furthermore, in the "transpose" row access operation, the second memory bank 156 is read in the same manner, but the second memory bank 156 and the fourth multiplexer sets 178a-178d are selected. In some embodiments, the first memory bank 154 and the second memory bank 156 are read in the "transpose" row access operation, similar to the memory array 102 shown in Figure 10.

[0104] In order to continue to correspond to the first row of data in the external data mapping table 186 during the "transpose" row access operation, the second memory bank 156 is selected, the xy address is located in column x = 0 and row y = 0, data 40 is read from memory cell 192a, received from multiplexer 178a, and transmitted to I / O terminal 172a (I / O[0]) and internal output terminal int-Q[0]. Data 40 is further received by output multiplexer 182a, transmitted to external output terminal ext-Q[0], and corresponded to the first row of external data mapping table 186 in Figure 13. Data 50 is read from memory cell 194b, received from multiplexer 178b, and transmitted to I / O terminal 172b (I / O[1]) and internal output terminal int-Q[1]. Data 50 is further received by output multiplexer 182b, transmitted to external output terminal ext-Q[1], and corresponds to the first row of external data mapping table 186 in Figure 13. Data 60 is read from memory unit 196c, received from multiplexer 178c, and transmitted to I / O terminal 172c (I / O[2]) and internal output terminal int-Q[2]. Data 60 is further received by output multiplexer 182c, transmitted to external output terminal ext-Q[2], and corresponds to the first row of external data mapping table 186 in Figure 13. Data 70 is read from memory unit 198d, received from multiplexer 178d, and transmitted to I / O terminal 172d (I / O[3]) and internal output terminal int-Q[3]. Data 70 is further received by output multiplexer 182d and transmitted to external output terminal ext-Q[3], and corresponds to the first row of external data mapping table 186 in Figure 13. Therefore, data can be transferred from the second memory bank 156 of memory array 102 to external output terminals ext-Q[0], ext-Q[1], ext-Q[2] and the first row of data in external data mapping table 186.

[0105] This operation can continue for column x=0, the remaining rows y=1, 2, and 3 in the second memory bank 156, and for any number of columns and rows (e.g., column x = 1, row y = 0, 1, 2, and 3). Thus, the user can eventually access the data rows in the external data corresponding table 186, which contains multiple rows with column offsets between them.

[0106] Figure 14 is a flowchart of a method for operating a memory device according to an embodiment of this disclosure. In step 200, the method includes storing a plurality of data in a plurality of memory cells of a memory array. In some embodiments, the memory cells are similar to memory cell 104 shown in Figure 5. In some embodiments, the memory cells are similar to a first memory cell set 158 ​​and a second memory cell set 160 shown in Figure 12. In some embodiments, the memory array is similar to memory array 102 shown in Figure 5. In some embodiments, the memory array is similar to memory array 152 shown in Figure 12.

[0107] In step 202, the method includes: reading the plurality of data from the plurality of memory cells through a plurality of read circuits. In some embodiments, the read circuits are similar to the read circuit 34 shown in Figures 1 and 2.

[0108] In step 204, the method includes selecting a first multiplexer set or a second multiplexer set. In some embodiments, the first plurality of multiplexers are similar to the first multiplexer 106a-106d shown in FIG. 5. In some embodiments, the first multiplexer set is similar to the first multiplexer set 170a-170d shown in FIG. 12. In some embodiments, the first multiplexer set is similar to the third multiplexer set 176a-176d shown in FIG. 12. In some embodiments, the second multiplexer set is similar to the second multiplexer set 110a-110d shown in FIG. 5. In some embodiments, the second multiplexer set is similar to the second multiplexer set 174a-174d shown in FIG. 12. In some embodiments, the second multiplexer set is similar to the fourth multiplexer set 178a-178d shown in FIG. 12.

[0109] In step 206, the method includes: if a first multiplexer set is selected, retrieving the plurality of data from the plurality of memory units through the first multiplexer set; and in step 208, transmitting the plurality of data to the plurality of I / O terminals in a first data sequence through the first multiplexer set.

[0110] In some embodiments, the method further includes retrieving the plurality of data from the plurality of memory cells through a first multiplexer set, and transmitting the plurality of data to the plurality of I / O terminals in a first data sequence order through the first multiplexer set. The method further includes: retrieving the plurality of data from the plurality of memory cells in the first data sequence order through a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer; wherein the first multiplexer has four input terminals selectively connected to the memory array and an output terminal selectively connected to the first I / O terminal; the second multiplexer has four input terminals selectively connected to the memory array and an output terminal selectively connected to the second I / O terminal; the third multiplexer has four input terminals selectively connected to the memory array and an output terminal selectively connected to the third I / O terminal; and the fourth multiplexer has four input terminals selectively connected to the memory array and an output terminal selectively connected to the fourth I / O terminal; and transmitting data in the first data sequence order to the first I / O terminal, the second I / O terminal, the third I / O terminal, and the fourth I / O terminal through the first multiplexer set.

[0111] In step 210, the method includes: if a second multiplexer set is selected, retrieving the plurality of data from the plurality of memory cells through the second multiplexer set; and in step 212, transmitting the plurality of data to the plurality of I / O terminals through the second multiplexer set in the order of second data rows transposed from the first data column order.

[0112] In some embodiments, the method further includes retrieving the plurality of data from the plurality of memory cells through a second multiplexer set and transmitting the plurality of data to the plurality of I / O terminals in a second data row order through the second multiplexer set; wherein the fifth multiplexer has four input terminals selectively connected to the memory array and an output terminal selectively connected to the first I / O terminal; the sixth multiplexer has four input terminals selectively connected to the memory array and an output terminal selectively connected to the second I / O terminal; the seventh multiplexer has four input terminals selectively connected to the memory array and an output terminal selectively connected to the third I / O terminal; and the eighth multiplexer has four input terminals selectively connected to the memory array and an output terminal selectively connected to the fourth I / O terminal; and transmitting the data to the fifth I / O terminal, the sixth I / O terminal, the seventh I / O terminal, and the eighth I / O terminal in a second data row order through the second multiplexer set.

[0113] In some embodiments, the method includes: retrieving the plurality of data from a first memory cell library via a first multiplexer set in a first data column sequence, and retrieving the plurality of data from the first memory cell library via a second multiplexer set in a second data row sequence.

[0114] In some embodiments, the method includes: retrieving the plurality of data from a second memory cell library via a third multiplexer set in a first data column sequence, and retrieving the plurality of data from a second memory cell library via a fourth multiplexer set in a second data row sequence.

[0115] Figure 15 is a block diagram of a computer system 220 for providing electronic devices, semiconductor devices, and methods according to an embodiment of this disclosure. Part or all of the design, layout, and fabrication of the semiconductor device (also referred to as a semiconductor circuit) can be performed by or with the assistance of the computer system 220. Furthermore, part or all of the design, layout, and fabrication of the electronic device can be performed by or with the assistance of the computer system 220. In some embodiments, the computer system 220 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an integrated circuit (IC).

[0116] In some embodiments, the computer system 220 is a general-purpose computing device including a processor 222 and a non-transitory computer-readable storage medium 224. The computer-readable storage medium 224 may be encoded by storing computer program code (e.g., executable instructions 226). The execution of the instructions 226 by the processor 222 provides design tools (at least partially) to implement some or all of the functions of the computer system 220, such as pre-placement simulation, post-placement simulation, routing, rerouting, and final routing. Furthermore, it includes manufacturing tools 228 to further place and physically implement the design and fabrication of the semiconductor device. In some embodiments, the execution of the instructions 226 by the processor 222 provides design tools (at least partially) to implement some or all of the functions of the computer system 220. In some embodiments, the computer system 220 includes a commercial router. In some embodiments, the computer system 220 includes an automatic place and route (APR) system.

[0117] Processor 222 is electrically coupled to computer-readable and storage medium 224 via bus 230 and to I / O interface 232 via bus 230. Network interface 234 is also electrically connected to processor 222 via bus 230. Network interface 234 is connected to network 236, allowing processor 222 and computer-readable and storage medium 224 to connect to external components via network 236. Processor 222 is used to execute computer program code or instructions 226 encoded in computer-readable and storage medium 224 to cause computer system 220 to perform some or all of the functions of computer system 220, such as providing the semiconductor devices and methods of this disclosure and other functions of computer system 220. In some embodiments, processor 222 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0118] In some embodiments, the computer-readable and storage medium 224 may be an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system, device, or equipment. For example, the computer-readable and storage medium 224 may include semiconductor or solid-state memory, magnetic tape, portable computer disk drive, random access memory (RAM), read-only memory (ROM), or hard magnetic memory. In some embodiments using optical discs, the computer-readable and storage medium 224 may include optical disc read-only memory (CD-ROM), optical disc read / write memory (CD-R / W), and / or digital video disc (DVD).

[0119] In some embodiments, the computer-readable and storage medium 224 may store computer program code or instructions 226, which can be used to cause the computer system 220 to perform some or all of the functions of the computer system 220. In some embodiments, the computer-readable and storage medium 224 may also store information that facilitates the performance of some or all of the functions of the computer system 220. In some embodiments, the computer-readable and storage medium 224 may store a database 238, which includes one or more of a component library, a digital circuit unit library, and a database.

[0120] The computer system 220 includes an I / O interface 232 coupled to external circuitry. In some embodiments, the I / O interface 232 includes a keyboard, numeric keypad, mouse, trackball, trackpad, touchscreen, and / or cursor keys for transmitting information and commands to the processor 222.

[0121] Network interface 234 is coupled to processor 222 and allows computer system 220 to communicate with network 236, which can be connected to one or more other computer systems. Network interface 234 may include: a wireless network interface, such as Bluetooth, wireless local area network, WiMAX, Universal Packet Radio Service, Wideband Code Division Multiple Access (WCDMA), etc.; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In some embodiments, some or all of the functions of computer system 220 may be performed in two or more systems similar to computer system 220.

[0122] The computer system 220 receives information through the I / O interface 232. The information received through the I / O interface 232 may include one or more instructions, data, design rules, component and unit libraries, and / or other parameters processed by the processor 222. This information may be transmitted to the processor 222 via the bus 230. Furthermore, the computer system 220 receives information related to the user interface (UI) through the I / O interface 232. This UI information may be stored as UI 240 on a computer-readable storage medium 224.

[0123] In some embodiments, some or all of the functions of the computer system 220 are implemented through a standalone software application executed by a processor. In some embodiments, some or all of the functions of the computer system 220 are implemented in a software application that is part of an additional software application. In some embodiments, some or all of the functions of the computer system 220 are used as a plug-in to a software application. In some embodiments, at least one function of the computer system 220 is used as a software application that is part of an EDA tool. In some embodiments, some or all of the functions of the computer system 220 are used as a software application used by the computer system 220. In some embodiments, the layout diagram is generated using a tool such as Virtuoso obtained by CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0124] In some embodiments, routing, layout, and other processing are implemented by a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as: one or more optical discs (e.g., digital video discs or digital optical discs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, and memory cards), etc.

[0125] As described above, embodiments of the computer system 220 include manufacturing tools 228 for implementing the manufacturing process of the computer system 220. For example, based on the final layout, a photolithographic mask can be generated for manufacturing a semiconductor device using the manufacturing tools 228.

[0126] Other aspects of device fabrication are disclosed in conjunction with Figure 16. Figure 16 is a block diagram of a semiconductor device fabrication system 242 and its associated semiconductor device fabrication process according to an embodiment of this disclosure. In some embodiments, based on the layout diagram, the semiconductor device fabrication system 242 can be used to fabricate one or more semiconductor masks and / or at least one component of a semiconductor device layer.

[0127] In Figure 16, the semiconductor device manufacturing system 242 includes entities such as design room 244, mask room 246, and semiconductor device manufacturing plant (Fab) 248, which interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of semiconductor devices (such as the semiconductor devices described herein). The entities in the semiconductor device manufacturing system 242 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as intranets and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 244, mask room 246, and semiconductor device manufacturing plant 248 may be owned by a single larger company. In some embodiments, two or more of the design room 244, mask room 246, and semiconductor device manufacturing plant 248 coexist in a common facility and use common resources.

[0128] Design room (or design team) 244 may generate a semiconductor device design layout 250. The semiconductor device design layout 250 contains various geometric patterns, or a semiconductor device layout designed for a semiconductor device. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the semiconductor structure to be manufactured. The layers are combined to form various semiconductor device characteristics. For example, a portion of the semiconductor device design layout 250 includes various semiconductor device features, such as diagonal vias, active regions or regions, gate electrodes, source electrodes, drain electrodes, metal lines, local vias, and openings for bonding pads formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Design room 244 implements a design process to generate the semiconductor device design layout 250. The semiconductor device design layout 250 is presented in one or more data files containing geometric pattern information. For example, the semiconductor device design layout 250 may be expressed in GDSII file format or DFII file format. In some embodiments, the design flow may include one or more of the following: analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design (including power via design), power voltage rail design, and reference voltage rail design.

[0129] Mask chamber 246 includes mask data preparation 252 and mask manufacturing 254. Mask chamber 246 uses semiconductor device design layout 250 to manufacture one or more masks 256 that will be used to manufacture layers of a semiconductor device or semiconductor structure. Mask chamber 246 performs mask data preparation 252, in which the semiconductor device design layout 250 is converted into a representative data file (RDF). Mask data preparation 252 provides the RDF to mask manufacturing 254. Mask manufacturing 254 includes a mask writer that converts the RDF into an image on a substrate, such as a mask (mask) 256 or a semiconductor wafer 258. The semiconductor device design layout 250 is manipulated by mask data preparation 252 to conform to the characteristics of the mask writer and / or the standards of the semiconductor device manufacturer 248. In Figure 16, mask data preparation 252 and mask manufacturing 254 are shown as separate components. In some embodiments, mask data preparation 252 and mask manufacturing 254 may be collectively referred to as mask data preparation.

[0130] In some embodiments, mask data preparation 252 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC can adjust the semiconductor device design layout 250. In some embodiments, mask data preparation 252 includes additional resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masking, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0131] In some embodiments, mask data preparation 252 includes a mask rule checker (MRC) that checks the semiconductor device design layout 250, which has undergone OPC processing, using a set of mask creation rules. These mask creation rules include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC may modify the semiconductor device design layout 250 to compensate for constraints during mask manufacturing 254, and may revert partial modifications performed by OPC to satisfy the mask creation rules.

[0132] In some embodiments, mask data preparation 252 includes lithography process checking (LPC) for simulation, which can be handled by a procedure of semiconductor device manufacturing plant 248. The LPC can simulate this procedure based on semiconductor device design layout 250 to create a simulated manufacturing apparatus. Processing parameters in the LPC simulation can include parameters associated with various processes in the semiconductor device manufacturing cycle, parameters related to the tools used to manufacture the semiconductor device, and / or other aspects of the manufacturing process. The LPC can consider various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, or combinations thereof. In some embodiments, after creating a simulated manufacturing apparatus via LPC, if the simulated apparatus is not close enough in shape to meet design rules, OPC and / or MRC can be repeated to further refine the semiconductor device design layout 250.

[0133] For clarity, the mask data preparation 252 described above has been simplified. In some embodiments, mask data preparation 252 includes additional features such as logic operations (LOPs) to modify the semiconductor device design layout 250 according to manufacturing rules. Furthermore, the procedures applied to the semiconductor device design layout 250 during mask data preparation 252 can be executed in various different sequences.

[0134] During the mask data preparation 252 and mask manufacturing 254, a mask 256 or a set of masks 256 may be manufactured based on the modified semiconductor device design layout 250. In some embodiments, mask manufacturing 254 may include performing one or more lithographic exposures based on the semiconductor device design layout 250. In some embodiments, based on the modified semiconductor device design layout 250, a pattern may be formed on the mask (photomask or screen) 256 using an electron beam or a combination of electron beams. The mask 256 may be formed using various techniques. In some embodiments, the mask 256 is formed using binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) is used to expose an image-sensitive material layer, such as a photoresist, coated on the wafer, and this radiation beam is blocked by the opaque areas but can penetrate the transparent areas. In one example, a binary mask version of mask 256 comprises a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 256 may be formed using phase shift technology. In a phase shift mask (PSM) version of mask 256, various features in the pattern formed on the phase shift mask may have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask may be attenuated PSM or alternating PSM. The mask produced by mask fabrication 254 can be used in a variety of processes. For example, such a mask may be used in an ion implantation process to form various doped regions in a semiconductor wafer 258, in an etching process to form various etched regions in a semiconductor wafer 258, and / or in other suitable processes.

[0135] Semiconductor device manufacturing plant 248 includes wafer manufacturing plant 260. Semiconductor device manufacturing plant 248 may be a semiconductor component manufacturing enterprise, which includes one or more manufacturing facilities for manufacturing various different semiconductor device products. In some embodiments, semiconductor device manufacturing plant 248 may be a semiconductor manufacturing plant. For example, there may be manufacturing facilities for manufacturing front end of line (FEOL) for multiple semiconductor device products, a second manufacturing facility for manufacturing BEOL for interconnect and packaging of semiconductor device products, and a third manufacturing facility for providing other services to the manufacturing plant business.

[0136] Semiconductor device manufacturer 248 uses a mask 256 manufactured by mask chamber 246 to manufacture the semiconductor structure or semiconductor device 262 of this disclosure. Therefore, semiconductor device manufacturer 248 uses semiconductor device design layout 250 at least indirectly to manufacture the semiconductor structure or semiconductor device 262 of this disclosure. Furthermore, semiconductor wafer 258 includes a silicon substrate or other suitable substrate on which a material layer is formed; and semiconductor wafer 258 also includes one or more of various doped regions, dielectric properties, multilayer interconnects, etc. (formed in subsequent manufacturing steps). In some embodiments, semiconductor wafer 258 is manufactured by semiconductor device manufacturer 248 using mask 256 to form the semiconductor device 262 of this disclosure. In some embodiments, semiconductor device manufacturing includes performing one or more lithography exposures at least indirectly based on semiconductor device design layout 250.

[0137] Embodiments of this disclosure provide a storage device for reading data from a memory array using "normal" columnar access operations and "transposed" row-based access operations. Embodiments of this disclosure include a first set of multiplexers and a second set of multiplexers. The first set of multiplexers retrieves data from memory cells and transmits the data to multiple I / O terminals in a first data column order. The second set of multiplexers retrieves data from memory cells and transmits the data to multiple I / O terminals in a second data row order transposed from the first data column order.

[0138] Embodiments of this disclosure further provide a method for operating a memory device, the method comprising: storing a plurality of data in a plurality of memory cells of a memory array; reading the plurality of data from the memory cells through a plurality of read circuits; and selecting a first multiplexer set or a second multiplexer set. If the first multiplexer set is selected, the method comprises retrieving data from the plurality of memory cells and transmitting the data to a plurality of I / O terminals in a first data column order. If the second multiplexer set is selected, the method comprises retrieving data from the plurality of memory cells and transmitting the data to the plurality of I / O terminals in a second data row order transposed from the first data column order.

[0139] The advantages of the above embodiments of this disclosure include the ability to rearrange data through a memory device without the need for additional buffers or macros, the ability of the memory device to adapt to different matrix calculations, such as calculations for AI applications, and the advantages of the above embodiments of this disclosure such as reduced power consumption, reduced latency and reduced area or size of the memory device.

[0140] In some embodiments, an apparatus includes a memory array, read circuitry, and a plurality of I / O terminals. The memory array is used to store data in memory cells. The read circuitry is used to read data from the memory cells. A first multiplexer set is used to retrieve data from the plurality of memory cells and transmit the data to the plurality of I / O terminals in a first data column order. A second multiplexer set is used to retrieve data from the plurality of memory cells and transmit the data to the plurality of I / O terminals in a second data row order transposed from the first data column order.

[0141] In other embodiments, an apparatus includes a memory array, a read circuit, and a plurality of I / O terminals. The memory array is used to store data in memory cells. The read circuit is used to read data from the memory cells. The plurality of I / O terminals includes a first I / O terminal and a second I / O terminal. A first multiplexer set includes a first multiplexer and a second multiplexer, the first multiplexer having a first input terminal selectively connected to the memory array and a first output terminal selectively connected to the first I / O terminal, and the second multiplexer having a second input terminal selectively connected to the memory array and a second output terminal selectively connected to the second I / O terminal. The first and second multiplexers are used for transmitting data in a plurality of data columns to the first I / O terminal and the second I / O terminal. The second multiplexer set includes a third multiplexer and a fourth multiplexer, the third multiplexer having a third input terminal selectively connected to the memory array and a third output terminal selectively connected to the first I / O terminal, and the fourth multiplexer having a fourth input terminal selectively connected to the memory array and a fourth output terminal selectively connected to the second I / O terminal. The third and fourth multiplexers are used to transmit multiple data rows to the first and second I / O terminals, wherein the data in the data rows is a transpose of the data in the data columns.

[0142] In other embodiments, a method of operating a memory device includes: storing a plurality of data in a plurality of memory cells of a memory array; reading the plurality of data from the memory cells through a plurality of read circuits; and selecting a first multiplexer set or a second multiplexer set. If the first multiplexer set is selected, the method includes retrieving data from the plurality of memory cells and transmitting the data to a plurality of I / O terminals in a first data column order. If the second multiplexer set is selected, the method includes retrieving data from the plurality of memory cells and transmitting the data to the plurality of I / O terminals in a second data row order transposed from the first data column order.

[0143] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" as used in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to".

[0144] In addition, unless otherwise specified in the specification, any singular case term also includes the meaning of the plural case.

[0145] The above are merely preferred embodiments of this disclosure. Various modifications and equivalent changes can be made to this disclosure without departing from its scope or spirit. In summary, all modifications and equivalent changes to this disclosure made within the scope of the following claims are within the scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] This disclosure document can be best understood through the following technical content by interpreting the accompanying drawings. It should be noted that, in accordance with common practice in the art, the elements in the drawings of this disclosure document are not drawn to scale. To clearly reveal the technical features of this disclosure document, the dimensions of the features in the drawings may be enlarged or reduced as appropriate. Furthermore, the drawings are examples of embodiments of this disclosure document and are not intended to limit the scope of this disclosure document. Figure 1 is a schematic diagram of a memory device according to an embodiment of this disclosure document for accessing data from a memory array in columnar and rowar formats. Figure 2 is a schematic diagram of an SRAM memory array electrically coupled to a memory device circuit according to an embodiment of this disclosure document. Figure 3 is a schematic diagram of a memory device according to an embodiment of this disclosure document, wherein the memory device includes a control circuit for performing columnar and rowar data access operations on the memory array in the memory device. Figure 4 is a schematic diagram of the SRAM cells used in the memory devices of Figures 1 and 3 according to an embodiment of this disclosure document. Figure 5 is a schematic diagram of a control circuit connected to a memory array according to an embodiment of this disclosure. Figure 6 is a schematic diagram of a multiplexer and I / O terminals according to an embodiment of this disclosure. Figure 7 is a schematic diagram of a control circuit performing a write operation on the memory array according to an embodiment of this disclosure. Figure 8 is a schematic diagram of an external data mapping table for writing data to the memory array according to an embodiment of this disclosure. Figure 9 is a schematic diagram of a control circuit performing a "normal" columnar access operation on the memory array according to an embodiment of this disclosure. Figure 10 is a schematic diagram of a control circuit performing a "transposed" rowar access operation on the memory array according to an embodiment of this disclosure. Figure 11 is a schematic diagram of an external data mapping table for reading data from the memory array according to an embodiment of this disclosure. Figure 12 is a schematic diagram of a control circuit connected to a memory array comprising a first memory bank (bank 0) and a second memory bank (bank 1) according to an embodiment of this disclosure. Figure 13 is a schematic diagram of an external data mapping table for data read from a first memory bank and a second memory bank through a "transpose" row-oriented access operation according to an embodiment of this disclosure. Figure 14 is a flowchart of a method for operating a memory device according to an embodiment of this disclosure. Figure 15 is a block diagram of a computer system for providing an electronic device, a semiconductor device, and a method according to an embodiment of this disclosure. Figure 16 is a block diagram of a semiconductor device manufacturing system and a related semiconductor device manufacturing process according to an embodiment of this disclosure.

Claims

1. A memory device comprising: a memory array for storing a plurality of data in a plurality of memory cells; a plurality of input / output (I / O) terminals; a first multiplexer set for retrieving the data from the memory cells and transmitting the data to the I / O terminals in a first data column order in the memory array; a second multiplexer set for retrieving the data from the memory cells and transmitting the data to the I / O terminals in a second data row order in the memory array transposed from the first data column order; and a plurality of input multiplexers for receiving external data and selectively providing an input multiplexer output data to the I / O terminals.

2. The memory device as claimed in claim 1, wherein the I / O terminals include a first I / O terminal, a second I / O terminal, a third I / O terminal, and a fourth I / O terminal.

3. The memory device as claimed in claim 2, wherein the first multiplexer set comprises: a first multiplexer having a plurality of inputs selectively connected to the memory array and an output selectively connected to the first I / O; and a second multiplexer having a plurality of inputs selectively connected to the memory array and an output selectively connected to the second I / O. A third multiplexer has multiple inputs selectively connected to the memory array and an output selectively connected to the third I / O terminal; And a fourth multiplexer having a plurality of inputs selectively connected to the memory array and an output selectively connected to the fourth I / O.

4. The memory device as claimed in claim 3, wherein the second multiplexer set includes: a fifth multiplexer having a plurality of inputs selectively connected to the memory array and an output selectively connected to the first I / O terminal; A sixth multiplexer has multiple inputs selectively connected to the memory array and an output selectively connected to the second I / O terminal; A seventh multiplexer has multiple inputs selectively connected to the memory array and an output selectively connected to the third I / O terminal; And an eighth multiplexer having a plurality of inputs selectively connected to the memory array and an output selectively connected to the fourth I / O terminal.

5. The memory device as claimed in claim 1, wherein the memory array comprises at least two memory cell libraries, wherein: A first memory cell library is selectively connected to the first multiplexer set and the second multiplexer set; and a second memory cell library is selectively connected to a third multiplexer set and a fourth multiplexer set.

6. The memory device as described in claim 5, wherein: The first multiplexer set is used to retrieve the data from the first memory cell library in the order of the first data column and to transmit the data to the I / O terminals in the order of the first data column; and the second multiplexer set is used to retrieve the data from the first memory cell library in the order of the second data row and to transmit the data to the I / O terminals in the order of the second data row.

7. The memory device as described in claim 5, wherein: The third multiplexer set is used to retrieve the data from the second memory cell library in the order of the first data column and to transmit the data to the I / O terminals in the order of the first data column; and the fourth multiplexer set is used to retrieve the data from the second memory cell library in the order of the second data row and to transmit the data to the I / O terminals in the order of the second data row.

8. The memory device as claimed in claim 1, wherein the memory array is a static random access memory array.

9. A memory device comprising: a memory array for storing a plurality of data in a plurality of memory cells; a plurality of read circuits for reading the data from the memory cells; a plurality of input / output (I / O) terminals, including a first I / O terminal and a second I / O terminal; a first multiplexer set including a first multiplexer and a second multiplexer, the first multiplexer having a plurality of first input terminals selectively connected to the memory array and a first output terminal selectively connected to the first I / O terminal, the second multiplexer having a plurality of second input terminals selectively connected to the memory array and a second output terminal selectively connected to the second I / O terminal, the first multiplexer and the second multiplexer being configured to transfer data of a plurality of data columns to the first I / O terminal and the second I / O terminal; and a second multiplexer set including a A third multiplexer and a fourth multiplexer, the third multiplexer having a plurality of third input terminals selectively connected to the memory array and a third output terminal selectively connected to the first I / O terminal, the fourth multiplexer having a plurality of fourth input terminals selectively connected to the memory array and a fourth output terminal selectively connected to the second I / O terminal, the third multiplexer and the fourth multiplexer being used to transmit data of a plurality of data rows to the first I / O terminal and the second I / O terminal, wherein the data of the plurality of data rows is transposed from the data of the plurality of data columns.

10. A method of operating a memory device, the method comprising: storing a plurality of data in a plurality of memory cells of a memory array; selecting a first set of multiplexers or a second set of multiplexers; wherein when the first set of multiplexers is selected: retrieving the data from the memory cells through the first set of multiplexers; and transmitting the data to a plurality of I / O terminals through the first set of multiplexers in a first data column order in the memory array; and wherein when the second set of multiplexers is selected: retrieving the data from the memory cells through the second set of multiplexers; transmitting the data to the I / O terminals through the second set of multiplexers in a second data row order in the memory array transposed from the first data column order; and receiving external data through a plurality of input multiplexers and selectively providing input multiplexer output data to the I / O terminals.

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