Display device

Abstract

One embodiment of the present invention provides a display device comprising: a first pixel disposed in a display area for displaying an image; a transmissive region disposed in the display area; and a partition wall comprising a conductive lower portion and an upper portion having an end portion protruding from the side of the lower portion, disposed in the display area. The first pixel comprises a plurality of sub-pixels surrounded by the partition wall. The transmissive region comprises a plurality of sub-regions surrounded by the partition wall and through which at least a portion of light incident upon the transmissive region is transmitted.

Description

Display device The present invention relates to a display device. In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. These display elements include a lower electrode, an organic layer covering the lower electrode, and a higher electrode covering the organic layer. A common voltage is applied to the higher electrode of each display element via wiring disposed in the display area. Furthermore, light transmittance is sometimes required in at least a portion of the display area where display elements are arranged. However, if the lower electrode or wiring is made of a light-shielding material such as metal, the light transmittance of the display device may be significantly reduced. Generally speaking, according to an embodiment, the display device includes: a first pixel disposed in a display area for displaying an image; a transmissive area disposed in the aforementioned display area; and a partition wall comprising a conductive lower portion and an upper portion having an end portion protruding from the side of the aforementioned lower portion, disposed in the aforementioned display area. The aforementioned first pixel includes a plurality of sub-pixels surrounded by the aforementioned partition wall. The aforementioned transmissive area includes a plurality of sub-regions surrounded by the aforementioned partition wall and through which at least a portion of the light incident upon the aforementioned transmissive area is transmitted. Depending on the implementation, a display device with excellent light transmittance can be provided. Several implementation forms are described with reference to the diagrams. The disclosed examples are merely one instance, and appropriate modifications that can be readily conceived by those skilled in the art to maintain the spirit of the invention are naturally included within the scope of this invention. Furthermore, to make the description clearer, the drawings may schematically show the width, thickness, shape, etc., of various parts compared to the actual form, but this is merely one example and does not limit the interpretation of the invention. Also, in this specification and the drawings, sometimes the same reference numerals are used for constituent elements that perform the same or similar functions as the constituent elements described in the previously shown drawings, and repeated detailed descriptions are appropriately omitted. Furthermore, in the diagram, the X-axis, Y-axis, and Z-axis, which are orthogonal to each other, are shown as needed for ease of understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of the plane that includes the X-direction and the Y-direction. Also, observing various elements parallel to the Z-direction is called a top view. The display devices in each embodiment are organic electroluminescent display devices with organic light-emitting diodes (OLEDs) as display elements, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle machines, tablet terminals, smartphones, mobile phone terminals, and wearable terminals. [First Embodiment] FIG1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film. In this embodiment, the shape of the substrate 10 viewed from above is rectangular. However, the shape of the substrate 10 viewed from above is not limited to a rectangle, and may be other shapes such as a square, a circle, or an oval. The display area DA has a plurality of pixels PX arranged in a matrix along the X and Y directions. Pixel PX includes a plurality of subpixels SP displaying different colors. In this embodiment, it is envisioned that pixel PX includes three subpixels SP1, SP2, and SP3 (the first to third subpixels). For example, subpixel SP1 displays green, subpixel SP2 displays blue, and subpixel SP3 displays red. However, the colors displayed by subpixels SP1, SP2, and SP3 are not limited to this example. Furthermore, pixel PX may include subpixels SP of other colors such as white, either together with or replacing any of subpixels SP1, SP2, and SP3. The display area DA includes a first area A1 and a second area A2 with higher light transmittance than the first area A1. A camera CR, for example, is disposed on the back side of the second area A2. This camera CR is capable of capturing images of objects on the display surface via the second area A2. Alternatively, other light-receiving elements, such as an illuminance sensor for detecting external light, can be disposed instead of the camera CR. Furthermore, the display area DA may include a plurality of second areas A2 facing the camera CR or the illuminance sensor. For example, the second region A2 is smaller than the first region A1. In the example of Figure 1, the second region A2 is located near the end of the display area DA and is surrounded by the first region A1. However, the arrangement of the second region A2 is not limited to this example. The second region A2 does not necessarily have to be completely surrounded by the first region A1; it can be configured with one or two sides facing the surrounding area SA. The second region A2 is, for example, a rectangle, but can be other shapes such as a circle. Figure 2 is a circuit diagram showing an example of the configuration of a pixel circuit PC that can be applied to each of the sub-pixels SP (SP1, SP2, SP3). The pixel circuit PC shown in the figure includes seven transistors TR1 to TR7 and one holding capacitor Cst. In the following description, one of the source and drain electrodes of each of transistors TR1 to TR7 is referred to as the first electrode, and the other is referred to as the second electrode. Similarly, one of the electrodes constituting the holding capacitor Cst is referred to as the first electrode, and the other is referred to as the second electrode. The first electrode of transistor TR1 is connected to node n1. The second electrode of transistor TR1 is connected to the signal line SL that supplies the image signal Sdata. The image signal Sdata is a signal written to the pixels for displaying the image. Transistor TR2 is equivalent to the driving transistor that supplies current to the light-emitting element DE contained in the sub-pixel SP. The first electrode of transistor TR2 is connected to node n1. The second electrode of transistor TR2 is connected to node n2. The first electrode of transistor TR3 is connected to node n3. The second electrode of transistor TR3 is connected to node n2. The first electrode of transistor TR4 is connected to node n2. The second electrode of transistor TR4 is connected to power line PL1, which supplies the power supply voltage VDDEL. The first electrode of transistor TR5 is connected to node n4. The second electrode of transistor TR5 is connected to node n1. The first electrode of transistor TR6 is connected to node n4. The second electrode of transistor TR6 is connected to the initialization line IL, which supplies the initialization voltage Vini. The first electrode of transistor TR7 is connected to node n2. The second electrode of transistor TR7 is connected to power line PL2, which supplies the power supply voltage VSH. The first electrode of capacitor Cst is connected to node n3. The second electrode of capacitor Cst is connected to node n4. The gate electrode of transistor TR1 is connected to scan line GL1, which supplies scan signal Sg1. The gate electrode of transistor TR3 is connected to scan line GL2, which supplies scan signal Sg2. The gate electrodes of transistors TR4, TR5, and TR6 are connected to scan line GL3, which supplies scan signal Sg3. The gate electrode of transistor TR7 is connected to scan line GL4, which supplies scan signal Sg4. The anode of display element DE is connected to node n4. The cathode of display element DE is connected to power line PL3, which supplies power voltage VSSEL. Power voltage VDDEL is equivalent to the anode voltage supplied to display element DE, and power voltage VSSEL is equivalent to the cathode voltage supplied to display element DE. Furthermore, the configuration of the pixel circuit PC is not limited to the example shown in Figure 2. For example, the pixel circuit PC may have 6 or fewer transistors or 8 or more transistors. Also, the pixel circuit PC may have a plurality of holding capacitors Cst. The number of scan lines and power lines connected to the pixel circuit PC can be increased or decreased depending on the configuration of the pixel circuit PC. Figure 3 is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3 in a pixel PX. In the example of Figure 3, subpixels SP2 and SP3 are arranged along the X direction with subpixel SP1. Furthermore, subpixels SP2 and SP3 are arranged along the Y direction. However, the layout of subpixels SP1, SP2, and SP3 is not limited to the example of Figure 3. A rib layer 5 is configured in the display area DA. Rib layer 5 has pixel apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example of Figure 3, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP1, respectively. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP2, respectively. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3, respectively. In Figure 3, the lower electrodes LE1, LE2, and LE3 are marked with diagonal lines. The portion of the lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel opening AP1 constitutes the display element DE1 of sub-pixel SP1. The portion of the lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel opening AP2 constitutes the display element DE2 of sub-pixel SP2. The portion of the lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel opening AP3 constitutes the display element DE3 of sub-pixel SP3. Display elements DE1, DE2, and DE3 may further include the cover layer described later. Rib layer 5 surrounds each of the display elements DE1, DE2, and DE3. A conductive partition wall 6 is disposed on the rib layer 5. A dotted pattern is shown for the partition wall 6 in Figure 3. The partition wall 6 overlaps the rib layer 5 in its entirety and has the same planar shape as the rib layer 5. That is, the partition wall 6 has openings in sub-pixels SP1, SP2, and SP3 respectively. From another perspective, the rib layer 5 and the partition wall 6 appear as a grid when viewed from above, surrounding each of the sub-pixels SP1, SP2, and SP3 (display elements DE1, DE2, and DE3). The partition wall 6 serves as a wiring to supply a common voltage to the upper electrodes UE1, UE2, and UE3. In the example of Figure 3, the ends of the lower electrodes LE1, LE2, and LE3 overlap with the rib layer 5 and the partition wall 6 as a whole. In another example, at least a portion of the ends of the lower electrodes LE1, LE2, and LE3 may not overlap with the partition wall 6. Figure 4 is a schematic cross-sectional view of the display panel PNL along line IV-IV in Figure 3. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits or wirings such as pixel circuits PC, scan lines GL1-GL4, signal lines SL, power lines PL1-PL3, and initialization lines IL, as shown in Figure 2. The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film to flatten the unevenness generated by the circuit layer 11. Lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. Rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by rib layer 5. Although not shown in the cross-section of Figure 4, the lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuit PC of the circuit layer 11 through contact holes provided in the organic insulating layer 12. The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. Consequently, the two ends of the upper portion 62 protrude more than the sides of the lower portion 61. The shape of this partition wall 6 is referred to as overhanging. In the example of Figure 4, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the shaft layer 64. Also, in the example of Figure 4, the two ends of the bottom layer 63 protrude from the side of the shaft layer 64. Organic layer OR1 covers lower electrode LE1 via pixel opening AP1. Upper electrode UE1 covers organic layer OR1 and faces lower electrode LE1. Organic layer OR2 covers lower electrode LE2 via pixel opening AP2. Upper electrode UE2 covers organic layer OR2 and faces lower electrode LE2. Organic layer OR3 covers lower electrode LE3 via pixel opening AP3. Upper electrode UE3 covers organic layer OR3 and faces lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower part 61 of partition wall 6. Display element DE1 includes a cover layer CP1 covering the upper electrode UE1. Display element DE2 includes a cover layer CP2 covering the upper electrode UE2. Display element DE3 includes a cover layer CP3 covering the upper electrode UE3. Cover layers CP1, CP2, and CP3 respectively function as optical adjustment layers to improve the light extraction efficiency emitted by organic layers OR1, OR2, and OR3. In the following description, the multilayer containing organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as stacked film FL1, the multilayer containing organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as stacked film FL2, and the multilayer containing organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as stacked film FL3. A portion of the laminated film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminated film FL1 surrounding the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the laminated film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminated film FL2 surrounding the partition wall 6 (the portion constituting the display element DE2). Furthermore, a portion of the laminated film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminated film FL3 surrounding the partition wall 6 (the portion constituting the display element DE3). Sealing layers SE11, SE12, and SE13 (first sealing layers) are respectively disposed in sub-pixels SP1, SP2, and SP3. Sealing layer SE11 continuously covers the overlay layer CP1 and the partition wall 6 surrounding sub-pixel SP1. Sealing layer SE12 continuously covers the overlay layer CP2 and the partition wall 6 surrounding sub-pixel SP2. Sealing layer SE13 continuously covers the overlay layer CP3 and the partition wall 6 surrounding sub-pixel SP3. In the example of Figure 4, the laminated film FL1 and sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 are separated from the laminated film FL2 and sealing layer SE12 on the partition wall 6. Furthermore, the laminated film FL1 and sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 are separated from the laminated film FL3 and sealing layer SE13 on the partition wall 6. Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1 (first resin layer). Resin layer RS1 is covered by sealing layer SE2 (second sealing layer). Sealing layer SE2 is covered by resin layer RS2 (second resin layer). Resin layers RS1, RS2, and sealing layer SE2 are continuously disposed throughout the entire display area DA, and a portion of them also extends to the peripheral area SA. A polarizing plate, touch panel, protective film, or cover glass can be further disposed on top of the resin layer RS2. This cover component can be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive). The organic insulating layer 12 is formed of organic insulating materials such as polyimide. The rib layer 5 and sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride oxide (SiON). In one example, the rib layer 5 is formed of silicon nitride oxide, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of resin materials (organic insulating materials) such as epoxy resin or acrylic resin. The lower electrodes LE1, LE2, and LE3 have: a reflective layer formed of, for example, silver, and a pair of conductive oxide layers respectively covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The upper electrodes UE1, UE2, and UE3 are formed of metallic materials such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 are equivalent to anodes, and the upper electrodes UE1, UE2, and UE3 are equivalent to cathodes. Organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including light-emitting layers. In one example, organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked along the Z direction. However, organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure containing a plurality of light-emitting layers. The capping layers CP1, CP2, and CP3 have a laminated structure formed by, for example, a plurality of overlapping transparent layers. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive indices of the sealing layers SE11, SE12, and SE13. In addition, at least one of the capping layers CP1, CP2, and CP3 may be omitted. The bottom layer 63 and the axial layer 64 of the partition wall 6 are formed of metallic materials. For example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used. Furthermore, the axial layer 64 can be formed of an insulating material. For example, the upper portion 62 of the partition wall 6 has a laminated structure consisting of a lower layer formed of a metallic material and an upper layer formed of a conductive oxide. As the metallic material forming the lower layer, materials such as titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloys, or molybdenum-niobium alloys can be used. As the conductive oxide forming the upper layer, materials such as ITO or IZO can be used. Alternatively, the upper portion 62 may have a single-layer structure of metallic material. Furthermore, the upper portion 62 may include a layer formed of an insulating material. A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the image signals of the signal line SL via the pixel circuits PC of the sub-pixels SP1, SP2, and SP3, respectively. Organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the emitting layer of organic layer OR1 emits light in the green wavelength band. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the emitting layer of organic layer OR2 emits light in the blue wavelength band. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the emitting layer of organic layer OR3 emits light in the red wavelength band. As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 can emit light of the same color (e.g., white). In this case, the display device DSP can have a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Furthermore, the display device DSP can have a layer containing quantum dots that generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3 excited by the light emitted by the light-emitting layers. Figure 5 is a schematic top view showing a portion of region A1. In this figure, rib 5, partition wall 6, and lower electrodes LE1, LE2, and LE3 are shown; other elements are omitted. Dotted patterns are added to partition wall 6, and oblique line patterns are added to lower electrodes LE1, LE2, and LE3. In region A1, a plurality of pixels PX are arranged along the X and Y directions. The layout of sub-pixels SP1, SP2, and SP3 in each pixel PX is the same as in the example of Figure 3. Thus, in region A1, rows are formed by repeated arrangement of a plurality of sub-pixels SP1 along the Y direction, and rows are formed by alternating arrangement of sub-pixels SP2 and SP3 along the Y direction. These rows are arranged alternately along the X direction. Figure 6 is a schematic top view showing a portion of region A2. As in Figure 5, rib 5, partition wall 6, and lower electrodes LE1, LE2, and LE3 are shown in Figure 6, with other elements omitted. Furthermore, dotted patterns are added to partition wall 6, and oblique line patterns are added to lower electrodes LE1, LE2, and LE3. Region A2 has a plurality of pixels PX and a plurality of transparent regions TA. The sub-pixels SP1, SP2, and SP3 in the pixels PX of Region A2 are arranged in the same way as the pixels PX of Region A1. The transmission region TA has the same size as the pixel PX. In the example of Figure 6, the pixel PX and the transmission region TA are arranged alternately along the X and Y directions. That is, the pixel PX is arranged in the second region A2 with half the density of the first region A1. Not limited to this example, a plurality of transmission regions TA can be arranged between, for example, two adjacent pixels PX along the X or Y direction. Also, a plurality of pixels PX can be arranged between two adjacent transmission regions TA along the X or Y direction. The transmission region TA comprises a plurality of sub-regions AS, each surrounded by a partition wall 6. For example, at least a portion of the light incident on the display surface of the display device DSP onto the transmission region TA is transmitted to the rear side of the display device DSP. Therefore, as described in the explanation of FIG1, the light transmittance of the second region A2 is higher than that of the first region A1. In the example of Figure 6, three sub-regions AS1, AS2, and AS3 (the first to third sub-regions) are formed in the transmission region TA. That is, the number of sub-pixels SP (SP1, SP2, SP3) in a pixel PX is the same as the number of sub-regions AS (AS1, AS2, AS3) in a transmission region TA, both being three. However, the number of sub-pixels SP in a pixel PX and the number of sub-regions AS in a transmission region TA do not necessarily have to be the same. In the example of Figure 6, subpixel SP1 has the same shape as subregion AS1, subpixel SP2 has the same shape as subregion AS2, and subpixel SP3 has the same shape as subregion AS3. The shape of the subpixel and subregion mentioned here refers to the shape of the area surrounded by partition wall 6 in top view. Furthermore, in the example of Figure 6, sub-regions AS2 and AS3 are arranged along the Y direction. Moreover, sub-regions AS2 and AS3 are each arranged with sub-region AS1 along the X direction. That is, the positional relationship between sub-regions AS1, AS2, and AS3 is the same as the positional relationship between sub-pixels SP1, SP2, and SP3. The partition wall 6 has: a first portion P1 dividing sub-pixels SP1, SP2, and SP3 within each pixel PX, and a second portion P2 dividing sub-regions AS1, AS2, and AS3 within each transmittance region TA. In the example of FIG6, the first portion P1 and the second portion P2 have the same shape. That is, the first portion P1 has: a portion extending along the Y direction between sub-pixels SP1 and SP2, SP3, and a portion extending along the X direction between sub-pixels SP2 and SP3. Similarly, the second portion P2 has: a portion extending along the Y direction between sub-regions AS1 and AS2, AS3, and a portion extending along the X direction between sub-regions AS2 and AS3. As described above, lower electrodes LE1, LE2, and LE3 are disposed in sub-pixels SP1, SP2, and SP3. Furthermore, pixel openings AP1, AP2, and AP3 that overlap with the lower electrodes LE1, LE2, and LE3 are respectively disposed in the rib layer 5. To address this, lower electrodes LE1, LE2, and LE3 are not configured in sub-regions AS1, AS2, and AS3. Furthermore, in the example of Figure 6, the rib layer 5 does not have openings in sub-regions AS1, AS2, and AS3. That is, sub-regions AS1, AS2, and AS3 overlap with the rib layer 5 as a whole. Figure 7 is another schematic top view showing a portion of the second region A2. Various wirings for driving sub-pixels SP1, SP2, and SP3 are arranged in the second region A2. These wirings include a plurality of wirings Lx extending along the X direction and a plurality of wirings Ly extending along the Y direction. Wirings Lx and Ly are both formed from the metal layer contained in circuit layer 11 shown in Figure 4. In one example, the plurality of wirings Lx includes the scan lines GL1 to GL4, power lines PL2 and PL3, and the initialization line IL shown in Figure 2. Also, the plurality of wirings Ly includes the signal line SL and the power line PL1 shown in Figure 2. In the example of Figure 7, most of the plurality of wiring lines Lx transversely cuts sub-pixels SP1, SP2, SP3 and sub-regions AS1, AS2, AS3 along the X direction. Also, most of the plurality of wiring lines Ly transversely cuts sub-pixels SP1, SP2, SP3 and sub-regions AS1, AS2, AS3 along the Y direction. The wirings Lx and Ly formed by the metal layer have light-shielding properties. In sub-regions AS1, AS2, and AS3, light passes through the portions that do not overlap with the wirings Lx and Ly. On the other hand, in sub-pixels SP1, SP2, and SP3, most of the light incident on the display device DSP is reflected or absorbed by the lower electrodes LE1, LE2, and LE3. Figure 8 is a schematic cross-sectional view of region A2 along line VIII-VIII in Figure 6. In this figure, substrate 10 and circuit layer 11 are omitted. As described above, the rib layer 5 does not have openings in sub-regions AS1, AS2, and AS3. Furthermore, the lower electrodes LE1, LE2, and LE3 are not disposed in sub-regions AS1, AS2, and AS3. Furthermore, in the example of Figure 8, in sub-region AS1, the laminated films FL1, FL2, FL3 (organic layers OR1, OR2, OR3, upper electrodes UE1, UE2, UE3, and capping layers CP1, CP2, CP3) and sealing layers SE11, SE12, SE13 are not provided. Therefore, in sub-region AS1, rib layer 5 is in contact with resin layer RS1. Similarly, in sub-regions AS2 and AS3, the laminated films FL1, FL2, FL3 and sealing layers SE11, SE12, SE13 are not provided, and rib layer 5 is in contact with resin layer RS1. If configured in this way, at least a portion of the light L incident on the second region A2 from the display surface side will pass through sub-regions AS1, AS2, and AS3. Therefore, the light L can be detected by a light-receiving element such as a camera CR as shown in FIG1. Figure 9 is a schematic cross-sectional view showing another configuration that can be applied to region A2. In this example, a laminated film FL1 and a sealing layer SE11 are disposed in sub-region AS1. The laminated film FL1 is divided by a partition wall 6 around the periphery of sub-region AS1. The sealing layer SE11 continuously covers the divided laminated film FL1 and partition wall 6. Even with this configuration, at least a portion of the light L incident on region A2 also passes through sub-region AS1. However, since light L passes through the laminated film FL1 and the sealing layer SE11, the transmittance may be reduced compared to the example in Figure 8. Based on this viewpoint, the configuration shown in Figure 8 is advantageous. The same structure as in Figure 9 can be applied to sub-regions AS2 and AS3. That is, a laminated film FL2 and a sealing layer SE12 can be disposed in sub-region AS2, and a laminated film FL3 and a sealing layer SE13 can be disposed in sub-region AS3. Figure 10 is a schematic top view showing another configuration that can be applied to region A2. In this figure, the rib layer 5 and the partition wall 6 near region TA are shown, while other elements are omitted. Rib 5 may have an opening 50 that overlaps with at least one of the subregions AS1, AS2, AS3. In the example of Figure 10, as an example of an opening 50, a plurality of linear openings 50x extending along the X direction and a plurality of linear openings 50y extending along the Y direction are shown. Specifically, four linear openings 50x arranged along the Y direction are located in sub-region AS1, one linear opening 50y is located in sub-region AS2, and two linear openings 50y arranged along the X direction are located in sub-region AS3. The width of the linear opening 50y in the X direction of sub-region AS2 is larger than that of the linear opening 50y in sub-region AS3. The number, shape, and arrangement of the linear openings 50x and 50y in sub-regions AS1, AS2, and AS3 are not limited to the example in Figure 10. For example, linear openings 50x can be provided in each of sub-regions AS1, AS2, and AS3. Also, linear openings 50y can be provided in each of sub-regions AS1, AS2, and AS3. Figure 11 is a schematic top view showing another example of opening 50. In this example, multiple point openings 50d are provided in sub-regions AS1, AS2, and AS3. In the example of Figure 11, the openings 50d at each point are perfect circles with the same diameter. However, this is not a limitation; the openings 50d can be oval, square, or other shapes. Furthermore, the diameter (or width) of each opening 50d can be different. The openings 50d can be provided together with the linear openings 50x and 50y shown in Figure 10 in sub-regions AS1, AS2, and AS3. Figure 12 is a schematic cross-sectional view of region A2 along line XII-XII in Figure 10. In the example of Figure 12, similar to Figure 8, the laminated films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 are not disposed in sub-region AS1. Therefore, each linear opening 50x is filled by the resin layer RS1. The resin layer RS1 contacts the organic insulating layer 12 through each linear opening 50x. As another example, the laminated film FL1 and the sealing layer SE11 can be arranged in sub-region AS1 in the same manner as in Figure 9. In this case, the laminated film FL1 (specifically the organic layer OR1) contacts the organic insulating layer 12 through each linear opening 50x. The same applies to sub-regions AS2 and AS3; laminated films FL2 and FL3 and sealing layers SE12 and SE13 can be arranged, or they can be omitted. When the rib layer 5 has openings 50, such as linear openings 50x, 50y or dot openings 50d, in the sub-regions AS1, AS2, and AS3, the decrease in transmittance caused by the rib layer 5 can be suppressed. This further improves the light transmittance of the transmission region TA. Next, an example of a manufacturing method for a display device DSP will be described. Figures 13A to 13I are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 13A to 13I, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted. When forming the display device DSP, firstly, a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10. Secondly, as shown in FIG13A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12. Subsequently, as shown in Figure 13B, a rib layer 5 is formed covering the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The formation of the rib layer 5 can be achieved, for example, by CVD (Chemical Vapor Deposition). Furthermore, as shown in Figure 13C, a partition wall 6 is formed on the rib layer 5. Specifically, firstly, a layer forming the base layer 63, the axial layer 64, and the upper layer 62 is formed, and these layers are patterned by etching. After the partition wall 6 is formed, as shown in Figure 13D, pixel openings AP1, AP2, and AP3 are formed on the rib layer 5 by dry etching. Next, the process for forming display elements DE1, DE2, and DE3 is carried out. In this embodiment, it is envisioned that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed. However, the formation order of display elements DE1, DE2, and DE3 is not limited to this example. When forming the display element DE1, firstly, as shown in FIG13E, a multilayer film FL1 and a sealing layer SE11 are formed. The multilayer film FL1, as shown in FIG4, includes: an organic layer OR1 that contacts the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a capping layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 are formed by vapor deposition. Furthermore, the sealing layer SE11 is formed by CVD. The laminated film FL1 and the sealing layer SE11 are formed not only in the display area DA, but also in the peripheral area SA. The laminated film FL1 is divided into multiple parts by a cantilevered partition wall 6. The sealing layer SE11 continuously covers each of the divided parts of the laminated film FL1 and the partition wall 6. Next, the laminated film FL1 and the sealing layer SE11 are patterned. In this patterning, as shown in FIG13F, a resist R is disposed on the sealing layer SE11. The resist R covers a portion of the sub-pixel SP1 and the surrounding partition wall 6. Subsequently, as shown in Figure 13G, the portions of the stacked film FL1 and the sealing layer SE11 exposed from the resist R are removed by etching with the resist R as a mask. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 remain, while the rest are removed. This forms the display element DE1 on the sub-pixel SP1. This etching may include wet etching and dry etching performed sequentially on the sealing layer SE11, the cover layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R is removed. Display element DE2 is formed in the same order as display element DE1. That is, when forming display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed on the entire display area DA and the peripheral area SA. As shown in Figure 4, the multilayer film FL2 includes: an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cover layer CP2 covering the upper electrode UE2. The organic layer OR2, the upper electrode UE2, and the capping layer CP2 are formed by vapor deposition. The sealing layer SE12 is formed by CVD. The laminated film FL2 is divided into multiple parts by overhanging partitions 6. The sealing layer SE12 continuously covers each of the divided parts of the laminated film FL2 and the partitions 6. By patterning this laminated film FL2 and the sealing layer SE2, as shown in FIG13H, the display element DE2 is formed on the sub-pixel SP2. Display element DE3 is formed in the same order as display elements DE1 and DE2. That is, when forming display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed on the entire display area DA and the peripheral area SA. As shown in Figure 4, the multilayer film FL3 includes: an organic layer OR3 that contacts the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cover layer CP3 covering the upper electrode UE3. The organic layer OR3, the upper electrode UE3, and the capping layer CP3 are formed by vapor deposition. The sealing layer SE13 is formed by CVD. The laminated film FL3 is divided into multiple parts by overhanging partitions 6. The sealing layer SE13 continuously covers each of the divided parts of the laminated film FL3 and the partitions 6. By patterning this laminated film FL3 and the sealing layer SE13, as shown in FIG13I, a display element DE3 is formed on the sub-pixel SP3. After forming display elements DE1, DE2, and DE3, resin layer RS1, sealing layer SE2, and resin layer RS2, as shown in Figure 4, are formed sequentially. Thus, the display device DSP with the structure shown in Figure 4 is completed. In the above embodiment, a second region A2 with light transmittance is formed in the display region DA. Therefore, even if a light-receiving element such as a camera CR is arranged on the back side of the second region A2 as shown in FIG1, the light incident on the display region DA can be detected by the light-receiving element. Furthermore, the laminated films FL1, FL2, and FL3 formed by vapor deposition sometimes have poor adhesion to the substrate. Therefore, during the manufacturing of a display device DSP, the laminated films FL1, FL2, and FL3, and the sealing layers SE11, SE12, and SE13 covering them, may peel off from the substrate. In this case, the peeled laminated films FL1, FL2, and FL3, and the sealing layers SE11, SE12, and SE13 may adhere to the substrate or contaminate the chamber of the manufacturing apparatus. The aforementioned delamination is likely to occur continuously and over a wide range during the formation of the stacked films FL1, FL2, and FL3. Within pixel PX, the stacked films FL1, FL2, and FL3 are finely segmented by the partition walls 6 surrounding the sub-pixels SP1, SP2, and SP3. Therefore, the aforementioned delamination is suppressed. Furthermore, in this embodiment, the through region TA is divided into a plurality of sub-regions AS (AS1, AS2, AS3) by the partition wall 6. In this way, the stacked films FL1, FL2, and FL3 are also finely segmented in the through region TA in the same way as the pixel PX, thereby suppressing the aforementioned peeling. In this way, the peeling of the laminated films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 can be suppressed during manufacturing, thereby improving the yield of the display device DSP. [Second Implementation] In the second embodiment, other structures applicable to the second region A2 are disclosed. For structures not mentioned in this embodiment, the same structures as in the first embodiment may be applied. Figure 14 is a schematic top view showing a portion of the second region of the second embodiment. In this figure, the rib layer 5, the partition wall 6, and the lower electrodes LE1, LE2, and LE3 are shown in the same manner as in Figure 6, with other elements omitted. Furthermore, dotted patterns are added to the partition wall 6, and diagonal lines are added to the lower electrodes LE1, LE2, and LE3. In this embodiment, the number of sub-pixels SP contained in one pixel PX is different from the number of sub-regions AS contained in one transmission region TA. Specifically, in the example of FIG14, pixel PX has 3 sub-pixels SP (SP1, SP2, SP3), and transmission region TA has 4 sub-regions AS (AS1, AS2, AS3, AS4). That is, in the example of FIG14, the number of sub-regions AS contained in one transmission region TA is greater than the number of sub-pixels SP contained in one pixel PX. In the example of Figure 14, subregions AS1 and AS2 are arranged along the X direction, and subregions AS3 and AS4 are arranged along the X direction. Furthermore, subregions AS1 and AS3 are arranged along the Y direction, and subregions AS2 and AS4 are arranged along the Y direction. Moreover, subregions AS1, AS2, AS3, and AS4 have the same shape. The partition wall 6 has: a first portion P1 dividing sub-pixels SP1, SP2, and SP3 in each pixel PX, and a second portion P2 dividing sub-regions AS1, AS2, AS3, and AS4 in each transmission region TA. In the example of FIG14, the shapes of the first portion P1 and the second portion P2 are different. That is, the first part P1, like the example in Figure 6, has a portion extending along the Y direction between sub-pixels SP1 and SP2, SP3, and a portion extending along the X direction between sub-pixels SP2 and SP3. On the other hand, the second part P2 is cross-shaped. Specifically, the second part P2 has a portion extending along the Y direction between sub-regions AS1, AS3 and AS2, AS4, and a portion extending along the X direction between sub-regions AS1, AS2 and AS3, AS4. In subregions AS1, AS2, AS3, and AS4, the same structure as that shown in subregion AS1 in Figures 8, 9, and 12 can be applied. When an opening 50 is provided in the rib layer 5 in subregions AS1, AS2, AS3, and AS4, the opening 50 can be a linear opening 50x or 50y as shown in Figure 10 or a point opening 50d as shown in Figure 11. As in this embodiment, even when the number of sub-pixels SP contained in a pixel PX differs from the number of sub-regions AS contained in a transmissive region TA, the same effect as in the first embodiment can be obtained. Furthermore, in the example of FIG. 14, compared to the first embodiment, the transmissive region TA is finely divided by the second portion P2 of the partition wall 6. Therefore, during the manufacturing of the display device DSP, the laminated films FL1, FL2, and FL3 formed in the transmissive region TA are finely segmented. Consequently, the aforementioned peeling can be further effectively suppressed. [Third Embodiment] In the third embodiment, another construction applicable to the second region A2 is disclosed. For constructions not mentioned in this embodiment, the same constructions as in the first and second embodiments can be applied. Figure 15 is a schematic top view showing a portion of region A2 in the third embodiment. In this figure, the partition wall 6, lower electrodes LE1, LE2, LE3, and a plurality of wirings Lx extending along the X direction are shown; other elements are omitted. Furthermore, dotted patterns are added to the partition wall 6, and oblique line patterns are added to the lower electrodes LE1, LE2, LE3. The structure of the first region A1 in this embodiment is the same as that shown in FIG. 5. Furthermore, FIG. 5 and FIG. 15 are of the same scale. That is, by comparing the two figures, it is clear that in this embodiment, the size of the pixel PX (first pixel) disposed in the second region A2 is different from the size of the pixel PX (second pixel) disposed in the first region A1. Specifically, the pixel PX disposed in the second region A2 is smaller than the pixel PX disposed in the first region A1. In one example, the pixel density of region A2 is the same as the pixel density of region A1. Here, pixel density refers to the number of pixels PX per unit area. In the example of Figure 15, the pixel PX located in the second region A2 has the same sub-pixels SP1, SP2, and SP3 as the pixel PX located in the first region A1. However, the sub-pixels SP1, SP2, and SP3 in the second region A2 have rounded corners. The region TA has four sub-regions AS1, AS2, AS3, and AS4. In the example of Figure 15, these sub-regions AS1, AS2, AS3, and AS4 are pentagonal. The second part P2 of the partition wall 6 is a cross-shaped division of these sub-regions AS1, AS2, AS3, and AS4. Furthermore, the shapes of the sub-regions AS1, AS2, AS3, and AS4 are not limited to this example and various other shapes can be applied. In subregions AS1, AS2, AS3, and AS4, the same structure as that of subregion AS1 shown in Figures 8, 9, and 12 can be applied. When an opening 50 is provided in the rib layer 5 in subregions AS1, AS2, AS3, and AS4, the opening 50 can be a linear opening 50x or 50y as shown in Figure 10 or a point opening 50d as shown in Figure 11. In the example of Figure 15, the transmission region TA may not be positioned between adjacent pixels PX along the X direction and between adjacent pixels PX along the Y direction. Each transmission region TA is located between adjacent pixels PX along an oblique direction intersecting the X and Y directions. From other perspectives, the transmission region TA is positioned offset relative to the pixels PX surrounding it along the X and Y directions. In the example of Figure 15, the area of ​​each of the sub-regions AS1, AS2, AS3, and AS4 is larger than the area of ​​any one of the sub-pixels SP1, SP2, and SP3. Not limited to this example, the area of ​​at least one of the sub-regions AS1, AS2, AS3, and AS4 may be smaller than the area of ​​any one of the sub-pixels SP1, SP2, and SP3. Each wiring Lx is configured not to overlap with sub-regions AS1, AS2, AS3, and AS4. That is, each wiring Lx overlaps with the partition wall 6 as a whole. In the example of Figure 15, the spacing between the plurality of wirings Lx is narrowed between the two transmittance regions TA arranged along the Y direction and widened between the two pixels PX arranged along the Y direction. Although the illustration is omitted in Figure 15, the same shape as the wiring Lx can be applied to multiple wirings Ly extending along the Y direction (refer to Figure 7). That is, each wiring Ly can be configured not to overlap with the transmission area TA. In this case, the spacing between the multiple wirings Ly can be narrowed between the two transmission areas TA arranged along the X direction and widened between the two pixels PX arranged along the X direction. As in this embodiment, the pixel PX is reduced in the second region A2, thereby distributing the pixel PX in the second region A2 with the same density as the first region A1, which improves the display quality of the second region A2. Furthermore, by configuring the light-shielding wirings Lx and Ly formed of metal material so that they do not overlap with the sub-regions AS1, AS2, AS3, and AS4, the light transmittance of the transmission region TA can be further improved. In the first to third embodiments described above, examples are shown where the through region TA has three or four sub-regions AS. However, this is not a limitation; each through region TA may have five or more sub-regions AS or two or fewer sub-regions AS. Furthermore, the plurality of sub-regions AS of each through region TA may have different shapes. Based on the display device and substrate described above as embodiments of the present invention, all display devices that can be designed, modified, and implemented by those skilled in the art, as long as they contain the essence of the present invention, are also within the scope of the present invention. Within the scope of the present invention, various modifications can be conceived by those skilled in the art, and such modifications should also be understood to be within the scope of the present invention. For example, for the above-described embodiments, any appropriate addition, deletion, or design change of constituent elements, or any addition, omission, or change of processes or conditions, as long as they possess the essence of the present invention, are also included within the scope of the present invention. Furthermore, any other effects resulting from the embodiments described above, which are clear from the description in this specification or which can be reasonably conceived by those skilled in the art, should be understood as effects resulting from the present invention. Cross-reference to related applications This invention application claims priority based on Japanese Patent Application No. 2024-11695, filed on January 30, 2024, and incorporates all the contents described in that Japanese Patent Application. 5: Rib layer 6: Separator 10: Substrate 11: Circuit layer 12: Organic insulating layer 50d: Dot opening 50x: Opening / Linear opening 50y: Opening / Linear opening 61: Lower part 62: Upper part 63: Bottom layer 64: Axis layer A1: Region 1 A2: Region 2 AP1, AP2, AP3: Pixel opening AS1, AS2, AS3: Sub-region CP1, CP2, CP3: Cover layer CR: Camera Cst: Holding capacitor DA: Display area DE: Light source / Display element DE1, DE2, DE3: Display element DSP: Display device FL1, FL2, FL3: Stacked film GL1, GL2, GL3, GL4: Scan line IL: Initialization line IV-IV, VIII-VIII, XII-XII: Line L: Light LE1, LE2, LE3: Lower electrode Lx, Ly: Wiring n1, n2, n3, n4: Node OR1, OR2, OR3: Organic layer; P1: Part 1; P2: Part 2; PC: Pixel circuit; PL1, PL2, PL3: Power line; PX: Pixel; R: Resist; RS1, RS2: Resin layer; SA: Peripheral area; Sdata: Image signal; SE2: Sealing layer; SE11, SE12, SE13: Sealing layer; Sg1, Sg2, Sg3, Sg4: Scan signal; SL: Signal line; SP1, SP2, SP3: Sub-pixel; TA: Transmitting area; TR1~TR7: Transistor; UE1, UE2, UE3: Upper electrode; VDDEL, VSH, VSSEL: Power supply voltage; Vini: Initialization voltage; X, Y, Z: Axis / Direction. Figure 1 is a diagram showing an example of the configuration of the display device according to the first embodiment. Figure 2 is a circuit diagram showing an example of the configuration applicable to pixel circuits provided by each sub-pixel. Figure 3 is a schematic top view showing an example of the layout of sub-pixels in one pixel. Figure 4 is a schematic cross-sectional view of the display panel along line IV-IV in Figure 3. Figure 5 is a schematic top view showing a portion of the first region. Figure 6 is a schematic top view showing a portion of the second region. Figure 7 is another schematic top view showing a portion of the second region. Figure 8 is a schematic cross-sectional view of the second region along line VIII-VIII in Figure 6. Figure 9 is a schematic cross-sectional view showing another configuration applicable to the second region. Figure 10 is a schematic top view showing yet another configuration applicable to the second region. Figure 11 is a schematic top view showing another example of the opening of the rib layer. Figure 12 is a schematic cross-sectional view of the second region along line XII-XII in Figure 10. Figure 13A is a schematic cross-sectional view showing the manufacturing process of the display device. Figure 13B is a schematic cross-sectional view showing the process continuing from Figure 13A. Figure 13C is a schematic cross-sectional view showing the process continuing from Figure 13B. Figure 13D is a schematic cross-sectional view showing the process continuing from Figure 13C. Figure 13E is a schematic cross-sectional view showing the process continuing from Figure 13D. Figure 13F is a schematic cross-sectional view showing the process continuing from Figure 13E. Figure 13G is a schematic cross-sectional view showing the process continuing from Figure 13F. Figure 13H is a schematic cross-sectional view showing the process continuing from Figure 13G. Figure 13I is a schematic cross-sectional view showing the process continuing from Figure 13H. Figure 14 is a schematic top view showing a portion of the second region of the second embodiment. Figure 15 is a schematic top view showing a portion of the second region of the third embodiment. 5: Rib layer 6: Partition wall A2: Area 2 AP1, AP2, AP3: Pixel apertures AS1, AS2, AS3: Subregions LE1, LE2, LE3: Lower electrodes P1: Part 1 P2: Part 2 PX: pixel SP1, SP2, SP3: Subpixels TA: Through the region VIII-VIII: Line X, Y, Z: Axis / Direction

Claims

1. A display device comprising: a first pixel disposed in a display area for displaying an image; a transmissive region disposed in the display area; and a partition wall comprising a conductive lower portion and an upper portion having an end portion projecting from the side of the lower portion, disposed in the display area; the first pixel comprising a plurality of sub-pixels surrounded by the partition wall; the transmissive region comprising a plurality of sub-regions surrounded by the partition wall and transmitting at least a portion of light incident on the transmissive region; each of the plurality of sub-pixels comprising: a lower electrode; an organic layer covering the lower electrode and emitting light in response to the application of a voltage; an upper electrode covering the organic layer and in contact with the lower portion of the partition wall; and the lower electrode is not disposed in the plurality of sub-regions; the organic layer and the upper electrode are not disposed in the plurality of sub-regions.

2. The display device of claim 1, wherein each of the aforementioned plurality of sub-pixels further includes an optical adjustment layer covering the aforementioned upper electrode; and the aforementioned optical adjustment layer is not disposed in the aforementioned plurality of sub-regions.

3. The display device of claim 2, wherein each of the aforementioned plurality of sub-pixels further includes a first sealing layer formed of inorganic insulating material covering the aforementioned optical adjustment layer; and the aforementioned first sealing layer is not disposed in the aforementioned plurality of sub-regions.

4. The display device of claim 1, further comprising a rib layer located below the aforementioned partition wall and having a pixel opening in each of the aforementioned plurality of sub-pixels, formed of an inorganic insulating material; and the aforementioned plurality of sub-regions overlapping the aforementioned rib layer.

5. The display device of claim 4, wherein the aforementioned rib layer has an opening that overlaps with at least one of the aforementioned plurality of sub-regions.

6. The display device of claim 5, wherein the aforementioned opening comprises a plurality of linear openings arranged in one of the aforementioned sub-regions.

7. The display device of claim 5, wherein the aforementioned opening comprises a plurality of dot openings dispersed in one of the aforementioned sub-regions.

8. The display device of claim 4, further comprising a first resin layer covering the aforementioned display area; and the aforementioned first resin layer being in contact with the aforementioned rib layer in the aforementioned plurality of sub-regions.

9. The display device of claim 8, further comprising a second sealing layer covering the aforementioned first resin layer and formed of an inorganic insulating material.

10. The display device of claim 9, further comprising a second resin layer covering the aforementioned second sealing layer.

11. The display device of claim 1, wherein the number of the aforementioned plurality of sub-pixels is the same as the number of the aforementioned plurality of sub-regions.

12. The display device of claim 11, wherein the plurality of subpixels includes a first subpixel, a second subpixel, and a third subpixel; and the plurality of subregions includes a first subregion, a second subregion, and a third subregion configured in the same positional relationship as the first subpixel, the second subpixel, and the third subpixel.

13. The display device of claim 12, wherein the aforementioned partition wall comprises: a first portion that divides the aforementioned first sub-pixel, the aforementioned second sub-pixel and the aforementioned third sub-pixel; and a second portion that divides the aforementioned first sub-region, the aforementioned second sub-region and the aforementioned third sub-region.

14. The display device of claim 13, wherein the aforementioned first part and the aforementioned second part have the same shape.

15. The display device of claim 1, wherein the number of the aforementioned plurality of sub-pixels is different from the number of the aforementioned plurality of sub-regions.

16. The display device of claim 15, wherein the number of the aforementioned plurality of sub-regions is greater than the number of the aforementioned plurality of sub-pixels.

17. The display device of claim 1, further comprising: a plurality of pixel circuits disposed in the aforementioned display area and driving the plurality of sub-pixels respectively; and a plurality of wirings supplying voltage or signals to the plurality of pixel circuits; wherein at least one of the plurality of wirings overlaps with the aforementioned partition wall but does not overlap with the aforementioned plurality of sub-regions.

18. The display device of claim 17, wherein the aforementioned display area has: a first region including the second pixel, and a second region including the first pixel and the aforementioned transparent region; and the first pixel is smaller than the second pixel.

Images