Ldmos structure and method of manufacturing the same

Abstract

A laterally diffused metal-oxide-semiconductor structure includes a substrate, a gate, a gate dielectric layer, a well region, at least one first lightly doped drain (LDD) region, at least one second LDD region, and a source / drain region. The gate is formed on the surface of the substrate, and the gate dielectric layer is disposed between the gate and the substrate. The well region is disposed within the surface of the substrate. At least one first LDD region is disposed within the well region on one side of the gate, and at least one second LDD region is disposed within the well region outside the first LDD region. The source / drain region is formed within the second LDD region.

Description

Technical Field

[0001] This invention relates to a power semiconductor device, and more particularly to a laterally diffused metal-oxide-semiconductor structure and a method for manufacturing the same. Prior Technology

[0002] In current high-voltage semiconductor devices (such as laterally diffused metal-oxide-semiconductor (LDMOS) transistors), shallow trench isolation (STI) structures are generally used as the isolation between the gate and the source / drain to improve the device's breakdown voltage.

[0003] However, current LDMOS transistors with STI structures suffer from small current Ids between the active and drain electrodes and large current Ib flowing through the substrate, and require a large device area. Summary of the Invention

[0004] This invention provides a laterally diffused metal-oxide-semiconductor structure that can maintain the breakdown voltage and improve the current Ids between the source and drain and the current Ib flowing through the substrate without the need to set an STI structure in the LDMOS device.

[0005] The present invention also provides a method for manufacturing a laterally diffused metal-oxide-semiconductor structure, which can produce LDMOS devices with high reliability and small area.

[0006] A laterally diffused metal-oxide-semiconductor structure of the present invention includes a substrate, a gate, a gate dielectric layer, a well region, at least one first lightly doped drain (LDD) region, at least one second LDD region, and a source / drain region. The gate is formed on the surface of the substrate, and the gate dielectric layer is disposed between the gate and the substrate. The well region is disposed within the surface of the substrate. The at least one first LDD region is disposed within the well region on one side of the gate, and the at least one second pair of LDD regions are disposed within the well region outside the at least one first LDD region on that side of the gate. The source / drain region is formed within the at least one second LDD region.

[0007] In one embodiment of the present invention, the at least one first LDD region is a first pair of LDD regions, respectively disposed in the well regions on both sides of the gate. The at least one second LDD region is a second pair of LDD regions, respectively disposed in the well regions outside the first pair of LDD regions. The source / drain region is formed within the second pair of LDD regions.

[0008] In one embodiment of the present invention, the doping concentration distribution of the first pair of LDD regions is smaller than that of the second pair of LDD regions.

[0009] In one embodiment of the present invention, the first pair of LDD regions overlaps with the gate portion.

[0010] In one embodiment of the present invention, the second pair of LDD regions does not overlap with the gate.

[0011] In one embodiment of the present invention, the second pair of LDD regions located on the same side of the gate are connected to the first pair of LDD regions.

[0012] In one embodiment of the present invention, the interface depth between the second pair of LDD regions and the first pair of LDD regions is less than the maximum depth of the second pair of LDD regions.

[0013] In one embodiment of the present invention, the above-mentioned laterally diffused metal oxide semiconductor structure is a symmetrical or asymmetrical laterally diffused metal oxide semiconductor.

[0014] In one embodiment of the present invention, the above-mentioned at least one first LDD region is a first pair of LDD regions, which are respectively disposed in the well areas on both sides of the gate electrode.

[0015] In one embodiment of the present invention, the above-mentioned at least one second LDD region is a second pair of LDD regions, which are respectively disposed in the well areas on both sides of the gate electrode.

[0016] In one embodiment of the present invention, the aforementioned source / drain region may also be formed in the well region on the other side of the gate.

[0017] A method for manufacturing a laterally diffused metal-oxide-semiconductor (LDD) structure according to the present invention includes the following steps: forming a well region within a substrate; forming at least one first LDD region within the well region; forming at least one second LDD region within the well region outside the at least one first LDD region; forming a gate dielectric layer on the surface of the substrate; forming a gate on the gate dielectric layer, wherein the at least one first LDD region is located between the gate and the at least one second LDD region; and forming a source / drain region within the at least one second LDD region.

[0018] In another embodiment of the present invention, the at least one first LDD region is a first pair of LDD regions, respectively formed in the well regions on both sides of the gate. The at least one second LDD region is a second pair of LDD regions, respectively formed in the well regions outside the first pair of LDD regions. The source / drain region is formed in the second pair of LDD regions.

[0019] In another embodiment of the present invention, the method for forming the first pair of LDD regions and the method for forming the second pair of LDD regions includes using the same implantation process to form four separate lightly doped implantation regions in the well region, and then performing annealing.

[0020] In another embodiment of the present invention, the method for forming the first pair of LDD regions and the method for forming the second pair of LDD regions includes performing a first implantation process in the well region where the second pair of LDD regions are to be formed, then performing a second implantation process in the well region where the first pair of LDD regions are to be formed, and then performing annealing.

[0021] In another embodiment of the invention, the gate is formed before the first pair of LDD regions are formed.

[0022] In another embodiment of the invention, the gate is formed before the formation of the second pair of LDD regions described above.

[0023] In the above embodiments of the present invention, the doping concentration distribution of the first pair of LDD regions is the same as that of the second pair of LDD regions.

[0024] In the above embodiments of the present invention, the doping concentration distribution of the first pair of LDD regions is different from that of the second pair of LDD regions.

[0025] To make the above features of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0026] Figure 1 is a cross-sectional view of a laterally diffused metal-oxide-semiconductor structure according to a first embodiment of the present invention. Figure 2 is a cross-sectional view of another laterally diffused metal-oxide-semiconductor structure according to the first embodiment. Figures 3A to 3D are cross-sectional views of the manufacturing process of a laterally diffused metal-oxide-semiconductor structure according to a second embodiment of the present invention. Figures 4A and 4B are cross-sectional views of an alternative example of the manufacturing process in the second embodiment. Figure 5 is a cross-sectional view of another alternative example in the manufacturing process of the second embodiment. Figure 6 is a cross-sectional view of an asymmetric laterally diffused metal-oxide-semiconductor structure according to a third embodiment of the present invention. Figure 7 is a cross-sectional view of an asymmetric laterally diffused metal-oxide-semiconductor structure according to a fourth embodiment of the present invention. Figure 8 is a cross-sectional view of an asymmetric laterally diffused metal-oxide-semiconductor structure according to a fifth embodiment of the present invention. Implementation

[0027] The present invention can be understood by referring to the following detailed description and the accompanying drawings. Furthermore, the dimensions of the various regions in the drawings are for illustrative purposes only and are not intended to limit the scope of the invention.

[0028] Figure 1 is a cross-sectional view of a laterally diffused metal-oxide-semiconductor structure according to a first embodiment of the present invention.

[0029] Referring to Figure 1, the laterally diffused metal-oxide-semiconductor structure of the first embodiment includes at least a substrate 100, a gate G1, a gate dielectric layer O1, well regions 102, a first pair of lightly doped drain (LDD) regions LDD1, a second pair of LDD regions LDD2, and a source / drain region S / D. The gate G1 is formed above the surface 100s of the substrate 100, and the gate dielectric layer O1 is disposed between the gate G1 and the substrate 100. Well regions 102 are disposed within the surface 100s of the substrate 100. The first pair of LDD regions LDD1 are disposed within the well regions 102 on both sides of the gate G1. In some embodiments, the first pair of LDD regions LDD1 partially overlaps with the gate G1. The second pair of LDD regions LDD2 are disposed within the well regions 102 outside the first pair of LDD regions LDD1; therefore, the first pair of LDD regions LDD1 is close to the gate G1, while the second pair of LDD regions LDD2 is far from the gate G1. The first pair of LDD regions, LDD1, and the second pair of LDD regions, LDD2, can be formed using the same implantation process. Therefore, the doping concentration distribution of the first pair of LDD regions, LDD1, can be the same as that of the second pair of LDD regions, and the dopants of the first pair of LDD regions, LDD1, and LDD2 can be the same. Similarly, the depth of the first pair of LDD regions, LDD1, formed using the same implantation process can be the same as or similar to the depth of the second pair of LDD regions, LDD2. In some embodiments, the second pair of LDD regions, LDD2, does not overlap with the gate G1. The source / drain regions, S / D, are formed within the second pair of LDD regions, LDD2. In some embodiments, the source / drain regions, S / D, are N+ regions, then the well region 102 is a P-type well, and the first pair of LDD regions, LDD1, and the second pair of LDD regions, LDD2, are N- regions; and so on.

[0030] In this embodiment, the second pair of LDD regions LDD2, located on the same side of the gate G1, is connected to the first pair of LDD regions LDD1. In some embodiments, the interface depth d1 between the second pair of LDD regions LDD2 and the first pair of LDD regions LDD1 is less than the maximum depth d2 of the second pair of LDD regions LDD2.

[0031] The laterally diffused metal-oxide-semiconductor structure of this embodiment does not require an additional isolation structure (such as STI or field oxide layer) between the gate G1 and the source / drain region S / D. Therefore, it can significantly reduce the device area and increase the current Ids between the source and drain, and significantly reduce the current Ib flowing through the substrate 100, thereby reducing the Ib / Ids ratio by at least one order of magnitude. Such improvements can enhance device reliability. On the other hand, compared with the existing LDMOS structure with isolation structure, the laterally diffused metal-oxide-semiconductor structure of this embodiment can significantly reduce the chip area while maintaining the same current Ids.

[0032] Figure 2 is a cross-sectional view of another laterally diffused metal-oxide-semiconductor structure of the first embodiment, wherein the same element symbols as in Figure 1 are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also be referred to the content of Figure 1, and will not be repeated here.

[0033] In Figure 2, the doping concentration distribution of the first pair of LDD regions LDD1 differs from that of the second pair of LDD regions LDD2'. For example, the doping concentration distribution of the first pair of LDD regions LDD1 is smaller than that of the second pair of LDD regions LDD2', and the dopants of the first pair of LDD regions LDD1 are different from those of the second pair of LDD regions LDD2'. The doping depth of the first pair of LDD regions LDD1 also differs from that of the second pair of LDD regions LDD2'. For example, the doping depth of the second pair of LDD regions LDD2' is deeper than that of the first pair of LDD regions LDD1. However, the present invention is not limited to this. The first pair of LDD regions LDD1 and the second pair of LDD regions LDD2' can be made similar but not exactly the same in terms of doping concentration distribution or doping depth by adjusting the implantation parameters.

[0034] Figures 3A to 3D are cross-sectional views of the manufacturing process of a laterally diffused metal-oxide-semiconductor structure according to a second embodiment of the present invention, wherein the same element symbols as in the first embodiment are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the first embodiment, and will not be repeated here.

[0035] Referring to Figure 3A, a well region 102 is formed in the substrate 100. The steps include, for example, first implanting a dopant from the surface 100s of the substrate 100 and then annealing it. [, , ]

[0036] Then, referring to Figure 3B, a patterned mask layer 300 can be formed on the substrate 100 first, and then the same implantation process 302 can be used to form four separate lightly doped implantation regions 304, 306, 308, and 310 in the well region 102.

[0037] Next, referring to Figure 3C, annealing is performed to form the first pair of LDD regions LDD1 and the second pair of LDD regions LDD2 within the well region 102. That is, the first pair of LDD regions LDD1 and the second pair of LDD regions LDD2 are formed using the same implantation parameters. Therefore, the doping concentration distribution of the first pair of LDD regions LDD1 is the same as that of the second pair of LDD regions LDD2, and the dopants of the first pair of LDD regions LDD1 and the second pair of LDD regions LDD2 are the same. After removing the patterned mask layer 300 of Figure 3B, a dielectric layer 312 and a conductive layer 314 can be sequentially formed on the substrate 100. The dielectric layer 312 is, for example, a silicon oxide layer, and the conductive layer 314 is, for example, a polycrystalline silicon layer, but is not limited to these.

[0038] Then, referring to Figure 3D, the dielectric layer 312 and conductive layer 314 in Figure 3C are patterned to form a gate dielectric layer O1 on the substrate 100 between the first pair of LDD regions LDD1, and a gate G1 is formed on the gate dielectric layer O1. After that, the source / drain region S / D is formed in the second pair of LDD regions LDD2.

[0039] Figures 4A and 4B are cross-sectional views of an alternative example of the manufacturing process of the second embodiment, wherein the same element symbols as those in Figure 3B are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also be referred to the above content, and will not be repeated here.

[0040] Figure 4A shows the steps following Figure 3A, which include forming a patterned photoresist layer 400 on the substrate 100, and then using a first implantation process 402 to form two separate lightly doped implantation regions 304' and 310' within the well region 102. The lightly doped implantation regions 304' and 310' are positioned at the locations where the second pair of LDD regions are to be formed.

[0041] Next, referring to Figure 4B, after removing the patterned photoresist layer 400 of Figure 4A, another patterned photoresist layer 404 is formed on the substrate 100. Then, using a second implantation process 406, two separate lightly doped implantation regions 306 and 308 are formed within the well region 102. The lightly doped implantation regions 306 and 308 are positioned at the locations where the first pair of LDD regions is to be formed. However, the present invention is not limited thereto. In other embodiments, the first implantation process 402 can be used to first form two separate lightly doped implantation regions within the well region 102 to form the first pair of LDD regions, and then the second implantation process 406 can be used to form two separate lightly doped implantation regions within the well region 102 to form the second pair of LDD regions. Since the first implantation process 402 and the second implantation process 406 have different implantation parameters, subsequent annealing can yield a first pair of LDD regions and a second pair of LDD regions with different doping concentration distributions, and the dopants in the first pair of LDD regions can be different from the dopants in the second pair of LDD regions.

[0042] Figure 5 is a cross-sectional view of another alternative example in the manufacturing process of the second embodiment, wherein the same element symbols as in Figure 3B are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also be referred to the above content, and will not be repeated here.

[0043] In Figure 5, the gate G1 is formed before the formation of the first pair of LDD regions LDD1. Therefore, during the implantation process 302 on the substrate 100, the gate G1 and the patterned mask layer 500 can be used as a mask to form four separate lightly doped implantation regions 304, 306, 308, and 310 within the well region 102. After subsequent annealing, the source / drain regions can be formed directly.

[0044] Figure 6 is a cross-sectional view of an asymmetric laterally diffused metal-oxide-semiconductor (LDMOS) structure according to a third embodiment of the present invention, wherein the same element symbols as in the second embodiment are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the second embodiment, and will not be repeated here.

[0045] In Figure 6, the difference between the asymmetric LDMOS structure and the above embodiment is that the doped regions within the well regions 102 on both sides of the gate G1 are not symmetrical, and do not have paired LDD regions. Taking the structure in Figure 6 as an example, the right side of the gate G1 has a lightly doped implanted region 308 and a lightly doped implanted region 310, but the left side of the gate G1 only has a lightly doped implanted region 304; that is, the asymmetric LDMOS structure in Figure 6 has a pair of second LDD regions (lightly doped implanted regions 304 and 310) and a single first LDD region (lightly doped implanted region 308). The aforementioned doped regions can be formed using the same implantation process, creating three separate lightly doped implanted regions 304, 308, and 310 within the well region 102, followed by annealing. The source / drain regions (S / D) are formed within the lightly doped implanted regions 304 and 310.

[0046] Figure 7 is a cross-sectional view of an asymmetric LDMOS structure according to the fourth embodiment of the present invention, wherein the same element symbols as those in Figure 6 are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content related to Figure 6, which will not be repeated here.

[0047] The structure in Figure 7 differs from that in Figure 6 in that there is only a lightly doped implantation region 306 to the left of the gate G1. The doping concentration distribution of the lightly doped implantation region 306 may be the same as that of the lightly doped implantation region 308, but different from that of the lightly doped implantation region 310. Therefore, the asymmetric LDMOS structure in Figure 7 has a pair of first LDD regions (lightly doped implantation region 306 and lightly doped implantation region 308) and a single second LDD region (lightly doped implantation region 310).

[0048] Figure 8 is a cross-sectional view of an asymmetric LDMOS structure according to the fifth embodiment of the present invention, wherein the same element symbols as those in Figure 6 are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content related to Figure 6, which will not be repeated here.

[0049] In Figure 8, only the source / drain region (S / D) is present to the left of gate G1, without an LDD region. Therefore, the asymmetric LDMOS structure in Figure 8 has only one first LDD region (lightly doped implantation region 308) and one second LDD region (lightly doped implantation region 310). The source / drain regions (S / D) are formed in the lightly doped implantation region 310 to the right of gate G1 and in the well region 102 to the left of gate G1, respectively.

[0050] Based on the above, this invention eliminates the need for an isolation structure between the gate and the source / drain regions, thus significantly reducing the device area and lowering the Ib / Ids ratio, thereby improving device reliability. Furthermore, the laterally diffused metal-oxide-semiconductor structure of this invention can also be applied to the design of asymmetric LDMOS, similarly eliminating the need for an isolation structure between the gate and the source / drain regions.

[0051] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0052] 100: Base 100s: Surface 102: Well Area 300, 500: Patterned dome layer 302: Implantation process 304, 304', 306, 306', 308, 310: Lightly doped implantation regions 312: Dielectric layer 314: Conductive layer 400, 404: Patterned photoresist layers 402: First Implantation Process 406: Second Implantation Process d1: Interface depth d2: Maximum depth D: Duct region G1, G2: Gate L1, L2: Length LDD1: First LDD region LDD2, LDD2': The second pair of LDD regions O1, O2: Gate dielectric layer S: Source region S / D: Source / Drain Region s1, s2: Spacing

Claims

1. A laterally diffused metal-oxide-semiconductor structure, comprising: Base; A gate is formed on the surface of the substrate; A gate dielectric layer is disposed between the gate and the surface of the substrate; A well region is disposed within the surface of the substrate; at least one first lightly doped drain (LDD) region is disposed within the well region on one side of the gate; at least one second LDD region is disposed within the well region outside the at least one first LDD region on the side of the gate; and a source / drain region is formed within the at least one second LDD region, wherein the source / drain region is an N+ region, the at least one first LDD region and the at least one second LDD region are both N- regions, and the doping concentration distribution of the at least one first LDD region is the same as that of the at least one second LDD region.

2. The laterally diffused metal-oxide-semiconductor structure as claimed in claim 1, wherein the at least one first LDD region is a first pair of LDD regions, respectively disposed in the well regions on both sides of the gate; the at least one second LDD region is a second pair of LDD regions, respectively disposed in the well regions outside the first pair of LDD regions; and the source / drain region is formed in the second pair of LDD regions.

3. The laterally diffused metal-oxide-semiconductor structure as claimed in claim 2, wherein the doping concentration distribution of the first pair of LDD regions is the same as that of the second pair of LDD regions.

4. The laterally diffused metal-oxide-semiconductor structure as claimed in claim 2, wherein the first pair of LDD regions overlaps with the gate portion.

5. The laterally diffused metal-oxide-semiconductor structure as claimed in claim 2, wherein the second pair of LDD regions does not overlap with the gate.

6. The laterally diffused metal-oxide-semiconductor structure as claimed in claim 2, wherein the second pair of LDD regions located on the same side of the gate are connected to the first pair of LDD regions.

7. The laterally diffused metal-oxide-semiconductor structure as claimed in claim 5, wherein the interface depth between the second pair of LDD regions and the first pair of LDD regions is less than the maximum depth of the second pair of LDD regions.

8. The laterally diffused metal-oxide-semiconductor structure as claimed in claim 1, wherein the laterally diffused metal-oxide-semiconductor structure is a symmetrical or asymmetrical laterally diffused metal-oxide-semiconductor.

9. The laterally diffused metal-oxide-semiconductor structure as claimed in claim 1, wherein the at least one first LDD region is a first pair of LDD regions, respectively disposed in the well regions on both sides of the gate.

10. The laterally diffused metal-oxide-semiconductor structure as claimed in claim 1, wherein the at least one second LDD region is a second pair of LDD regions, respectively disposed in the well region on both sides of the gate.

11. The laterally diffused metal-oxide-semiconductor structure as claimed in claim 1, wherein the source / drain region is further formed in the well region on the other side of the gate.

12. A method for manufacturing a laterally diffused metal-oxide-semiconductor structure, comprising: A well zone is formed within the basement; At least one first lightly doped drain (LDD) region is formed within the well region, wherein the at least one first LDD region is an N- region; at least one second LDD region is formed within the well region outside the at least one first LDD region, wherein the at least one second LDD region is an N- region, and the doping concentration distribution of the at least one first LDD region is the same as that of the at least one second LDD region; a gate dielectric layer is formed on the surface of the substrate; a gate is formed on the gate dielectric layer, wherein the at least one first LDD region is located between the gate and the at least one second LDD region; and a source / drain region is formed within the at least one second LDD region, wherein the source / drain region is an N+ region.

13. A method for manufacturing a laterally diffused metal-oxide-semiconductor structure as claimed in claim 12, wherein the at least one first LDD region is a first pair of LDD regions, respectively formed in the well regions on both sides of the gate; the at least one second LDD region is a second pair of LDD regions, respectively formed in the well regions outside the first pair of LDD regions; and the source / drain region is formed in the second pair of LDD regions.

14. A method for manufacturing a laterally diffused metal-oxide-semiconductor structure as claimed in claim 13, wherein the methods for forming the first pair of LDD regions and forming the second pair of LDD regions include: Using the same implantation process, four separate lightly doped implantation regions are formed within this well area; And then annealing.

15. A method for manufacturing a laterally diffused metal-oxide-semiconductor structure as claimed in claim 13, wherein the methods for forming the first pair of LDD regions and forming the second pair of LDD regions include: The first implantation process is performed in the well area where the second pair of LDD zones are to be formed; A second implantation process is performed within the well area where the first pair of LDD zones are to be formed; and annealing is performed.

16. A method for manufacturing a laterally diffused metal-oxide-semiconductor structure as claimed in claim 13, wherein the doping concentration distribution of the first pair of LDD regions is the same as that of the second pair of LDD regions.

17. A method of manufacturing a laterally diffused metal-oxide-semiconductor structure as claimed in claim 13, wherein the gate is formed prior to the formation of the first pair of LDD regions.

18. A method for manufacturing a laterally diffused metal-oxide-semiconductor structure as claimed in claim 13, wherein the gate is formed after the second pair of LDD regions are formed.

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