Semiconductor devices including compound semiconductor materials with a superlattice layer, and method for making such semiconductor devices

Abstract

A semiconductor device may include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer may include a plurality of stacked layer groups, wherein each layer group includes a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer confined within a lattice of an adjacent substrate semiconductor portion. The semiconductor device may further include a group III nitride semiconductor stack including a plurality of group III nitride semiconductor layers located above the superlattice layer.

Description

[Technical Field]

[0001] This disclosure generally relates to semiconductor devices, and more specifically to semiconductor devices using enhanced semiconductor materials and related methods. [Previous Technology]

[0002] Numerous structures and techniques have been proposed to improve the performance of semiconductor devices by utilizing methods such as enhancing charge carrier mobility. For example, U.S. Patent Application No. 2003 / 0057416 by Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon, which also include impurity-free zones that would otherwise degrade performance in other ways. The biaxial strain created by these strained material layers in the upper silicon layer alters the carrier mobility, thereby enabling the fabrication of higher speed and / or lower power devices. U.S. Patent Application Publication No. 2003 / 0034529 by Fitzgerald et al. discloses a CMOS inverter based on a similar strained silicon technique.

[0003] U.S. Patent No. 6,472,685 B2, granted to Takagi, discloses a semiconductor device comprising a silicon and carbon layer sandwiched between silicon layers, such that the conduction band and valence band of the second silicon layer are subjected to tensile strain. Thus, electrons with a smaller effective mass, induced by the electric field applied to the gate, are confined within the second silicon layer, thereby indicating that its N-channel MOSFET has a higher mobility.

[0004] U.S. Patent No. 4,937,204, granted to Ishibashi et al., discloses a superlattice comprising a plurality of layers, fewer than eight monolayers, each containing a fractional or binary semiconductor layer or a binary compound semiconductor layer, wherein the plurality of layers are alternately grown epitaxially. The direction of the main current is perpendicular to each layer of the superlattice.

[0005] U.S. Patent No. 5,357,119 to Wang et al. discloses a silicon-germanium short-period superlattice that achieves higher mobility by reducing alloy scattering in the superlattice. Based on a similar principle, U.S. Patent No. 5,683,934 to Candelaria discloses a MOSFET with better mobility comprising a channel layer comprising an alloy of silicon and a second material, wherein the second material is present in a percentage of the silicon lattice to subject the channel layer to tensile stress.

[0006] U.S. Patent No. 5,216,262 granted to Tsu discloses a quantum well structure comprising two barrier regions and an epitaxially grown semiconductor thin layer sandwiched between them. Each barrier region is composed of approximately two to six alternating SiO2 / Si monolayers with a thickness ranging from one to the other. The barrier regions are further sandwiched with a much thicker silicon segment.

[0007] In an article titled "Phenomena in silicon nanostructure devices," published online on September 6, 2000, in *Applied Physics and Materials Science & Processing*, pp. 391–402, Tsu revealed a silicon / oxygen semiconductor-atomic superlattice (SAS). This silicon / oxygen superlattice structure was shown to be useful for silicon quantum and light-emitting devices. Specifically, it revealed how to fabricate and test a green electroluminescence diode structure. The current flow direction in this diode structure is vertical, that is, perpendicular to the SAS layers. The SAS revealed in this article can comprise semiconductor layers separated by adsorbed species such as oxygen atoms and CO molecules. The silicon grown outside the adsorbed oxygen monolayer is described as an epitaxial layer with a relatively low defect density. One of the SAS structures comprises a 1.1 nm thick silicon portion, approximately eight atomic layers thick, while the silicon portion of another structure is twice that thickness. In a paper titled "Chemical Design of Direct-Gap Light-Emitting Silicon" published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002), Luo et al. further discussed Tsu's luminescent SAS structure.

[0008] U.S. Patent No. 7,105,895 to Wang et al. discloses a thin silicon barrier structure with oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen, which can reduce the current flowing perpendicularly through the lattice by more than four orders of magnitude. Its insulating / barrier layer allows low-defect epitaxial silicon to be deposited adjacent to the insulating layer.

[0009] British Patent Application No. 2,347,520 by Mears et al., which has been published, discloses that aperiodic photonic band-gap (APBG) structures can be applied to electronic bandgap engineering. Specifically, the application discloses that material parameters, such as the location of band minimums and effective mass, can be adjusted to obtain new aperiodic materials with the desired band structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity, and dielectric or magnetic permeability, are also disclosed as potentially being designed into the material.

[0010] In addition, U.S. Patent No. 6,376,337 to Wang et al. discloses a method for fabricating an insulating or barrier layer for a semiconductor device, comprising depositing a layer of silicon and at least one other element on a silicon substrate such that the deposited layer is substantially defect-free, thereby allowing substantially defect-free epitaxial silicon to be deposited on the deposited layer. Alternatively, a monolayer may consist of one or more elements, preferably including oxygen, which is absorbed on the silicon substrate. Multiple insulating layers sandwiched between the epitaxial silicon form a barrier complex.

[0011] Although the above methods already exist, we hope to further enhance the use of advanced semiconductor materials and processing technologies in order to improve the performance of semiconductor devices. [Summary of the Invention]

[0012] A semiconductor device may include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer may include a plurality of stacked layer groups, wherein each layer group includes a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer confined within a lattice of an adjacent substrate semiconductor portion. The semiconductor device may further include a group III nitride semiconductor stack including a plurality of group III nitride semiconductor layers located above the superlattice layer.

[0013] In one example embodiment, the group III nitride semiconductor stack may include a group III nitride semiconductor nucleation layer adjacent to the superlattice layer, a group III nitride semiconductor transition layer adjacent to the group III nitride semiconductor nucleation layer, at least one group III nitride semiconductor buffer layer adjacent to the group III nitride semiconductor transition layer, a group III nitride semiconductor spacer layer adjacent to the at least one group III nitride semiconductor buffer layer, and a group III nitride semiconductor barrier layer adjacent to the group III nitride semiconductor spacer layer. For example, the group III nitride semiconductor nucleation layer may include aluminum nitride, the group III nitride semiconductor transition layer may include at least one of aluminum nitride, gallium nitride, and aluminum gallium nitride, the at least one group III nitride semiconductor buffer layer may include gallium nitride, the group III nitride semiconductor spacer layer may include aluminum nitride, and the group III nitride semiconductor barrier layer may include aluminum gallium nitride.

[0014] In some embodiments, the semiconductor substrate may include a single-crystal silicon substrate with a (111) crystal orientation offset angle of 0.5° or less. Meanwhile, for example, the substrate semiconductor monolayer may include silicon, and the at least one non-semiconductor monolayer may include oxygen and / or carbon.

[0015] A method for manufacturing a semiconductor device may include forming a superlattice layer on a semiconductor substrate, the superlattice layer comprising a plurality of stacked layer groups. Each layer group may include a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer confined within a lattice of an adjacent substrate semiconductor portion. The method may also include forming a group III nitride semiconductor stack comprising a plurality of group III nitride semiconductor layers located above the superlattice layer.

[0016] In one example embodiment, forming the group III nitride semiconductor stack may include forming a group III nitride semiconductor nucleation layer adjacent to the superlattice layer, forming a group III nitride semiconductor transition layer adjacent to the group III nitride semiconductor nucleation layer, forming at least one group III nitride semiconductor buffer layer adjacent to the group III nitride semiconductor transition layer, forming a group III nitride semiconductor spacer layer adjacent to the at least one group III nitride semiconductor buffer layer, and forming a group III nitride semiconductor barrier layer adjacent to the group III nitride semiconductor spacer layer.

[0017] For example, the group III nitride semiconductor nucleation layer may include aluminum nitride, the group III nitride semiconductor transition layer may include at least one of aluminum nitride, gallium nitride, and aluminum gallium nitride, the at least one group III nitride semiconductor buffer layer may include gallium nitride, the group III nitride semiconductor spacer layer may include aluminum nitride, and the group III nitride semiconductor barrier layer may include aluminum gallium nitride.

[0018] In one example embodiment, the semiconductor substrate may include a single-crystal silicon substrate with an offset angle of 0.5° or less for its (111) crystal orientation. For example, the substrate semiconductor monolayer may include silicon, and the at least one non-semiconductor monolayer may include oxygen and / or carbon.

Implementation Method

[0030] Exemplary embodiments are described in detail with reference to the accompanying drawings, which are exemplary embodiments. However, embodiments may be implemented in many different forms and should not be construed as limited to the specific examples provided in this specification. Rather, these embodiments are provided only to make the invention disclosed herein more complete and exhaustive. Throughout this specification and the drawings, the same reference numerals refer to the same elements, and apostrophes (') are used to identify similar elements in different embodiments.

[0031] Generally speaking, this disclosure relates to semiconductor devices that have an enhanced semiconductor superlattice inside to provide better performance. In this disclosure, the enhanced semiconductor superlattice may also be referred to as an MST layer or "MST technology".

[0032] In detail, the MST technology involves advanced semiconductor materials, such as the superlattice 25, which will be further described below. In previous literature, the applicant has reasoned that the superlattice structure described in this specification can reduce the effective mass of charge carriers, thereby increasing charge carrier mobility. For example, please refer to U.S. Patent No. 6,897,472, the entire contents of which are incorporated herein by reference.

[0033] Further development by the applicant confirms that the presence of an MST layer can advantageously improve the mobility of free carriers in semiconductor materials, such as at the interface between silicon and an insulator (such as SiO2 or HfO2). The applicant's theory (but not to be bound by this theory) suggests that this may occur through various mechanisms. One mechanism is to reduce the concentration of charged impurities near the interface, thereby reducing the diffusion of these impurities and / or trapping them to prevent them from reaching the vicinity of the interface. Charged impurities cause Coulomb scattering, which in turn reduces mobility. Another mechanism is to improve interface quality. For example, oxygen released from the MST film can provide oxygen to the Si-SiO2 interface, thereby reducing the presence of substoichiometric SiOx. Alternatively, the trapping of interstitials by the MST layer can reduce the concentration of interstitial silicon near the Si-SiO2 interface, thereby reducing the tendency to form substoichiometric SiOx. It is known that substoichiometric SiOx at the Si-SiO2 interface exhibits poorer insulating properties compared to stoichiometric SiO2. Reducing the amount of substoichiometric SiOx at the interface can more effectively confine free carriers (electrons or holes) within silicon, thereby increasing the mobility of these carriers under the influence of an electric field parallel to the interface. This is a standard practice in field-effect transistor (FET) structures. Scattering caused by the direct influence of the interface is called "surface-roughness scattering," which can be advantageously reduced by the presence of adjacent MST layers after tempering or during thermal oxidation.

[0034] In addition to their superior mobility, these MST structures are formed or used in a manner that enables them to provide piezoelectric, pyroelectric, and / or ferroelectric properties that are advantageous for various types of component applications, as further discussed in the applicant’s U.S. Patent No. 7,517,702, the entire contents of which are incorporated herein by reference.

[0035] Referring to Figures 1 and 2, the material or structure is in the form of a superlattice 25, the structure of which is controlled at the atomic or molecular level and can be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 comprises a plurality of stacked layer groups 45a-45n, as shown in the schematic cross-sectional view of Figure 1.

[0036] As shown in the figure, each layer group 45a-45n of the superlattice 25 includes a plurality of stacked substrate semiconductor monolayers 46 (which define individual substrate semiconductor portions 46a-46n) and a non-semiconductor monolayer 50 thereon. For clarity, the non-semiconductor monolayer 50 is represented by speckles in Figure 1.

[0037] As shown in the figure, the non-semiconductor monolayer 50 comprises a non-semiconductor monolayer that is confined within a lattice of an adjacent substrate semiconductor portion. The term "confined within a lattice of an adjacent substrate semiconductor portion" refers to at least some semiconductor atoms from the opposing substrate semiconductor portions 46a-46n being chemically bonded together through the non-semiconductor monolayer 50 between these opposing substrate semiconductor portions, as shown in Figure 2. Generally, this configuration can be made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n using atomic layer deposition technology, so that the available semiconductor bonding sites are not completely (i.e., not completely or less than 100% coverage) occupied by bonds to non-semiconductor atoms, as will be discussed further below. Therefore, when more semiconductor material monolayer 46 is deposited on or above a non-semiconductor monolayer 50, the newly deposited semiconductor atoms can fill the remaining unoccupied semiconductor atom bonding sites below the non-semiconductor monolayer.

[0038] In other embodiments, it is possible to use more than one such non-semiconductor monolayer. It should be noted that when this specification refers to a non-semiconductor monolayer or a semiconductor monolayer, it means that the material used in the monolayer, if formed in a bulk form, would be either non-semiconductor or semiconductor. That is, the characteristics exhibited by a single monolayer of a material (e.g., silicon) are not necessarily the same as those exhibited when formed in a bulk form or a relatively thick layer, as will be understood by those skilled in the art.

[0039] Furthermore, this superlattice structure can also advantageously serve as a barrier against the diffusion of dopants and / or materials between multiple layers vertically above and below the superlattice 25. Therefore, these characteristics advantageously allow the superlattice 25, in one example embodiment, to provide an interface for high-k dielectrics, which not only reduces the diffusion of high-k materials into the channel region but also advantageously reduces unwanted scattering effects and improves device mobility, as will be understood by those skilled in the art to which this invention pertains.

[0040] As shown in the figure, the superlattice 25 may also include a capping layer 52 above an upper layer group 45n. The capping layer 52 may include a plurality of substrate semiconductor monolayers 46. The capping layer 52 may include 2 to 100 monolayers of substrate semiconductors, preferably 10 to 50 monolayers.

[0041] Each substrate semiconductor portion 46a-46n may include one substrate semiconductor selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, group IV semiconductors also include group IV-IV semiconductors, as will be understood by those skilled in the art. More specifically, the substrate semiconductor may include, for example, at least one of silicon and germanium.

[0042] Each non-semiconductor monolayer 50 may comprise a non-semiconductor selected from, for example, the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor preferably also has the property of remaining thermally stable during the deposition of the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process, as will be understood by those skilled in the art to which this invention pertains.

[0043] It should be noted that the term "monolayer" here refers to a single atomic layer or a single molecular layer. It should also be noted that the non-semiconductor monolayer 50 provided by a single monolayer should also include monolayers where all possible positions are not fully occupied (i.e., incomplete or less than 100% coverage). For example, referring to the atomic diagram of Figure 2, it presents a 4 / 1 repeating structure with silicon as the substrate semiconductor material and oxygen as one of the bandgap modifiers. Only half of the possible positions for oxygen atoms are occupied.

[0044] In other embodiments and / or when using different materials, the occupancy is not necessarily half-full, as those skilled in the art will understand. In fact, those skilled in atomic deposition will understand that, even in this schematic diagram, it can be seen that in a given monolayer, individual oxygen atoms are not precisely aligned along a flat plane. For example, a preferred occupancy range is one-eighth to one-half of the possible oxygen positions being filled, but other occupancy ranges may be used in certain embodiments.

[0045] Since silicon and oxygen are currently widely used in general semiconductor manufacturing processes, manufacturers will be able to immediately apply the materials described in this specification. Atomic deposition or monolayer deposition are also widely used techniques. Therefore, semiconductor devices incorporating the superlattice 25 of this invention can be readily adopted and implemented, as will be understood by those skilled in the art.

[0046] Another embodiment of the superlattice 25' with different characteristics according to the present invention will now be described with reference to FIG. 3. In this embodiment, the repeating pattern is 3 / 1 / 5 / 1. More specifically, the bottommost substrate semiconductor portion 46a' has three monolayers, and the second bottom substrate semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25'. Each non-semiconductor monolayer 50' may contain a single monolayer. With regard to this silicon / oxygen superlattice 25', the increase in charge carrier mobility is independent of the orientation of the planes of these layers. Other elements in FIG. 3 not mentioned here are similar to those discussed above with reference to FIG. 1, and will not be discussed again.

[0047] In some embodiments, each substrate semiconductor portion of the superlattice may have the same number of monolayers of thickness. In other embodiments, at least some substrate semiconductor portions of the superlattice may have different numbers of monolayers of thickness. In still other embodiments, each substrate semiconductor portion of the superlattice may have different numbers of monolayers of thickness.

[0048] Referring now to the example embodiments of Figures 4 to 6, one or more of the above-described MST thin films are incorporated into group III nitride semiconductor (e.g., gallium nitride and aluminum nitride) devices to provide fabrication and / or performance advantages over conventional group III nitride devices. As background, various methods exist for fabricating group III nitride structures on silicon substrates, such as for high-power, high-frequency, and high-temperature applications. For example, these structures can be used in radio frequency transistors, power transistors, piezoelectric sensors, and optoelectronic devices (e.g., light-emitting diodes, micro-light-emitting diodes, lasers, optical detectors, etc.), as detailed below. However, due to material variations, such methods may suffer from excessive stress and / or bending.

[0049] As shown in the figure, the semiconductor device 100 of Figure 4 includes an MST thin film 125 on a substrate 101 to provide mechanical compliance for stress management. More specifically, in the illustrated example, the MST thin film 125 serves more as a mechanical interface between the silicon (111) substrate and the overlying stack 102 of the group III nitride layer than as an enhancement of the electrical behavior of the aforementioned MST thin film. More specifically, the applicant's theory (but not the applicant's intention to be bound by this theory) suggests that the MST thin film 125 interface will advantageously provide less stress in the overlying nitride film, thereby reducing wafer curvature (warpage / bending), which in turn facilitates the growth of a thicker gallium nitride layer.

[0050] Above the aluminum nitride nucleation layer 103 is a transition layer 104. The most common type of transition layer is a gradient aluminum gallium nitride layer as shown, or a superlattice of alternating semiconductor materials may also be used. Above the transition layer 104 is a first gallium nitride buffer layer 105, which is typically doped with, for example, carbon or iron to improve breakdown performance.

[0051] The nucleation layer 103, the transition layer 104, and the first gallium nitride buffer layer 105 are crucial for stress management. In the case of electronic components such as transistors, the thickness of the transition layer 104 and the first gallium nitride buffer layer 105 typically depends on the voltage (higher voltage = thicker epitaxy = more difficult). For example, for radio frequency and microwave applications (e.g., at operating voltage < 200V and operating frequency > 100MHz), the total thickness can be on the order of approximately 1.5µm, while for power electronics applications (e.g., at operating frequency < 10MHz), the total thickness can be on the order of approximately 4-6µm.

[0052] A second gallium nitride buffer layer 106 is located above the first gallium nitride buffer layer 105 and is typically undoped to promote the desired two-dimensional electron gas (2DEG) transport characteristics. Above the second gallium nitride buffer layer 106 is a barrier layer 107 (here, aluminum gallium nitride), which is the main driving factor for the on-state characteristics (drain current, pinch-off voltage, etc.). The illustrated configuration also provides an aluminum nitride spacer layer 108, a gallium nitride capping layer 109, and a SiNx capping layer, but these layers are provided as needed. The aluminum nitride spacer layer 108 helps enhance transport characteristics. The gallium nitride capping layer 109 helps reduce leakage current and / or customize surface characteristics, while the SiNx capping layer 110 helps passivate the surface.

[0053] The illustrated example also shows a 2DEG layer 112, which is an electron thin layer located below the aluminum nitride spacer layer 108 or at the interface between the aluminum gallium nitride barrier layer 107 and the second gallium nitride buffer layer 106. It should be noted that the 2DEG layer 112 is not grown as the other layers of the stack 102, but rather is a result of the layer design. The 2DEG layer 112 can carry current during device operation.

[0054] In the illustrated embodiment, the MST layer 125 is grown on a silicon (111) substrate 101, followed by the growth of a capping layer 152. Generally, the capping layer 152 is relatively small, allowing the MST film 125 to be close to the overlying layer (here, the aluminum nitride nucleation layer 103) to provide maximum stress relief. For example, the thickness of the capping layer 152 can be in the range of 3-5 nm, but other thicknesses can be used in different embodiments. In addition to the lattice mismatch between silicon (111) and aluminum nitride, there is also a lattice mismatch between aluminum nitride and gallium nitride, where the aluminum nitride lattice is slightly smaller. The MST film 125 can advantageously alleviate the stress caused by these two mismatches.

[0055] Different variations of the MST film 125 may also be used, such as using oxygen (MST-O) or carbon (MST-C) as the non-semiconductor material (or in some cases a combination of both). Other variations may include the number of layers / thickness, layer configuration (e.g., 3 / 1 / 5 / 1, 4 / 1, etc.), and the depth of the MST layer 125 in the substrate, which is determined by the thickness of the capping layer 152.

[0056] In this regard, Figure 5 provides another example semiconductor device 100', wherein the MST-C layer 125' is located directly adjacent to the aluminum nitride nucleation layer 103' on top of the substrate 101'. That is, this configuration incorporates the MST-C thin film 125' (e.g., an MST thin film comprising a silicon monolayer 46 and a carbon non-semiconductor monolayer 50), which is designed to house a large amount of carbon within the silicon substrate 101', and more specifically, very close to the surface (and may not have a capping layer). The applicant's theory (but does not wish to be bound by this theory) suggests that this could advantageously transform the surface of the substrate 101' into a "silicon carbide-like" substrate, meaning that it offers the advantages of silicon carbide (a wide-bandgap semiconductor material that has a better lattice match with gallium nitride than silicon) without the high costs associated with fabricating a full silicon carbide substrate. The MST-C thin film 125' exhibits properties similar to silicon carbide, which can provide improved lattice matching and enhanced thermal conductivity, as will be understood by those skilled in the art.

[0057] For this application, the MST-C thin film 125' can be grown using a layering method similar to that described above, and different silicon carbide "characteristics" can be provided by tempering at different temperatures. That is, although the MST-C thin film 125' is not bulk silicon carbide, the applicant's theory is that it will exhibit sufficient bulk silicon carbide characteristics to achieve the aforementioned advantages in improved lattice matching and thermal conductivity compared to silicon substrates.

[0058] This method is particularly advantageous because it overcomes the difficulties of previous attempts to grow epitaxial silicon carbide on silicon, such as nucleation and registry. Although the evolution of lattice mismatch and defect structures may be reduced when gallium nitride is grown over the MST-C thin film 125', the aluminum nitride nucleation layer 103' can still be used (although it may be omitted in some configurations). Further details regarding the bonding of carbon monolayers in the MST thin film are set forth in U.S. Patent No. 11,837,634 to Weeks et al., which has been assigned to the applicant and is incorporated herein by reference in its entirety.

[0059] In some embodiments, element 100 or 100' can be used in radio frequency (RF) applications, wherein the MST film 125 is used to reduce parasitic channel effects. As background, during the nucleation and growth of gallium nitride on a silicon substrate, group III materials diffuse into the substrate. This forms a P-type region in the substrate 101, thereby creating parasitic channels. Since the MST film 125 can influence the dopant diffusion profile and help terminate diffusion tailing into silicon, positioning the MST film 125 relatively close to the surface of the substrate 101 can similarly suppress dopant diffusion into the substrate beneath the MST film. For example, in the case of RF components, this can advantageously provide improved power and efficiency and reduce microwave losses.

[0060] Conventional methods for suppressing this diffusion involve lowering the processing temperature. However, this can lead to other problems, particularly in terms of stress management. The method of the present invention, incorporating the MST film 125, allows for the reduction of parasitic channels while also allowing fabrication at higher desired temperatures to enhance stress management. Furthermore, those skilled in the art will understand that in some embodiments, the MST film 125 can also achieve localization of the anti-charge (dopane) to counteract any potential dopant that may penetrate from above.

[0061] In some embodiments, a nitrogen-containing MST film 125 may be used to provide beneficial effects relative to the aluminum nitride nucleation layer 103. More specifically, the applicant's theory (but not to be bound by it) suggests that the nitrogen-containing MST film 125 can reduce complexity by using the same material (N) as the top nucleation layer 103 (aluminum nitride). Furthermore, in some configurations, a silicon nitride barrier layer between the substrate and the nucleation layer 103 may also help reduce aluminum migration.

[0062] Referring now to FIG6, in some embodiments, the MST film 125 can serve as a self-separating layer to advantageously peel off the stack 102 of group III nitride epitaxial crystals. More specifically, if the MST film 125 is close to the surface of the silicon substrate 101, the MST film can serve as a separation layer (by definition, a layer with weaker mechanical strength) to separate or remove the layer above the MST film from the substrate 101 below. This can be done mechanically, as will be understood by those skilled in the art to which this invention pertains. The technical advantage provided by this method is that if the top cap layer 152 is used sparingly or not at all, everything above the MST spacer layer 125 is group III nitride and can be relatively easily bonded to a second substrate 113, such as a heat sink (e.g., for power components), a sapphire substrate (e.g., for optical components), or in some cases, can be used with both ends exposed (e.g., for front and back transmission).

[0063] To function as a separation layer, in some embodiments, the MST film 125 may have a higher concentration of non-semiconductor atoms than for applications used to enhance conductivity. In other words, in the case of the MST-O layer 125 (silicon / oxygen), the MST layer may be closer to an oxide layer and exhibit less bulk silicon characteristics, as will be understood by those skilled in the art. Oxygen-based MST films allow for the isolation of hydrogen adjacent to oxygen, which can be used to help weaken bonds and reduce strength. Therefore, in some embodiments, hydrogen may be introduced into the stack to reduce the strength of the MST layer 125, making it a separation layer.

[0064] For applications such as micro-light-emitting diodes, the stripped group III nitride stack can be bonded to a pre-patterned complete CMOS digital wafer and interconnected through group III materials to produce a light-emitting diode display, as will be understood by those skilled in the art. Examples of nitrides that can be used for different applications above the separation layer include aluminum nitride, gallium nitride, indium nitride, scandium nitride, and their alloys.

[0065] It should be noted that the MST layer 125 can be used with a variety of different (111) wafer configurations, including on-axis and off-axis wafers. For many applications, silicon (111) wafers have an off-cut angle of about 4°, while conventional gallium nitride device implementations use on-axis (no off-cut angle, 0°) silicon (111) wafers. The applicant's theory (but the applicant does not wish to be bound by this theory) suggests that the MST film can advantageously provide stress harmonization for a relatively wide range of wafers, including on-axis (111) wafers and 4° off-axis (111) wafers. In some embodiments, to minimize the lattice mismatch between silicon (111) and aluminum nitride, it may be desirable to use on-axis (111) wafers or off-axis wafers with an off-cut angle of about 0.5° or less. For another example, the thickness of the MST thin film 125 can be as high as about 100 nm, and more specifically in the range of about 20 nm to 100 nm.

[0066] The illustrated structure 100 is used for electronic components, but those skilled in the art will understand that many other embodiments are possible and fall within the scope of this disclosure, which combine different configurations of Group IIIA / B materials on top to manufacture different types of circuits. Utilizing these different component configurations, the interface of the MST thin film 125 can advantageously provide less end wafer warp compared to conventional components without this interface. In addition to creating a mechanically compliant layer to improve stress / strain control of gallium nitride epitaxy, the MST layer 125 also provides other technical advantages, including: the ability to use SEMI standard substrates instead of thicker silicon substrates; the ability to grow thinner epitaxial stacks (improving reactor yield); and improved Group III nitride crystal quality.

[0067] Referring also to flowchart 170 of FIG7, a method for manufacturing the above-described structure begins at block 171. In block 172, a superlattice 125 (or 125' in the case of element 100') is formed on substrate 101. Then, in block 173, a group III nitride stack 102 may be formed on superlattice 125 / capping layer 152. In block 174, as in some embodiments described above, the gallium nitride stack 102 may be separated from substrate 101 as needed and bonded to a second substrate 113 (block 175), or exposed at both ends for use. As shown, the method of FIG7 ends at block 176.

[0068] Referring now to the exemplary embodiments of Figures 8 and 9, MST films 225, 225' are advantageously integrated into piezoelectric elements or filters 200, 200'. The illustrated elements incorporate MST films 225, 225' at a relatively shallow depth in the substrates 201, 201' (e.g., silicon (111) substrates) to provide the stress management described above. Similarly, the depth of the capping layers 252, 252' can vary as needed and may be omitted in some cases. In the same manner as described above, MST films 225, 225' advantageously allow high-quality (i.e., fewer defects) piezoelectric layers 214, 214' to be grown on the substrates 201, 201'. In the illustrated example, piezoelectric layers 214, 214' are crystalline aluminum nitride filter materials, but different piezoelectric materials (including aluminum nitride, scandium nitride, or alloys thereof) may be used in different embodiments.

[0069] Furthermore, the piezoelectric filters 200, 200' further include electrodes 215, 215' located on the piezoelectric layers 214, 214'. The former is configured to generate acoustic waves along the surface of the piezoelectric layer to define a surface acoustic wave (SAW) filter (Figure 8), and the latter is configured to generate acoustic waves within the piezoelectric layer to define a bulk acoustic wave (BAW) filter (Figure 9). In addition, the MST layers 225, 225' can also reduce the curvature (warpage and / or bending) after wafer growth, as described above.

[0070] Referring also to flowchart 270 of Figure 10, starting at block 271, as shown, a method for fabricating piezoelectric elements 200, 200' includes forming superlattice layers 225, 225' (and optionally capping layers 252, 252') on substrates 201, 201' (block 272), and then forming piezoelectric layers 214, 214' above the superlattice (block 273). For example, crystalline aluminum nitride or other suitable piezoelectric materials can be used. Furthermore, in block 274, electrodes 215, 215' are formed in a suitable configuration of a particular element (e.g., SAW or BAW). As shown, the method of Figure 10 ends at block 275.

[0071] Referring now to the example embodiment of FIG11, an MST thin film is advantageously integrated into a CMOS / Group III nitride hybrid device 300. As background, attempts have been made to integrate gallium nitride devices directly with silicon logic circuits. However, such methods are generally not feasible for wafer-scale integration. Part of the difficulty lies in the fact that the fabrication of CMOS devices requires silicon with a crystal orientation (100). However, as mentioned above, this is not ideal for the formation of Group III nitride materials. Instead, a first MST layer 325a (and a capping layer 352a, if desired) is formed on a silicon (111) processing wafer 301. The active element layer 311 and the buried oxide (BOX) layer 303 of silicon (100) are located above the MST thin film 325a and the capping layer 352a above the processing wafer 301 to form silicon CMOS circuit elements 313. However, between the CMOS element regions, silicon (100) can be etched down to the silicon (111) processing wafer 301. A group III nitride element layer 312 can be epitaxially grown in this window (trench), on which second-type circuit elements 314 can be formed to provide the hybrid circuit configuration. Thus, the group III nitride element layer 312 can have lower stress, as further described above.

[0072] In the illustrated example, a second MST layer 325b (and a capping layer 352b, if desired) is disposed beneath one (or more) CMOS circuit elements 313 to provide features such as enhanced mobility and / or dopant profile control, as described above. In some embodiments, the first MST layer 325a on the silicon (111) processing wafer 301 may comprise carbon (MST-C), as described above. Generally, the processing wafer 301 may experience relatively high temperature fluctuations, for which the MST-C thin film 325a is particularly advantageous, as will be understood by those skilled in the art to which this invention pertains.

[0073] In one example embodiment, the example CMOS / III-family integration can be used in microprocessor circuits that typically require downconversion to achieve a suitable low operating voltage. The example embodiment advantageously allows this step to be performed locally when needed, which the applicant theoretically believes (but does not wish to be bound by) can significantly save energy in microprocessor applications. This method can also be applied to other types of electronic components (e.g., RF transistors, power transistors, etc.), piezoelectric sensors, and optoelectronic components (e.g., light-emitting diodes, micro-light-emitting diodes, lasers, optical detectors, etc.).

[0074] The example configuration advantageously allows for the monolithic integration of silicon CMOS devices 313 and group III nitride (e.g., gallium nitride) devices 314 on bonded SOI wafers with different silicon orientations. Other methods may employ cavity SOI, etc., as will be understood by those skilled in the art to which this invention pertains. Furthermore, the method of this invention combines the advantages of MST thin films for independent group III nitride epitaxial structures and utilizes these advantages to improve the ability of heterogeneous integration (i.e., reducing stress and / or the ability to grow thinner films).

[0075] Referring now to flowchart 370 of FIG12, a method for manufacturing a hybrid semiconductor device 300 begins at block 371, which forms an MST layer 325a (and, if desired, a capping layer 352a) on a processing wafer 301 (block 372). As shown, the method further includes forming a first silicon element layer 311 (e.g., a silicon (100) layer) on the superlattice 325a (block 373), and forming a second element layer 312 laterally adjacent to the first element layer on the superlattice (block 374). The second element layer 312 comprises a group III nitride semiconductor (e.g., gallium nitride, aluminum nitride, or a stack of group III nitride material layers as described above). As shown in blocks 375 to 376, the method also includes forming a first element 313 (e.g., CMOS) on the first element layer 311, and forming a second element 314 on the second element layer 312. As shown in the figure, the method in Figure 12 ends at square 377.

[0076] In a variation of the above embodiments, the MST film can be used to deliver non-semiconductor atoms (e.g., oxygen, carbon, nitrogen) to the silicon / aluminum nitride interface. More specifically, the MST film can be tempered at a relatively high temperature, causing atoms from the non-semiconductor monolayer to be repositioned from their original positions in the MST film of the silicon substrate to the silicon / aluminum nitride interface region. For example, tempering or heating can be performed before, during, or after the aluminum nitride formation step, causing non-semiconductor atoms from the MST layer to accumulate at the silicon / aluminum nitride interface.

[0077] As further described in U.S. Patent No. 10,109,479, which is also assigned to the assignee and whose entire contents are incorporated herein by reference, the embedded insulating layer can be formed by depositing an MST layer and then tempering the structure. Tempering can be performed in an inert atmosphere (e.g., nitrogen, argon, helium, etc.) at about 750°C or higher, preferably in a temperature range of about 800°C to 1000°C. In some embodiments, a non-inert atmosphere (e.g., hydrogen) may also be used, depending on the temperature range used. For example, with oxygen, tempering causes the inserted non-semiconductor monolayer to decompose spinodally.

[0078] The applicant's theory (but not to be bound by it) suggests that oxygen atoms in the oxygen-MST layer (MST-O) will diffuse, and some of these oxygen atoms will relocate to the silicon / aluminum nitride interface. According to embodiments, the original MST film structure may no longer exist after tempering and / or further processing. It should be understood that the tempering time, temperature, and environment, as well as the dosage and monolayer spacing in the examples, can vary depending on the specific application and the materials used. Generally, the number of non-semiconductor atoms located at the silicon / aluminum nitride interface can be 40% to 60% of the number of non-semiconductor atoms in the initially formed MST film.

[0079] The applicant's theory is that repositioning non-semiconductor atoms to the silicon / aluminum nitride interface can provide similar stress-relieving benefits to the MST film directly adjacent to the interface, as described above. That is, both methods can be used to position non-semiconductor atoms in the directly adjacent interface region or in the interface region, but in slightly different ways.

[0080] This result can also be achieved using other methods in different embodiments, such as depositing a single non-semiconductor monolayer on top of the silicon substrate before forming the aluminum nitride layer. In this case, the number of deposited non-semiconductor atoms may still be relatively low, allowing semiconductor bonds to propagate between the non-semiconductor atoms to sustain crystal growth, as described above regarding MST thin film formation. In yet another example method, non-semiconductor atoms can be embedded into the silicon / aluminum nitride interface to achieve stress-reducing properties.

[0081] Those skilled in the art to which this invention pertains will benefit from the content disclosed in this specification and the accompanying drawings, thereby conceiving various modifications and other embodiments. Therefore, it should be understood that this invention is not limited to the specific embodiments disclosed in this specification, and related modifications and embodiments also fall within the scope of the appended patent applications. [Simplified Explanation of the Diagram]

[0019] Figure 1 is an enlarged schematic cross-sectional view of a superlattice for a semiconductor device according to an example embodiment.

[0020] Figure 2 is a perspective atomic diagram of a portion of the superlattice shown in Figure 1.

[0021] Figure 3 is an enlarged schematic cross-sectional view of a superlattice according to another example embodiment.

[0022] Figure 4 is a schematic cross-sectional view of a semiconductor device comprising a stack of group III nitride semiconductors with a superlattice layer, which provides advantages in the example embodiment.

[0023] Figure 5 is a schematic cross-sectional view of another semiconductor device, which includes a stack of group III nitride semiconductors with a superlattice layer that provides enhanced stress / strain control in the example embodiment.

[0024] FIG6 is a schematic cross-sectional view illustrating, according to an example embodiment, the group III nitride semiconductor stack of FIG4 and the silicon (111) substrate separated at the superlattice layer to couple with the second substrate.

[0025] Figure 7 is a flowchart illustrating the method of manufacturing the embodiments of Figures 4 to 6.

[0026] Figures 8 and 9 are schematic cross-sectional views of an exemplary piezoelectric element, which includes a group III nitride piezoelectric layer located on a superlattice layer.

[0027] Figure 10 is a flowchart illustrating an example method for manufacturing the piezoelectric elements of Figures 8 and 9.

[0028] Figure 11 is a schematic cross-sectional view of a semiconductor device that simultaneously contains group III nitride and silicon circuit regions above a superlattice.

[0029] Figure 12 is a flowchart illustrating the method of manufacturing the semiconductor device of Figure 11.

Claims

1. A semiconductor element, comprising: A single-crystal silicon substrate having a (111) crystal orientation with an offset angle of 0.5° or less; a superlattice layer on the single-crystal silicon substrate comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer confined within a lattice of an adjacent substrate semiconductor portion, and a capping layer located above the highest of the plurality of stacked layer groups, the capping layer having a thickness in the range of 3 nm to 5 nm; and a group III nitride semiconductor stack located above the superlattice layer and comprising a group III nitride semiconductor nucleation layer adjacent to the capping layer, a group III nitride semiconductor transition layer adjacent to the group III nitride semiconductor nucleation layer, and at least one group III nitride semiconductor buffer layer adjacent to the group III nitride semiconductor transition layer.

2. The semiconductor device of claim 1, wherein the group III nitride semiconductor nucleation layer comprises aluminum nitride.

3. The semiconductor device of claim 1, wherein the group III nitride semiconductor transition layer comprises at least one of aluminum nitride, gallium nitride, and aluminum gallium nitride.

4. The semiconductor device of claim 1, wherein the at least one group III nitride semiconductor buffer layer comprises gallium nitride.

5. The semiconductor device of claim 1, wherein the group III nitride semiconductor stack further comprises: A group III nitride semiconductor spacer layer adjacent to the at least one group III nitride semiconductor buffer layer; and a group III nitride semiconductor barrier layer adjacent to the group III nitride semiconductor spacer layer.

6. The semiconductor device of claim 5, wherein the group III nitride semiconductor spacer layer comprises aluminum nitride.

7. The semiconductor device of claim 5, wherein the group III nitride semiconductor barrier layer comprises aluminum gallium nitride.

8. The semiconductor device of claim 1, wherein the substrate semiconductor monolayer comprises silicon.

9. The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer comprises oxygen.

10. The semiconductor element of claim 1, wherein the at least one non-semiconductor monolayer comprises carbon.

11. A method for manufacturing a semiconductor device, comprising: A superlattice layer is formed on a single-crystal silicon substrate having a (111) crystal orientation and an offset angle of 0.5° or less. The superlattice layer includes a plurality of stacked layer groups, each layer group including a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer confined within a lattice of an adjacent substrate semiconductor portion. A capping layer is formed on top of the tallest of the plurality of stacked layer groups, the thickness of the capping layer being in the range of 3 nm to 5 nm. A group III nitride semiconductor stack is formed on top of the superlattice layer and includes a group III nitride semiconductor nucleation layer adjacent to the capping layer, a group III nitride semiconductor transition layer adjacent to the group III nitride semiconductor nucleation layer, and at least one group III nitride semiconductor buffer layer adjacent to the group III nitride semiconductor transition layer.

12. The method of claim 11, wherein the group III nitride semiconductor nucleation layer comprises aluminum nitride.

13. The method of claim 11, wherein the group III nitride semiconductor transition layer comprises at least one of aluminum nitride, gallium nitride, and aluminum gallium nitride.

14. The method of claim 11, wherein the at least one group III nitride semiconductor buffer layer comprises gallium nitride.

15. The method of claim 11, wherein forming the group III nitride semiconductor stack further comprises: A group III nitride semiconductor spacer layer is formed adjacent to the at least one group III nitride semiconductor buffer layer; and a group III nitride semiconductor barrier layer is formed adjacent to the group III nitride semiconductor spacer layer.

16. The method of claim 15, wherein the group III nitride semiconductor spacer layer comprises aluminum nitride.

17. The method of claim 15, wherein the group III nitride semiconductor barrier layer comprises aluminum gallium nitride.

18. The method of claim 11, wherein the substrate semiconductor monolayer comprises silicon.

19. The method of claim 11, wherein the at least one non-semiconductor monolayer comprises oxygen.

20. The method of claim 11, wherein the at least one non-semiconductor monolayer comprises carbon.

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