Semiconductor memory devices

Abstract

An embodiment provides a semiconductor memory device and a semiconductor device capable of manufacturing high-quality semiconductor devices. The semiconductor memory device of this embodiment includes: an oxide semiconductor extending in a vertical direction; a first electrode comprising a first conductor containing a first oxide conductive material and connected to the upper end of the oxide semiconductor; a gate electrode, separated by a gate insulating film and facing the oxide semiconductor; a second electrode disposed below the oxide semiconductor and extending in the vertical direction; a dielectric layer disposed on the outer peripheral surface of the second electrode; and a third electrode disposed on the outer peripheral surface of the dielectric layer. The second electrode comprises a second conductor containing a second oxide conductive material and connected to the lower end of the oxide semiconductor, and has an facing surface that faces the inner peripheral surface of the third electrode across the dielectric layer.

Description

Technical Field

[0001] [References to related applications] This application enjoys priority to Japanese Patent Application No. 2024-158967 (filed on September 13, 2024). This application includes all contents of the basic application by reference to that basic application.

[0002] This embodiment relates to a semiconductor memory device and a semiconductor device. Prior Technology

[0003] In semiconductor devices, metal oxides containing indium and tin are sometimes used in the electrodes. Summary of the Invention

[0004] In the manufacturing process of semiconductor devices that use metal oxides in electrodes, a technique is required to produce high-quality semiconductor devices.

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device and a semiconductor device capable of manufacturing high-quality semiconductor devices.

[0006] An embodiment of the semiconductor memory device includes: an oxide semiconductor extending in a vertical direction; a first electrode comprising a first conductor containing a first oxide conductive material and connected to the upper end of the oxide semiconductor; a gate electrode, separated from the oxide semiconductor by a gate insulating film and facing the oxide semiconductor; a second electrode disposed below the oxide semiconductor and extending in the vertical direction; a dielectric layer disposed on the outer peripheral surface of the second electrode; and a third electrode disposed on the outer peripheral surface of the dielectric layer, wherein the second electrode comprises a second conductor containing a second oxide conductive material and connected to the lower end of the oxide semiconductor, and has a facing surface that faces the inner peripheral surface of the third electrode across the dielectric layer.

[0007] The semiconductor device of one embodiment includes: an oxide semiconductor extending in a vertical direction; a first electrode comprising a first conductor containing a first oxide conductive material and connected to the upper end of the oxide semiconductor; a gate electrode having a gate insulating film separating it from the oxide semiconductor; and a second electrode connected to the lower end of the oxide semiconductor and containing a second oxide conductive material, wherein the oxide semiconductor does not contact a first contact portion of the second electrode or a gap contained in the second electrode.

[0008] An embodiment of the semiconductor memory device includes: the semiconductor device; a first capacitor electrode connected to a second electrode; a second capacitor electrode facing the first capacitor electrode; and a dielectric film disposed between the first capacitor electrode and the second capacitor electrode. Simple Explanation of the Diagram

[0009] Figure 1 is a circuit diagram illustrating an example of the circuit structure of the memory cell array in the first embodiment. Figure 2 is a cross-sectional schematic diagram illustrating a structural example of a semiconductor memory device in the first embodiment, showing a cross-sectional view parallel to the ZX plane. Figure 3 shows a detailed cross-sectional view of the semiconductor memory device 101 when observed in a cross-section 70ZX parallel to the ZX plane and within the oxide semiconductor layer 70. Figure 4 shows a detailed cross-sectional view of the semiconductor memory device 101 when observed in a cross-section 70YZ parallel to the YZ plane and contained in the oxide semiconductor layer 70. Figure 5 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 6 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 7 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 8 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 9 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 10 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 11 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 12 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 13 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 14 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 15 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 16 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 17 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 18 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 19 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 20 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 21 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 22 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 23 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 24 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the semiconductor memory device in the first embodiment. Figure 25 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the capacitor in the first embodiment. Figure 26 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the capacitor in the first embodiment. Figure 27 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the capacitor in the first embodiment. Figure 28 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the capacitor in the first embodiment. Figure 29 is a cross-sectional view parallel to the YZ plane showing the manufacturing process of the capacitor in the first embodiment. Figure 30 shows a detailed cross-sectional view of a modified example of the semiconductor memory device 101 when observed in a cross-section 70ZX parallel to the ZX plane and in a cross-section 70ZX contained in the oxide semiconductor layer 70. Figure 31 shows a detailed cross-sectional view of a modified example of the semiconductor memory device 101 when observed in a cross-section 70YZ parallel to the YZ plane and in a cross-section 70YZ contained in the oxide semiconductor layer 70. Figure 32 shows a cross-sectional view of the semiconductor memory device 102 when observed in a cross-section 70ZX parallel to the ZX plane and in a cross-section 70ZX contained in the oxide semiconductor layer 70. Figure 33 is a plan view of capacitor 120 viewed from above. Figure 34 is a schematic diagram illustrating the gap 301. Figure 35 is a plan view of the metal oxide layer 50a viewed from below. Figure 36 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device of the comparative example. Figure 37 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device of the comparative example. Figure 38 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device of the comparative example. Figure 39 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device of the comparative example. Figure 40 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor device of the comparative example. Figure 41 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor memory device in the second embodiment. Figure 42 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor memory device in the second embodiment. Figure 43 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor memory device in the second embodiment. Figure 44 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor memory device in the second embodiment. Figure 45 is a cross-sectional view parallel to the ZX plane showing the manufacturing process of the semiconductor memory device in the second embodiment. Figure 46 is a diagram illustrating a modified example of slit 301, namely slit 302. Figure 47 is a diagram illustrating a modified example of slit 301, namely slit 303. Figure 48 is a diagram illustrating a modified example of slit 301, namely slit 304. Figure 49 is a diagram illustrating a modified example of slit 301, namely slit 305. Implementation

[0010] The present embodiment will now be described with reference to the accompanying drawings. To facilitate understanding, the same symbols will be used to label the same components in each drawing as much as possible, and repeated descriptions will be omitted.

[0011] [First Implementation Form] The structure of the semiconductor memory device according to the first embodiment will be described. In various figures, the X-axis, Y-axis, and Z-axis are sometimes shown. The X-axis, Y-axis, and Z-axis form a right-handed three-dimensional orthogonal coordinate system. Hereinafter, the direction of the arrow on the X-axis is sometimes referred to as the X-axis+ direction, and the direction opposite to the arrow is sometimes referred to as the X-axis- direction; the same applies to the other axes. Furthermore, the Z-axis+ direction and the Z-axis- direction are sometimes referred to as "above" and "below," respectively. Additionally, the planes orthogonal to the X-axis, Y-axis, or Z-axis are sometimes referred to as the YZ plane, ZX plane, or XY plane, respectively. Furthermore, the Z-axis direction is sometimes referred to as the "vertical direction." "Above," "below," and "vertical direction" are merely terms indicating relative positional relationships within the figures and are not terms defining orientations based on the vertical direction.

[0012] In addition, except where specifically described, the dimensions of the constituent components shown in the figures are sometimes shown differently from the actual dimensions in order to facilitate understanding of the explanation.

[0013] In this specification, "connection" includes not only physical connection but also electrical connection, and unless otherwise specified, "connection" includes not only direct connection but also indirect connection.

[0014] In this specification, "formed above" includes not only the case where it is formed in contact with the ground above, but also the case where it is formed above, separated from other objects, unless otherwise specified. The same applies to cases such as "formed below".

[0015] The semiconductor memory device 101 in the first embodiment is an oxide semiconductor-random access memory (OS-RAM) including an array of memory cells.

[0016] As shown in Figure 1, the memory cell array includes: multiple memory cells MC, multiple word lines WL, and multiple bit lines BL.

[0017] In Figure 1, as an example of multiple character lines WL, character lines WL n, WL n+1, and WL n+2 are shown (where n is a positive integer). Additionally, in Figure 1, as an example of bit lines BL, bit lines BL m, BL m+1, and BL m+2 are shown (where m is a positive integer). Furthermore, the number of memory cells MC is not limited to the number shown in Figure 1.

[0018] Multiple memory cells (MCs) can be arranged in a matrix to form a memory cell array. A memory cell (MC) includes a memory transistor (MTR) that is a field-effect transistor (FET) and a memory capacitor (MCP).

[0019] A series of memory cells MC arranged along the column direction are connected to the word line WL (e.g., word line WL n) corresponding to their respective column (e.g., the nth column). A series of memory cells MC arranged along the row direction are connected to the bit line BL (e.g., bit line BL m+2) corresponding to their respective row (e.g., the (m+2)th row).

[0020] In detail, the gate of the memory transistor MTR contained in the memory cell MC is connected to the word line WL corresponding to the column to which the memory cell MC belongs. One of the sources or drains of the memory transistor MTR is connected to the bit line BL corresponding to the row to which the memory cell MC belongs.

[0021] One electrode of the memory capacitor MCP contained in the memory cell MC is connected to either the source or the drain of the memory transistor MTR contained in the memory cell MC. The other electrode of the memory cell MC is connected to a power supply line (not shown) that supplies a specific potential.

[0022] The memory cell MC is configured such that, by switching the memory transistor MTR based on the potential of the corresponding word line WL, data can be retained by accumulating charge in the memory capacitor MCP caused by the current flowing through the corresponding bit line BL.

[0023] As shown in Figure 2, the semiconductor memory device 101 includes: a semiconductor substrate 10, a circuit 11 (an example of a "semiconductor circuit"), a capacitor 20, a semiconductor device 30, a conductor 33, an insulating layer 34, an insulating layer 35, and an insulating layer 63.

[0024] The capacitor 20 includes: a dielectric layer 22 (an example of a "dielectric film"), a conductor 23, an electrode 24 (a "second electrode"), and an electrode 25 (an example of a "third electrode" and a "second capacitor electrode").

[0025] The semiconductor device 30 includes: a field-effect transistor 40 (an example of a "semiconductor element"), an electrode 50 disposed above the field-effect transistor 40 (an example of a "first electrode"), and an electrode 24 disposed below the field-effect transistor 40 (an example of a "second electrode").

[0026] The field-effect transistor 40 includes: an oxide semiconductor layer 70 (an example of "oxide semiconductor"), a gate insulating film 43, a conductive layer 42 (an example of "gate electrode"), and an insulating layer 45. The field-effect transistor 40 corresponds to the memory transistor MTR of the memory cell MC (see Figure 1).

[0027] An oxide semiconductor layer 70 is formed in the insulating layer 45 and has an upper end 70a and a lower end 70b. The oxide semiconductor layer 70 is a columnar body extending in the vertical direction. The oxide semiconductor layer 70 has a central axis 70d (an example of a "second central axis") that is substantially parallel to the Z-axis. The oxide semiconductor layer 70 forms the channel of the field-effect transistor 40. The oxide semiconductor layer 70 has an amorphous structure.

[0028] The oxide semiconductor layer 70 is an oxygen-deficient semiconductor that serves as a donor. The oxide semiconductor layer 70 contains at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), iridium (Ir), ruthenium (Ru), and titanium (Ti), as well as oxygen.

[0029] In this embodiment, the oxide semiconductor layer 70 includes indium, zinc, and gallium as metal elements. Specifically, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, namely indium gallium zinc oxide (IGZO) (InGaZnO). Furthermore, the oxide semiconductor layer 70 may also be other types of oxide semiconductors.

[0030] The field-effect transistor 40 is a so-called vertical transistor having a channel extending in the Z-axis direction (vertical direction) that is substantially perpendicular to the surface of the semiconductor substrate 10.

[0031] The conductive layer 42 is separated from the gate insulating film 43 and faces the oxide semiconductor layer 70. Specifically, the conductive layer 42 functions as the gate electrode of the field-effect transistor 40, and the gate insulating film 43 surrounds the oxide semiconductor layer 70 between the upper end 70a and the lower end 70b. The conductive layer 42 may contain, for example, tungsten (W).

[0032] The conductive layer 42 consists of a plurality of electrodes that extend substantially parallel to the Y-axis and are repeatedly arranged in the X-axis direction. These electrodes correspond to the character lines WL (see Figure 1).

[0033] The gate insulating film 43 may include, for example, a silicon nitride film (Si3N4) containing silicon and nitrogen. The gate insulating film 43 is formed in such a way that it covers the entire periphery of the side surface of the oxide semiconductor layer 70.

[0034] Electrode 50 is formed above oxide semiconductor layer 70 and connected to the upper end 70a of oxide semiconductor layer 70. Electrode 50 includes: metal oxide layer 50a (an example of "first conductor"), barrier metal layer 50b, and metal film 50c.

[0035] The metal oxide layer 50a is connected to the upper end 70a of the oxide semiconductor layer 70. In this embodiment, the metal oxide layer 50a is in contact with the upper end 70a of the oxide semiconductor layer 70. The metal oxide layer 50a contains a first oxide conductive material. Specifically, the first oxide conductive material is an oxide conductive material containing indium and tin as metal elements. More specifically, the first oxide conductive material is indium tin oxide (ITO).

[0036] A metal film 50c is disposed above the metal oxide layer 50a and contains tungsten. A barrier metal layer 50b is formed between the metal oxide layer 50a and the metal film 50c. The barrier metal layer 50b contains, for example, titanium and nitrogen. In this embodiment, the barrier metal layer 50b is formed of titanium nitride (TiN).

[0037] Circuit 11 comprises a decoder for selecting a plurality of memory cells MC in the semiconductor memory device 101, namely capacitor 20 and a specified memory cell MC in field-effect transistor 40, a sense amplifier connected to bit line BL, and peripheral circuitry including a register containing static random access memory (SRAM). Circuit 11 may also include CMOS circuitry of field-effect transistors having P-channel field-effect transistors (Pch-FETs) and N-channel field-effect transistors (Nch-FETs) formed by complementary metal-oxide-semiconductor (CMOS) processes.

[0038] The field-effect transistor of circuit 11 can be formed using a semiconductor substrate 10, such as a single-crystal silicon substrate. P-FET and N-FET are so-called transverse field-effect transistors that have a channel region, a source region, and a drain region on the semiconductor substrate 10, and have channels in a region close to the surface of the semiconductor substrate 10 for allowing carriers to flow in the X-axis or Y-axis direction, which is substantially parallel to the surface of the semiconductor substrate 10. Furthermore, the semiconductor substrate 10 may also have P-type or N-type conductivity. For convenience, FIG2 illustrates an example of the field-effect transistor of circuit 11.

[0039] Capacitor 20 is the memory capacitor MCP contained in the memory cell MC (see Figure 1). Figure 2 shows four capacitors 20, but the number of capacitors 20 is not limited to four.

[0040] Figure 3 shows a detailed cross-sectional view of the semiconductor memory device 101 when observed in a cross-section 70ZX parallel to the ZX plane and within the oxide semiconductor layer 70. Figure 4 shows a detailed cross-sectional view of the semiconductor memory device 101 when observed in a cross-section 70YZ parallel to the YZ plane and within the oxide semiconductor layer 70.

[0041] As shown in Figures 3 and 4, capacitor 20 is disposed below oxide semiconductor layer 70 and above semiconductor substrate 10. Electrode 24 in capacitor 20 is disposed below oxide semiconductor layer 70 and has a columnar shape extending in the vertical direction. The upper end of electrode 24 is connected to the lower end 70b of oxide semiconductor layer 70.

[0042] A dielectric layer 22 is disposed on the outer peripheral surface 24o of the electrode 24. An electrode 25 is disposed on the outer peripheral surface 22o of the dielectric layer 22.

[0043] In detail, electrode 24 includes: a conductive film 21 (an example of a "third conductor") and a metal oxide layer 32 (an example of a "second conductor").

[0044] The metal oxide layer 32 comprises a second oxide conductive material. The second oxide conductive material comprises at least one selected from indium (In), zinc (Zn), tin (Sn), iridium (Ir), ruthenium (Ru), titanium (Ti), and tungsten (W), as well as oxygen.

[0045] In this embodiment, the second oxide conductive material comprises indium, tin, and oxygen. Specifically, the second oxide conductive material is indium-tin oxide (ITO), the same as that in the metal oxide layer 50a.

[0046] The upper end of the metal oxide layer 32 contacts the lower end 70b of the oxide semiconductor layer 70. The metal oxide layer 32 has a columnar shape extending in the vertical direction. The metal oxide layer 32 has a central axis 32d (an example of a "first central axis") that is substantially parallel to the Z-axis. The central axis 32d is aligned with the central axis 70d.

[0047] The lower part of the outer peripheral surface of the metal oxide layer 32 is a facing surface 32a that faces the inner peripheral surface 25i of the electrode 25 across the dielectric layer 22.

[0048] A conductive film 21 in electrode 24 is disposed between the metal oxide layer 32 and the dielectric layer 22. Specifically, the conductive film 21 is disposed on the outer peripheral surface of the metal oxide layer 32. The conductive film 21 has a cup shape with an opening at the top, and the metal oxide layer 32 is housed within the cup.

[0049] The conductive film 21 comprises, for example, titanium and nitrogen. In this embodiment, the conductive film 21 is formed of titanium nitride. The outer peripheral surface of the conductive film 21 becomes the outer peripheral surface 24o of the electrode 24.

[0050] The dielectric layer 22 includes an insulating film 22a and an insulating film 22b. The insulating film 22a is disposed on the outer peripheral surface 24o of the electrode 24. The insulating film 22a has a cup shape with an opening at the top, and the electrode 24 is housed within the cup.

[0051] An insulating film 22b is disposed on the outer peripheral surface of the insulating film 22a. The insulating film 22b has a cup shape with an opening at the top, and the insulating film 22a is housed within the cup.

[0052] The upper end of the metal oxide layer 32, the opening above the conductive film 21, the opening above the insulating film 22a, and the opening above the insulating film 22b are aligned in the Z direction.

[0053] Insulating films 22a and 22b are formed of materials with high dielectric constants. Specifically, insulating film 22a may contain materials such as ZrO containing zirconium and oxygen. Insulating film 22b may contain materials such as ZrAlO containing zirconium, aluminum, and oxygen. The outer peripheral surface of insulating film 22b becomes the outer peripheral surface 22o of dielectric layer 22.

[0054] Electrode 25 is disposed on a portion below the outer peripheral surface 22o of dielectric layer 22. Electrode 25 has a cup shape with an opening at the top, and a portion below dielectric layer 22 is housed within the cup. In addition, electrode 25 has a lower end that abuts against the upper surface of conductor 23.

[0055] Electrode 25 may contain, for example, titanium and nitrogen. In this embodiment, electrode 25 is formed of titanium nitride. The upper opening of electrode 25 is located below the upper end of metal oxide layer 32. The inner peripheral surface 25i of electrode 25 faces a portion below the outer peripheral surface 24o of electrode 24, separated by dielectric layer 22.

[0056] The conductor 23 is in contact with the lower ends of the plurality of electrodes 25 contained in the plurality of capacitors 20. The conductor 23 functions, for example, as a grounding electrode for grounding. The conductor 23 may contain materials such as tungsten or titanium nitride.

[0057] As shown in Figure 2, the conductor 33 includes wiring that electrically connects the circuit 11 to the semiconductor device 30. The conductor 33 may include through-hole wiring, for example, having through-hole wiring extending in the Z-axis direction and connecting the character line WL to the circuit 11 disposed on the semiconductor substrate 10. The conductor 33 may contain copper, for example.

[0058] An insulating layer 34 is disposed between the plurality of capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0059] An insulating layer 35 is disposed above the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen. The upper surface of the insulating layer 35 is aligned in the Z direction with the upper end of the electrode 24 and the upper end of the dielectric layer 22.

[0060] [Manufacturing Method of Semiconductor Memory Devices] Hereinafter, as an example of a method for manufacturing a semiconductor memory device according to a first embodiment, the method for manufacturing a semiconductor memory device 101 will be described.

[0061] First, as shown in Figure 5, an insulating layer 34 and an insulating layer 35 are sequentially formed above the conductor 23. The conductor 23, the insulating layer 34, and the insulating layer 35 extend along planes that are approximately parallel to the XY plane.

[0062] Next, as shown in Figure 6, a hard mask layer 36 and a photoresist layer 37 are sequentially formed above the insulating layer 35. The hard mask layer 36 and the photoresist layer 37 extend along planes that are approximately parallel to the XY plane. Then, using photolithography, exposure, development, and stripping are performed on the surface of the photoresist layer 37 to form multiple openings 37a in the photoresist layer 37.

[0063] Next, as shown in FIG7, the exposed hard mask layer 36 is removed through the opening 37a of the resist layer 37 by reactive ion etching. In this way, an opening 36a is formed in the hard mask layer 36 that is continuous with the opening 37a.

[0064] Next, as shown in FIG8, a portion of the insulating layer 35 and a portion of the insulating layer 34 are removed by reactive ion etching through openings 37a and 36a. This forms a capacitor via CH whose bottom reaches the conductor 23.

[0065] Next, as shown in Figure 9, a film electrode 25 is formed on the inner surface of the capacitor hole CH and above the insulating layer 35.

[0066] Next, as shown in FIG10, an insulating layer 134 is formed above the electrode 25. The insulating layer 134 is, for example, a silicon oxide film containing silicon and oxygen. Then, a portion above the insulating layer 134 is removed by reactive ion etching. In this way, an insulating layer 134 is formed that fills a portion below the buried capacitor via CH.

[0067] Next, as shown in FIG11, the electrode 25, which is located above the end above the insulating layer 134, is removed by etching. This forms the electrode 25 disposed on the inner surface of the capacitor hole CH. Furthermore, the upper end of the electrode 25 is located below the surface above the insulating layer 35.

[0068] Next, as shown in Figure 12, the insulating layer 134 inside the capacitor hole CH is removed by etching.

[0069] Next, as shown in Figure 13, insulating film 22b, insulating film 22a and conductive film 21 are sequentially deposited on the inner surface of capacitor hole CH and the surface above insulating layer 35.

[0070] Next, as shown in Figure 14, a metal oxide layer 32 is deposited on the surface above the conductive film 21. The metal oxide layer 32 is deposited inside the capacitor aperture CH, for example, by atomic layer deposition (ALD).

[0071] Next, as shown in Figure 15, a portion of the upper part of each of the metal oxide layer 32, conductive film 21, insulating film 22a, and insulating film 22b is removed by chemical mechanical polishing, exposing the insulating layer 35. This forms the metal oxide layer 32, conductive film 21, insulating film 22a, and insulating film 22b separated for each capacitor hole CH. Furthermore, the upper ends of each of the metal oxide layer 32, conductive film 21, insulating film 22a, and insulating film 22b are aligned in the Z-direction.

[0072] Next, as shown in Figure 16, an insulating film 45b, a conductive layer 42, and an insulating film 45a are sequentially disposed above the insulating layer 35. The insulating film 45b, the conductive layer 42, and the insulating film 45a extend along planes that are approximately parallel to the XY plane.

[0073] Next, as shown in Figure 17, a mask is formed above the insulating film 45a, for example, by photolithography, followed by the formation of a transistor hole TH by reactive ion etching. The transistor hole TH extends substantially parallel to the Z-axis and penetrates the insulating film 45a, the conductive layer 42, and the insulating film 45b. At the bottom of the transistor hole TH, the surface above the metal oxide layer 32 is exposed. The transistor hole TH has a tapered shape that decreases in size towards the lower cross-section.

[0074] Next, as shown in Figure 18, a gate insulating film 43 is formed on the surface above the covered insulating film 45a and on the inner surface of the transistor hole TH.

[0075] Next, as shown in Figure 19, a portion of the gate insulating film 43 is etched by reactive ion etching. This exposes the surface above the metal oxide layer 32 at the bottom of the transistor hole TH.

[0076] Next, as shown in Figure 20, an oxide semiconductor layer 70 is formed on the surface above the insulating film 45a and the transistor hole TH. The lower end 70b of the oxide semiconductor layer 70 contacts the surface above the metal oxide layer 32 exposed at the bottom of the transistor hole TH. In this way, the transistor hole TH is filled by the oxide semiconductor layer 70.

[0077] Next, as shown in FIG21, a portion of the oxide semiconductor layer 70 is removed, exposing the surface above the insulating film 45a. At this time, the surface of the upper end 70a of the oxide semiconductor layer 70 is aligned in the Z direction with the upper end of the gate insulating film 43 and the surface above the insulating film 45a.

[0078] Next, as shown in Figure 22, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are sequentially formed above the oxide semiconductor layer 70 and the insulating film 45a. The metal oxide layer 50a, the barrier metal layer 50b, and the metal film 50c extend along planes that are approximately parallel to the XY plane.

[0079] Next, as shown in Figure 23, a portion of each of the metal film 50c, the barrier metal layer 50b, and the metal oxide layer 50a is etched to form electrodes 50 for each oxide semiconductor layer 70. The electrodes 50 function as landing pads.

[0080] Next, as shown in FIG24, an insulating layer 63 is formed to cover the electrode 50. The insulating layer 63 may contain, for example, silicon oxide. Then, a portion of the insulating layer 63 is chemically mechanically polished to expose the surface above the electrode 50.

[0081] [Manufacturing Method of Capacitor 120] Hereinafter, the manufacturing method of capacitor 120 having a structure different from that of capacitor 20 will be described.

[0082] First, as shown in FIG25, the manufacturing method of capacitor 120 differs from that of capacitor 20 shown in FIG15 in that an electrode 124 is deposited on the surface above the conductive film 21 instead of the metal oxide layer 32. The electrode 124 may contain, for example, SiGe containing silicon and germanium. For example, the electrode 124 is deposited inside the capacitor aperture CH by chemical vapor deposition (CVD).

[0083] Next, as shown in Figure 26, a portion of the upper part of each of the electrode 124, conductive film 21, insulating film 22a, and insulating film 22b is removed by chemical mechanical polishing, exposing the insulating layer 35. This forms the electrode 124, conductive film 21, insulating film 22a, and insulating film 22b, separated for each capacitor hole CH. Furthermore, the upper ends of each of the electrode 124, conductive film 21, insulating film 22a, and insulating film 22b are aligned in the Z-direction.

[0084] Next, as shown in FIG27, a portion above the electrode 124 is removed by etching. In doing so, an electrode 124 (an example of a "first capacitor electrode") is formed that fills a portion below the capacitor hole CH.

[0085] Next, as shown in Figure 28, a barrier metal layer 224 and a metal oxide layer 132 are sequentially deposited above the capacitor aperture CH. The barrier metal layer 224, for example, comprises titanium nitride containing nitrogen and titanium. The metal oxide layer 132, for example, comprises ITO.

[0086] Next, as shown in Figure 29, a portion of the upper part of each of the metal oxide layer 132 and the barrier metal layer 224 is removed by chemical mechanical polishing, exposing the insulating layer 35. Moreover, the upper ends of each of the insulating layer 35, insulating film 22b, insulating film 22a, conductive film 21, barrier metal layer 224 and metal oxide layer 132 are aligned in the Z direction.

[0087] (Effect) As shown in Figures 25 to 29, the manufacturing method of capacitor 120 includes the steps of chemical mechanical polishing, forming a recess based on removing a portion above electrode 124, depositing barrier metal layer 224 and metal oxide layer 132, and chemical mechanical polishing from the deposition of electrode 124 to the completion of capacitor 120.

[0088] In contrast, in the manufacturing method of capacitor 20, as shown in Figures 14 and 15, capacitor 20 is completed by chemical mechanical polishing after depositing the metal oxide layer 32. That is, capacitor 20 can be manufactured through a simple process.

[0089] In addition, in capacitor 120, the resistance value will increase due to the contact resistance between metal oxide layer 132 and barrier metal layer 224 and between barrier metal layer 224 and electrode 124.

[0090] In contrast, in capacitor 20, a metal oxide layer 32 is provided instead of the structure of metal oxide layer 132, electrode 124 and barrier metal layer 224, without generating the contact resistance, thus reducing the resistance value.

[0091] Furthermore, the volume of the metal oxide layer 132 in capacitor 120 is smaller than that of the metal oxide layer 32 in capacitor 20. Therefore, the metal oxide layer 132 may sometimes disappear due to the formation step (see Figure 18) and etching step (see Figure 19) of the gate insulating film 43.

[0092] In contrast, in capacitor 20, the large volume structure of metal oxide layer 32 can suppress the disappearance of metal oxide layer 132 in the formation step (see Figure 18) and etching step (see Figure 19) of gate insulating film 43.

[0093] Furthermore, a structure in which the electrode 124 (see Figure 26) provided instead of the metal oxide layer 32 contacts the lower end 70b of the oxide semiconductor layer 70 is also considered, but due to the poor matching of the work functions of SiGe and IGZO, the resistance value will be higher.

[0094] In contrast, in the semiconductor memory device 101, the resistance value can be reduced by using a structure in which the metal oxide layer 32 (ITO) with a well-matched work function contacts the lower end 70b of the oxide semiconductor layer 70 (IGZO).

[0095] (Modification of semiconductor memory device 101) Figure 30 shows a detailed cross-sectional view of a modified example of the semiconductor memory device 101 when observed in a cross-section 70ZX parallel to the ZX plane and within the oxide semiconductor layer 70. Figure 31 shows a detailed cross-sectional view of a modified example of the semiconductor memory device 101 when observed in a cross-section 70YZ parallel to the YZ plane and within the oxide semiconductor layer 70.

[0096] As shown in Figures 30 and 31, a modified example of the semiconductor memory device 101, compared to the semiconductor memory device 101 shown in Figures 3 and 4, includes a capacitor 20a instead of a capacitor 20.

[0097] Electrode 24 in capacitor 20a does not contain conductive film 21, unlike electrode 24 in capacitor 20. That is, the outer peripheral surface of metal oxide layer 32 becomes the outer peripheral surface 24o of electrode 24.

[0098] Thus, by eliminating the conductive film 21, the step of stacking the conductive film 21 can be omitted. That is, the capacitor 20a can be manufactured using a simple process.

[0099] [Second Implementation Form] The semiconductor memory device 102 of the second embodiment will be described. From the second embodiment onwards, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, the same effects resulting from the same structure will not be mentioned sequentially for each embodiment.

[0100] Figure 32 shows a cross-sectional view of the semiconductor memory device 102 when observed in a cross-section 70ZX parallel to the ZX plane and in a cross-section 70ZX contained in the oxide semiconductor layer 70.

[0101] As shown in FIG32, the semiconductor memory device 102 of the second embodiment, compared with the semiconductor memory device 101 shown in FIG3 and FIG4, includes a semiconductor device 30B and a capacitor 120 instead of semiconductor device 30 and capacitor 20.

[0102] Compared to capacitor 20, capacitor 120 includes an electrode 124, a metal oxide layer 132, and a barrier metal layer 224 instead of metal oxide layer 32.

[0103] Figure 33 is a plan view of capacitor 120 viewed from above. As shown in Figures 32 and 33, in semiconductor device 30B, barrier metal layer 224 forms a downwardly recessed portion 224a.

[0104] In detail, the barrier metal layer 224 has an upwardly opening cup shape. The lower surface of the barrier metal layer 224 is in contact with the upper surface of the electrode 124. The side surface of the barrier metal layer 224 is in contact with the upper inner peripheral surface of the conductive film 21.

[0105] The metal oxide layer 132 (an example of the "second electrode") is embedded in the recess 224a. The upper ends of the insulating layer 35, insulating film 22b, insulating film 22a, conductive film 21, barrier metal layer 224 and metal oxide layer 132 are aligned in the Z direction.

[0106] Furthermore, the metal oxide layer 132 is connected to the lower end 70b of the oxide semiconductor layer 70 and contains a second oxide conductive material. In this embodiment, the upper surface 211 of the metal oxide layer 132 is in contact with the lower end 70b of the oxide semiconductor layer 70.

[0107] The contact portion 201 (an example of the "first contact portion") between the metal oxide layer 132 and the oxide semiconductor layer 70 is generally circular. The metal oxide layer 132 is a cylinder having a central axis extending in the vertical direction.

[0108] Figure 34 is a schematic diagram illustrating the gap 301. As shown in Figures 32-34, the metal oxide layer 132 includes the gap 301. When the metal oxide layer 132 is viewed along the vertical direction, the centroid 211cg of the upper surface 211 of the metal oxide layer 132 overlaps with the gap 301.

[0109] For example, when ITO is filled into the recess 224a by sputtering, although ITO is filled in the outer periphery 211o of the side near the recess 224a, the filling in the central portion 211c, which is far from the side and close to the center of gravity 211cg, sometimes becomes insufficient.

[0110] The portion of the cavity that is not filled with ITO is called gap 301. In this embodiment, gap 301 has a spindle shape that is elongated in the vertical direction.

[0111] Additionally, the metal oxide layer 132 filling the recess 224a includes a lateral alignment portion 132L and a longitudinal alignment portion 132V. The lateral alignment portion 132L is located near the side of the recess 224a, and the ITO is aligned along a plane parallel to the XY plane. The longitudinal alignment portion 132V is located closer to the centroid 211cg than the lateral alignment portion 132L, and the ITO is aligned along an axis parallel to the Z-axis.

[0112] The contact portion 201 between the oxide semiconductor layer 70 and the metal oxide layer 32 and the gap 301 contained in the metal oxide layer 32 are not in contact.

[0113] When the metal oxide layer 132 is observed along the vertical direction, the contact portion 201 is far from the center of gravity 211cg. Preferably, when the metal oxide layer 132 is observed along the vertical direction, the contact portion 201 does not overlap with the gap 301.

[0114] Furthermore, the contact portion 201 is closer to the outer periphery of the metal oxide layer 132 than the center of gravity 211cg. In detail, when the metal oxide layer 132 is viewed along the vertical direction, the distance between the contact portion 201 and the outer periphery of the metal oxide layer 132 is shorter than the distance between the contact portion 201 and the center of gravity 211cg.

[0115] Figure 35 is a plan view of the metal oxide layer 50a viewed from below. As shown in Figures 32 and 35, when the metal oxide layer 50a is viewed along the vertical direction, the center of gravity 212cg of the contact portion 202 (an example of the "second contact portion") between the oxide semiconductor layer 70 and the metal oxide layer 50a overlaps with the center of gravity 212cg of the surface 212 below the metal oxide layer 50a.

[0116] Furthermore, the contact portion 202 may not overlap with the center of gravity 212cg. In this case, it is preferable that the contact portion 202 is closer to the center of gravity 212cg than the outer periphery of the metal oxide layer 50a. Specifically, when the metal oxide layer 50a is viewed along the vertical direction, the distance between the contact portion 202 and the center of gravity 212cg is shorter than the distance between the contact portion 202 and the outer periphery of the metal oxide layer 50a.

[0117] (Topic) Figures 36-40 are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the comparative example.

[0118] First, as shown in Figure 36, a slit 301 is formed in the metal oxide layer 132. When the metal oxide layer 132 is viewed along the vertical direction, the slit 301 overlaps with the center of gravity 211cg.

[0119] Next, as shown in Figure 37, a transistor hole TH is formed by reactive ion etching. However, when the transistor hole TH is formed by overlapping the bottom of the transistor hole TH with the center of gravity 211cg, the transistor hole TH sometimes penetrates the metal oxide layer 132 due to the presence of gap 301. In this case, the metal oxide layer 132 is exposed on the sidewall of the transistor hole TH.

[0120] Next, as shown in Figure 38, a gate insulating film 43 is formed by covering the inner surface of the transistor aperture TH. However, the temperature of the metal oxide layer 132 rises due to the heat applied during the formation of the gate insulating film 43, and the metal oxide layer 132 sometimes disappears.

[0121] Next, as shown in Figure 39, the gate insulating film 43 at the bottom of the transistor hole TH is etched by reactive ion etching. However, since the transistor hole TH has a conical shape, the area at the bottom of the transistor hole TH is small, making the etching of the gate insulating film 43 difficult.

[0122] Next, as shown in Figure 40, an oxide semiconductor layer 70 is formed in the transistor hole TH. However, since the transistor hole TH has a tapered shape, the contact area between the oxide semiconductor layer 70 at the lower end 70b and the conductive film 21 will be smaller.

[0123] [Manufacturing method of semiconductor memory device 102] Hereinafter, as an example of a method for manufacturing a semiconductor memory device according to a second embodiment, the method for manufacturing a semiconductor memory device 102 will be described.

[0124] First, as shown in Figure 41, a slit 301 is formed in the metal oxide layer 132. When the metal oxide layer 132 is viewed along the vertical direction, the slit 301 overlaps with the center of gravity 211cg.

[0125] Next, as shown in Figure 42, the transistor hole TH is formed by reactive ion etching in such a way that the bottom of the transistor hole TH is far from the center of gravity 211cg. In this way, the continuity between the transistor hole TH and the gap 301 located directly below the center of gravity 211cg can be suppressed, thus suppressing the situation where the transistor hole TH penetrates the metal oxide layer 132.

[0126] Next, as shown in FIG43, a gate insulating film 43 is formed by covering the inner surface of the transistor aperture TH. At this time, unlike the case shown in FIG38, since the exposure of the metal oxide layer 132 is suppressed at the bottom of the transistor aperture TH, the disappearance of the metal oxide layer 132 can be suppressed even if the temperature of the metal oxide layer 132 rises due to the heat applied during the formation of the gate insulating film 43.

[0127] Next, as shown in Figure 44, the gate insulating film 43 at the bottom of the transistor hole TH is etched by reactive ion etching. Unlike the case shown in Figure 39, since the bottom of the transistor hole TH can be located at a higher position, the area of ​​the bottom of the transistor hole TH can be sufficiently ensured, and the gate insulating film 43 can be etched well.

[0128] Next, as shown in FIG45, an oxide semiconductor layer 70 is formed in the transistor hole TH. Unlike the case shown in FIG40, since the lower end 70b of the oxide semiconductor layer 70 can be located at a higher position, the area of ​​the contact portion 201 can be sufficiently ensured.

[0129] (Examples of variations in the shape of the slit) The shape of the slit 301 is not limited to a spindle shape (see Figure 32), and sometimes it can be other shapes. For example, as shown in Figure 46, the slit 302 can also be a columnar structure that is elongated in the vertical direction and has its upper and lower ends exposed from the metal oxide layer 132. That is, the slit 302 penetrates the metal oxide layer 132.

[0130] Furthermore, as shown in Figure 47, the slit 303 is not limited to a structure that penetrates the metal oxide layer 132 like the slit 302; it can also be a columnar structure that is long in the vertical direction and embedded in the metal oxide layer 132. Alternatively, the upper or lower end of the slit 303 may be exposed from the metal oxide layer 132.

[0131] Alternatively, as shown in Figure 48, the gap 304 can also be a structure with its upper end exposed from the metal oxide layer 132 and having a tapered shape that tapers from top to bottom.

[0132] Alternatively, as shown in Figure 49, the slit 305 can also be a structure with its upper and lower ends exposed from the metal oxide layer 132 and having a conical shape with its diameter increasing from top to bottom.

[0133] Furthermore, the shapes of gaps 301 to 305 are largely determined by the shape of the metal oxide layer 132, i.e., the shape of the recess 224a. The shapes of the metal oxide layers 132 in adjacent capacitors 120 are mostly similar. Therefore, gaps of roughly the same shape are mostly formed in adjacent metal oxide layers 132.

[0134] Furthermore, in the semiconductor memory device 101, the structure in which the central axis 70d of the oxide semiconductor layer 70 is aligned with the central axis 32d of the metal oxide layer 32 has been described, but it is not limited to this. The central axis 70d and the central axis 32d may also be arranged apart in a direction intersecting the vertical direction. Specifically, it may also be a structure in which the semiconductor device 30B is disposed above the capacitor 20.

[0135] Furthermore, in capacitor 120, the structure of the recess 224a formed by the barrier metal layer 224 has been described, but it is not limited thereto. It is also possible that at least a portion of the recess 224a is formed by other electrodes or insulating films.

[0136] Furthermore, in the semiconductor memory device 102, a structure in which the metal oxide layer 132 includes any one of the gaps 301 to 305 has been described, but it is not limited to this. The metal oxide layer 132 may also be a structure without gaps 301 to 305. Even when the metal oxide layer 132 includes any one of the gaps 301 to 305, the semiconductor memory device 102 exhibits good electrical characteristics. Therefore, even when the metal oxide layer 132 does not include gaps 301 to 305, the semiconductor memory device 102 will naturally also exhibit good electrical characteristics.

[0137] (a) A semiconductor device, wherein The semiconductor device further includes An insulating film or electrode forming at least a portion of the recess. The second electrode is embedded into the recess. When the second electrode is observed along the vertical direction, the first contact portion does not overlap with the gap.

[0138] The present embodiment has been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. Any design modifications made by those skilled in the art to these specific examples that possess the features of this disclosure are also included within the scope of this disclosure. The components included in each specific example, as well as their configuration, conditions, shapes, etc., are not limited to those illustrated and can be appropriately modified. The combinations of the components included in each specific example can be appropriately changed as long as no technical contradiction arises.

[0139] 10: Semiconductor substrate 11: Circuit 20, 20a, 120: Capacitors 21: Conductive film 22: Dielectric layer 22a, 22b, 45a, 45b: Insulating film 22i, 25i: Inner circumferential surface 22°, 24°: outer perimeter 23, 33: Conductors 24, 25, 50, 124: Electrodes 30, 30B: Semiconductor devices 32, 50a, 132: Metal oxide layers 32a: Opposing surfaces 32d, 70d: Central axis 34, 35, 45, 63, 134: Insulation layer 36: Hard mask layer 36a, 37a: Opening 37: Resist layer 40: Field-effect transistor 42: Conductive layer 43: Gate insulating film 50b, 224: Barrier metal layer 50c: Metallic film 70: Oxide semiconductor layer 70a: Upper end 70b: Lower end 70YZ, 70ZX: Sections 101, 102: Semiconductor memory devices 132L: Lateral alignment section 132V: Longitudinal alignment section 201, 202: Contact Department 211, 212: Face 211c: Central Department 211cg, 212cg: Center of gravity 211o: Peripheral part 224a: concave part 301, 302, 303, 304, 305: Gaps BL, BL m, BL m+1, BL m+2: Bit lines CH: Capacitor orifice MC: Memory Unit MCP: Memory Capacitor MTR: Memory Transistor TH: Transistor aperture WL, WL n, WL n+1, WL n+2: Character lines X, Y, Z: Axis / Direction

Claims

1. A semiconductor memory device, comprising: An oxide semiconductor extends in a vertical direction; a first electrode includes a first conductor containing a first oxide conductive material and connected to the upper end of the oxide semiconductor; A gate electrode is disposed below the oxide semiconductor and extends in the vertical direction; a dielectric layer is disposed on the outer peripheral surface of the second electrode. The second electrode includes a third electrode disposed on the outer peripheral surface of the dielectric layer. The second electrode includes a second conductor containing a second oxide conductive material and is connected to the lower end of the oxide semiconductor. It also has a facing surface that faces the inner peripheral surface of the third electrode across the dielectric layer.

2. The semiconductor memory device of claim 1, wherein the second electrode further comprises a third conductor disposed between the second conductor and the dielectric layer, and the third conductor contains titanium and nitrogen.

3. The semiconductor memory device as claimed in claim 1, wherein the second oxide conductive material comprises at least one selected from indium, zinc, tin, iridium, ruthenium, titanium and tungsten, and oxygen.

4. The semiconductor memory device of claim 1, wherein the second conductor is a column having a first central axis extending along the vertical direction, the oxide semiconductor is a column having a second central axis extending along the vertical direction, and the first central axis and the second central axis are spaced apart in a direction intersecting the vertical direction.

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