Semiconductor memory devices

Abstract

This invention provides a semiconductor memory device that can be preferably manufactured. The semiconductor memory device includes a first wafer and a second wafer bonded together via a plurality of bonding electrodes. The first wafer and the second wafer include a perimeter region (RES) disposed in a manner surrounding a memory region. The second wafer includes a plurality of perimeters, a first wiring layer, and a second wiring layer disposed and spaced apart in the perimeter region (RES) surrounding the memory region. The first wiring layer includes a plurality of second conductive layers disposed at positions that coincide with a plurality of first perimeters (excluding the outermost perimeter) when viewed from a first direction, and are electrically connected to the plurality of first perimeters. The second wiring layer includes a fourth conductive layer disposed at positions that coincide with the outermost second perimeter of the plurality of perimeters when viewed from the first direction, are not electrically connected to the second perimeters, and are spaced apart from the second perimeters.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Prior Technology

[0002] A known semiconductor memory device includes a substrate, a plurality of conductive layers deposited along a direction intersecting the surface of the substrate, a semiconductor layer facing the plurality of conductive layers, and a gate insulating layer disposed between the conductive layers and the semiconductor layer. The gate insulating layer may include, for example, an insulating charge storage layer such as silicon nitride (SiN) or a conductive charge storage layer such as a floating gate, and a memory portion capable of storing data. Summary of the Invention

[0003] The present invention provides a semiconductor memory device that can be preferably manufactured.

[0004] One embodiment of a semiconductor memory device includes a first wafer and a second wafer bonded together via a plurality of bonding electrodes. The first wafer and the second wafer include: a memory region containing a memory cell array or peripheral circuitry connected to the memory cell array; and an edge sealing region disposed to surround the memory region. The first wafer includes: a semiconductor substrate; and a plurality of first conductive layers disposed in the edge sealing region and connected to the semiconductor substrate in a first direction intersecting the surface of the semiconductor substrate. The second wafer includes: a plurality of edges extending along a first direction in the edge sealing region and arranged to surround the memory region when viewed from the first direction, spaced apart from the inner peripheral side to the outer peripheral side of the edge sealing region; and a first wiring layer disposed on the second wafer side relative to the plurality of edges. The second wiring layer is disposed on the second wafer side relative to the first wiring layer and includes a plurality of wirings containing tungsten (W). The first wiring layer includes a plurality of second conductive layers disposed in the sealing region and at a position that coincides with a plurality of first sealing edges other than the outermost periphery when viewed from the first direction, and is electrically connected to the plurality of first sealing edges. The second wiring layer includes: a plurality of third conductive layers disposed in the sealing region and at a position that coincides with a plurality of first sealing edges when viewed from the first direction, and is connected to the plurality of first sealing edges; and a fourth conductive layer disposed in the sealing region and at a position that is further outward than the plurality of third conductive layers when viewed from the first direction, is not electrically connected to the second sealing edge that is the outermost periphery when viewed from the first direction, and is separated from the second sealing edge. Simple Explanation of the Diagram

[0005] Figure 1 is a schematic exploded perspective view showing a structural example of the semiconductor memory device according to the first embodiment. Figure 2 is a schematic bottom view showing a structural example of the wafer CM. Figure 3 is a schematic bottom view showing a structural example of the wafer CM. Figure 4 is a schematic bottom view showing an enlarged portion of Figure 2. Figure 5 is a schematic plan view showing a structural example of the wafer CP. Figure 6 is a schematic plan view showing an enlarged portion of Figure 5. Figure 7 is a schematic cross-sectional view showing a portion of the structure of the memory die MD. Figure 8 is a schematic cross-sectional view showing an enlarged portion of Figure 7. Figure 9 is a schematic cross-sectional view showing an enlarged portion of Figure 8. Figure 10 is a schematic cross-sectional view showing a structural example of the sealing region and the notched region of the first embodiment. Figure 11 is a schematic bottom view for explaining the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 12 is a schematic cross-sectional view for explaining the manufacturing method. Figure 13 is a schematic cross-sectional view for explaining the manufacturing method. Figure 14 is a schematic cross-sectional view for explaining the manufacturing method. Figure 15 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 16 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 17 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 18 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 19 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 20 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 21 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 22 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 23 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 24 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 25 is a schematic plan view for illustrating the manufacturing method. Figure 26 is a schematic perspective view for illustrating the manufacturing method. Figure 27 is a schematic perspective view for illustrating the manufacturing method. Figure 28 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 29 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 30 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 31 is a schematic plan view showing the arrangement of multiple sealing edges in the sealing region and the arrangement of the wiring layer M1 in Embodiment 1 of the first embodiment. Figure 32 is a schematic plan view showing an enlarged portion of Figure 31. Figure 33 is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the sealing edge ES6 when cut along the dashed line E-E' in Figure 31. Figure 34 is a schematic plan view showing the arrangement of multiple sealing edges in the sealing region and the arrangement of the wiring layer M1 in Embodiment 2 of the first embodiment. Figure 35 is a schematic plan view showing an enlarged portion of Figure 34. Figure 36 is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the sealing edge ES6 when cut along the dashed line F-F' in Figure 34.Figure 37 is a schematic plan view showing the arrangement of multiple sealing edges in the sealing area and the wiring layer M1 in Embodiment 3 of the first embodiment. Figure 38 is a schematic plan view showing a portion of Figure 37 enlarged. Figure 39 is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the sealing edge ES6 when cut along the dashed line G-G' in Figure 37. Figure 40 is a schematic plan view showing the arrangement of multiple sealing edges in the sealing area and the wiring layer M1 in Embodiment 4 of the first embodiment. Figure 41 is a schematic plan view showing a portion of Figure 40 enlarged. Figure 42 is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the sealing edge ES6 when cut along the dashed line H-H' in Figure 40. Figure 43 is a schematic plan view showing the arrangement of multiple sealing edges in the sealing area and the wiring layer M1 in Embodiment 5 of the first embodiment. Figure 44 is a schematic plan view showing a portion of Figure 43 enlarged. Figure 45 is a schematic cross-sectional view showing the structure of the sealing edge ES6 and the conductive layer below the sealing edge ES6 in another embodiment. Figure 46 is a schematic cross-sectional view showing the structure of the sealing edge ES6 and the conductive layer below the sealing edge ES6 in another embodiment. Figure 47 is a schematic cross-sectional view showing the structure of the sealing edge ES6 and the conductive layer below the sealing edge ES6 in another embodiment. Figure 48 is a schematic cross-sectional view showing the structure of the sealing edge ES6 and the conductive layer below the sealing edge ES6 in another embodiment. Figure 49 is a schematic plan view showing the arrangement of multiple sealing edges in the sealing area and the arrangement of wiring layers M0 and M1 in another embodiment. Figure 50 is a schematic cross-sectional view showing the structure of wiring layers M0 and M1 located below the sealing edge ES6 when cut along the dotted line I-I' in Figure 49. Implementation

[0006] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the drawings.

[0007] Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the present invention. Moreover, the following figures are illustrative, and sometimes certain structures are omitted for ease of explanation. Furthermore, regarding multiple embodiments, common parts are sometimes annotated with the same symbols and descriptions are omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" sometimes refers to the memory chip after dicing and sometimes to the wafer before dicing. Moreover, in the former case, it sometimes refers to the memory chip after packaging and sometimes to the memory chip before packaging. Moreover, in the latter case, it sometimes refers to the wafer before bonding and sometimes to the wafer after bonding.

[0009] Furthermore, in this specification, the term "electrically connected" to the second structure can refer to either the first structure being directly connected to the second structure, or the first structure being connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is disconnected, the first transistor is still "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when the term "first structure" is referred to as "connected" "between" the second and third structures, it sometimes means that the first, second, and third structures are connected in series and the second structure is connected to the third structure via the first structure.

[0011] Furthermore, in this specification, when the term "circuit" is used to refer to two wirings being "conducted," it sometimes means that the circuit includes a transistor that is located in the current path between the two wirings and that the transistor is in a conducting state.

[0012] Furthermore, in this specification, the specified direction that is parallel to the surface of the substrate is called the X direction, the direction that is parallel to the surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction that is perpendicular to the surface of the substrate is called the Z direction.

[0013] Furthermore, in this specification, the direction along the specified surface is sometimes referred to as the first direction, the direction along the specified surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the specified surface is referred to as the third direction. These first directions, second directions, and third directions may correspond to any of the X, Y, and Z directions, or they may not correspond to each other.

[0014] Furthermore, in this specification, when using terms such as "upper" or "lower," for example, the portion of two chips or wafers contained in a memory die or wafer that has external bonding pads that can be connected to a bonding wire may be designated as the upper side, and the portion that does not have such external bonding pads may be designated as the lower side. Furthermore, when referring to structures contained in a memory die or wafer, for example, the direction along the Z direction away from the lower side of the semiconductor substrate contained in the wafer may be referred to as upper, and the direction along the Z direction towards the lower side of the semiconductor substrate contained in the wafer may be referred to as lower. Moreover, when referring to a structure as a lower surface or lower end, it may refer to the surface or end of the semiconductor substrate on the lower side of the wafer containing that structure; when referring to an upper surface or upper end, it may refer to the surface or end of the lower side of the wafer containing that structure that is opposite to the semiconductor substrate. Furthermore, a surface intersecting the X or Y direction may be referred to as a side surface, etc.

[0015] Furthermore, in this specification, the terms "width," "length," or "thickness" used to refer to a specified direction in relation to structures, components, etc., sometimes refer to the width, length, or thickness of a cross-section observed by a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0016] [First Embodiment] [Structure of Memory Die MD] FIG1 is a schematic exploded perspective view showing an example of the structure of a semiconductor memory device according to this embodiment. As shown in FIG1, the memory die MD includes a chip CM on the memory cell array side and a chip CP on the peripheral circuit side.

[0017] On the upper surface of the wafer CM, there are multiple external bonding pad electrodes PX that can be connected to bonding lines (not shown). Furthermore, on the lower surface of the wafer CM, there are multiple bonding electrodes PI1. And on the upper surface of the wafer CP, there are multiple bonding electrodes PI2. Hereinafter, regarding the wafer CM, the surface with the multiple bonding electrodes PI1 will be referred to as the surface, and the surface with the multiple external bonding pad electrodes PX will be referred to as the back surface. Similarly, regarding the wafer CP, the surface with the multiple bonding electrodes PI2 will be referred to as the surface, and the surface opposite to the surface will be referred to as the back surface. In the illustrated example, the surface of the wafer CP is located above the back surface of the wafer CP, and the back surface of the wafer CM is located above the surface of the wafer CM.

[0018] The wafer CM and wafer CP are configured such that the surface of the wafer CM faces the surface of the wafer CP. Multiple bonding electrodes PI1 are respectively provided corresponding to multiple bonding electrodes PI2, and are positioned to bond with the multiple bonding electrodes PI2. The bonding electrodes PI1 and PI2 function as bonding electrodes for bonding the wafer CM and wafer CP and making them electrically conductive.

[0019] Furthermore, in the example of Figure 1, corners a1, a2, a3, and a4 of the wafer CM correspond to corners b1, b2, b3, and b4 of the wafer CP, respectively.

[0020] Figures 2 and 3 are schematic bottom views showing examples of the structure of a wafer CM. A portion of the structure of the bonding electrodes PI1, etc., is omitted in Figure 3. Figure 4 is a schematic bottom view showing an enlarged portion of Figure 2. Figure 5 is a schematic plan view showing an example of the structure of a wafer CP. Figure 6 is a schematic plan view showing an enlarged portion of Figure 5. Figure 7 is a schematic cross-sectional view showing a portion of the structure of a memory die MD. Figure 8 is a schematic cross-sectional view showing an enlarged portion of Figure 7. Figure 9 is a schematic cross-sectional view showing an enlarged portion of Figure 8. Furthermore, while Figure 9 shows a YZ cross-section, the same structure as in Figure 9 is observed when viewing a cross-section other than the YZ cross-section (e.g., the XZ cross-section) along the central axis of the semiconductor layer 120.

[0021] [Structure of the Chip CM] As shown in Figure 2, the chip CM includes four memory planar regions RMP arranged along the X and Y directions. Furthermore, the chip CM includes a peripheral region RP located further along the Y direction from the four memory planar regions RMP. The peripheral region RP includes multiple input / output regions RIO arranged along the X direction. Moreover, the chip CM has a sealing region RES surrounding the four memory planar regions RMP and the multiple input / output regions RIO. Furthermore, as shown in Figure 4, a cutout region RK is provided outside the sealing region RES. Moreover, sometimes a portion of the cutout region RK remains after cutting, and sometimes no portion remains. In the following description, the region inside the sealing region RES (including the four memory planar regions RMP and the peripheral region RP) is sometimes referred to as the memory region RM.

[0022] For example, as shown in Figure 7, the chip CM includes a substrate structure L SB, memory cell array layers L MCA1 and L MCA2 disposed below the substrate structure L SB, and multiple wiring layers CH, M0, M1, and MB disposed below the memory cell array layers L MCA1 and L MCA2. The memory cell array layers L MCA1 and L MCA2 each include multiple word line layers L WL arranged along the Z direction. An insulating layer 111, such as silicon oxide (SiO2), is disposed between the multiple word line layers L WL arranged along the Z direction.

[0023] [Structure of substrate structure L SB of chip CM] For example, as shown in Figure 7, the substrate structure L SB includes a conductive layer 100 disposed on the upper surface of the memory cell array layer L MCA1, an insulating layer 101 disposed on the upper surface of the conductive layer 100, a back wiring layer MA disposed on the upper surface of the insulating layer 101, and an insulating layer 102 disposed on the upper surface of the back wiring layer MA.

[0024] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or a metal such as tungsten (W), or a silicate such as tungsten silicate (WSi).

[0025] The conductive layer 100 functions as part of the source line of a Not AND, NAND flash memory. Four conductive layers 100 are provided corresponding to four memory planar regions RMP (Figure 2) arranged along the X and Y directions. At the X and Y ends of the memory planar regions RMP, regions VZ without the conductive layer 100 are provided.

[0026] The insulating layer 101 may contain, for example, silicon oxide (SiO2).

[0027] The back-side wiring layer MA contains multiple wiring layers. These multiple wiring layers may also contain, for example, aluminum (Al).

[0028] A portion of the multiple wiring ma functions as part of the source line of the NAND flash memory. Four wiring ma are provided corresponding to the four memory planar regions RMP (Figure 2) arranged along the X and Y directions. Each wiring ma is electrically connected to the conductive layer 100.

[0029] Furthermore, a portion of the multiple wiring ma functions as external bonding pad electrodes PX. Multiple wiring ma are provided corresponding to multiple input / output regions R IO (FIG. 2) arranged along the X direction. The wiring ma is connected to the via contact electrodes CC in the memory cell array layers L MCA1 and L MCA2 in the region VZ without the conductive layer 100. Moreover, a portion of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0030] The insulating layer 102 is, for example, a passivation layer containing a resin material such as polyimide in the upper layer.

[0031] [Structure in the memory plane region RMP of memory cell array layers LMCA1 and LMCA2 of the chip CM] For example, as shown in Figure 3, multiple memory blocks BLK arranged along the Y direction are provided in memory cell array layers LMCA1 and LMCA2. As shown in Figure 7, an inter-block structure ST is provided between two adjacent memory blocks BLK along the Y direction.

[0032] For example, as shown in Figure 8, the memory block BLK includes multiple conductive layers 110 arranged along the Z direction corresponding to multiple character line layers L WL, multiple semiconductor layers 120 extending along the Z direction, and multiple gate insulating films 130 respectively disposed between the multiple conductive layers 110 and the multiple semiconductor layers 120.

[0033] The conductive layer 110 has a generally plate-like shape extending along the X direction. The conductive layer 110 may also include a laminated film of barrier conductive film such as titanium nitride (TiN) and metal film such as tungsten (W). Furthermore, the conductive layer 110 may also include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B).

[0034] Furthermore, one or more of the uppermost conductive layers 110 among the multiple conductive layers 110 function as the select gate line of the NAND flash memory and the gate electrode of the multiple select transistors connected to the select gate line. These multiple conductive layers 110 correspond to each memory block BLK and are electrically independent.

[0035] Furthermore, the multiple conductive layers 110 located below them function as word lines of the NAND flash memory and gate electrodes of multiple memory cells (memory transistors) connected to the word lines. These multiple conductive layers 110 correspond to each memory block BLK and are electrically independent.

[0036] Furthermore, one or more conductive layers 110 located below it function as the select gate line of the NAND flash memory and the gate electrodes of a plurality of select transistors connected to the select gate line. The width of these plurality of conductive layers 110 in the Y direction is smaller than that of the other conductive layers 110. Moreover, an insulating layer such as silicon oxide (SiO2) is provided between two adjacent conductive layers 110 in the Y direction.

[0037] Semiconductor layers 120 are arranged in a predetermined pattern along the X and Y directions. Semiconductor layers 120 function as memory cells and channel regions for selecting transistors in NAND flash memory. Semiconductor layers 120 may contain, for example, polysilicon (Si). Semiconductor layers 120 have a generally cylindrical shape, and an insulating layer 125, such as silicon oxide, is provided in the central portion.

[0038] Semiconductor layer 120 includes semiconductor region 120L contained in memory cell array layer L MCA1 and semiconductor region 120U contained in memory cell array layer L MCA2. Furthermore, semiconductor layer 120 includes semiconductor region 120J connected to the lower end of semiconductor region 120L and the upper end of semiconductor region 120U, impurity region 122 connected to the upper end of semiconductor region 120L, and impurity region 121 connected to the lower end of semiconductor region 120U.

[0039] Semiconductor region 120L has a generally cylindrical shape extending along the Z direction. The outer peripheral surfaces of semiconductor region 120L are surrounded by a plurality of conductive layers 110 contained in the memory cell array layer L MCA1, and face these conductive layers 110. Furthermore, the radial width W 120LL of the upper end of semiconductor region 120L is smaller than the radial width W 120LU of the lower end of semiconductor region 120L.

[0040] Semiconductor region 120U has a generally cylindrical shape extending along the Z direction. The outer peripheral surfaces of semiconductor region 120U are surrounded by a plurality of conductive layers 110 contained in the memory cell array layer L MCA2, and face these conductive layers 110. Furthermore, the radial width W 120UL of the upper end of semiconductor region 120U is smaller than the radial width W 120UU and the width W 120LU of the lower end of semiconductor region 120U.

[0041] Semiconductor regions 120J are respectively disposed below the plurality of conductive layers 110 contained in memory cell array layer L MCA1, and above the plurality of conductive layers 110 contained in memory cell array layer L MCA2. Furthermore, the radial width W 120J of semiconductor region 120J is greater than the widths W 120LU and W 120UU.

[0042] Impurity region 122 is connected to the conductive layer 100. In the example of FIG8, the boundary line between semiconductor region 120L and impurity region 122 is indicated by dashed lines. Impurity region 122 may contain, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0043] Impurity region 121 contains, for example, N-type impurities such as phosphorus (P). In the example of Figure 8, the boundary line between semiconductor region 120 U and impurity region 121 is shown by dashed lines. Impurity region 121 is connected to bit line BL via wiring ch and wiring Vy (Figure 7).

[0044] The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example, as shown in FIG9, the gate insulating film 130 includes a tunneling insulating film 131, a charge storage film 132, and a barrier insulating film 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunneling insulating film 131 and the barrier insulating film 133 include, for example, silicon oxide (SiO2). The charge storage film 132 includes, for example, silicon nitride (SiN) and other films capable of storing charge. The tunneling insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120, except for the contact portion between the semiconductor layer 120 and the conductive layer 100. Moreover, as shown in FIG8, an insulating layer 126 such as silicon oxide (SiO2) is provided between the gate insulating film 130 and the conductive layer 100.

[0045] Furthermore, Figure 9 shows an example where the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also include, for example, a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0046] For example, as shown in Figure 8, the inter-block structure ST includes a conductive layer 141 extending along the Z and X directions and an insulating layer 142 disposed on the side of the conductive layer 141. The conductive layer 141 is connected to the conductive layer 100. The conductive layer 141 may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 141 functions as part of the source line of a NAND flash memory, for example.

[0047] [Structure in the peripheral region RP of memory cell array layers L MCA1 and L MCA2 of the wafer CM] In the peripheral region RP, as shown in Figure 7, multiple via contact electrodes CC are provided corresponding to the external pad electrode PX. These multiple via contact electrodes CC are connected at their upper ends to the wiring ma, which functions as the external pad electrode PX.

[0048] [The structure of wiring layers CH, M0, M1 and MB of the wafer CM] For example, as shown in Figure 7, the multiple wirings contained in wiring layers CH, M0, M1 and MB are electrically connected to at least one of the structures of memory cell array layers L MCA1 and L MCA2 and the structure in the wafer CP.

[0049] The wiring layer CH comprises multiple wirings ch to serve as multiple wirings. These multiple wirings ch may also include, for example, multilayer films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). The wirings ch are provided corresponding to the multiple semiconductor layers 120 and are connected to the lower ends of the multiple semiconductor layers 120.

[0050] The wiring layer M0 comprises multiple wirings m0. These multiple wirings m0 may, for example, comprise a laminate of barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu). Furthermore, a portion of the multiple wirings m0 functions as bit lines BL. The bit lines BL are, for example, arranged along the X direction and extending along the Y direction.

[0051] For example, as shown in Figure 7, the wiring layer M1 includes multiple wirings m1. These multiple wirings m1 may also include, for example, stacked films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W).

[0052] The wiring layer MB includes multiple bonding electrodes PI1. These multiple bonding electrodes PI1 may also include, for example, stacked films of barrier conductive films such as titanium nitride (TiN) PI1B and metal films such as copper (Cu) PI1M.

[0053] Furthermore, as shown in Figure 4, in the edge sealing region RES, in the wiring layers CH, M0, and M1, a pattern of lines and spaces extending along the four sides of the memory die MD can also be formed. Moreover, in the wiring layer MB, at least a portion of the pattern of lines and spaces pM1 can also be formed.

[0054] [Structure of Chip CP] For example, as shown in Figure 5, the chip CP corresponds to the memory planar region RP and includes four peripheral circuit regions RPC arranged along the X and Y directions. Furthermore, the chip CP includes a circuit region RC located in the region opposite to the peripheral region RP. The circuit region RC includes multiple input / output regions IO arranged along the X direction. Moreover, the chip CP has a sealing region ES surrounding the four peripheral circuit regions RPC and the input / output regions IO. Furthermore, as shown in Figure 6, a cutout region RK is provided outside the sealing region ES. Furthermore, similar to the chip CM, in the chip CP, the cutout region RK sometimes leaves a portion after cutting, but sometimes it does not. Similar to the chip CM, in the following description, the region inside the sealing region ES (containing the four peripheral circuit regions RPC and the circuit region RC) is sometimes referred to as the memory region RM.

[0055] Moreover, as shown in FIG7, for example, the chip CP includes a semiconductor substrate 200, an electrode layer GC disposed above the semiconductor substrate 200, and wiring layers D0, D1, D2, D3, D4, and DB disposed above the electrode layer GC.

[0056] [Structure of Semiconductor Substrate 200 of Wafer CP] Semiconductor substrate 200 includes, for example, P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of semiconductor substrate 200, for example, there are N-type well regions 200N containing N-type impurities such as phosphorus (P), P-type well regions 200P containing P-type impurities such as boron (B), semiconductor substrate regions 200S without N-type well regions 200N and P-type well regions 200P, and insulating regions 200I. N-type well regions 200N, P-type well regions 200P, and semiconductor substrate regions 200S function as part of multiple transistors Tr and multiple capacitors constituting peripheral circuits, respectively.

[0057] Furthermore, as shown in Figure 6, in the sealing region R ES, on the surface of the semiconductor substrate 200, a pattern of lines and spaces extending along the four sides of the memory chip MD can also be formed by the semiconductor substrate region 200S and the insulating region 200I.

[0058] [Structure of the electrode layer GC of the wafer CP] For example, as shown in FIG7, an electrode layer GC is provided on the upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200 in the Z direction. Moreover, each region of the semiconductor substrate 200 and the plurality of electrodes gc contained in the electrode layer GC are respectively connected to the via contact electrode CS.

[0059] The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S of the semiconductor substrate 200 function as channel regions for multiple transistors Tr that constitute peripheral circuits and as one electrode of multiple capacitors, respectively.

[0060] The multiple electrodes gc contained in the electrode layer GC function as gate electrodes of multiple transistors Tr that constitute the peripheral circuit, and as the other electrode of multiple capacitors.

[0061] The through-hole contact electrode CS extends along the Z-direction and is connected at its lower end to the upper surface of the semiconductor substrate 200 or the electrode gc. At the connection point between the through-hole contact electrode CS and the semiconductor substrate 200, an impurity region containing N-type or P-type impurities is provided. The through-hole contact electrode CS may also include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0062] Furthermore, the pattern p P1 shown in FIG6 can also be formed in the electrode layer GC.

[0063] [The structure of wiring layers D0, D1, D2, D3, D4, and DB in the chip CP] For example, as shown in Figure 7, the multiple wirings contained in D0, D1, D2, D3, D4, and DB are electrically connected to at least one of the structures of memory cell array layer LMCA1, memory cell array layer LMCA2, and the structure in the chip CP.

[0064] Wiring layers D0, D1, and D2 each contain multiple wirings d0, d1, and d2. These multiple wirings d0, d1, and d2 may also include, for example, laminated films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W).

[0065] Wiring layers D3 and D4 each contain multiple wirings d3 and d4. These multiple wirings d3 and d4 may also include, for example, laminated films of barrier conductive films such as titanium nitride (TiN) and metal films such as copper (Cu).

[0066] The wiring layer DB contains multiple bonding electrodes PI2. These multiple bonding electrodes PI1 may also include, for example, multilayer films of barrier conductive films such as titanium nitride (TiN) PI2B and metal films such as copper (Cu) PI2M.

[0067] Here, if copper (Cu) metal films pI1M and pI2M are used in the bonding electrodes PI1 and PI2, the metal films pI1M and pI2M will be integrated, making it difficult to define their boundaries. However, the bonding structure can be identified by the deformation of the shape of the bonding electrodes PI1 and PI2 due to the deviation in the bonding position, and by the positional deviation of the barrier conductive films pI1B and pI2B (the generation of discontinuous parts in the side). Moreover, when the bonding electrodes PI1 and PI2 are formed by an inlay process, each side has a conical shape. Therefore, in the cross-sectional shape along the Z direction of the portion where the bonding electrodes PI1 and PI2 are bonded, the sidewalls are not straight, but non-rectangular. Furthermore, when the bonding electrodes PI1 and PI2 are bonded, a barrier metal covers the bottom, side, and top surfaces of the Cu forming them. In contrast, in typical wiring layers using Cu, an insulating layer (such as SiN or SiCN) with Cu's antioxidant properties is provided on the upper surface of the Cu layer, but no barrier metal is provided. Therefore, even without any misalignment of the bonding position, it can be distinguished from ordinary wiring layers.

[0068] Furthermore, the pattern p P1 as described with reference to FIG6 can also be formed in wiring layers D0, D1, D2, D3, and D4. Moreover, at least a portion of the pattern p P1 as described with reference to FIG6 can also be formed in wiring layer DB.

[0069] [Structure of sealing area R ES, etc.] Figure 10 is a schematic cross-sectional view showing an example of the structure of sealing area R ES and cut area RK in the first embodiment.

[0070] In the memory cell array layers LMCA1 and LMCA2 of the edge-sealing region RES, there are multiple edge-sealing ES1~ES6.

[0071] Edge seals ES1 to ES6 extend along the Z-direction and are arranged in a ring shape in the XY plane viewed from the Z-direction, outside the memory region RM, spaced apart from the inner periphery to the outer periphery of the edge seal region RM. Edge seals ES1 to ES6 are structures formed simultaneously with the inter-block structure ST as described with reference to FIG8, and similar to the inter-block structure ST, include, for example, a conductive layer such as tungsten and an insulating layer disposed on the side of the conductive layer. Edge seals ES1 to ES6 serve to prevent cracks generated when cutting monolithic semiconductor wafers from the wafer, or to prevent contaminants such as impurity ions from entering from the outside. Edge seals ES1 to ES6 are provided in a manner that surrounds the entire memory region RM, but may also be provided only in a part of it. At least one of edge seals ES2 and ES3 is provided in a manner that surrounds the entire memory region RM. Furthermore, edge seals ES1 to ES6 are sometimes also referred to as protective rings or sealing rings, or crack blocking parts.

[0072] Edge sealing ES1 is the edge sealing ES1 to ES6 located at the innermost perimeter (the side closest to the memory region within the edge sealing area R ES) when viewed from the Z direction. Edge sealing ES1 is connected to wiring ch, wiring m0, and wiring m1, but not to the bonding electrode PI1 of the wiring layer MB. Specifically, as shown in Figure 10, edge sealing ES1 is connected to wiring ch at the position that coincides when viewed from the Z direction, and is electrically connected to wiring Vy, wiring m0, wiring V1, and wiring m1 at the position that coincides when viewed from the Z direction. However, edge sealing ES1 is not electrically connected to the bonding electrode PI1. Furthermore, there is no bonding electrode PI1 located below edge sealing ES1.

[0073] Edge seals ES2 and ES3 are positioned further outward than edge seal ES1 when viewed from the Z-direction. In the example shown in Figure 10, edge seal ES3 is positioned further outward than edge seal ES2 when viewed from the Z-direction. Edge seals ES2 and ES3 are connected to wiring layers CH, M0, M1, and MB. Specifically, as shown in Figure 10, edge seals ES2 and ES3 are connected to wiring ch at the position overlapping when viewed from the Z-direction, and are electrically connected to wiring Vy, m0, V1, m1, VB, and bonding electrode PI1 at the position overlapping when viewed from the Z-direction. Edge seals ES2 and ES3 are further electrically connected to bonding electrode PI2 and multiple wirings d0, d1, d2, d3, and d4 on the wafer CP. Moreover, edge seals ES2 and ES3 are connected to wiring ma of the back wiring layer MA. Therefore, edge sealing ES2 and edge sealing ES3 allow the charge accumulated during the manufacturing process of the chip CM to dissipate (eliminate static electricity) through the semiconductor substrate that forms the chip CM. In addition, edge sealing ES2 and edge sealing ES3 can prevent impurities such as hydrogen from entering the memory region RM from the outside.

[0074] Edge sealing ES5 is positioned further outward than edge sealing ES3 when viewed from the Z-direction. Edge sealing ES5 is connected to wiring ch, wiring m0, and wiring m1, but not to the bonding electrode PI1 of the wiring layer MB. Specifically, as shown in Figure 10, edge sealing ES5 is connected to wiring ch at the position overlapping when viewed from the Z-direction, and is electrically connected to wiring Vy, wiring m0, wiring V1, and wiring m1 at the position overlapping when viewed from the Z-direction. However, edge sealing ES5 is not electrically connected to the bonding electrode PI1. Edge sealing ES5 can suppress the intrusion of impurities such as hydrogen into the memory region RM from the outside. Furthermore, edge sealing ES5 can suppress the propagation of cracks or peeling generated from the cut area RK at the outer edge of the wafer during the dicing process to the memory region RM.

[0075] Edge banding ES6 is located at the outermost periphery when viewed from the Z direction (the side closest to the cut area RK within the edge banding area R ES). Edge banding ES6 is connected to wiring ch, but not to wiring m1. Specifically, below edge banding ES6, there is no wiring layer M0 or wiring layer MB, and wiring m1 is provided with wiring layer M1 that is separated from edge banding ES6 and not electrically connected.

[0076] [Manufacturing Method] Next, the manufacturing method of the memory die (MD) will be described with reference to Figures 11 to 30. Figures 11 and 25 are schematic bottom views for explaining the manufacturing method. Figures 12 to 24 are schematic cross-sectional views for explaining the manufacturing method. Figures 26 and 27 are schematic perspective views for explaining the manufacturing method. Furthermore, Figures 12 to 24 show cross-sections corresponding to those in Figure 10.

[0077] In the manufacturing of the memory die MD in this embodiment, a wafer WM corresponding to the chip CM and a wafer WP corresponding to the chip CP are manufactured (see Figure 26). These two wafers WM and WP are bonded together (see Figure 27), and after the back wiring layer MA (Figure 7) and the like are formed, they are monolithically cut.

[0078] [Manufacturing Method of Wafer WM] Figure 11 shows the surface of a semiconductor substrate 150 corresponding to a wafer WM. As shown in Figure 11, a plurality of memory regions RM and cut-out regions RK are provided on the surface of the semiconductor substrate 150. The plurality of memory regions RM become memory dies MD after being cut. Furthermore, the structure in the cut-out regions RK is not used for voltage input / output of the memory cell array, or for input / output of data signals or other signals of the memory cell array.

[0079] During the fabrication of the wafer WM, as shown in FIG12, an insulating layer 112 such as silicon oxide (SiO2) is formed on the surface of the semiconductor substrate 150. Next, a semiconductor layer 100A such as silicon is formed on the surface of the insulating layer 112. This step is performed, for example, by chemical vapor deposition (CVD) or thermal oxidation.

[0080] Next, as shown in Figure 13, multiple insulating layers 111 and multiple sacrificial layers 110A are alternately formed in the semiconductor layer 100A of the sealing region R ES and the notched region RK using methods such as chemical vapor deposition (CVD). Furthermore, a photoresist 162 is formed in a portion of the region other than the sealing region R ES.

[0081] Next, by repeatedly removing the sacrificial layer 110A and the insulating layer 111, and removing a portion of the resist 162, a stepped structure for connecting the conductive layer 110 (as illustrated with reference to FIG8) and a contact electrode (not shown) is formed. Furthermore, in the example of FIG14, a stepped structure is also formed at the boundary between the cut region RK and the sealing region RES. These steps are performed, for example, by wet etching or dry etching methods.

[0082] Next, as shown in FIG. 15, for example, an insulating layer 113 is formed on the surface of the structure shown in FIG. 14 in the cut region RK, in the sealing region RES and the cut region RK. Next, multiple insulating layers 111 and multiple sacrificial layers 110A are formed alternately. These steps are performed, for example, by methods such as CVD. Furthermore, a photoresist 163 is formed in a portion of the area excluding the sealing region RES.

[0083] Next, the stepped structure is formed by repeatedly removing the sacrificial layer 110A and the insulating layer 111, and removing a portion of the resist 163. Furthermore, in the example of Figure 16, a stepped structure is also formed at the boundary between the cut area RK and the sealing area RES. These steps are performed, for example, by wet etching or dry etching methods.

[0084] Next, as shown in FIG17, for example, an insulating layer 113 such as silicon oxide (SiO2) is formed on the surface of the structure shown in FIG16. This step is performed, for example, by CVD.

[0085] Next, as shown in Figure 18, a resist 164 is formed that opens the areas corresponding to the sealing edges ES1 to ES6 (Figure 10), and the insulating layer 113 at the positions corresponding to the sealing edges ES1 to ES6 is removed to form trenches EST1 to EST6. Trenches EST1 to EST6 extend along the Z and X directions, penetrating the insulating layer 113 to expose the surface of the semiconductor layer 100A. This step is performed, for example, by a method such as reactive ion etching (RIE). Moreover, although not shown, trenches EST1 to EST6 are formed simultaneously with the trenches in the inter-block structure ST (Figure 7) that forms the memory planar region RMP and the notch region RK. Furthermore, although not shown, trenches are also formed in the notch region RK in this step.

[0086] Next, as shown in FIG19, for example, the sacrificial layer 110A is removed via the trenches formed in the steps described with reference to FIG18, thereby forming the conductive layer 110. In this way, the sacrificial layer 110A is replaced by the conductive layer 110. The step of removing the sacrificial layer 110A is performed, for example, by a method such as wet etching, and the step of forming the conductive layer 110 is performed, for example, by a method such as CVD. Subsequently, the inter-block structure ST is formed within the trenches that become the inter-block structure ST (FIG. 7), and edge seals ES1 to ES6 are formed within trenches EST1 to EST6. This step is performed, for example, by methods such as CVD and RIE.

[0087] Next, as shown in Figures 20 and 21, wiring ch is formed by an inlay process.

[0088] For example, as shown in Figure 20, a through hole is formed at the position corresponding to the wiring ch, exposing one end of the sealing edge ES1 to sealing edge ES6. A conductive layer chB is formed inside the through hole and on the surface of the insulating layer 113. The through hole is formed, for example, by a method such as RIE. The conductive layer chB is formed, for example, by a method such as CVD.

[0089] Next, as shown in Figure 21, a portion of the conductive layer chB is removed to form multiple wirings ch. This step is performed, for example, by a method such as chemical mechanical polishing (CMP).

[0090] Next, as shown in Figure 22, a wiring layer M0 is formed using a mosaic process. In this step, wiring Vy and wiring m0 are formed on the wiring ch formed on the edge seals ES1 to ES5 using physical vapor deposition (PVD). On the other hand, wiring Vy and wiring m0 are not formed on the wiring ch formed on the edge seal ES6.

[0091] Next, as shown in Figure 23, a wiring layer M1 is formed using an inlay process. In this step, wiring V1 and wiring m1 are formed on wiring m0 above edge banding ES1 to edge banding ES5 (in the -Z direction in the figure) using PVD or the like. On the other hand, wiring V1 is not formed above edge banding ES6 (in the -Z direction in the figure), only wiring m1 is formed. The wiring layer M1 above edge banding ES6 is formed in a floating state separated from edge banding ES6.

[0092] Next, as shown in Figure 24, a wiring layer MB is formed using an inlay process. In this step, wiring VB is formed on wiring m1 formed above edge seals ES2 to ES3 using PVD or the like. Furthermore, bonding electrode PI1 is formed on wiring VB formed above edge seals ES2 and ES3 using PVD or the like. On the other hand, bonding electrode PI1 is not formed above edge seals ES1, ES5, and ES6.

[0093] [Manufacturing Method of Wafer WP] Figure 25 shows the surface of the semiconductor substrate 250 corresponding to the wafer WP. As shown in Figure 25, the surface of the semiconductor substrate 250, like the surface of the semiconductor substrate 150, also has multiple memory regions RM and cutout regions RK between these multiple memory regions RM. The structures on the wafer WP are formed by film deposition steps such as CVD, patterning steps such as photolithography, etching, CMP and other processing steps.

[0094] [Steps after bonding wafers WM and WP] After the fabrication of wafers WM and WP, ​​for example, as shown in Figure 26, the surface of wafer WM is brought face to face with the surface of wafer WP. Then, for example, as shown in Figures 27 and 28, wafers WM and WP are bonded together. In this bonding step, for example, wafer WM is pressed towards wafer WP, thereby making wafer WM tightly bonded to wafer WP and performing heat treatment, etc. In this way, wafer WM is bonded to wafer WP via bonding electrodes PI1 and PI2.

[0095] Next, the semiconductor substrate 150 and insulating layer 112 of the wafer WM are removed.

[0096] Next, the back wiring layer MA and the like are formed to form the substrate structure L SB as shown in FIG10.

[0097] Specifically, as shown in Figure 29, a portion of the semiconductor layer 100A is removed to form contact holes corresponding to the positions of sealing edges ES1 to ES6. This step is performed, for example, by a method such as RIE. Next, an insulating layer 101 is formed. This step is performed, for example, by a method such as CVD. Next, the insulating layer 101 is removed from the contact holes corresponding to the positions of sealing edges ES1 to ES6. This exposes sealing edges ES1 to ES6. This step is performed, for example, by a method such as RIE. Next, a metal layer is formed on the upper surface of the insulating layer 101, the side surfaces of the insulating layer 101 in the X and Y directions (including the inner peripheral surfaces of the contact holes), and the upper surface of the insulating layer 103 by a method such as CVD, and a portion of the formed metal layer is removed by a method such as RIE to form wiring ma. This step is performed, for example, by a method such as RIE.

[0098] Next, as shown in FIG30, an insulating layer 102 is formed on the upper surface of the insulating layer 101, the upper surface of the wiring ma, and the side surfaces of the wiring ma in the X and Y directions (including the inner peripheral surface inside the contact hole). This step is performed, for example, by a method such as CVD.

[0099] Subsequently, the bonded wafers WM and WP are cut along the cutting line DL provided in the notch region RK. Thus, the structures provided in each memory die region RMD become memory dies MD. Furthermore, a portion of the notch region RK sometimes becomes part of the memory die MD as shown in FIG10.

[0100] [Effects of the First Embodiment] In the first embodiment, as shown in FIG10, the chip CP and the chip CM include a sealing region R ES that surrounds the memory region RM and a cutout region RK located outside the sealing region R ES. In the sealing region R ES, a plurality of sealing edges ES1 to ES6 are provided, extending along the Z direction and arranged to surround the memory region RM when viewed from the Z direction, and are spaced apart from the inner periphery to the outer periphery of the sealing region R ES. Sealing edges ES1 to ES5 are connected to wiring m0 of wiring layer M0 and wiring m1 of wiring layer M1. On the other hand, below the outermost sealing edge ES6, a wiring m1 of wiring layer M1 is provided that is not electrically connected to sealing edge ES6 and is spaced apart from sealing edge ES6 in the Z direction.

[0101] Here, as described above, at least one of the edge sealing ES2 and edge sealing ES3 is provided to surround the entire memory region RM. Furthermore, edge sealing ES2 and edge sealing ES3 are connected to the region extending from the lower surface of the substrate structure L SB to the upper surface of the semiconductor substrate 200 via wiring layers CH, M0, M1, MB, and multiple wiring layers D0-D4 and wiring DB within the chip CP. In this way, edge sealing ES2 and edge sealing ES3 allow the charge accumulated during the manufacturing process of the chip CM to dissipate (eliminate static electricity) through the semiconductor substrate forming the chip CM. Moreover, edge sealing ES2 and edge sealing ES3 can suppress the intrusion of impurities such as hydrogen into the memory region from the outside.

[0102] Furthermore, edge sealing ES1 is provided on the inner periphery of edge sealing ES2 and edge sealing ES3, and edge sealing ES5 and edge sealing ES6 are provided on the outer periphery. In this way, the area corresponding to edge sealing ES2 and edge sealing ES3 can be opened with good precision in the steps described with reference to FIG18, thereby making edge sealing ES2 and edge sealing ES3 better manufactured.

[0103] Here, in the steps described with reference to FIG27, it is ideal that the insulating layer 113 is exposed on the surface of wafers WM and WP by a certain proportion or more. This is so that the insulating layers 113 can be connected to each other when wafers WM and WP are bonded. For this reason, edge seals ES1, ES5, and ES6 are not connected to the bonding electrode PI1. Moreover, for better bonding of wafers WM and WP, ​​it is ideal that the surfaces of wafers WM and WP are flat.

[0104] Here, as illustrated with reference to FIG23, the wiring layer M1 is formed by a damascene process. As described above, in the damascene process, an opening is formed in the insulating layer, and a conductive layer is formed on the opening and the upper surface of the insulating layer. Then, a planarization method such as CMP is used to remove the conductive layer formed on the upper surface of the insulating layer, leaving a conductive layer in the opening. Here, if the density (coverage ratio) of the conductive layer in the opening is not fixed during the planarization method such as CMP, unevenness may sometimes occur on the surface of wafer WM and wafer WP.

[0105] In particular, in this embodiment, the wiring m0 within wiring layer M0 contains copper, and the wiring m1 within wiring layer M1 contains tungsten. Furthermore, the tungsten corresponding to wiring m1 is formed by PVD. This is because, since wiring m0 contains copper, it is difficult to use high-temperature processes. In this case, the unevenness problem is particularly prone to occur due to the texture of the formed tungsten film.

[0106] Therefore, in this embodiment, a wiring layer M1 is provided below the outermost edge ES6. This results in a less sparse coverage of the wiring layer M1 below the edge ES6, compared to the case where the wiring layer M1 is not provided below the edge ES6. This reduces the difference in coverage between the edge region RES and other regions in the wafer CM. Consequently, compared to the case where the wiring layer M1 is not provided below the edge ES6, the step difference between the edge region RES and other regions is reduced, improving the accuracy of the bonding steps for the bonding wafers WM and WP, ​​thereby improving the yield of the semiconductor memory device.

[0107] However, edge sealing ES6 is located on the outermost periphery among edge sealing ES1 to edge sealing ES6 in the edge sealing region R ES. Therefore, in the steps described, for example, with reference to FIG20, when forming edge sealing ES6, materials such as tungsten or silicon oxide may not be well embedded into the interior of groove EST6, resulting in a recess. Therefore, if all wiring ch, wiring m0, and wiring m1 in wiring layers CH, M0, and M1 are formed above edge sealing ES6 (in the -Z direction), unevenness may be formed on the surface of wafer WM due to the influence of this recess.

[0108] Therefore, in the first embodiment, the wiring layer CH, wiring ch in wiring layer M0, and wiring m0 are omitted below the edge sealing ES6 (in the -Z direction). According to this method, from the formation of the edge sealing ES6 until the formation of wiring m1 in wiring layer M1, the surface side (negative side in the Z direction) of the edge sealing ES6 can be flattened by means of the insulating layer 113 or the like.

[0109] [Example 1] In the first embodiment, for example as shown in FIG10, the width of the wiring m1 in the Y direction of the floating wiring layer M1 located below the edge ES6 is described as being the same as the width of the edge ES6 in the Y direction, but it is not limited thereto. Hereinafter, Examples 1 to 4 of the first embodiment will be described as cases where the width of the floating wiring layer M1 located below the edge ES6 in the Y direction is larger than the width of the edge ES6 in the Y direction.

[0110] Figure 31 is a schematic plan view showing the arrangement of the plurality of sealing edges ES1 to ES6 of the sealing area R ES in Embodiment 1 of the first embodiment and the arrangement of the wiring layer M1. Figure 32 is a schematic plan view showing an enlarged portion of Figure 31. In Figure 32, a portion c of Figure 31 is shown enlarged. Figure 33 is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the sealing edge ES6 when cut along the dashed line E-E' in Figure 31. For structures identical to those in Figure 10, the same reference numerals are used and repeated descriptions are omitted.

[0111] In the edge-sealing area R ES, a virtual pattern of multiple island-shaped wiring layers M1 arranged along the X and Y directions can also be formed, as shown in Figure 31. Figure 31 illustrates a virtual pattern of multiple wiring layers M1 arranged at a specified interval along the X and Y directions.

[0112] Furthermore, in the edge sealing area RES, as shown in Figure 31, edge sealing ES1 to edge sealing ES6 are arranged in a ring around the memory area RM (not shown). Also, the wiring layer M1 is configured to coincide with edge sealing ES1 to edge sealing ES5 when viewed from the Z direction.

[0113] Edge banding ES1 to ES5, viewed from the Z-direction, are located near the center of wiring layer M1. As shown in Figures 31 and 32, the width of wiring layer M1 that coincides with edge banding ES1 to ES5, viewed from the Z-direction, is the same as or greater than the width of edge banding ES1 to ES5. On the other hand, as shown in Figures 31 and 32, edge banding ES6 is located at one end of wiring layer M1, which is wider than edge banding ES6 when viewed from the Z-direction. As shown in Figure 33, the width of wiring m1a of the floating wiring layer M1 below edge banding ES6 in the Y-direction is greater than the width of edge banding ES6 in the Y-direction. Furthermore, as shown in Figure 33, edge banding ES6 can also partially coincide with one end of wiring layer M1 when viewed from the Z-direction, but it can also be configured not to coincide with wiring layer M1.

[0114] Therefore, in Example 1, the processing accuracy (processing deviation) of the edge banding ES6 can be taken into account when setting the wiring layer M1 below the edge banding ES6.

[0115] Furthermore, by setting the width of the wiring layer M1 below the sealing edge ES6 in the Y direction to be greater than the width of the sealing edge ES6 in the Y direction, the coverage of the wiring layer M1 in the Z direction of the sealing edge ES6 can be increased. This reduces the difference in coverage of the wiring layer M1 at the ends of the sealing edge region R ES and the notched region RK in the chip CM.

[0116] Furthermore, in Figures 31 and 32, when viewing the edge ES6 from the Z direction, a wiring layer M1 with a width larger than the edge ES6 can be seen, but this is not the only possibility. Wiring layer M0 or wiring layer V1 may also be visible. In this case, when viewed from the Z direction, for example, as shown in Figure 33, wiring layer M0 and wiring layer V1, or wiring layer M0 and wiring layer V1, may be arranged between the edge ES6 and wiring layer M1.

[0117] [Example 2] FIG34 is a schematic plan view showing the configuration of the sealing area R ES1 to sealing area ES6 and the wiring layer M1 in Example 2 of the first embodiment. FIG35 is a schematic plan view showing a portion of FIG34 enlarged. In FIG35, a portion d of FIG34 is enlarged. FIG36 is a schematic cross-sectional view showing the structure of the wiring layer M1 located below sealing area ES6 when cut along the dashed line F-F' in FIG34. For structures identical to those in FIG31 to FIG33, the same reference numerals are used and repeated descriptions are omitted.

[0118] In the edge sealing area RES, as shown in Figure 34, edge sealing ES1 to edge sealing ES6 are arranged in a ring around the memory area RM (not shown). The wiring layer M1 is configured to coincide with edge sealing ES1 to edge sealing ES6 when viewed from the Z direction.

[0119] For example, as shown in Figures 35 and 36, the edge banding ES6 is located near the center of the wiring layer M1 when viewed from the Z direction. When viewed from the Z direction, the width of the wiring m1b of the wiring layer M1 that coincides with the edge banding ES6 is greater than the width of the edge banding ES6.

[0120] By making the width of the wiring layer M1 below the sealing edge ES6 greater in the Y direction than the width of the sealing edge ES6 in the Y direction, the coverage of the wiring layer M1 in the Z direction of the sealing edge ES6 can be increased. This reduces the difference in coverage of the wiring layer M1 at the ends of the sealing edge region R ES and the notched region RK in the wafer CM.

[0121] Furthermore, in Figures 34 and 35, when viewing the edge banding ES6 from the Z direction, wiring layer M1 can be seen, but it is not limited to this. Wiring layer M0 or wiring layer V1 can also be seen. In this case, when viewed from the Z direction, for example, as shown in Figure 36, wiring layer M0 and wiring layer V1, or wiring layer M0 and wiring layer V1, are arranged between the edge banding ES6 and wiring layer M1.

[0122] [Example 3] FIG37 is a schematic plan view showing the arrangement of the plurality of sealing edges ES1 to ES6 of the sealing area R ES in Example 3 of the first embodiment and the arrangement of the wiring layer M1. FIG38 is a schematic plan view showing a portion of FIG37 enlarged. In FIG38, a portion e of FIG37 is enlarged. FIG39 is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the sealing edge ES6 when cut along the dashed line G-G' of FIG37. For structures identical to those in FIG31 to 33, the same reference numerals are used and repeated descriptions are omitted.

[0123] In the edge sealing area RES, as shown in Figure 37, edge sealing ES1 to edge sealing ES6 are arranged in a ring around the memory area RM (not shown). The wiring layer M1 is configured to coincide with edge sealing ES1 to edge sealing ES5 when viewed from the Z direction.

[0124] For example, as shown in Figures 37-39, the wiring layer M1 below the edge ES6 (in the -Z direction) is located near both sides of the edge ES6. Furthermore, as shown in Figure 39, when viewed from the Z direction, there are multiple wiring layers M1 below the edge ES6, but the total width of the multiple wirings m1c in the Y direction of the floating wiring layer M1 can also be greater than the width of the edge ES6 in the Y direction. Moreover, as shown in Figure 39, the multiple wirings m1c can also partially overlap with the edge ES6 when viewed from the Z direction, but they can also be configured not to overlap with the edge ES6.

[0125] Therefore, even if the size of the wiring layer M1 located below the sealing edge ES6 in the Y direction cannot be as large as in Embodiments 1 and 2, the total width of the wiring layer M1 located below the sealing edge ES6 in the Y direction can be set to be greater than the width of the sealing edge ES6 in the Y direction. Thus, the coverage of the wiring layer M1 in the Z direction of the sealing edge ES6 can be increased, thereby reducing the difference in coverage of the wiring layer M1 at the ends of the sealing edge region R ES and the notched region RK in the wafer CM.

[0126] Furthermore, in Figures 37 and 38, when viewing the edge banding ES6 from the Z direction, wiring layer M1 can be seen, but it is not limited to this. Wiring layer M0 or wiring layer V1 can also be seen. In this case, when viewed from the Z direction, for example, as shown in Figure 39, wiring layer M0 and wiring layer V1, or wiring layer M0 and wiring layer V1, are arranged between edge banding ES6 and wiring layer M1.

[0127] [Example 4] In Embodiment 1 and Embodiments 1 to 3, the case where the floating wiring layer M1 located below the edge banding ES6 is arranged in a straight line when viewed from the Z direction was described, but it is not limited to this. In the following Embodiment 4, the case where the floating wiring layer M1 is arranged in a serpentine manner when viewed from the Z direction will be described.

[0128] Figure 40 is a schematic plan view showing the arrangement of the multiple sealing edges ES1 to ES6 of the sealing area R ES in Embodiment 4 of the first embodiment and the arrangement of the wiring layer M1. Figure 41 is a schematic plan view showing an enlarged portion of Figure 40. In Figure 41, a partial area f of Figure 40 is shown enlarged. Figure 42 is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the sealing edge ES6 when cut along the H-H' dashed line in Figure 40. For structures identical to those in Figures 31 to 33, the same reference numerals are used and repeated descriptions are omitted.

[0129] In the edge-sealing area RES, as shown in Figure 40, edge-sealing ES1 to edge-sealing ES6 are arranged in a ring around the memory area RM (not shown). Furthermore, wiring layer M1 is configured to coincide with edge-sealing ES1 to edge-sealing ES5 when viewed from the Z direction.

[0130] For example, as shown in Figures 40 and 41, the wiring layer M1 located below the edge ES6 (in the -Z direction) partially overlaps with and serpentine with the edge ES6 when viewed from the Z direction. More specifically, as shown in Figure 41, the wiring layer M1 (of wiring m1d) located below the edge ES6 (in the -Z direction) has multiple local areas that, when viewed from the Z direction, have a specified angle with the edge ES6. These multiple local areas partially overlap with the edge ES6 when viewed from the Z direction. Furthermore, the specified angle is approximately 15 to 75 degrees, which is appropriately determined to improve the coverage of the wiring layer M1 located below the edge ES6 (in the -Z direction) when viewed from the Z direction.

[0131] Moreover, as shown in Figure 42, when viewed from the Z direction, the width of the wiring m1d of the wiring layer M1 located below the edge ES6 in the Y direction is greater than the width of the edge ES6 in the Y direction.

[0132] Thus, in Embodiment 4, the wiring layer M1 below the sealing edge ES6 can be arranged in a serpentine manner, partially overlapping with the sealing edge ES6 when viewed from the Z direction. Therefore, even if the size of the wiring layer M1 below the sealing edge ES6 in the Y direction cannot be as large as in Embodiments 1 and 2, the coverage of the wiring layer M1 in the Z direction of the sealing edge ES6 can be increased, thereby reducing the difference in coverage between the wiring layer M1 at the ends of the sealing edge region R ES and the notched region RK in the wafer CM.

[0133] Furthermore, in Figures 40 and 41, when viewing the edge banding ES6 from the Z direction, wiring layer M1 can be seen, but it is not limited to this. Wiring layer M0 or wiring layer V1 can also be seen. In this case, when viewed from the Z direction, for example, as shown in Figure 42, wiring layer M0 and wiring layer V1, or wiring layer M0 and wiring layer V1, are arranged between the edge banding ES6 and wiring layer M1.

[0134] [Example 5] In Embodiment 1 and Embodiments 1 to 4, the case where the floating wiring layer M1 located below the sealing edge ES6 is connected (continuously) when viewed from the Z direction was described, but it is not limited to this. In the following Embodiment 5, the case where the floating wiring layer M1 is arranged in a discontinuous manner when viewed from the Z direction will be described.

[0135] Figure 43 is a schematic plan view showing the arrangement of the plurality of sealing edges ES1 to ES6 of the sealing area R ES in Embodiment 5 of the first embodiment and the arrangement of the wiring layer M1. Figure 44 is a schematic plan view showing a portion of Figure 43 enlarged. Furthermore, the schematic cross-sectional view showing the structure of the wiring layer M1 located below the sealing edge ES6 is the same as that in Figure 36, so the description is omitted. Moreover, for structures identical to those in Figures 31 and 32, the same reference numerals are used and repeated descriptions are omitted.

[0136] In the edge-sealing area RES, as shown in Figure 43, edge-sealing ES1 to edge-sealing ES6 are arranged in a ring around the memory area RM (not shown). Furthermore, wiring layer M1 is configured to coincide with edge-sealing ES1 to edge-sealing ES5 when viewed from the Z direction.

[0137] For example, as shown in Figures 43 and 44, the wiring layer M1 below the edge ES6 (in the -Z direction) has a portion that partially overlaps with the edge ES6 when viewed from the Z direction, but is discontinuous. More specifically, as shown in Figure 44, the wiring layer M1 below the edge ES6 (in the -Z direction) is a single wiring layer comprising multiple locally separated regions when viewed from the Z direction. These multiple locally separated regions at least partially overlap with the edge ES6 when viewed from the Z direction. Furthermore, the distance between adjacent locally separated regions in the X direction (the distance of the discontinuous portion) only needs to be a predetermined proportion of the length of the locally separated region in the X direction (wiring length).

[0138] Moreover, as shown in Figure 44, when viewed from the Z direction, the width of the wiring layer M1 located below the edge ES6 in the Y direction is greater than the width of the edge ES6 in the Y direction.

[0139] Thus, in Embodiment 5, the wiring layer M1 below the sealing edge ES6 can be provided in a manner that has a portion that partially overlaps with and is discontinuous with the sealing edge ES6 when viewed from the Z direction. This increases the coverage of the wiring layer M1 in the Z direction of the sealing edge ES6 compared to the case where no wiring layer M1 is provided below the sealing edge ES6, thereby reducing the difference in coverage between the wiring layer M1 at the ends of the sealing edge region R ES and the notched region RK in the wafer CM.

[0140] Furthermore, the wiring layer M1 below the edge seal ES6 is designed with discontinuous portions, thus suppressing the phenomenon that cracks or peeling generated from the cut area RK at the outer edge of the wafer during the dicing process can progress along the wiring layer M1 below the edge seal ES6.

[0141] Furthermore, the wiring layer M1 located below the edge banding ES6 is not limited to a single wiring layer comprising multiple local areas separated when viewed from the Z direction, but can also be multiple wiring layers as described in Example 3.

[0142] Furthermore, in Figures 43 and 44, when viewing the edge ES6 from the Z direction, wiring layer M1 can be seen, but it is not limited to this. Wiring layer M0 or wiring layer V1 can also be seen.

[0143] [Other Embodiments] The first embodiment and the semiconductor memory devices of Examples 1 to 5 have been described above. However, the above semiconductor memory devices are merely examples, and the specific structure, etc., can be adjusted appropriately.

[0144] Figures 45-48 are schematic cross-sectional views illustrating the structure of the edge sealing ES6 and the conductive layer below the edge sealing ES6 in other embodiments.

[0145] For example, the following scenario is described: as shown in FIG10, the sealing edge ES6 of the first embodiment is connected to the wiring ch at the position that coincides when viewed from the Z direction. Below the sealing edge ES6, there is a wiring m1 of a wiring layer M1 that is separated from the sealing edge ES6 and is not electrically connected, but it is not limited to this. As long as there is no wiring layer M0 and a wiring m1d of wiring layer M1 that is separated from the sealing edge ES6 is provided, it is acceptable.

[0146] Specifically, for example, as shown in Figure 45, the edge sealing ES6 is connected to the wiring ch at the position that coincides when viewed from the Z direction, the wiring ch is connected to the wiring Vy, and below the edge sealing ES6, there is a wiring m1d of the wiring layer M1 that is separated from the edge sealing ES6 and is not electrically connected.

[0147] Furthermore, for example, as shown in Figure 46, the edge sealing ES6 is connected to the wiring ch at the position that coincides when viewed from the Z direction. Below the edge sealing ES6, there is a wiring m1d that is separated from the edge sealing ES6 and is not electrically connected to the wiring layer M1, and the wiring m1d is connected to the wiring V1.

[0148] Moreover, for example, as shown in Figure 47, the edge sealing ES6 is connected to the wiring ch at the position that coincides when viewed from the Z direction, the wiring ch is connected to the wiring Vy, and below the edge sealing ES6, there is a wiring m1d of the wiring layer M1 that is separated from the edge sealing ES6 and is not electrically connected, and the wiring m1d is connected to the wiring V1.

[0149] Furthermore, as long as the wiring m1d of wiring layer M1 is separated from and not electrically connected to the sealing edge ES6, wiring m0d of wiring layer M0 can also be provided. Specifically, for example, as shown in Figure 48, the sealing edge ES6 can be connected to the wiring ch at the position that coincides when viewed from the Z direction. Below the sealing edge ES6, wiring m1d of wiring layer M1, which is separated from and not electrically connected to the sealing edge ES6, is provided. Wiring m1d is connected to wiring V1, and wiring V1 is connected to wiring m0d of wiring layer M0. Wiring m0d of wiring layer M0 is located at the position that coincides with wiring ch when viewed from the Z direction, but is separated from and not electrically connected to wiring ch.

[0150] Next, we will describe the structure in which the wiring m1d of the wiring layer M1 located below the sealing edge ES6 can also be electrically connected to the sealing edge ES6. At this time, the wiring layer M0 can be configured to coincide with the wiring layer M1 when viewed from the Z direction.

[0151] Figure 49 is a schematic plan view showing the configuration of the sealing area R ES1 to sealing area ES6 and the wiring layer M0 and wiring layer M1 in other embodiments. Figure 50 is a schematic cross-sectional view showing the structure of wiring layer M0 and wiring layer M1 located below sealing area ES6 when cut along the dotted line I-I' in Figure 49.

[0152] In the edge sealing area RES, as shown in Figure 49, edge sealing ES1 to edge sealing ES6 are arranged in a ring around the memory area RM (not shown). Furthermore, wiring layers M0 and M1 can be positioned either to coincide with edge sealing ES1 to edge sealing ES5 when viewed from the Z direction, or not to coincide with edge sealing ES1 to edge sealing ES5.

[0153] The wiring layer M1 located below the edge banding ES6 (in the -Z direction) can, for example, be configured as shown in Figure 50, at positions that partially overlap with the edge banding ES6 when viewed from the Z direction, and at positions that do not overlap with the edge banding ES6.

[0154] Specifically, wiring m1d of wiring layer M1 can be configured at a position that partially overlaps with the edge banding ES6, and wiring m1d' of wiring layer M1 can be configured at a position that does not overlap with the edge banding ES6. These wirings are separated.

[0155] Alternatively, the wiring m0d of wiring layer M0 can be configured to coincide with the wiring m1d of wiring layer M1, which is located at a position partially overlapping with the edge ES6 when viewed from the Z direction, and the wiring m1d and wiring m0d can be electrically connected. Similarly, the wiring m0d of wiring layer M0 can be configured to coincide with the wiring m1d' of wiring layer M1, which is located at a position not overlapping with the edge ES6 when viewed from the Z direction, and the wiring m1d' and wiring m0d can be electrically connected via wiring V1.

[0156] In this case, for example as shown in Figure 50, the edge banding ES6 is electrically connected to the wiring ch, wiring Vy, wiring m0d, wiring V1 and wiring m1d at the position that coincides when viewed from the Z direction, and the edge banding ES6 is not electrically connected to the wiring m0d, wiring V1 and wiring m1d at the position that does not coincide when viewed from the Z direction.

[0157] Furthermore, as shown in Figure 49, below the edge ES6 (in the -Z direction), there are wiring layers M0 and M1 located at positions that coincide with and do not coincide with the edge ES6. These wiring layers are a single wiring layer containing multiple local areas that are separated when viewed from the Z direction.

[0158] Thus, edge banding ES6 is located on the outermost periphery among edge banding ES1 to edge banding ES6 in the edge banding area R ES. However, as mentioned above, below edge banding ES6, at a position that does not overlap with edge banding ES6 and is further outward than edge banding ES6, wiring layers M0 and M1 are provided instead of electrically connected to edge banding ES6 and wiring ch and wiring Vy are omitted. Therefore, wiring ch and wiring m0 in wiring layers CH and M0 can also be provided below edge banding ES6 without omitting them.

[0159] Furthermore, the following scenario is described: a wiring layer M0 is installed below the edge banding ES6 (in the -Z direction) and at a position where the wiring layer M1 is located but does not overlap with the edge banding ES6, but it is not limited to this scenario; the wiring layer M0 may also be omitted.

[0160] [Other] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0161] 100, 110, 141, chB: Conductive layer 100A, 120: Semiconductor layer 101, 102, 111, 112, 113, 125, 126, 142, 200G, SHE: Insulation layer 110A: Sacrificial Layer 120 J, 120 L, 120 U: Semiconductor regions 121, 122: Impurity regions 130: Gate insulating film 131: Tunneling Insulation Film 132: Charge storage membrane 133: Barrier insulating film 150, 200, 250: Semiconductor substrate 162, 163, 164: Corrosion resist 200I: Insulation Area 200N: N-type trap region 200P: P-type trap region 200S: Semiconductor substrate area a1, a2, a3, a4, b1, b2, b3, b4: Corners BL: Bitline BLK: Memory Block c, d, e, f: Local regions CC, CS: Through-hole contact electrodes CH, D0, D1, D2, D3, D4, DB, M0, M1, MB: Wiring layers ch, d0, d1, d2, d3, d4, m0, m0d, m1, m1a, m1b, m1c, m1d, m1d', ma, V1, VB, Vy: Wiring CM, CP: Chip DL: Cutting line ES1, ES2, ES3, ES4, ES5, ES6: Edge Sealing EST1, EST2, EST3, EST5, EST6: slot GC: Electrode layer gc: electrode LMCA1, LMCA2: Memory Cell Array Layer LSB: Matrix structure L WL: Character Line Layer MA: Backside wiring layer MD: Memory chip PI1, PI2: Bonding electrodes PI1B, PI2B: Barrier conductive film PI1M, PI2M: Metallic films PM1, PP1: Pattern PX: External solder pad electrode RC: Circuit area R ES: Edge Sealing Area R IO: Input / Output Area RK: Incision area RM: Memory area R MD: Memory die region R MP: Memory Plane Region RP: Surrounding Area RPC: Peripheral Circuit Area ST: Inter-block structure Tr: transistor TV: Opening VZ: Region W 120J, W 120LL, W 120LU, W 120UL, W 120UU: Width WM, WP: Wafer X, Y, Z: Direction

Claims

1. A semiconductor memory device, comprising a first wafer and a second wafer bonded together via a plurality of bonding electrodes, wherein the first wafer and the second wafer comprise: The memory region includes a memory cell array or peripheral circuitry connected to the memory cell array; The first wafer includes: a semiconductor substrate; and a plurality of first conductive layers disposed in the edge sealing region and connected to the semiconductor substrate in a first direction intersecting the surface of the semiconductor substrate. The second wafer includes: a plurality of edges extending along the first direction in the edge sealing region and arranged to surround the memory region when viewed from the first direction, spaced apart from the inner periphery to the outer periphery of the edge sealing region; a first wiring layer disposed on the first wafer side relative to the plurality of edges; and a second wiring layer disposed on the first wafer side relative to the first wiring layer, including a plurality of wirings containing tungsten (W). The first wiring layer includes a plurality of second conductive layers disposed in the edge sealing region and located at positions that coincide with a plurality of first edges other than the outermost periphery when viewed from the first direction, and are electrically connected to the plurality of first edges. The second wiring layer includes: A plurality of third conductive layers are disposed in the sealing area and are located at positions that coincide with the plurality of first sealing edges when viewed from the first direction, and are electrically connected to the plurality of first sealing edges; and a fourth conductive layer is disposed in the sealing area and is located at a position further outward than the plurality of third conductive layers when viewed from the first direction, is not electrically connected to the second sealing edge that is the outermost edge when viewed from the first direction, and is separated from the second sealing edge.

2. The semiconductor memory device of claim 1, wherein one of the plurality of first sealing edges is electrically connected to one of the plurality of bonding electrodes via one of the plurality of second conductive layers and one of the plurality of third conductive layers, and the other of the plurality of first sealing edges is not electrically connected to any of the plurality of bonding electrodes.

3. The semiconductor memory device as claimed in claim 1, wherein the fourth conductive layer includes a portion that overlaps with the second sealing edge when viewed from the first direction.

4. The semiconductor memory device as claimed in claim 1, wherein the fourth conductive layer includes a portion that does not coincide with the second sealing edge when viewed from the first direction.

5. The semiconductor memory device of claim 1, wherein the second sealing edge includes a first extension extending along a second direction intersecting the first direction, the fourth conductive layer includes a second extension extending along the second direction, and the width of the second extension in a third direction intersecting the first and second directions is greater than the width of the first extension in the second direction.

6. The semiconductor memory device of claim 1, wherein the second wiring layer further includes a fifth conductive layer, the fifth conductive layer being disposed in the sealing region and located on the outer periphery side of the second sealing edge when viewed from the first direction, not electrically connected to the second sealing edge, and spaced apart from the second sealing edge, and the fourth conductive layer being located on the inner periphery side of the second sealing edge when viewed from the first direction.

7. The semiconductor memory device as claimed in claim 6, wherein the fourth conductive layer and the fifth conductive layer do not coincide with the second sealing edge when viewed from the first direction.

8. The semiconductor memory device of claim 1, wherein the fourth conductive layer, when viewed from the first direction, partially overlaps with and serpentine with the second sealing edge.

9. The semiconductor memory device of claim 8, wherein the fourth conductive layer has a plurality of local regions that are respectively at a predetermined angle to the second sealing edge when viewed from the first direction, and the plurality of local regions partially overlap with the second sealing edge when viewed from the first direction.

10. The semiconductor memory device of claim 8, wherein the fourth conductive layer is a wiring comprising a plurality of locally spaced regions as viewed from the first direction, the plurality of locally spaced regions at least partially overlapping the second sealing edge as viewed from the first direction.

11. A semiconductor memory device, comprising a first wafer and a second wafer bonded together via a plurality of bonding electrodes, wherein the first wafer and the second wafer comprise: The memory region includes a memory cell array or peripheral circuitry connected to the memory cell array; The first wafer includes: a semiconductor substrate; and a plurality of first conductive layers disposed in the edge sealing region and connected to the semiconductor substrate in a first direction intersecting the surface of the semiconductor substrate. The second wafer includes: a plurality of edges extending along the first direction in the edge sealing region and arranged to surround the memory region when viewed from the first direction, spaced apart from the inner peripheral side to the outer peripheral side of the edge sealing region; a first wiring layer disposed on the first wafer side relative to the plurality of edges; and a second wiring layer disposed on the first wafer side relative to the first wiring layer, including a plurality of wirings containing tungsten (W). The first wiring layer includes a plurality of second conductive layers disposed in the edge sealing region and at a position coinciding with the plurality of edges when viewed from the first direction, and electrically connected to the plurality of edges. The second wiring layer includes: A plurality of third conductive layers are disposed in the sealing area, and are disposed at a position that coincides with the plurality of sealing edges when viewed from the first direction, and are electrically connected to the plurality of sealing edges; and a fourth conductive layer is disposed in the sealing area, further to the outer periphery and inner periphery than the third conductive layer disposed at a position that coincides with the first sealing edge which is the outermost periphery when viewed from the first direction, is disposed separately from the third conductive layer, is not electrically connected to the first sealing edge, and is separated from the first sealing edge.

12. The semiconductor memory device of claim 11, wherein the first wiring layer includes a fifth conductive layer disposed in the sealing region and disposed further on the outer and inner peripheral sides than the second conductive layer disposed at a position coinciding with the first sealing edge when viewed from the first direction, spaced apart from the second conductive layer, not electrically connected to the first sealing edge, and spaced apart from the first sealing edge.

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