Driving circuit for display panel

Abstract

This invention provides a driving circuit for a display panel, comprising a driving signal generating circuit that generates a driving signal during one frame to drive a display element of the display panel. The driving signal has at least a first on pulse width, at least a first off pulse width, at least a second on pulse width, and at least a second off pulse width. The first on pulse width is greater than the second on pulse width, and the first off pulse width is less than the second off pulse width. Using the driving circuit of this invention can reduce electromagnetic interference and improve display quality.

Description

Technical Field

[0001] The present invention relates to a driving circuit, and in particular to a driving circuit for a display panel. Prior Art

[0002] Display devices have become essential equipment for electronic products to display information. Display devices have evolved from liquid crystal display devices to sub-millimeter light-emitting diode (Mini LED) display devices and micro light-emitting diode (Micro LED) display devices. As a display element, light-emitting diodes can improve the display quality of display devices. Conventional technology to drive the above-mentioned light-emitting diodes will cause high electromagnetic interference (EMI), which will affect the display quality.

[0003] Based on the above, the present invention provides a driving circuit for a display panel. The driving circuit can reduce EMI and improve display quality. Summary of the invention

[0004] One purpose of the present invention is to provide a driving circuit for a display panel, which changes the frequency of a driving signal for driving a display element during a frame period, thereby reducing electromagnetic interference and improving display quality.

[0005] The present invention provides a driving circuit for a display panel, which includes a driving signal generating circuit. The driving signal generating circuit generates a driving signal during a frame period to drive a display element of the display panel. The driving signal has at least one first conduction pulse width, at least one second conduction pulse width, and at least one third conduction pulse width. The first conduction pulse width is greater than the second conduction pulse width and the third conduction pulse width, and the second conduction pulse width is less than the third conduction pulse width. The driving signal generating circuit generates the second conduction pulse width at a time during the frame period, and then generates the first conduction pulse width or the third conduction pulse width.

[0006] The present invention further provides a driving circuit for a display panel, which includes a driving signal generating circuit. The driving signal generating circuit generates a driving signal during a frame period to drive a display element of the display panel. The driving signal has at least one first on-pulse width and at least one first off-pulse width, at least one second on-pulse width, and at least one second off-pulse width. The first on-pulse width is greater than the second on-pulse width, and the first off-pulse width is less than the second off-pulse width.

[0007] The present invention further provides a driving circuit for a display panel, comprising a driving signal generating circuit, wherein the driving signal generating circuit generates a driving signal having a plurality of first conduction pulse widths during an F-1 frame period to drive a display element of the display panel, and generates a driving signal having a plurality of second conduction pulse widths during an F frame period to drive the display element. The second conduction pulse widths are different from the first conduction pulse widths, the time during the F-1 frame period is the same as the time during the F frame period, and F is an integer greater than 2. Simple diagram description

[0008] FIG1 is a schematic diagram of an embodiment of the drive structure of the present invention; FIG2 is a block diagram of an embodiment of a driver and a display element of the present invention; FIG3 is a block diagram of an embodiment of a controller and a driver of the present invention; FIG4 is a block diagram of an embodiment of a driving circuit of the present invention; FIG5 is a schematic diagram of a first embodiment of a driving signal; FIG6 is a schematic diagram of a second embodiment of a driving signal; FIG7 is a schematic diagram of a third embodiment of a driving signal; FIG8 is a schematic diagram of a fourth embodiment of a driving signal; FIG9 is a schematic diagram of a fifth embodiment of a driving signal; FIG10 is a schematic diagram of a sixth embodiment of a driving signal; Figures 11 to 13 are schematic diagrams of the seventh to ninth embodiments of the driving signal. Implementation

[0009] In order to enable you, the examiner, to have a further understanding and recognition of the features and effects achieved by the present invention, embodiments and accompanying descriptions are provided as follows:

[0010] Certain words are used in the specification and claims to refer to specific components. However, those with ordinary knowledge in the technical field of the present invention should understand that manufacturers may use different terms to refer to the same component. Moreover, the specification and claims do not use the difference in name as a way to distinguish components, but use the difference in the overall technology of the components as the criterion for distinction. The term "including" mentioned throughout the specification and claims is an open term and should be interpreted as "including but not limited to". Furthermore, the term "coupled" includes any direct and indirect connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly connected to the second device, or can be indirectly connected to the second device through other devices or other connection means.

[0011] Please refer to the first and second figures. The first figure is a schematic diagram of an embodiment of the driving structure of the present invention, and the second figure is a block diagram of an embodiment of the driver and display element of the present invention. As shown in the figure, the driving structure includes a controller 1 and a plurality of drivers 2 to drive the sub-pixels of a plurality of pixels of the display panel 10 to display images. The drivers 2 are arranged in a plurality of rows, and each driver 2 is coupled to a plurality of display elements 4 to drive the display elements 4 to emit light. The display elements 4 are sub-pixels. In one embodiment of the present invention, the display elements 4 can be sub-millimeter light-emitting diodes or micro-light-emitting diodes. The controller 1 is coupled to the drivers 2 and transmits an input data Din, a timing signal DCK, a clock signal PWMCLK and an enable signal EN to the driver 2. In one embodiment of the present invention, the controller 1 can be an independent chip. Since the drivers 2 are arranged in a plurality of rows, the pixels arranged in rows and columns on the display panel 10 can be controlled.

[0012] Please refer to the third figure, which is a block diagram of an embodiment of the controller and driver of the present invention. As shown in the figure, each driver 2 includes an enable circuit 6, a storage circuit 7 and a drive circuit 9. The enable circuit 6 receives an enable signal EN, and enables the storage circuit 7 according to the enable signal EN to receive input data Din according to the timing signal DCK. The drive circuit 9 couples the storage circuit 7 and the display elements 4, and generates a plurality of drive signals according to the input data Din received by the storage circuit 7 and the clock signal PWMCLK to drive the display elements 4 to generate light so as to display images. After the first driver 2 drives the display elements 4, the enable circuit 6 of the first driver 2 will disable the storage circuit 7 of the first driver 2, and send an enable signal EN to the enable circuit 6 of the second driver 2 to perform the above-mentioned action, and drive the display elements 4 coupled to the second driver 2, and so on.

[0013] Please refer to FIG. 4, which is a block diagram of an embodiment of the driving circuit of the present invention. As shown in the figure, the storage circuit 7 is coupled to the enabling circuit 6 and receives the input data Din and the timing signal DCK. The enabling circuit 6 enables the storage circuit 7 according to the received enabling signal, drives the storage circuit 7 to receive the input data Din according to the timing signal DCK, and stores the input data Din. The driving circuit 9 includes a driving signal generating circuit, which includes a plurality of comparison circuits 91, a counter 93, and a plurality of level conversion circuits 95. The comparison circuits 91 are coupled to the storage circuit 7 and the counter 93. The counter 93 receives the clock signal PWMCLK, and outputs a counting signal according to the counting of the clock signal PWMCLK. The counting signal changes with the counting of the counter 93. Each comparison circuit 91 receives the counting signal and the pixel data of the input data Din stored in the storage circuit 7, and compares the counting signal with the pixel data. When the pixel data is greater than the counting signal, the comparison circuit 91 outputs a driving signal with a driving level, such as a high level. In another embodiment of the present invention, when the pixel data is less than the count signal, the comparison circuit 91 outputs a driving signal with a driving level. The level conversion circuits 95 are coupled to the comparison circuits 91 and convert the level of the driving signal output by the comparison circuits 91. In one embodiment of the present invention, the level conversion circuit 95 may not be required. One end of the display elements 4 is coupled to a supply voltage VDD, and a switch MOS is coupled between the other end of the display elements 4 and a ground terminal. The driving signal generated by the comparison circuit 91 is used to control the switch MOS to drive current to flow through the display elements 4 to generate light. From the above description, it can be seen that the time when the comparison circuit 91 continues to generate the driving level of the driving signal is the driving time, that is, the time for driving the display element 4, which determines the brightness of the display element 4.

[0014] Please refer to FIG5, which is a schematic diagram of an embodiment of the driving signal. As shown in the figure, the driving signal has a conduction pulse width (high level) and a cut-off pulse width (low level) during a frame period, that is, the driving signal has a pulse width modulation (PWM), and the conduction pulse width determines the time when the display element 4 generates light.

[0015] Please refer to FIG. 6, which is a schematic diagram of another embodiment of the driving signal. As shown in the figure, the driving signal has a plurality of on-pulse widths and a plurality of off-pulse widths during a frame period, that is, the driving signal has N pulse width modulations. The driving signal shown in FIG. 6 is better than the driving signal shown in FIG. 5, and can reduce the flicker phenomenon of the display element 4. Similarly, when the display element 4 is driven to display for 0.1 seconds, and the frame period is 0.2 seconds, the driving signal in FIG. 5 drives the display element 4 to be continuously lit for 0.1 seconds and continuously off for 0.1 seconds, which is easy to cause flicker. If the driving signal shown in FIG. 6 has 10 on-pulse widths, it means that 0.1 seconds is divided into 10 on-pulse widths, and the display element 4 is driven to display for 0.01 seconds respectively. In this way, during the frame period, the display element 4 is still lit for 0.1 seconds, but the flicker can be reduced. However, if the display element 4 is continuously driven with the same width of on-pulse width, there will be higher electromagnetic interference.

[0016] Please refer to FIG. 7, which is a schematic diagram of the third embodiment of the driving signal. As shown in the figure, the driving circuit 9 generates a driving signal during a frame period. The driving signal has a plurality of first conduction pulse widths and a plurality of second conduction pulse widths. The first conduction pulse width is greater than the second conduction pulse width, which indicates that the frequency of the clock signal PWMCLK received by the driving circuit 9 is the first frequency f1 or the second frequency f2. The driving circuit 9 generates the first conduction pulse width according to the clock signal PWMCLK having the first frequency f1, and generates the second conduction pulse width according to the clock signal PWMCLK having the second frequency f2. The first frequency f1 is less than the second frequency f2. Since the frequency of the driving signal changes during a frame period, electromagnetic interference can be reduced. The counter 93 counts based on a fixed number of clock pulses to generate the first conduction pulse width and the second conduction pulse width. For example, the counter 93 counts again each time the clock signal PWMCLK reaches 4096, which indicates that the maximum value of the count signal is 4096.

[0017] Please refer to FIG8, which is a schematic diagram of the fourth embodiment of the driving signal. As shown in the figure, the driving circuit 9 generates a driving signal during a frame period. The driving signal has a plurality of first conduction pulse widths, a plurality of second conduction pulse widths, and a plurality of third conduction pulse widths. The first conduction pulse width is greater than the second conduction pulse width and the third conduction pulse width, and the second conduction pulse width is less than the third conduction pulse width. This indicates that the frequency of the clock signal PWMCLK received by the driving circuit 9 is the first frequency f1, the second frequency f2, or the third frequency f3. The driving circuit 9 generates the first conduction pulse width according to the clock signal PWMCLK having the first frequency f1, and generates the second conduction pulse width according to the clock signal PWMCLK having the second frequency f2. The driving circuit 9 generates the third conduction pulse width according to the clock signal PWMCLK having the third frequency f3. The first frequency f1 is less than the second frequency f2 and the third frequency f3, and the third frequency f3 is less than the second frequency f2. In one embodiment of the present invention, at a certain time in the frame period, the second conduction pulse width is first generated, and then the first conduction pulse width or the third conduction pulse width is generated, that is, the second conduction pulse width is first generated according to the clock signal PWMCLK with the second frequency f2, and then the first conduction pulse width or the third conduction pulse width is generated according to the clock signal PWMCLK with the first frequency f1 or the third frequency f3. The counter 93 counts based on the fixed number of clocks to generate the first, second, and third conduction pulse widths.

[0018] In one embodiment of the present invention, the driving signal generating circuit sequentially generates N first conduction pulse widths of the first conduction pulse widths, P second conduction pulse widths of the second conduction pulse widths, and Q third conduction pulse widths of the third conduction pulse widths within a frame period and outside a certain time, wherein N, P, and Q are integers greater than 0, that is, the first, second, or third conduction pulse widths can be continuously generated. Alternatively, the driving signal generating circuit sequentially generates Q third conduction pulse widths of the third conduction pulse widths, P second conduction pulse widths of the second conduction pulse widths, and N first conduction pulse widths of the first conduction pulse widths.

[0019] The driving circuit 9 of the present invention generates a driving signal during a plurality of frames, and the time of the frame periods is the same, and the driving signal has at least one of the first, second and third conduction pulse widths. That is, the driving signal is generated during an F-1 frame period, an F frame period, and an F+1 frame period, and the driving signal has at least one of the first conduction pulse width, the second conduction pulse width and the third conduction pulse width. The time of the F-1 frame period, the time of the F frame period and the time of the F+1 frame period are the same, and F is an integer greater than 2.

[0020] Please refer to FIG. 9, which is a schematic diagram of the fifth embodiment of the driving signal. As shown in the figure, there are multiple pulse width modulation cycles (PWM cycles) in one frame period, and the frequency of the clock signal PWMCLK is continuously increased from the first frequency f1 to the second frequency f2 (in this embodiment, odd-numbered PWM cycles) over time, and then continuously decreased from the second frequency f2 to the first frequency f1 (in this embodiment, even-numbered PWM cycles) over time. In this way, during the period when the frequency of the clock signal PWMCLK is changed from the first frequency f1 to the second frequency f2, the driving circuit 9 generates a first on-pulse width and a first off-pulse width according to the clock signal PWMCLK, and generates a second on-pulse width and a second off-pulse width according to the clock signal PWMCLK during the period when the frequency of the clock signal PWMCLK is changed from the second frequency f2 to the first frequency f1. The first on-pulse width is greater than the second on-pulse width, and the first off-pulse width is less than the second off-pulse width. The first on-pulse width can be equal to the second off-pulse width, and the second on-pulse width can be equal to the first off-pulse width. The counter 93 counts based on a fixed number of clock pulses to generate a first on-pulse width, a first off-pulse width, a second on-pulse width, and a second off-pulse width.

[0021] Please refer to FIG. 10, which is a schematic diagram of the sixth embodiment of the driving signal. As shown in the figure, there are multiple PWM cycles in one frame period, and the frequency of the clock signal PWMCLK is directly changed from the first frequency f1 to the third frequency f3 and then directly changed to the second frequency f2 (in this embodiment, odd PWM cycles) over time, and then directly changed from the second frequency f2 to the third frequency f3 over time, and then directly changed to the first frequency f1 (in this embodiment, even PWM cycles) over time, so that the driving circuit 9 generates a driving signal with a variable pulse width, and the driving signal is similar to the driving signal of the embodiment of FIG. 9.

[0022] Please refer to Figures 11 to 13. The driving circuit 9 of the present invention generates driving signals during multiple frame periods, and the time of these frame periods is the same to drive the same display element. The driving signal generated during each frame period has the same on-pulse width and off-pulse width, but the on-pulse width and off-pulse width of different frame periods are different, which means that the driving circuit generates driving signals during different frame periods according to three different frequency clock signals PWMCLK. For example, Figure 11 shows that the driving circuit 9 generates a driving signal with a first on-pulse width and a first off-pulse width during the F-1 frame period, Figure 12 shows that the driving circuit 9 generates a driving signal with a third on-pulse width and a third off-pulse width during the F frame period, and Figure 13 shows that the driving circuit 9 generates a driving signal with a second on-pulse width and a second off-pulse width during the F+1 frame period. The time of the F-1 frame period, the time of the F frame period, and the time of the F+1 frame period are the same, and F is an integer greater than 2.

[0023] Therefore, this invention is novel, progressive and can be used in industry. It should undoubtedly meet the patent application requirements of my country's Patent Law. Therefore, I have filed an invention patent application in accordance with the law and pray that the patent will be approved by the Bureau as soon as possible. I am grateful for your prayers.

[0024] However, the above is only an embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent changes and modifications based on the structure, characteristics and spirit described in the patent application scope of the present invention should be included in the patent application scope of the present invention.

[0025] 1: Controller 2: Driver 4: Display components 6: Enable circuit 7: Storage circuit 9: Driving circuit 10: Display Panel Din: Input data DCK: Timing signal EN:Enable signal f1: first frequency f2: second frequency f3: third frequency MOS: Switch PWMCLK: clock signal VDD: voltage

Claims

1. A driving circuit for a display panel, comprising: a driving signal generating circuit that generates a driving signal during one frame to drive a display element of the display panel, the driving signal having at least a first on-pulse width, at least a second on-pulse width, and at least a third on-pulse width, wherein the first on-pulse width is greater than the second on-pulse width and the third on-pulse width, and the second on-pulse width is less than the third on-pulse width; wherein... During a period of the frame, the drive signal generation circuit first generates the second conduction pulse width, and then continues to generate the first conduction pulse width or the third conduction pulse width.

2. The driving circuit as described in claim 1, wherein the driving signal generating circuit first generates the second conduction pulse width, then generates the first conduction pulse width, and then generates the third conduction pulse width during the time period of the frame.

3. The driving circuit as described in claim 1, wherein the driving signal generating circuit first generates the second conduction pulse width and then generates the third conduction pulse width and then generates the first conduction pulse width during the time period of the frame.

4. The driving circuit as claimed in claim 1, wherein the driving signal generating circuit generates the first conduction pulse width, the second conduction pulse width, and the third conduction pulse width according to a fixed number of complex clock cycles.

5. The driving circuit as claimed in claim 1, wherein the driving signal generating circuit generates the driving signal based on a clock signal having a plurality of clocks, one frequency of the clock signal being a first frequency, a second frequency, or a third frequency, and the driving signal generating circuit generates a first conduction pulse width based on the clock signal having the first frequency, generates a second conduction pulse width based on the clock signal having the second frequency, and generates a third conduction pulse width based on the clock signal having the third frequency.

6. The driving circuit as described in claim 1, wherein the at least one first conduction pulse width includes a plurality of first conduction pulse widths, the at least one second conduction pulse width includes a plurality of second conduction pulse widths, the at least one third conduction pulse width includes a plurality of third conduction pulse widths, and the driving signal generating circuit sequentially generates N first conduction pulse widths, P second conduction pulse widths, and Q third conduction pulse widths during the frame period and outside the time period, wherein N, P, and Q are integers greater than 1.

7. The driving circuit as described in claim 1, wherein the at least one first conduction pulse width includes a plurality of first conduction pulse widths, the at least one second conduction pulse width includes a plurality of second conduction pulse widths, the at least one third conduction pulse width includes a plurality of third conduction pulse widths, and the driving signal generating circuit sequentially generates Q third conduction pulse widths, P second conduction pulse widths, and N first conduction pulse widths during the frame period and outside the time period, wherein N, P, and Q are integers greater than 1.

8. The driving circuit as claimed in claim 1, wherein the frame period is a frame F period, the driving signal generating circuit generates the driving signal during a frame F-1 period and a frame F+1 period, the driving signal having at least one of the first conduction pulse width, the second conduction pulse width and the third conduction pulse width, the time of the frame F-1 period, the time of the frame F period and the time of the frame F+1 period are the same, and F is an integer greater than 2.

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