Semiconductor structure and fabrication method thereof

Abstract

A semiconductor structure includes a substrate having at least one through-silicon via (TSV) formation region; a dielectric layer disposed on the substrate; and at least one TSV disposed in the TSV formation region, penetrating the dielectric layer and entering the substrate, wherein the at least one TSV includes a plurality of radially extending stress-relieving slits.

Claims

1. A semiconductor structure comprising: a substrate having at least one through-silicon via (TSV) formation region thereon; a dielectric layer disposed on the substrate; and at least one TSV disposed in the TSV formation region, penetrating the dielectric layer and entering the substrate, wherein, The at least one through-silicon via includes a plurality of radially extending stress-relief slits, wherein the plurality of stress-relief slits extend longitudinally over the entire thickness of the at least one through-silicon via.

2. The semiconductor structure as described in claim 1, wherein, The at least one through-silicon hole has a circular shape when viewed from above.

3. The semiconductor structure as described in claim 1, wherein, The plurality of stress-relieving slits are symmetrically distributed around the circumference of the at least one through-silicon via.

4. The semiconductor structure as described in claim 1, wherein, The at least one through-silicon via has a gear shape when viewed from above, including a plurality of toothed portions, wherein the plurality of stress-relieving slits are disposed between the plurality of toothed portions.

5. The semiconductor structure as described in claim 1, wherein, Each of the plurality of stress-relief slits comprises two long sides with a length less than or equal to W / 5, and a bottom side with a width less than or equal to W / 10, wherein W is the width of the at least one through-silicon via.

6. The semiconductor structure as described in claim 5, wherein, The angle between one of the two longer sides and the base is equal to or greater than 90 degrees.

7. The semiconductor structure as claimed in claim 1, wherein, The at least one through-silicon via includes a copper core layer, an adhesive layer surrounding the copper core layer, and a pad oxide layer surrounding the adhesive layer.

8. The semiconductor structure as claimed in claim 1, wherein, The dielectric layer and the substrate extend into the plurality of stress-relief slits.

9. The semiconductor structure as claimed in claim 1, wherein, The substrate includes a plurality of element regions, wherein at least one TSV forming region is disposed between the plurality of element regions.

10. The semiconductor structure as described in claim 9, wherein, These multiple component regions are deep trench capacitor regions.

11. A method of forming a semiconductor structure, comprising: providing a substrate having at least one through-silicon via (TSV) formation region; forming a dielectric layer on the substrate; and forming at least one TSV in the TSV formation region, wherein, The at least one through-silicon via penetrates the dielectric layer and enters the substrate, wherein the at least one through-silicon via includes a plurality of radially extending stress-relief slits, wherein the plurality of stress-relief slits extend longitudinally over the entire thickness of the at least one through-silicon via.

12. The method as described in claim 11, wherein, The at least one through-silicon hole has a circular shape when viewed from above.

13. The method as described in claim 11, wherein, The plurality of stress-relieving slits are symmetrically distributed around the circumference of the at least one through-silicon via.

14. The method as described in claim 11, wherein, The at least one through-silicon via has a gear shape when viewed from above, including a plurality of toothed portions, wherein the plurality of stress-relieving slits are disposed between the plurality of toothed portions.

15. The method as described in claim 11, wherein, Each of the plurality of stress-relief slits comprises two long sides with a length less than or equal to W / 5, and a bottom side with a width less than or equal to W / 10, wherein W is the width of the at least one through-silicon via.

16. The method as described in claim 15, wherein, The angle between one of the two longer sides and the base is equal to or greater than 90 degrees.

17. The method as described in claim 11, wherein, The at least one through-silicon via includes a copper core layer, an adhesive layer surrounding the copper core layer, and a pad oxide layer surrounding the adhesive layer.

18. The method as described in claim 11, wherein, The dielectric layer and the substrate extend into the plurality of stress-relief slits.

19. The method as described in claim 11, wherein, The substrate includes a plurality of element regions, wherein at least one TSV forming region is disposed between the plurality of element regions.

20. The method as described in claim 19, wherein, These multiple component regions are deep trench capacitor regions.

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