Manufacturing method for semiconductor device

Abstract

An embodiment provides a method for manufacturing a semiconductor device with improved reliability. The method for manufacturing a semiconductor device according to the embodiment includes: a first step, in which a first load is applied to a semiconductor element to press the bumps of the semiconductor element against a wiring substrate, and ultrasonic vibration is not applied to the bumps or ultrasonic vibration of a first intensity is applied to the bumps to deform the bumps; and a second step, in which, after the first step, a second load is applied to the semiconductor element to press the bumps of the semiconductor element against the wiring substrate, and ultrasonic vibration of a second intensity stronger than the first intensity is applied to the bumps to bond the bumps to the pads of the wiring substrate.

Description

Technical Field

[0001] The implementation method relates to a method for manufacturing a semiconductor device. Prior Technology

[0002] In semiconductor devices using flip-chip technology, ultrasonic vibrations can be applied to connect the substrate and the flip-chip bumps. In semiconductor devices using NAND memory chips, technologies for bonding flip-chip to the substrate are also being researched. Summary of the Invention

[0003] The embodiment provides a method for manufacturing a semiconductor device with improved reliability.

[0004] The method for manufacturing a semiconductor device according to the embodiment includes: a first step, which involves applying a first load to a semiconductor element to press the bumps of the semiconductor element against a wiring substrate, and not applying ultrasonic vibration to the bumps or applying ultrasonic vibration of a first intensity to the bumps to deform the bumps; and a second step, which involves, after the first step, applying a second load to the semiconductor element to press the bumps of the semiconductor element against the wiring substrate, and applying ultrasonic vibration of a second intensity stronger than the first intensity to the bumps to bond the bumps to the pads of the wiring substrate. Simple Explanation of the Diagram

[0005] Figure 1 is a flowchart of the manufacturing method of the semiconductor device according to the embodiment. Figure 2 is a partial schematic diagram of the semiconductor device according to the embodiment. Figure 3 shows the curves of deformation of load, ultrasonic intensity, and bump height in the manufacturing method of the semiconductor device according to the embodiment. Figure 4 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 5 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 6 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 7 shows the curves of deformation of load, ultrasonic intensity, and bump height in the manufacturing method of the semiconductor device according to the embodiments. Figure 8 shows the curves of deformation of load, ultrasonic intensity, and bump height in the manufacturing method of the semiconductor device according to the embodiments. Figure 9 shows the curves of deformation of load, ultrasonic intensity, and bump height in the manufacturing method of the semiconductor device according to the embodiments. Figure 10 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 11 is a flowchart of the manufacturing method of the semiconductor device according to the embodiment. Figure 12 shows the curves of deformation of load, ultrasonic intensity, and bump height in the manufacturing method of the semiconductor device according to the embodiments. Figure 13 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 14 is a flowchart of the manufacturing method of the semiconductor device according to the embodiment. Figure 15 shows the curves of deformation of load, ultrasonic intensity, and bump height in the manufacturing method of the semiconductor device according to the embodiments. Figure 16 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 17 is a flowchart of the manufacturing method of the semiconductor device according to the embodiment. Figure 18 shows the curves of deformation of load, ultrasonic intensity, and bump height in the manufacturing method of the semiconductor device according to the embodiments. Figure 19 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 20 is a flowchart of the manufacturing method of the semiconductor device according to the embodiments. Figure 21 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Figure 22 is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. Implementation

[0006] This specification provides multiple examples of expressions for some elements. Furthermore, these examples are merely illustrative and do not preclude the possibility of expressing the elements in other ways. Also, elements for which no multiple expressions are provided may be expressed in other ways.

[0007] Furthermore, the attached diagrams are schematic diagrams, and the relationship between thickness and planar dimensions, as well as the ratio of thicknesses of each layer, may sometimes differ from the actual object. Also, the attached diagrams may sometimes contain parts with different dimensional relationships and ratios. Additionally, some symbols have been omitted from the attached diagrams.

[0008] (First Embodiment) The first embodiment relates to a method for manufacturing a semiconductor device. Figure 1 shows a flowchart of the method for manufacturing the semiconductor device. Figure 2 shows a partial schematic diagram of the semiconductor device 100. The semiconductor device 100 of the embodiment is a semiconductor package in which semiconductor elements are mounted, and the semiconductor elements include one or more selected from the group consisting of a computing device, a control device, and a memory device. The schematic diagrams of the embodiment are all schematic cross-sectional views.

[0009] The semiconductor device 100 has a wiring substrate 1 and a semiconductor element 2. The wiring substrate 1 has a solder pad 11. The semiconductor element 2 has an electrode 21 and a bump 22.

[0010] The preferred numerical range of the first embodiment is also applicable to other embodiments.

[0011] Wiring substrate 1 is a support substrate for semiconductor device 2. More specifically, wiring substrate 1 is a multilayer wiring substrate. Wiring substrate 1 is electrically connected to semiconductor device 2 via solder pads 11. Wiring substrate 1 is provided with hemispherical electrodes such as solder balls (not shown) for connecting to the outside of semiconductor device 100.

[0012] The pad 11 contains a conductor such as Cu, Ni / Au, or Ni / Pd / Au. The width of the pad 11 is, for example, 20 μm or more and 30 μm or less, and the height is, for example, 10 μm or more and 20 μm or less.

[0013] Semiconductor element 2 is, for example, an arithmetic element or a memory element. Semiconductor element 2 is connected via flip-chip. Bumps 22 are provided on the electrodes 21 of semiconductor element 2. Semiconductor element 2 is connected to wiring substrate 1 via bumps 22.

[0014] The bump 22 is, for example, solder, and contains one or more metals selected from the group consisting of Sn, Ag, Cu, Ni, Pb, Bi and In.

[0015] Electrode 21 is, for example, a Cu pillar of semiconductor element 2.

[0016] Semiconductor element 2 is a bare wafer or a semiconductor element sealed with a mold. The bumps 22 of semiconductor element 2, which is a bare wafer or a semiconductor element sealed with a mold, are connected to the wiring substrate 1.

[0017] Preferably, the semiconductor device 100 also includes other semiconductor elements. When the semiconductor device 100 is a memory device, the other semiconductor elements are NAND memory chips, and semiconductor element 2 is a controller chip that controls the reading, writing, and erasing of the NAND memory chips.

[0018] The height H1 of bump 22 refers to the height of bump 22 after the manufacturing method of semiconductor device 100 of the embodiments has been implemented. The crushing height H2 refers to the height of bump 22 crushed by the manufacturing method of semiconductor device 100 including the first embodiment and other embodiments. Preferably, the height H1 of bump 22 is the height of bump 22 on the center side of semiconductor element 2, and not the height of bump 22 on the outer periphery side.

[0019] The crushing height H2 is preferably 40% to 72% of H1, more preferably 48% to 64%, and even more preferably 52% to 60%.

[0020] The crushing height H2 is preferably 10 μm to 18 μm, more preferably 12 μm to 16 μm, and even more preferably 13 μm to 15 μm.

[0021] The crushing height H2 is preferably 40% to 72% of H1 and 10 μm to 18 μm, more preferably 48% to 62% of H1 and 12 μm to 16 μm, and even more preferably 52% to 60% of H1 and 13 μm to 15 μm.

[0022] The manufacturing method of the semiconductor device 100 shown in the flowchart of Figure 1 includes: a first step, which involves applying a first load P1 to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, and not applying ultrasonic vibration to the bump 22 or applying ultrasonic vibration of a first intensity US1 to the bump 22 to deform the bump 22; and a second step, which involves applying a second load P2 to the semiconductor element 2 after the first step to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, and applying ultrasonic vibration of a second intensity US2 that is stronger than the first intensity US1 to bond the bump 22 to the pad 11 of the wiring substrate 1.

[0023] Preferably, before step 1, flux or the like is applied to the bump 22 and / or the pad 11 so that flux is provided on the surface of the connection between the bump 22 and the pad 11.

[0024] In step 1, the bump 22 is crushed. In step 2, the bump 22 is joined to the pad 11.

[0025] Referring to a partial schematic diagram of the semiconductor device 100 in Figure 2, a curve showing the deformation of load, ultrasonic intensity, and bump height in the manufacturing method of the semiconductor device 100 in Figure 3, and schematic diagrams showing the manufacturing method of the semiconductor device 100 in Figures 4 to 6, the manufacturing method of the semiconductor device 100 according to the first embodiment will be described.

[0026] In the first embodiment, a method for not applying ultrasonic vibration to the protrusion 22 in the first step and a method for applying ultrasonic vibration of the first intensity US1 to the protrusion 22 will be described respectively. First, the method for not applying ultrasonic vibration to the protrusion 22 in the first step will be described, and then the method for applying ultrasonic vibration of the first intensity US1 to the protrusion 22 will be described.

[0027] The horizontal axis of the curve in Figure 3 represents the time elapsed for the step of joining the semiconductor element 2 with the wiring substrate 1. In the vertical axis of the curve, the dashed line represents the intensity of the load applied to the semiconductor element 2, the thick solid line represents the intensity (US power) of the ultrasonic vibration applied to the bump 22, and the two-dot dashed line represents the height of the deformation of the bump 22.

[0028] Figure 4 shows a schematic diagram of Figure 3 at time A (the beginning of step 1) when the elapsed time is zero. Figure 5 shows a schematic diagram of Figure 3 at time B (from the middle to the end of step 1). Figure 6 shows a schematic diagram of Figure 3 at time C (from the middle to the end of step 2). Figure 3 shows the height HA of the deformation of bump 22 in step 1. Figure 3 shows the height HB of the deformation of bump 22 in step 2. Figure 3 shows the total height HC of the deformation of bump 22 during the processing of the embodiment.

[0029] In the first embodiment, from the start of the process of deforming the bump 22 and joining the bump 22 with the solder pad 11 to the end, the total height HC of the deformation of the bump 22 is the total height of the deformation of the bump 22 in the first step and the second step (=HA+HB). However, in other embodiments, the total height HC of the deformation of the bump 22 includes the height of the deformation of the bump 22 in steps other than the first step and the second step.

[0030] The first step will be described with reference to the schematic diagrams in Figures 4 and 5. In the first step, a load is applied to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, and the bump 22 is deformed without ultrasonic vibration. Before the first step, neither a load nor ultrasonic vibration is applied. For example, the suction cup portion used to pick up the semiconductor element 2 and place it on the wiring substrate 1 is preferably a suction nozzle that vibrates ultrasonically. By using the load intensity applied by the suction nozzle and the output of the ultrasonic vibration, the load and the intensity of the ultrasonic vibration in this embodiment can be adjusted.

[0031] As shown in the schematic diagram of Figure 4, the first step begins with the bump 22 and the solder pad 11 aligned. A first load P1 is applied to the semiconductor element 2 in the direction where the wiring substrate 1 and the semiconductor element 2 are adjacent to each other, as shown in the schematic diagram of Figure 5, to deform the bump 22. In the first step of the first embodiment, ultrasonic vibration is not applied to the bump 22; instead, the bump 22 is deformed by applying a load.

[0032] The height of the bump 22 before deformation is, for example, 20 μm or more and 40 μm or less. The diameter of the bump 22 before deformation is, for example, 30 μm or more and 50 μm or less. The height of the bump 22, etc., can be determined by observing the distance between the semiconductor element 2 and the wiring substrate 1 during manufacturing.

[0033] The first load P1 varies with time, increasing continuously or intermittently from the start of the first step. When the set load intensity is reached, the load intensity is either reduced after maintaining a fixed load intensity, or maintained at a fixed load intensity, or reduced. In the curve of Figure 3, when the first load P1 reaches the set load intensity, the load intensity is reduced to the second load P2 of the second step after maintaining a fixed load intensity.

[0034] In step 1, the bump 22 is deformed by applying the first load P1, so the distance H3 between the semiconductor element 2 and the wiring substrate 1 in Figure 4 (the distance between the planar portion of the semiconductor element 2 and the planar portion of the wiring substrate 1) is reduced to the distance H4 between the semiconductor element 2 and the wiring substrate 1 in Figure 5. The height HA of the bump 22 in step 1 is [distance H3 at the beginning of step 1] - [distance H4 at the end of step 1].

[0035] The second step will be described with reference to the schematic diagram in FIG6. In the second step, a second load P2 is applied to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, and an ultrasonic vibration of a second intensity US2 is applied to the bump 22 to bond the bump 22 to the pad 11 of the wiring substrate 1. In the second step, both the load and the ultrasonic vibration are applied to bond the bump 22 of the semiconductor element 2 to the pad 11 of the wiring substrate 1.

[0036] The second load P2 presses the bump 22 of the semiconductor element 2 against the wiring substrate 1 at, for example, a fixed load, starting from the second step. The second load P2 can be a fixed load or the load can be varied. The maximum value of the second load P2 is set to be a load weaker than the maximum value of the first load P1.

[0037] Since the bump 22 has been deformed in the first step, even if the same load is applied in the second step, the height of the bump 22 in the second step will be less than the height of the bump 22 in the first step.

[0038] In step 2, ultrasonic vibration of intensity US2 is applied to bump 22 to heat bump 22 and increase the temperature of the processing point between bump 22 and pad 11 to bond bump 22 and pad 11.

[0039] The ultrasonic vibration applied to the bump 22 is preferably applied to the bump 22 from the semiconductor element 2 side.

[0040] The second intensity US2 is preferably a linear increase in intensity over time starting from the beginning of the second step. When the second intensity US2 reaches the set intensity, the intensity of the ultrasonic vibration is kept constant, or the intensity of the ultrasonic vibration is reduced after keeping the intensity of the ultrasonic vibration constant. In the second step, the ultrasonic vibration can also be applied at the maximum intensity of the second intensity US2 starting from the beginning of the second step.

[0041] In step 2, bump 22 is sometimes deformed by applying ultrasonic vibration of a second intensity US2 and a second load P2. The distance H4 between semiconductor element 2 and wiring substrate 1 in Figure 5 is reduced to the distance H5 between semiconductor element 2 and wiring substrate 1 in Figure 6. The height HB of bump 22 changing in step 2 is [distance H4 at the end of step 1] - [distance H5 at the end of step 2]. The height HB of bump 22 changing in step 2 is sometimes zero.

[0042] Referring to the curves of load, ultrasonic intensity and bump height deformation in the manufacturing method of semiconductor device 100 in Figures 7, 8 and 9, and the schematic diagram of the manufacturing method of semiconductor device 100 in Figure 10, the method of applying ultrasonic vibration of first intensity US1 to bump 22 will be explained.

[0043] The curve in Figure 7 differs from that in Figure 3 in that an ultrasonic vibration of intensity US1 is applied to the protrusion 22 in step 1. Apart from the ultrasonic vibration in step 1, the curve in Figure 3 is identical to the curve in Figure 7.

[0044] The curve in Figure 8 is a variation of the curve in Figure 7. Except for the ultrasonic vibration in step 1, the curves in Figure 7 and Figure 8 are the same.

[0045] The curve in Figure 9 is a variation of the curve in Figure 7. Except for the ultrasonic vibration in step 1, the curve in Figure 7 is the same as the curve in Figure 9.

[0046] In the first step, as shown in the schematic diagram of Figure 10, an ultrasonic vibration of the first intensity US1 is applied to the bump 22, and a first load P1 is applied to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, thereby deforming the bump 22.

[0047] In step 1, bump 22 is deformed by applying ultrasonic vibration of intensity US1 to bump 22 and applying load of load P1. As a result, the distance H3 between semiconductor element 2 and wiring substrate 1 in FIG4 is reduced to the distance H4 between semiconductor element 2 and wiring substrate 1 in FIG10. The height HA of bump 22 in step 1 is [distance H3 at the beginning of step 1] - [distance H4 at the end of step 1 (FIG10)].

[0048] The first intensity US1 varies with time, either continuously or intermittently, starting from the first step. When the set ultrasonic vibration intensity is reached, the first step ends, or the ultrasonic vibration intensity is reduced after maintaining a fixed intensity, or the ultrasonic vibration intensity remains fixed, or the ultrasonic vibration intensity is reduced. The first intensity US1 can also be a fixed intensity that does not change with time or remains substantially unchanged. In the curves of Figure 7, the ultrasonic vibration of the first intensity US1 shows a linear increase.

[0049] As a variation of the curve in Figure 7, as shown by the curve in Figure 8, an ultrasonic vibration of a first intensity US1, which is weaker than the second intensity US2 in the second step, can be applied to the protrusion 22. By applying a fixed and weaker first intensity US1 in the first step, the joint can be made more secure.

[0050] Alternatively, as shown by the curve in Figure 9, ultrasonic vibration of intensity US1 can be applied before the first load P1, without applying any load before the first step. The time for applying ultrasonic vibration of intensity US1 to the protrusion 22 before applying the first load P1 in the first step is set to 0.1 s to 1.0 s. By applying ultrasonic vibration of intensity US1 before applying the first load P1 in the first step, the joint can be made more secure. In the curve in Figure 9, when ultrasonic vibration is applied to the protrusion 22 in the first step, it is preferable to apply ultrasonic vibration of intensity US1 to the protrusion without applying the first load P1 before applying the first load P1.

[0051] The first load P1 is better than the second load P2 (the load integral value of the first load P1 is greater than the load integral value of the second load P2).

[0052] The maximum value of the first load P1 is preferably 100% to 250% of the maximum value of the second load P2, more preferably 110% to 200%, and even more preferably 120% to 140%.

[0053] The second intensity US2 of the ultrasonic vibration in step 2 is preferably stronger than the first intensity US1 of the ultrasonic vibration in step 1 (the integral value of the ultrasonic vibration intensity of the second intensity US2 is greater than the integral value of the ultrasonic vibration intensity of the first intensity US1). The integral value of the ultrasonic vibration intensity of the second intensity US2 is preferably more than 1500% and less than 2000% of the integral value of the ultrasonic vibration intensity of the first intensity US1.

[0054] The maximum value of the first intensity US1 is preferably greater than 0% of the maximum value of the second intensity US2 and less than 70%, more preferably more than 0% and less than 50%, and even more preferably more than 0% and less than 30%.

[0055] The average value of the first strength US1 is preferably greater than 0% and less than 70% of the average value of the second strength US2, more preferably more than 0% and less than 50%, and even more preferably more than 0% and less than 30%.

[0056] Preferably, the first load P1 is a strong load, and the bump 22 is subjected to greater deformation in the first step where no ultrasonic vibration is applied or a weaker first intensity US1 ultrasonic vibration is applied. If the bump 22 is subjected to greater deformation in the first step, since no ultrasonic vibration is applied or a weaker ultrasonic vibration is applied, the formation of protrusions that are easily formed on the surface due to ultrasonic vibration in the first step can be suppressed.

[0057] For example, when a load that deforms the bump 22 and a strong ultrasonic vibration for bonding are applied to the bump 22 at the same time, the shape of the bump 22 changes significantly. The bump 22 is more likely to come into contact with the prepreg on the surface of the wiring board 1, or a larger protrusion is more likely to form on the surface of the bump 22.

[0058] If the bump 22 is in contact with the prepreg on the surface of the wiring board 1, a short circuit will not occur because the prepreg is an insulator. However, the ultrasonic vibration can easily propagate to the wiring board 1 side, making it difficult for the hypothetical ultrasonic vibration to be fully transmitted to the bump 22, resulting in insufficient bonding between the bump 22 and the solder pad 11. Insufficient bonding can lead to decreased yield and reliability.

[0059] Furthermore, if strong ultrasonic vibration is applied while applying a heavy load, such as one that crushes the bump 22, large protrusions may easily form on the surface of the bump 22 containing solder. If large protrusions form on the bump 22, the bumps 22 may come into contact with each other, leading to a short circuit. If the bump 22 is in a short-circuited or easily short-circuited state, it will result in a decrease in yield and reliability.

[0060] The height HA of the bump 22 that changes in the first step is preferably more than 30% of the total height (HA+HB) of the bump 22 that deforms in the first and second steps, more preferably more than 50%, and even more preferably more than 60%.

[0061] The height HA of the bump 22 that changes in the first step is preferably more than 30% and less than 100% of the total height (HA+HB) of the bump 22 that deforms in the first and second steps, more preferably more than 50% and less than 100%, and even more preferably more than 60% and less than 100%.

[0062] The height HA of the bump 22 that changes in the first step is preferably more than 30% and less than 95% of the total height (HA+HB) of the bump 22 that deforms in the first and second steps, more preferably more than 50% and less than 95%, and even more preferably more than 60% and less than 95%.

[0063] The height HB of the protrusion 22 deformed in step 2 is preferably more than 0% and less than 200% of the height HA of the protrusion 22 deformed in step 1, more preferably more than 0% and less than 100%, and even more preferably more than 0% and less than 75%.

[0064] The height HB of the protrusion 22 deformed in step 2 is preferably greater than 0% and less than 200% of the height HA of the protrusion 22 deformed in step 1, more preferably greater than 0% and less than 100%, and even more preferably greater than 0% and less than 75%.

[0065] In steps 1 and 2, the temperature of bump 22 is preferably below the melting point of bump 22. In step 2, the temperature of bump 22 is preferably higher than the temperature of bump 22 in step 1.

[0066] By causing the protrusion 22 to deform more significantly in the first step, where no ultrasonic vibration is applied to the protrusion 22 or a weaker ultrasonic vibration of the first intensity US1 is applied to the protrusion 22, the deformation height of the protrusion 22 becomes smaller in the second step. Even if a stronger ultrasonic vibration of the second intensity US2 is applied to the protrusion 22, the accidental deformation of the protrusion 22 can be suppressed.

[0067] In the implementation, by dividing the first step into a main crushing step of the bump 22 and the second step into a main bonding step of the bump 22 to the pad 11, it is possible to suppress the bump 22 from undergoing large deformation unexpectedly in both the first and second steps, which helps to improve yield and reliability.

[0068] (Second Implementation) The second embodiment relates to a method for manufacturing a semiconductor device 100. The second embodiment adds a third step to the method for manufacturing the semiconductor device 100 of the first embodiment. Descriptions of aspects common to both the second and first embodiments are omitted.

[0069] Figure 11 shows a flowchart of the manufacturing method of the semiconductor device 100. The manufacturing method of the semiconductor device 100 in the second embodiment also includes a third step, which is to apply a third load P3 to the semiconductor element 2 before the first step to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, and to apply ultrasonic vibration of a third intensity US3, which is weaker than the second intensity US2, to the bump 22 to deform the bump 22.

[0070] Preferably, before step 3, flux or the like is applied to the bump 22 and / or the pad 11 so that flux is provided on the surface of the connection between the bump 22 and the pad 11.

[0071] Referring to the curves of load, ultrasonic intensity, and bump height deformation in the manufacturing method of semiconductor device 100 in FIG12 and the schematic diagram of the manufacturing method of semiconductor device 100 in FIG13, the manufacturing method of semiconductor device 100 according to the second embodiment will be described. The curves of load, ultrasonic intensity, and bump height deformation in the manufacturing method of semiconductor device 100 in FIG12 also show the curves of load, ultrasonic intensity, and bump height deformation in the third step.

[0072] Figure 13 shows a schematic diagram of Figure 12 when the elapsed time is E (from the middle to the end of step 3). Figure 12 shows the height HA of the protrusion 22 deformed in step 1, the height HB of the protrusion 22 deformed in step 2, the height HD of the protrusion 22 deformed in step 3, and the total height HC (=HA+HB+HD) of the protrusion 22 deformed in the processing of the second embodiment.

[0073] The third step begins with the alignment of the bump 22 and the solder pad 11 as shown in the schematic diagram of Figure 4. Furthermore, a third load P3 is applied to the semiconductor element 2 in the direction where the wiring substrate 1 and the semiconductor element 2 are adjacent to each other, and an ultrasonic vibration of a third intensity US3 is applied to the bump 22 to deform the bump 22.

[0074] The third load P3 increases continuously or intermittently over time starting from the third step. When the set load strength is reached, the third step ends, or the load strength is reduced while maintaining a fixed load strength, or the load strength is maintained at a fixed load strength, or the load strength is reduced. In the curve of Figure 12, the load of the third load P3 increases linearly until it reaches the strength of the first load P1.

[0075] The third intensity, US3, varies with time, either continuously or intermittently, starting from the beginning of step 3. When the set ultrasonic vibration intensity is reached, step 3 ends; or the ultrasonic vibration intensity is reduced while maintaining a fixed intensity; or the ultrasonic vibration intensity remains fixed; or the ultrasonic vibration intensity is reduced. In the curves of Figure 12, the ultrasonic vibration of the third intensity, US3, shows a linear increase.

[0076] In step 3, as shown by the curve in Figure 12, a fixed intensity of ultrasonic vibration can also be applied as in step 1, as shown by the curve in Figure 8. Specifically, in step 3, a fixed intensity of ultrasonic vibration of a third strength US3 can also be applied to the protrusion 22.

[0077] In step 3, as shown by the curve in Figure 12, a fixed intensity of ultrasonic vibration can also be applied as in step 1, as shown by the curve in Figure 9. Specifically, in step 3, a fixed intensity of ultrasonic vibration of a third strength US3 can also be applied to the protrusion 22 before applying the third load P3.

[0078] In step 3, the bump 22 is deformed by applying the third load P3, so the distance H3 between the semiconductor element 2 and the wiring substrate 1 in Figure 4 is reduced to the distance H6 between the semiconductor element 2 and the wiring substrate 1 in Figure 13. The height HD of the bump 22 in step 3 is [distance H3 at the beginning of step 3] - [distance H6 at the end of step 3].

[0079] The height HD of bump 22 that changes in step 1 after step 3 is [distance H6 at the beginning of step 1] - [distance H4 at the end of step 1].

[0080] The maximum value of the third load P3 is preferably less than the maximum value of the first load P1. The maximum value of the third load P3 is preferably more than 10% and less than 60% of the maximum value of the first load P1, more preferably more than 20% and less than 50%, and even more preferably more than 25% and less than 45%.

[0081] The maximum value of the third load P3 is preferably less than the maximum value of the second load P2. The maximum value of the third load P3 is preferably more than 20% and less than 80% of the maximum value of the second load P2, more preferably more than 30% and less than 70%, and even more preferably more than 40% and less than 60%.

[0082] The maximum value of the third strength US3 is preferably 400% to 900% of the maximum value of the first strength US1, more preferably 500% to 800%, and even more preferably 600% to 700%.

[0083] The maximum value of the third strength US3 is preferably greater than 0% of the maximum value of the second strength US2 and less than 100%, more preferably greater than 0% and less than 75%, and even more preferably greater than 0% and less than 50%.

[0084] The average value of the third strength US3 is preferably 400% to 900% of the first strength US1, more preferably 500% to 800%, and even more preferably 600% to 700%.

[0085] The average value of the third strength US3 is preferably greater than 0% and less than 70% of the average value of the second strength US2, more preferably greater than 0% and less than 75%, and even more preferably greater than 0% and less than 50%.

[0086] The height HD of the bump 22 that changes in the third step is preferably less than 50% of the total height (HA+HB+HD) of the bump 22 that is deformed in the first, second and third steps, more preferably less than 30%, and even more preferably less than 20%.

[0087] The height HD of the bump 22 changing in step 3 is preferably more than 5% and less than 50% of the total height (HA+HB+HD) of the bump 22 deformed in steps 1, 2 and 3, more preferably more than 5% and less than 30%, and even more preferably more than 5% and less than 20%.

[0088] The height HD of the bump 22 changing in step 3 is preferably more than 5% and less than 50% of the height (HA) of the bump 22 deformed in step 1, more preferably more than 5% and less than 30%, and even more preferably more than 5% and less than 20%.

[0089] In steps 1, 2, and 3, the temperature of bump 22 is preferably below its melting point. The temperature of bump 22 in step 2 is preferably higher than the temperature of bump 22 in step 1.

[0090] Preferably, the third load P3 is a weak load, and the bump 22 is slightly deformed in the third step of applying ultrasonic vibration with a weaker third intensity US3. By weakly bonding the bump 22 to the pad 11 before the first step of causing a larger deformation of the bump 22, the bump 22 and the pad 11 can be bonded to each other with higher reliability after the first step.

[0091] (Third Implementation) The third embodiment relates to a method for manufacturing a semiconductor device 100. The third embodiment adds a fourth step to the method for manufacturing the semiconductor device 100 of the first embodiment. The fourth step can also be performed after the second step of the second embodiment. Descriptions of aspects common to the third embodiment, the first embodiment, and the second embodiment are omitted.

[0092] Figure 14 shows a flowchart of the manufacturing method of the semiconductor device 100. The manufacturing method of the semiconductor device 100 in the third embodiment also includes a fourth step, which is after the second step, applying a fourth load P4 to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, and not applying ultrasonic vibration to the bump 22 to deform the bump 22.

[0093] Referring to the curves of load, ultrasonic intensity, and bump height deformation in the manufacturing method of semiconductor device 100 in FIG15 and the schematic diagram of the manufacturing method of semiconductor device 100 in FIG16, the manufacturing method of semiconductor device 100 according to the third embodiment will be described. In the curves of load, ultrasonic intensity, and bump height deformation in the manufacturing method of semiconductor device 100 in FIG15, the curves of load, ultrasonic intensity, and bump height deformation in the fourth step are also shown.

[0094] Figure 16 shows a schematic diagram of Figure 15 when the elapsed time is F (from the beginning to the end of step 4). Figure 15 shows the height HA of the protrusion 22 deformed in step 1, the height HB of the protrusion 22 deformed in step 2, the height HE of the protrusion 22 deformed in step 4, and the total height HC (=HA+HB+HE) of the protrusion 22 deformed in the processing of the third embodiment.

[0095] Step 4 begins at the end of step 2. In step 4, a fourth load P4 is applied to semiconductor element 2 to press the bump 22 of semiconductor element 2 against wiring substrate 1, and no ultrasonic vibration is applied to the bump 22 to deform it.

[0096] The fourth load P4 increases continuously or intermittently over time starting from the fourth step. When the set load strength is reached, the fourth step ends, or the load strength is reduced while maintaining a fixed load strength, or the load strength is maintained at a fixed load strength, or the load strength is reduced. In the curve of Figure 15, the load of the fourth load P4 increases linearly from the strength of the second load P2.

[0097] In step 4, the bump 22 is deformed by applying the fourth load P4, and thus deformed by further crushing the height of the bump 22 after it is joined with the solder pad 11 in step 2. The height HE of the bump 22 in step 4 is [distance H5 at the end of step 2] - [distance H7 at the end of step 4].

[0098] The maximum value of the fourth load P4 is preferably greater than the maximum value of the first load P1. The maximum value of the fourth load P4 is preferably more than 80% and less than 250% of the maximum value of the first load P1, more preferably more than 90% and less than 200%, and even more preferably more than 100% and less than 150%.

[0099] The average value of the fourth load P4 is preferably less than the average value of the first load P1. The average value of the fourth load P4 is preferably more than 80% and less than 250% of the average value of the first load P1, more preferably more than 90% and less than 200%, and even more preferably more than 100% and less than 150% of the average value of the first load P1.

[0100] The maximum value of the fourth load P4 is preferably greater than the maximum value of the second load P2. The maximum value of the fourth load P4 is preferably 300% to 1200% of the maximum value of the second load P2, more preferably 500% to 1000%, and even more preferably 600% to 900%.

[0101] The average value of the fourth load P4 is preferably greater than the average value of the second load P2. The average value of the fourth load P4 is preferably 300% to 1200% of the average value of the second load P2, more preferably 500% to 1000%, and even more preferably 600% to 900%.

[0102] In step 4, it is preferable not to apply ultrasonic vibration to the protrusion 22.

[0103] In the third embodiment, the height HB of the protrusion 22 deformed in the second step is preferably 0 μm or more and 7 μm or less, more preferably 0 μm or more and 5 μm or less, and even more preferably 0 μm or more and 3 μm or less.

[0104] The height HE of the bump 22 in step 4 is preferably less than 50% of the total height (HA+HB+HE) of the bump 22 in steps 1, 2 and 4, more preferably less than 30%, and even more preferably less than 20%.

[0105] The height HE of the bump 22 in step 4 is preferably more than 5% and less than 50% of the total height (HA+HB+HE) of the bump 22 deformed in steps 1, 2 and 4, more preferably more than 5% and less than 30%, and even more preferably more than 5% and less than 20%.

[0106] The height HE of the bump 22 in step 4 is preferably more than 5% and less than 50% of the height (HA) of the bump 22 in step 1, more preferably more than 5% and less than 30%, and even more preferably more than 5% and less than 20%.

[0107] In steps 1, 2, and 4, the temperature of bump 22 is preferably below its melting point. The temperature of bump 22 in step 2 is preferably higher than the temperature of bump 22 in step 1 and higher than the temperature of bump 22 in step 4.

[0108] The fourth load P4 is preferably a strong load that slightly deforms the bump 22. By further crushing the bump 22 without applying ultrasonic vibration after engagement, the bump 22 can be reliably engaged with the pad 11 and deformed.

[0109] (Fourth implementation) The fourth embodiment relates to a method for manufacturing a semiconductor device 100. The fourth embodiment adds a fifth step to the method for manufacturing the semiconductor device 100 of the first embodiment. The fifth step may also be performed after the second step of the second embodiment. The fifth step may also be performed before or / and after the fourth step of the third embodiment. Descriptions of aspects common to the fourth embodiment and the first through third embodiments are omitted.

[0110] Figure 17 shows a flowchart of the manufacturing method of the semiconductor device 100. The manufacturing method of the semiconductor device 100 in the fourth embodiment also includes a fifth step, which is after the second step, applying a fifth load P5 to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, and applying an ultrasonic vibration of a fourth intensity US4 to the bump 22 to deform the bump 22.

[0111] Referring to the curves of load, ultrasonic intensity, and bump height deformation in the manufacturing method of semiconductor device 100 in FIG18 and the schematic diagram of the manufacturing method of semiconductor device 100 in FIG19, the manufacturing method of semiconductor device 100 according to the fourth embodiment will be described. In the curves of load, ultrasonic intensity, and bump height deformation in the manufacturing method of semiconductor device 100 in FIG18, the curves of load, ultrasonic intensity, and bump height deformation in the fifth step are also shown.

[0112] Figure 19 shows a schematic diagram of Figure 18 when the elapsed time is G (from the beginning to the end of step 5). Figure 18 shows the height HA of the protrusion 22 deformed in step 1, the height HB of the protrusion 22 deformed in step 2, the height HF of the protrusion 22 deformed in step 5, and the total height HC (=HA+HB+HF) of the protrusion 22 deformed during the processing of the fourth embodiment.

[0113] Step 5 begins at the end of step 2. In step 5, a fifth load P5 is applied to semiconductor element 2 to press the bump 22 of semiconductor element 2 against wiring substrate 1, and an ultrasonic vibration of a fourth intensity US4 is applied to bump 22 to deform bump 22.

[0114] The fifth load P5 increases continuously or intermittently over time starting from the fifth step. When the set load strength is reached, the fifth step ends, or the load strength is reduced while maintaining a fixed load strength, or the load strength is maintained at a fixed load strength, or the load strength is reduced. In the curve of Figure 18, the load of the fifth load P5 increases linearly from the strength of the second load P2.

[0115] The fourth intensity, US4, varies with time, either continuously or intermittently, starting from the fifth step. When the set ultrasonic vibration intensity is reached, the fifth step ends, or the ultrasonic vibration intensity is reduced after maintaining a fixed intensity, or the ultrasonic vibration intensity remains fixed, or the ultrasonic vibration intensity is reduced. In the curves of Figure 18, the ultrasonic vibration of the fourth intensity, US4, increases linearly from the intensity of the second intensity, US2.

[0116] In step 5, the bump 22 is deformed by applying the fifth load P5, and thus deformed by further crushing the height of the bump 22 after it is joined with the solder pad 11 in step 2. The height HF of the bump 22 in step 5 is [distance H5 at the end of step 2] - [distance H8 at the end of step 5].

[0117] The maximum value of the fifth load P5 is preferably greater than the maximum value of the first load P1. The maximum value of the fifth load P5 is preferably 40% to 120% of the maximum value of the first load P1, more preferably 60% to 100%, and even more preferably 70% to 90%.

[0118] The average value of the fifth load P5 is preferably less than the average value of the first load P1. The average value of the fifth load P5 is preferably 40% to 120% of the average value of the first load P1, more preferably 60% to 100%, and even more preferably 70% to 90%.

[0119] The maximum value of the fifth load P5 is preferably greater than the maximum value of the second load P2. The maximum value of the fifth load P5 is preferably 100% to 600% of the maximum value of the second load P2, more preferably 200% to 500%, and even more preferably 250% to 450%.

[0120] The average value of the fifth load P5 is preferably greater than the average value of the second load P2. The average value of the fifth load P5 is preferably 100% to 600% of the average value of the second load P2, more preferably 200% to 500%, and even more preferably 250% to 450%.

[0121] The maximum value of the fourth strength US4 is preferably 800% to 1700% of the maximum value of the first strength US1, more preferably 1000% to 1500%, and even more preferably 1100% to 1400%.

[0122] The maximum value of the fourth strength US4 is preferably 70% to 130% of the maximum value of the second strength US2, more preferably 80% to 120%, and even more preferably 90% to 110%.

[0123] The average value of the fourth strength US4 is preferably 800% to 1700% of the average value of the first strength US1, more preferably 1000% to 1500%, and even more preferably 1100% to 1400%.

[0124] The average value of the fourth strength US4 is preferably 70% to 130% of the average value of the second strength US2, more preferably 80% to 120%, and even more preferably 90% to 110%.

[0125] In the fourth embodiment, the height HB of the protrusion 22 deformed in the second step is preferably 0 [μm] to 7 [μm], more preferably 0 [μm] to 5 [μm], and even more preferably 0 [μm] to 3 [μm].

[0126] The height HF of the bump 22 that changes in step 5 is preferably less than 50% of the total height (HA+HB+HF) of the bump 22 that changes in steps 1, 2 and 5, more preferably less than 30%, and even more preferably less than 20%.

[0127] The height HF of the bump 22 changing in step 5 is preferably more than 5% and less than 50% of the total height (HA+HB+HF) of the bump 22 deformed in steps 1, 2 and 5, more preferably more than 5% and less than 30%, and even more preferably more than 5% and less than 20%.

[0128] The height HF of the bump 22 in step 5 is preferably more than 5% and less than 50% of the height (HA) of the bump 22 in step 1, more preferably more than 5% and less than 30%, and even more preferably more than 5% and less than 20%.

[0129] In steps 1, 2, and 5, the temperature of bump 22 is preferably below its melting point. The temperature of bump 22 in step 2 and step 5 is preferably higher than the temperature of bump 22 in step 1.

[0130] The fifth load P5 is preferably a strong load that slightly deforms the bump 22. By applying ultrasonic vibration after engaging the bump 22 to further crush the bump 22, the bump 22 can be more reliably engaged with the pad 11 and deformed.

[0131] (Fifth Embodiment) The fifth embodiment relates to a method for manufacturing a semiconductor device 100. The fifth embodiment adds a sixth and a seventh step to the manufacturing methods of the semiconductor device 100 in the first to fourth embodiments. The sixth step can also be performed after the second step of the second embodiment. Descriptions of aspects common to the fifth embodiment and the first to fourth embodiments are omitted.

[0132] Figure 20 shows a flowchart of the manufacturing method of the semiconductor device 100. Referring to Figures 21 and 22, which show schematic diagrams of the manufacturing method of the semiconductor device 100, the manufacturing method of the semiconductor device 100 according to the fifth embodiment will be described. The manufacturing method of the semiconductor device 100 according to the fifth embodiment also includes a sixth step of heating the semiconductor element 2 and the wiring substrate 1 after the second step, after the fourth step, or after the fifth step, and a seventh step of cleaning and annealing the components after the sixth step.

[0133] Step 6 is performed after the processing of embodiments 1 to 4 is completed, that is, after the deformation of bump 22 and the bonding of bump 22 and pad 11 are completed.

[0134] In step 6, as shown in the schematic diagram of FIG21, heat X is applied to the semiconductor element 2 and the wiring substrate 1. Specifically, in step 6, the semiconductor element 2 and the wiring substrate 1 to be bonded are heated using an oven or the like, which promotes the growth of the alloy layer of the bonded bumps 22 and solder pads 11. By the alloy growth of the bonded bumps 22 and solder pads 11, the bonding strength is improved, thereby helping to improve the reliability of the semiconductor device 100.

[0135] The processing temperature of step 6 (the temperature of bump 22) is preferably below the melting point of bump 22. In step 6, from the viewpoint of effectively promoting alloy growth, the processing temperature of step 6 is preferably 80°C or higher. When flux is applied to bump 22 and / or solder pad 11 before step 1 or step 3, from the viewpoint of preventing flux sintering during heat treatment, the processing temperature of step 6 is preferably 150°C or lower. The processing temperature of step 6 is preferably 80°C or higher and 150°C or lower.

[0136] From the viewpoint of promoting alloy growth, the heat treatment time in step 6 is preferably 15 minutes or more. From the viewpoint of preventing flux sintering, the heat treatment time in step 6 is preferably 10 hours or less. The heat treatment time in step 6 is preferably 15 minutes or more but less than 10 hours.

[0137] When using flux, it is preferable to perform step 7. In step 7, as shown in the schematic diagram of Figure 22, a cleaning solution W is used to clean the component heated in step 6. The cleaning solution W is preferably an alkaline cleaning solution, acetone, or isopropanol. Since the bump 22 and the solder pad 11 have been firmly bonded up to step 6, the joint between the bump 22 and the solder pad 11 is not easily damaged by the cleaning pressure in step 7.

[0138] The heat treatment in step 6 improves the reliability of the joint between bump 22 and pad 11, thereby contributing to the improvement of the reliability of semiconductor device 100. Furthermore, even with the cleaning in step 7, the improved reliability of the joint between bump 22 and pad 11 makes the joint less susceptible to damage from the cleaning pressure, thus contributing to the improvement of the reliability and yield of semiconductor device 100.

[0139] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0140] 1: Wiring board 2: Semiconductor components 11: Pad 21: Electrode 22: Bump 100: Semiconductor devices H1: Height H2: Crushing height H3: Distance H4: Distance H5: Distance H6: Distance H7: Distance H8: Distance HA: Altitude HB: Height HC: Total Height HD: Height HE: Height HF: Altitude P1: First load P2: 2nd load P3: The third load P4: Fourth Load P5: The fifth load US1: Level 1 Intensity US2: Level 2 US3: Level 3 Strength US4: Level 4 Strength X: Hot

Claims

1. A method for manufacturing a semiconductor device, comprising: The first step involves applying a first load to the semiconductor element to press the bumps of the semiconductor element against the wiring substrate, without applying ultrasonic vibration to the bumps or applying ultrasonic vibration of a first intensity to the bumps to deform them; and the second step involves, after the first step, applying a second load to the semiconductor element to press the bumps of the semiconductor element against the wiring substrate, and applying ultrasonic vibration of a second intensity to the bumps to bond the bumps to the pads of the wiring substrate, wherein when the first intensity of ultrasonic vibration is applied to the bumps in the first step, the second intensity is stronger than the first intensity.

2. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the ultrasonic vibration of the first intensity is not applied in the first step described above.

3. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the maximum value of the first load is more than 100% and less than 250% of the maximum value of the second load.

4. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the maximum value of the first strength is greater than 0% of the maximum value of the second strength and is less than 70%.

5. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the bump change height in the first step is 30% or more of the total bump deformation height in the first step and the second step.

6. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the bump change height in the first step is more than 60% and less than 100% of the total bump deformation height in the first step and the second step.

7. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the bump change height in the second step is more than 0% and less than 200% of the bump change height in the first step.

8. A method for manufacturing a semiconductor device as claimed in claim 1, wherein in the first step, before applying the first load, ultrasonic vibration of the first intensity is applied to the bump to deform the bump.

9. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising a third step, which is performed before the first step, by applying a third load to the semiconductor element to press the bumps of the semiconductor element against the wiring substrate, and by applying an ultrasonic vibration of a third intensity weaker than the second intensity to the bumps to deform the bumps.

10. The method for manufacturing a semiconductor device as claimed in claim 9, wherein the bump change height in the third step is less than 50% of the total bump deformation height in the first, second and third steps, and the bump change height in the first step is more than 30% of the total bump deformation height in the first, second and third steps.

11. The method for manufacturing a semiconductor device as claimed in claim 9, wherein the maximum value of the third strength is greater than 0% of the maximum value of the second strength and is less than 100%.

12. The method for manufacturing a semiconductor device as claimed in claim 9, wherein the maximum value of the third strength is more than 400% and less than 900% of the maximum value of the first strength.

13. The method for manufacturing a semiconductor device as claimed in claim 9, wherein the maximum value of the third load is more than 10% and less than 60% of the maximum value of the first load.

14. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising a fourth step, which is performed after the second step above, wherein a fourth load is applied to the semiconductor element to press the bumps of the semiconductor element against the wiring substrate, and ultrasonic vibration is not applied to the bumps to deform them, wherein in the fourth step, the maximum value of the fourth load is more than 300% and less than 1200% of the maximum value of the first load.

15. The method for manufacturing a semiconductor device as claimed in claim 14, wherein the bump change height in step 4 is less than 50% of the total bump deformation height in steps 1, 2 and 4, and the bump change height in step 1 is 30% or more of the total bump deformation height in steps 1, 2 and 4.

16. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising a fifth step, which is performed after the second step, wherein a fifth load is applied to the semiconductor element to press the bumps of the semiconductor element against the wiring substrate, and an ultrasonic vibration of a fourth intensity is applied to the bumps to deform the bumps, wherein the maximum value of the fifth load is more than 40% and less than 120% of the maximum value of the first load.

17. The method for manufacturing a semiconductor device as claimed in claim 16, wherein the bump change height in step 5 is less than 50% of the total bump deformation height in steps 1, 2 and 5, and the bump change height in step 1 is 30% or more of the total bump deformation height in steps 1, 2 and 5.

18. A method for manufacturing a semiconductor device as claimed in claim 9 or 10, wherein in the first step, the temperature of the bump is below the melting point of the bump; in the second step, the temperature of the bump is below the melting point of the bump; and in the third step, the temperature of the bump is below the melting point of the bump.

19. The method of manufacturing a semiconductor device as claimed in claim 16, further comprising a sixth step, which is performed after the fifth step of claim 16, by heating the semiconductor element and the wiring substrate.

20. A method for manufacturing a semiconductor device as claimed in claim 19, further comprising a 7th step, which is performed after the 6th step, of cleaning the heated component, wherein the heating temperature is below the melting point of the bump.

21. A method for manufacturing a semiconductor device as claimed in claim 14 or 15, wherein in the first step, the temperature of the bump is below the melting point of the bump; in the second step, the temperature of the bump is below the melting point of the bump; and in the fourth step, the temperature of the bump is below the melting point of the bump.

22. A method for manufacturing a semiconductor device as claimed in claim 16 or 17, wherein in the first step, the temperature of the bump is below the melting point of the bump; in the second step, the temperature of the bump is below the melting point of the bump; and in the fifth step, the temperature of the bump is below the melting point of the bump.

Images