Semiconductor device

Abstract

A semiconductor device includes: a semiconductor-on-insulator (SOI) substrate; and a vertical active element disposed in a first region of the SOI substrate. The vertical active element includes: a pair of source regions disposed in the SOI substrate; a pair of gate electrodes disposed on opposite sides of the source regions; a pair of drain electrodes disposed on opposite sides of the gate electrodes; and a buried layer located below the source regions and the gate electrodes, electrically connected to the drain electrodes. The semiconductor device further includes: a horizontal active element disposed in a second region of the SOI substrate; and an isolation structure separating the vertical active element from the horizontal active element.

Claims

1. A semiconductor device, comprising: A semiconductor-on-insulator (SOI) substrate, wherein the SOI substrate has a first epitaxial layer; a vertical active element disposed in a first region of the SOI substrate, comprising: a pair of source regions disposed in the SOI substrate; a pair of gate electrodes disposed on opposite sides of the pair of source regions; a pair of drain electrodes disposed on opposite sides of the pair of gate electrodes; and a buried layer located below the pair of source regions and the pair of gate electrodes and electrically connected to the pair of drain electrodes, wherein the pair of drain electrodes extends through the first epitaxial layer; a horizontal active element disposed in a second region of the SOI substrate; and an isolation structure separating the vertical active element from the horizontal active element.

2. The semiconductor device of claim 1, wherein the vertical active element is a discrete device and the horizontal active element is a bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) transistor.

3. The semiconductor device of claim 2, wherein the discrete element includes a split-gate transistor (SGT).

4. The semiconductor device of claim 2 further includes a heavily doped region sandwiched between the pair of source regions, wherein the heavily doped region has a first conductivity type and the pair of source regions have a second conductivity type, wherein the first conductivity type is different from the second conductivity type.

5. The semiconductor device of claim 4, wherein the heavily doped region is laterally adjacent to the pair of source regions.

6. The semiconductor device of claim 4, wherein the heavily doped region and the pair of source regions are disposed in a well region, wherein the well region has the first conductivity type.

7. The semiconductor device of claim 4, wherein the semiconductor substrate on the insulating layer further comprises: A substrate having this second conductivity type; An insulating layer is disposed on the substrate, wherein the first epitaxial layer is disposed on the insulating layer and has the second conductivity type.

8. The semiconductor device of claim 7, wherein the insulating layer extends continuously across the first region and the second region.

9. The semiconductor device of claim 7, wherein the semiconductor substrate on the insulating layer further includes a second epitaxial layer disposed between the insulating layer and the first epitaxial layer, and has the second conductivity type.

10. The semiconductor device of claim 9, wherein the buried layer is disposed within the second epitaxial layer.

11. The semiconductor device of claim 10, wherein the buried layer extends upward from the interface between the second epitaxial layer and the first epitaxial layer.

12. The semiconductor device of claim 11, wherein the pair of drain electrodes are a pair of metal sinkers that extend through the first epitaxial layer and are in physical contact with the buried layer.

13. The semiconductor device of claim 9, wherein the isolation structure is a deep trench isolation (DTI) structure that extends through the first epitaxial layer and the second epitaxial layer and touches the insulating layer.

14. The semiconductor device of claim 1 further includes a pair of blocking blocks that laterally separate the pair of drain electrodes from the pair of gate electrodes.

15. The semiconductor device of claim 1, wherein the pair of gate electrodes further comprises: A first structure having a first dimension; And a second structure on top of the first structure, wherein the second structure has a second dimension that is larger than the first dimension.

16. The semiconductor device of claim 15 further includes a gate dielectric layer, comprising: A first part is disposed on opposite sides and bottom of the first structure; and a second part is disposed between the first structure and the second structure, and on opposite sides of the second structure.

17. The semiconductor device of claim 4, wherein the horizontal active element further comprises: A first transistor having the second conductivity type; a second transistor adjacent to the first transistor and having the first conductivity type; And a third transistor, separated from the second transistor by the isolation structure, and having the second conductivity type.

18. The semiconductor device of claim 17, wherein the first transistor and the second transistor are metal-oxide semiconductor (MOS) transistors, and the third transistor is a lateral-diffused metal-oxide semiconductor (LDMOS) transistor.

19. The semiconductor device of claim 18, wherein the first transistor, the second transistor, and the third transistor constitute the bicarrier-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor transistor.

20. The semiconductor device as claimed in claim 1 further includes: A pair of source contacts, configured to pass through an interlayer dielectric (ILD) layer and physically contact the pair of source regions; a pair of gate contacts, configured to pass through the interlayer dielectric layer and physically contact the pair of gate electrodes; and a pair of drain contacts, configured to pass through the interlayer dielectric layer and physically contact the pair of drain electrodes.

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