Nanosheet transistors structure and the methods of forming the same

Abstract

A method for forming a nanosheet transistor includes depositing a multilayer stack comprising alternating sacrificial layers and semiconductor layers. The sacrificial layers include a bottom sacrificial layer and an upper sacrificial layer. The bottom sacrificial layer has a first thickness, and the upper sacrificial layer is located above the bottom sacrificial layer. The upper sacrificial layer has a second thickness less than the first thickness. The method further includes patterning the multilayer stack to form protruding fins, forming dummy gate stacks on the protruding fins, forming source / drain regions adjacent to the dummy gate stacks, removing the dummy gate stacks and the sacrificial layers in the protruding fins to leave recesses, and forming alternative gate stacks in the recesses.

Description

Technical Field

[0001] none Prior Technology

[0002] Technological advancements in integrated circuit (IC) materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than its predecessor. Throughout IC development, functional density (e.g., the number of interconnects per die area) has generally increased, while geometric dimensions have decreased. This scaling-down process typically provides benefits through increased manufacturing efficiency and reduced associated costs.

[0003] This miniaturization process has also increased the complexity of processing and manufacturing ICs, and similar advancements are needed in IC processing and manufacturing to achieve these progresses. For example, gate-all-around (GAA) transistors have been introduced to replace planar transistors. The structure of GAA transistors and methods for manufacturing GAA transistors are under development. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] The following detailed description, taken in conjunction with the accompanying drawings, provides the best understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figures 1 to 4 and 5A-1, 5A-2, 5B-1, 5B-2 to 12A-1, 12A-2, 12B-1, and 12B-2 illustrate intermediate stages in the formation of a gate-all-around (GAA) transistor according to some embodiments. Figure 13 is a process flow diagram illustrating the formation of a transistor according to some embodiments. Implementation

[0006] The following disclosure provides various embodiments or examples of different features for implementing this disclosure. Specific examples of components and arrangements are described below to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or above a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or text may be repeated in various examples. This repetition is for simplicity and clarity and is not, in itself, merely a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, the spatially related terms used herein, such as "below," "under," "below," "above," and "on," are for ease of description in order to depict the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientation shown in the figure, these spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0008] Gate-all-around (GAA) transistors can be formed from nanosheet transistors and / or nanowire transistors. According to some embodiments, the bottom spacing between the bottom nanostructure and the underlying semiconductor strip (sub-channel) is greater than the top spacing between adjacent (semiconductor) nanostructures above. Therefore, it is possible to fill the bottom spacing with a first work function layer and a second work function layer above the first work function layer. The second work function layer has the function of increasing the threshold voltage of the sub-channel. The top spacing can be partially filled by the gate stack and does not include the second work function layer. When the GAA transistor is turned off, the leakage current through the sub-channel is thus reduced.

[0009] The embodiments discussed herein provide examples of how the subject matter of this application can be made or used, and modifications that will be readily understood by one of ordinary skill in the art, while remaining within the scope of consideration for different embodiments. Throughout the various figures and illustrative embodiments, the same reference numerals are used to indicate the same elements. While method embodiments may be discussed in a particular order of execution, other method embodiments may be performed in any logical order.

[0010] Figures 1 through 12A-1, 12A-2, 12B-1, and 12B-2 are cross-sectional views illustrating intermediate stages in the formation of a gate-all-around (GAA) transistor according to some embodiments of this disclosure. The corresponding process is also schematically reflected in the process flow shown in Figure 13.

[0011] Referring to Figure 1, a perspective view of wafer 10 is shown. Wafer 10 includes a multilayer structure comprising a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., while other substrates and / or structures may be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon germanium on insulator, etc. Substrate 20 may be doped to be a p-type semiconductor, but in other embodiments, substrate 20 may be doped to be an n-type semiconductor.

[0012] According to some embodiments, the multilayer stack 22 is formed through a series of deposition processes for depositing alternating materials. A particular process is shown as process 202 of process flow 200 shown in Figure 13. According to some embodiments, the multilayer stack 22 includes a first layer 22A and a second layer 22B, the first layer 22A being formed of a first semiconductor material and the second layer 22B being formed of a second semiconductor material different from the first semiconductor material.

[0013] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is achieved through epitaxial growth, and the corresponding deposition method can be vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), ultra-high vacuum chemical vapor deposition (UHVCVD), reduced-pressure chemical vapor deposition (RPCVD), or similar methods.

[0014] Once the first layer 22A has been deposited on the substrate 20, the second layer 22B is deposited on top of the first layer 22A. According to some embodiments, the second layer 22B is formed of or includes a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or combinations thereof, which differs from the first semiconductor material of the first layer 22A. For example, according to some embodiments, the first layer 22A is silicon-germanium, and the second layer 22B is formed of silicon, or vice versa. It should be understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0015] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a similar thickness to the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, the first layer 22A is formed to a first thickness, which is in the range of about 9 nm and about 10 nm. However, any suitable thickness may be used and remains within the scope of the embodiments.

[0016] Once the second layer 22B has been formed over the first layer 22A, the deposition process is repeated to form a retention layer in the multilayer stack 22 until the top layer required for the multilayer stack 22 has been formed.

[0017] According to some embodiments, the bottom semiconductor layer 22A (denoted as 22A-1) has a thickness T1, and the upper semiconductor layer 22A (denoted as 22A-2) has a thickness T2. The thickness T2 of the upper layers 22A-2 may be the same as or different from each other. Thickness T1 is greater than thickness T2. The ratio T1 / T2 may range between about 1.2 and about 2.0, and may range between about 1.5 and 1.8. According to some embodiments, thickness T1 may range between about 13.5 nm and about 15 nm, and thickness T2 may range between about 9 nm and about 10 nm. The second layer 22B may also have the same thickness as the upper layer 22A-2, or a different thickness. According to some embodiments, the first layer 22A is removed in a subsequent process and is optionally referred to throughout the description as the sacrificial layer 22A.

[0018] According to some embodiments, pad oxide layers and hard mask layers (not shown) may be formed over the multilayer stack 22. These layers are patterned, as well as subsequent patterning for the multilayer stack 22.

[0019] Referring to Figure 2, the multilayer stack 22 and a portion of the underlying substrate 20 are patterned in an etching process to form trenches 23. A specific process is shown as process 204 of process flow 200 shown in Figure 13. The trenches 23 extend into the substrate 20. The retained portion of the multilayer stack 22 is hereinafter referred to as multilayer stack 22'. A portion of the substrate 20 below multilayer stack 22' is left and is hereinafter referred to as semiconductor strip 20'. Multilayer stack 22' includes semiconductor layers 22A and 22B. Hereinafter, semiconductor layer 22A is also referred to as a sacrificial layer, and semiconductor layer 22B is also referred to as a nanostructure. A portion of multilayer stack 22' and the underlying semiconductor strip 20' are collectively referred to as semiconductor strip 24.

[0020] In the above embodiments, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes to allow the formation of patterns with, for example, a spacing smaller than that obtained by a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be subsequently used to pattern the GAA structure.

[0021] Figure 3 illustrates the formation of isolation region 26, which may also be referred to as a shallow trench isolation (STI) region throughout the description. A specific process is shown as process 206 of process flow 200 shown in Figure 13. STI region 26 may include a substrate oxide (not shown), which may be a thermal oxide formed through thermal oxidation of the surface layer of substrate 20. The substrate oxide may also be a silicon oxide layer deposited using methods such as ALD, high-density plasma chemical vapor deposition (HDPCVD), etc. STI region 26 may also include a dielectric material above the substrate oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on-glass, HDPCVD, etc. Next, a planarization process such as Chemical Mechanical Polish (CMP) or Mechanical Grinding can be performed to flatten the top surface of the dielectric material, and the remaining portion of the dielectric material is the STI region 26.

[0022] Next, the STI region 26 is recessed such that the top of the semiconductor strip 24 protrudes beyond the top surface 26T of the retained portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 comprises the top of the multilayer stack 22' and the semiconductor strip 20'. The recess of the STI region 26 can be performed via a dry etching process, wherein, for example, NF3 and NH4 are used as etching gases. During the etching process, plasma is generated. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 26 is performed via a wet etching process. For example, the etching chemicals may include HF.

[0023] Next, Figure 4 shows two device regions 100A and 100B in the same wafer 10 and the same device die, both of which are also used to form GAA transistors, which can be nanosheet transistors or nanowire transistors. The structures formed in device regions 100A and 100B can share the same formation process, including the processes shown in Figures 1 through 3. The width of the multilayer stack 22' in device region 100A can be equal to, greater than, or less than the width of the multilayer stack 22' in device region 100B.

[0024] According to some embodiments, device region 100A is an n-type device region (where an n-type transistor is formed), and device region 100B is a p-type device region (where a p-type transistor is formed). According to some alternative embodiments, device region 100A is a p-type device region, and device region 100B is an n-type device region. According to another alternative embodiment, both device regions 100A and 100B are n-type device regions, or both device regions 100A and 100B are p-type device regions. In the examples below, it can be assumed that device regions 100A and 100B are an n-type device region and a p-type device region, respectively, and each of device regions 100A and 100B can be another type of device region in any combination.

[0025] As shown in Figure 4, a dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. A specific process is shown as process 208 of process flow 200 shown in Figure 13. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, the dummy gate electrode 34 may be formed using polycrystalline silicon or amorphous silicon, and other materials such as amorphous carbon may be used.

[0026] Each of the dummy gate stacks 30 may also include one (or a plurality of) hard masking layers 36 above the dummy gate electrode 34. The hard masking layers 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The dummy gate stacks 30 may span one or a plurality of protruding fins 28 and STI regions 26 between the protruding fins 28. The dummy gate stacks 30 also have a length direction perpendicular to the length direction of the protruding fins 28. The formation of the dummy gate stacks 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer above the dummy gate dielectric layer, depositing one or more hard masking layers, and patterning the formed layers via a patterning process.

[0027] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacers 38 are formed of dielectric materials such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon carbonitride oxynitride (SiOCN), and may have a single-layer structure or a multilayer structure including a plurality of dielectric layers. The formation process of the gate spacers 38 may include depositing one or more dielectric layers, followed by performing anisotropic etching on the dielectric layers. The retained portion of the dielectric layers is the gate spacers 38.

[0028] Figures 5A-1 and 5A-2 show cross-sectional views of the structure subsequently formed after the source / drain region 48A and the overlying dielectric layer in device region 100A of Figure 4. Figures 5B-1 and 5B-2 show cross-sectional views of the structure subsequently formed after the source / drain region 48B and the overlying dielectric layer in device region 100B of Figure 4. Throughout the description, figures with reference numbers "A-1" or "A-2" are obtained for device region 100A, and respectively by cross-sections GL-GL and CL-CL. Figures with reference numbers "B-1" or "B-2" are obtained for device region 100B of Figure 4, and respectively by cross-sections GL-GL and CL-CL. For example, Figure 5A-1 shows a reference cross-section GL-GL ("GL" represents gate length) in Figure 4, wherein the reference cross-section GL-GL is parallel to the gate length direction. Figure 5A-2 shows the reference cross section CL-CL ("CL" represents the channel length) in Figure 4, where the cross section CL-CL cuts through the protruding fin 28.

[0029] Referring to Figures 5A-2 and 5B-2, the portion of the protruding fin 28 (Figure 4) not directly located below the dummy gate stack 30 and gate spacer 38 is recessed via an etching process to form a recess (occupied by regions 48A and 48B). A separate process is shown as process 210 of process flow 200 shown in Figure 13. For example, a dry etching process can be performed using mixtures of C2F6, CF4, SO2 and HBr, Cl2 and O2, and mixtures of HBr, Cl2, O2 and CH2F2 to etch the multilayer stack 22' and the underlying semiconductor strip 20'. The bottom of the recess is at least flush with the bottom of the multilayer stack 22', or at least lower than the bottom of the multilayer stack 22'. The etching can be anisotropic, such that the sidewalls of the multilayer stack 22' facing the recess 42 are vertical and straight.

[0030] Next, internal spacers 46 are formed. Individual process shown is process 212 of process flow 200 shown in Figure 13. The formation process may include a sacrificial layer 22A formed by etching horizontal recesses, and horizontal recesses formed by filling with dielectric materials such as SiO2, SiOC, SiON, SiOCN, etc.

[0031] Figure 5A-2 further illustrates the formation of the source / drain region 48A in device region 100A, and Figure 5B-2 further illustrates the formation of the source / drain region 48B in device region 100B. Source / drain regions 48A and 48B may be referred to individually or collectively as sources or drains, depending on the context. The individual process is shown as process 214 of process flow 200 shown in Figure 13. Source / drain regions 48A and 48B may extend to a distance between approximately 50 nm and approximately 55 nm below the bottom nanostructure 22B.

[0032] When the region is n-type, source / drain regions 48A and 48B may include silicon or silicon carbide, and may be doped with n-type elements such as As, P, Sb, or combinations thereof. For example, when the region is n-type, source / drain regions 48A and 48B may include SiAs, SiP, SiCP, SiAsP, SiSb, etc. When the region is p-type, source / drain regions 48A and 48B may include silicon, SiGe, or Ge, and may further include p-type doped elements such as boron, indium, or combinations thereof. For example, when the region is p-type, source / drain regions 48A and 48B may include SiGeB, GeB, etc.

[0033] The formation of source / drain regions 48A and 48B can be performed via an epitaxial process. Furthermore, when source / drain regions 48A and 48B have the same conductivity type, they can be epitaxially grown via the same epitaxial process. In the example embodiment where device regions 100A and 100B are respectively an n-type device region and a p-type device region, source / drain region 48A is an n-type region, and source / drain region 48B is a p-type region.

[0034] Figures 5A-1, 5A-2, 5B-1, and 5B-2 further illustrate the formation of the contact etch stop layer (CESL) 50 and the inter-layer dielectric (ILD) 52. A specific process is shown as process 216 of process flow 200 shown in Figure 13. The CESL 50 may be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. The ILD 52 may comprise a dielectric material formed, for example, using FCVD, spin-coated glass, CVD, or any other suitable deposition method. ILD 52 can be formed from oxygen-containing dielectric materials, such as silica, phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), and undoped silicate glass (USG).

[0035] A planarization process, such as CMP or mechanical polishing, is performed to flatten the top surface of the ILD 52. According to some embodiments, the planarization process may remove the hard mask layer 36 to expose the dummy gate electrode 34, or may stop on the hard mask layer 36. According to some embodiments, after the planarization process, the dummy gate electrode 34 (or hard mask layer 36), the gate spacer 38, and the top surface of the ILD 52 are flush within process variations.

[0036] Referring to Figures 6A-1, 6A-2, 6B-1, and 6B-2, the dummy gate electrode 34 (and hard mask layer 36, if retained) and dummy gate dielectric 32 in device regions 100A and 100B are removed in one or more etching processes, such that recesses 58A and 58B (collectively referred to as recesses 58) are formed in device regions 100A and 100B, respectively. A specific process is shown as process 218 of process flow 200 shown in Figure 13. A multilayer stack 22' is exposed to recesses 58A and 58B.

[0037] Referring to Figures 7A-1, 7A-2, 7B-1, and 7B-2, recesses 58A and 58B extend downwards between nanostructures 22B by etching away the sacrificial layer 22A. As can be understood from Figures 6A-1 and 6B-1, after removing the dummy gate dielectric 32 and the dummy gate electrode 34, the sidewalls of the sacrificial layer 22A are exposed, thus enabling the removal of the sacrificial layer 22A. A specific process is shown as process 220 of process flow 200 shown in Figure 13.

[0038] Due to the difference in thicknesses T1 and T2 (Figure 1) between the bottom sacrificial layer 22A-1 and the upper sacrificial layer 22A-2, the spacing S1 between the semiconductor strip 20' and the bottommost nanostructure 22B above it is equal to or slightly different from (due to the etching process) the thickness T1. The spacing S2 between adjacent nanostructures 22B is equal to or slightly different from (due to the etching process) the thickness T2, where the thickness T2 is less than the thickness T1. According to some embodiments, the ratio S1 / S2 can be in the range of approximately 1.2 and 2.0.

[0039] Referring to Figures 8A-1, 8A-2, 8B-1, and 8B-2, gate dielectric 62 is formed. A specific process is shown as process 222 of process flow 200 shown in Figure 13. According to some embodiments, each of the gate dielectrics 62 includes an interface layer 64 and a high-dielectric-constant dielectric layer 66 on the interface layer 64. The interface layer 64 may have a thickness ranging from about 1 nm to about 1.5 nm. The thickness of the interface layer 64 may also be less than 1 / 3 of the pitch S2 (Figures 7A-1 and 7B-1). According to some embodiments, the gate dielectrics 62 in device regions 100A and 100B share a common formation process. The interface layer 64 may be formed of or comprise silicon oxide, which may be deposited via a conformal deposition process such as ALD or CVD. The interface layer 64 may also be formed via an oxidation process.

[0040] According to some embodiments, the high-dielectric-constant dielectric layer 66 includes one or more dielectric layers. For example, the high-dielectric-constant dielectric layer 66 may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The high-dielectric-constant dielectric layer 66 may also be deposited via conformal deposition processes such as ALD or CVD. The high-dielectric-constant dielectric layer 66 may have a thickness ranging from about 1 nm to about 1.5 nm, which may be substantially the same as the thickness of the interface layer 64.

[0041] Referring to Figures 9B-1 and 9B-2, a view is shown in device region 100B, forming a first work function layer 68B. A specific process is shown as process 224 of process flow 200 shown in Figure 13. According to some embodiments of forming p-type transistors in device region 100B, the work function layer 68B can be a p-type work function layer having a work function higher than the mid-gap work function (approximately 4.5 eV to approximately 4.6 eV). For example, the work function of the work function layer 68B can be in the range between approximately 4.6 eV and approximately 5.2 eV. According to some embodiments, the work function layer 68B can be formed of or include TiN, TiC, TiCN, etc.

[0042] According to an alternative embodiment, for example, the work function layer 68B may have an intermediate gap work function in the range of about 4.5 eV and about 4.6 eV. The corresponding work function layer 68B may include tungsten. The forming process may include ALD, CVD, etc.

[0043] According to some embodiments, a work function layer 68B is conformally deposited on a high-dielectric-constant dielectric layer 66. The thickness of the work function layer 68B can be greater than T2 / 2 and less than T1 / 2 (Figure 1). For example, the thickness of the work function layer 68B can be in the range of about 3 nm to about 4.5 nm. The work function layers 68B deposited on adjacent semiconductor nanostructures 22B are thus merged together without gaps between them. On the other hand, a gap is left between the bottom nanostructure 22B and the semiconductor strip 20'. According to some embodiments, the spacing S1 (equal to the thickness T1 in Figure 1) is greater than about 13.5 nm and can be in the range of about 13.5 nm to about 15 nm. The reserved spacing S3 can be greater than about 1 nm and can be in the range of about 1 nm to about 3 nm.

[0044] Figures 9A-1 and 9A-2 illustrate the structure in device region 100A after the formation of work function layer 68B, according to some embodiments. A high-dielectric-constant dielectric layer 66 may be exposed. According to some embodiments, the formation of work function layer 68B may include a blanket conformal deposition process such that when work function layer 68B is deposited to device region 100B, work function layer 68B may also be deposited to device region 100A. An etch mask (not shown) may then be formed to cover device region 100B, followed by an etching process to remove work function layer 68B from device region 100A, thus exposing the high-dielectric-constant dielectric layer 66 again. The etch mask is then removed.

[0045] Figures 10A-1, 10A-2, 10B-1, and 10B-2 illustrate the deposition of the work function layer 68A. A specific process is shown as process 226 of process flow 200 shown in Figure 13. The thickness of the work function layer 68A can range from approximately 6 nm to approximately 7 nm. According to some embodiments of forming an n-type transistor in device region 100A, the work function layer 68A can have a work function smaller than the intermediate gap work function and can range from approximately 4.0 eV to approximately 4.5 eV. According to some embodiments, the work function layer 68A can be formed of or include aluminum-containing materials such as TiAl, TiAlC, TiAlN, TaAl, TaAlC, TaAlN, etc.

[0046] According to an alternative embodiment, for example, the work function layer 68A may have an intermediate gap work function in the range of about 4.5 eV and about 4.6 eV. The corresponding work function layer 68B may include tungsten. The forming process may include ALD, CVD, etc. Other materials such as Si, Ti, etc. may also be used.

[0047] Figures 10A-1, 10A-2, 10B-1, and 10B-2 further illustrate the composition of the upper layers of gate electrodes 76A and 76B. A specific process is shown as process 228 of process flow 200 shown in Figure 13. According to some embodiments, the silicon layer 70 comprises deposited element silicon (rather than silicon compounds). For example, deposition can be achieved by immersing the wafer 10 in a silicon-containing precursor such as silane or di-silane. The thickness of the silicon layer 70 can range from about 1 nm to about 2 nm. A binder layer 72, which may include TiN, is deposited on the silicon layer 70. The binder layer 72 can be formed via deposition processes such as CVD, ALD, etc. The thickness of the binder layer 72 can range from about 1 nm to about 3 nm, and can also range from about 1 nm to about 2 nm, or from about 2.5 nm to about 3 nm.

[0048] A filler metal region 74 is further deposited on the adhesive layer 72, completely filling the retained recesses 58A and 58B. The deposition thickness of the filler metal region 74 can be in the range of approximately 3 nm to approximately 4 nm. A planarization process, such as CMP or mechanical polishing, is then performed to leave gate electrodes 76A and 76B in device regions 100A and 100B, respectively.

[0049] In device region 100A, the gate dielectric 62 and the gate electrode 76A integrally form a gate stack 78A. In device region 100B, the gate dielectric 62 and the gate electrode 76B integrally form a gate stack 78B. The heights of the gate stacks 78A and 78B can be in the range of approximately 12 nm and approximately 14 nm. Therefore, GAA transistors 110A and 110B are formed in device regions 100A and 100B, respectively.

[0050] In device region 100A, according to some embodiments, the work function layer 68A completely fills the bottom gap between nanostructure 22B1 and semiconductor strip 20', and upper layers such as silicon layer 70 and adhesive layer 72 do not fill into the bottom gap. According to some alternative embodiments, in addition to work function layer 68B, some other layers such as silicon layer 70 or both silicon layer 70 and adhesive layer 72 fill into the bottom gap, while the upper gap completely fills work function layer 68A.

[0051] In device region 100B, according to some embodiments, work function layers 68A and 68B completely fill the bottom gap between nanostructure 22B1 and semiconductor strip 20', and upper layers such as silicon layer 70 and adhesive layer 72 do not fill into the bottom gap. According to some alternative embodiments, some other layers such as silicon layer 70 or both silicon layer 70 and adhesive layer 72 fill into the bottom gap, while the upper gap completely fills work function layer 68B. A dielectric hard mask 80 is formed over gate stacks 78A and 78B. The formation process may include etching recesses in the gate stacks 78A and 78B, and filling the resulting recesses with a dielectric material. A planarization process is performed to flatten the top surfaces of the dielectric hard mask 80 and ILD 52.

[0052] Figures 11A-1, 11A-2, 11B-1, and 11B-2, and Figures 12A-1, 12A-2, 12B-1, and 12B-2 illustrate the formation of the upper feature. According to some embodiments, as shown in Figures 11A-1, 11A-2, 11B-1, and 11B-2, source / drain silicide layers 82 are formed on source / drain regions 48A and 48B, and source / drain contact plugs 84 are formed in ILD 52. An etch stop layer 86 and an ILD 88 are further formed, and source / drain contact plugs 92 are formed in the etch stop layer 86 and ILD 88. The formation of the source / drain contact plugs 92 includes a planarization process such as CMP. Figures 12A-1, 12A-2, 12B-1, and 12B-2 show the formation of a gate contact plug 90 through a dielectric hard shield 80 to be electrically connected to gate electrodes 76A and 76B.

[0053] In device region 100A, as shown in Figures 12A-1 and 12A-2, the work function layer 68A completely fills the gaps between adjacent semiconductor nanostructures 22B, and completely fills the gaps between the bottom semiconductor nanostructure 22B and the semiconductor strip 20'. Accordingly, all channels formed by the semiconductor nanostructures 22B and the sub-channels 20' are controlled by a gate stack 78A having the work function layer 68A.

[0054] The nanosheet transistor 110A can be considered to include two types of sub-transistors. The first sub-transistor 110A-1 includes a sub-channel 20' as its own channel, a gate stack 78A portion between the sub-channel 20' and the semiconductor nanostructure 22B1 as its own gate stack, and a source / drain region 48A as its own source / drain region. The second sub-transistor 110A-2 includes semiconductor nanostructures 22B1 and 22B2 as channels, a portion of the upper part of the gate stack 78A as the gate stack, and further includes a source / drain region 48A as its own source / drain region. Sub-transistors 110A-1 and 110A-2 are connected in parallel to form transistor 110A. Sub-transistors 110A-1 and 110A-2 may have the same threshold voltage.

[0055] In device region 100B, on the other hand, as shown in Figures 11B-1 and 11B-2, the work function layer 68B completely fills the gap between adjacent semiconductor nanostructures 22B2. Therefore, the corresponding work function layer is work function layer 68B. Work function layers 68B and 68A (collectively referred to as work function layer 68B'), on the other hand, completely fill the bottom gap between the bottom semiconductor nanostructure 22B1 and the semiconductor strip 20'.

[0056] The nanosheet transistor 110B can be considered to include two types of sub-transistors. The first sub-transistor 110B-1 includes a sub-channel 20' as its own channel, a gate stack 78B portion between the sub-channel 20' and the bottom semiconductor nanostructure 22B1 as its own gate stack, and a source / drain region 48B as its own source / drain region. The second sub-transistor 110B-2 includes semiconductor nanostructures 22B1 and 22B2 as channels, a portion of the upper part of the gate stack 78B as the gate stack, and a source / drain region 48B as its own source / drain region. Sub-transistors 110B-1 and 110B-2 are connected in parallel to form transistor 110A.

[0057] According to embodiments where some work function layers 68B have p-type work functions (e.g., work function WF68B), work function layer 68A has a work function WF68A that is smaller than work function WF68B. Therefore, assuming transistor 110B is a p-type transistor, the effective work function of the gate electrode 76B of the first sub-transistor 110B-1 is lower than the individual work function WF68B. The threshold voltage Vt68B1 of sub-transistor 110B-1 is higher than the threshold voltage Vt68B2 of sub-transistor 110B-2.

[0058] It should be understood that subchannel 20' is prone to leakage, especially as the width of the nanosheet increases. According to some embodiments, by adjusting the work function layers 68A and 68B of the gate stack 78B portion for subchannel 20', when transistor 110B is turned off, subchannel 20' is better shut off because the threshold voltage Vt68B1 of subtransistor 110B-1 is higher than the threshold voltage Vt68B2 of subtransistor 110B-2, and leakage current through subchannel 20' is reduced.

[0059] According to some of the above example embodiments, transistor 110A is an n-type transistor, and transistor 110B is a p-type transistor. Therefore, the work function layer 68B is a p-type work function layer or an intermediate gap work function layer, and the work function layer 68A has a lower work function than the work function layer 68B (which can be a p-type work function, an intermediate gap work function, or an n-type work function) to increase the threshold voltage of the sub-transistor 100B-1.

[0060] According to an alternative embodiment, transistor 110A is a p-type transistor, and transistor 110B is an n-type transistor. Therefore, the work function layer 68B is an n-type work function layer or an intermediate gap work function layer, and the work function layer 68A has a higher work function (which can be an n-type work function, an intermediate gap work function, or a p-type work function) than the work function layer 68B to increase the threshold voltage of the sub-transistor 100B-1.

[0061] According to another alternative embodiment, transistors 110A and 110B are both p-type transistors. Therefore, the work function layer 68B is a p-type work function layer or an intermediate gap work function layer, and the work function layer 68A has a lower work function than the work function layer 68B (which may be an n-type work function or an intermediate gap work function) to increase the threshold voltage of the sub-transistor 100B-1.

[0062] According to another alternative embodiment, transistors 110A and 110B are both n-type transistors. Therefore, the work function layer 68B is an n-type work function layer or an intermediate gap work function layer, and the work function layer 68A has a higher work function (which may be a p-type work function or an intermediate gap work function) than the work function layer 68B to increase the threshold voltage of the sub-transistor 100B-1.

[0063] The embodiments disclosed herein have several advantageous features. By forming a multifunctional layer at the bottom of the gate stack for GAA transistors, the threshold voltage of the bottom sub-transistor is increased, and leakage through the sub-channels is reduced.

[0064] According to some embodiments of this disclosure, the method includes depositing a multilayer stack comprising alternating sacrificial layers and semiconductor layers, wherein the sacrificial layers include a bottom sacrificial layer and an upper sacrificial layer, the bottom sacrificial layer having a first thickness, and the upper sacrificial layer being located above the bottom sacrificial layer, wherein the upper sacrificial layer has a second thickness less than the first thickness. The multilayer stack is patterned to form a first protruding fin. A first dummy gate stack is formed on the first protruding fin. A first source / drain region is formed adjacent to the first dummy gate stack. The sacrificial layers in the first dummy gate stack and the first protruding fin are removed to leave a first recess, and a first alternative gate stack is formed in the first recess.

[0065] In one embodiment, the ratio of one of the first thickness and the second thickness is greater than about 1.2. In one embodiment, the first recess includes a bottom recess and an upper recess. The bottom recess is below the bottommost semiconductor layer in the first protruding fin, wherein forming the first alternative gate stack includes depositing a first work function layer and depositing a second work function layer into the bottom recess. The upper recess is above the bottommost semiconductor layer, wherein the first alternative gate stack includes a first work function layer in the upper recess. In one embodiment, depositing the first work function layer results in the entirety of one of the upper recesses being filled.

[0066] In one embodiment, the first work function layer and the second work function layer comprise different materials. In one embodiment, the first source / drain region is in a p-type transistor, wherein the second work function layer has a lower work function than the first work function layer. In one embodiment, the first work function layer has a p-type work function, and the second work function layer has an n-type work function. In one embodiment, the first work function layer has a first p-type work function, and the second work function layer has a second p-type work function, the second p-type work function being lower than the first p-type work function.

[0067] In one embodiment, the first source / drain region is in an n-type transistor, wherein the second work function layer has a higher work function than the first work function layer. In one embodiment, the first work function layer has an n-type work function, and the second work function layer has a p-type work function. In one embodiment, the first work function layer has a first n-type work function, and the second work function layer has a second n-type work function, wherein the second n-type work function is higher than the first n-type work function.

[0068] In one embodiment, the patterned multilayer stack further results in the formation of a second protruding fin, and the method further includes forming a second dummy gate stack on the second protruding fin. A second source / drain region is formed adjacent to the second dummy gate stack. The second dummy gate stack and the sacrificial layer in the second protruding fin are removed to leave a second recess, and a second alternative gate stack is formed in the second recess, wherein all second recesses are filled with the same work function layer.

[0069] According to some embodiments of this disclosure, the structure includes a semiconductor strip, a first isolation region, a second isolation region, a semiconductor nanostructure, a gate stack, and a semiconductor region. The second isolation region is located on the opposite side of the semiconductor strip. The semiconductor nanostructure overlaps the semiconductor strip, wherein upper semiconductor nanostructures in the semiconductor nanostructure overlap lower semiconductor nanostructures in the semiconductor nanostructure. The gate stack includes a bottom and a top. The bottom has a first height, located between the semiconductor strip and the semiconductor nanostructure. The top is located between adjacent semiconductor nanostructures, and has a second height, which is smaller than the first height. The semiconductor region is adjacent to and in contact with the semiconductor nanostructure.

[0070] In one embodiment, the upper portion of the gate stack has a uniform height. In one embodiment, the bottom of the gate stack includes a first work function layer and a second work function layer, the second work function layer being surrounded by the first work function layer, wherein the upper portion of the gate stack includes the first work function layer but does not include the second work function layer. In one embodiment, the bottom further includes a silicon layer, the silicon layer being surrounded by the second work function layer. In one embodiment, the ratio of one of the first height to the second height is greater than about 1.2.

[0071] According to some embodiments of this disclosure, the structure includes a semiconductor nanostructure, a gate stack, and a semiconductor region. Upper semiconductor nanostructures in the semiconductor nanostructure respectively cover lower semiconductor nanostructures in the semiconductor nanostructure. The gate stack includes a bottom and an upper portion. The bottom portion is located below the bottommost semiconductor nanostructure of the semiconductor nanostructure, and includes a first work function layer and a second work function layer, the second work function layer surrounding the first work function layer, wherein all layers in the bottom portion have a first total number. The upper portion is located between adjacent semiconductor nanostructures, and includes a second work function layer, wherein all layers in the upper portion have a second total number, the second total number being less than the first total number. The semiconductor region is adjacent to and in contact with the semiconductor nanostructure. In one embodiment, the upper portion of the gate stack does not include a second work function layer. In one embodiment, the first height of the bottom portion is higher than the second height of the upper portion.

[0072] The features of many embodiments outlined above will enable those skilled in the art to better understand the viewpoints of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or adapting other processes and structures to achieve the same purpose and / or attain the same benefits as the embodiments described herein. Those skilled in the art will also understand that such equivalent architectures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0073] 10: Wafer 20:Substrate 20': Semiconductor strip / subchannel 22: Multi-layer stacking 22': Multi-layer stacking 22A: Semiconductor layer / First layer / Sacrificial layer 22A-1: Bottom Sacrificial Layer 22A-2: Upper layer / Upper sacrificial layer 22B: Semiconductor layer / second layer / nanostructure 22B1: Nanostructure 22B2: Nanostructure 23: Trench 24: Semiconductor strips 26: Isolation Zone / Shallow Trench Isolation Zone 26T: Top surface 28: Protruding fins 30: Dummy gate stack 32: Dummy gate dielectric 34: Dummy gate electrode 36: Hard mask layer 38: Gate spacer 42: Depression 46: Internal spacers 48A: Source / Drain Region / Region 48B: Source / Drain Region / Region 50: Contact Etching Stop Layer 52: Interlayer Dielectric 58: Depression 58A: Depression 58B: Depression 62: Gate Dielectric 64: Interface Layer 66: High dielectric constant dielectric layer 68A: Work Function Layer 68B: Work Function Layer 68B': Work Function Layer 70: Silicon layer 72: Adhesive layer 74: Filled metal area 76A: Gate electrode 76B: Gate electrode 78A: Gate Stacking 78B: Gate Stacking 80: Dielectric hard shield 82: Source / Drain Silicate Layer 84: Source / Drain Contact Plug 86: Etching Stop Layer 88:ILD 90: Gate contact plug 92: Source / Drain contact plug 100A: Equipment Area 100B: Equipment Area 110A: GAA transistor / nano-sheet transistor / transistor 110A-1: First sub-transistor 110A-2: Second sub-transistor 110B: GAA transistor / nano-sheet transistor / transistor 110B-1: First sub-transistor 110B-2: Second Sub-transistor 200: Manufacturing Process 202: Process 204: Process 206: Manufacturing Process 208: Process 210: Manufacturing Process 212: Manufacturing Process 214: Manufacturing Process 216: Manufacturing Process 218: Manufacturing Process 220: Process 222: Manufacturing Process 224: Manufacturing Process 226: Manufacturing Process 228: Manufacturing Process CL-CL: Cross-section GL-GL: Cross section T1: Thickness T2: Thickness S1: Spacing S2: Spacing S3: Spacing

[0074] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming nanosheet transistors, comprising: A multilayer stack is deposited, comprising: a plurality of sacrificial layers and a plurality of semiconductor layers alternately disposed, wherein the sacrificial layers include: a bottom sacrificial layer having a first thickness; and a plurality of upper sacrificial layers located above the bottom sacrificial layer, wherein the upper sacrificial layers have a plurality of second thicknesses less than the first thickness; the multilayer stack is patterned to form a first protruding fin; a first dummy gate stack is formed on the first protruding fin; a first source / drain region is formed adjacent to the first dummy gate stack; the first dummy gate stack and the sacrificial layers in the first protruding fin are removed to leave a plurality of first recesses, wherein the first recesses include: a bottom recess below a bottommost semiconductor layer of the semiconductor layers in the first protruding fin; and a plurality of upper recesses above the bottommost semiconductor layer; and a first alternative gate stack is formed in the first recesses, the first alternative gate stack comprising: A bottom, recessed therein and having a first height; and a plurality of upper portions, recessed therein and having a plurality of second heights less than the first height, and the upper portions having the same height, wherein the semiconductor layers have the same third height.

2. The method as described in claim 1, wherein a ratio of one of the first thicknesses to one of the second thicknesses is greater than about 1.

2.

3. The method as described in claim 1, wherein forming the first alternative gate stack comprises: A first work function layer and a second work function layer are deposited into the bottom depression; And the first alternative gate stack includes: the first work function layer in the upper recesses.

4. The method as described in claim 3, wherein the first work function layer and the second work function layer comprise different materials.

5. A structure of a nanosheet transistor, comprising: A semiconductor strip; a first isolation region and a second isolation region on opposite sides of the semiconductor strip; a plurality of semiconductor nanostructures overlapping the semiconductor strip, wherein a plurality of upper semiconductor nanostructures of the semiconductor nanostructures overlap a plurality of lower semiconductor nanostructures of the semiconductor nanostructures; a gate stack comprising: a bottom having a first height, wherein the bottom is between the semiconductor strip and the semiconductor nanostructures; and a plurality of upper portions between adjacent semiconductor nanostructures, wherein the upper portions have a plurality of second heights less than the first height, and the upper portions of the gate stack have the same height, wherein the semiconductor nanostructures have the same third height; and a semiconductor region adjacent to and in contact with the semiconductor nanostructures.

6. The structure as described in claim 5, wherein the ratio of the first height to the second height is greater than about 1.

2.

7. The structure as described in claim 5, wherein the bottom of the gate stack includes: First work function layer; And a second work function layer surrounded by the first work function layer, wherein the upper portions of the gate stack include the first work function layer and do not include the second work function layer.

8. A structure of a nanosheet transistor, comprising: A plurality of semiconductor nanostructures, wherein a plurality of upper semiconductor nanostructures of the semiconductor nanostructures respectively cover a plurality of lower semiconductor nanostructures of the semiconductor nanostructures; A gate stack includes: a bottom layer below a bottom semiconductor nanostructure and having a first height, wherein the bottom layer includes: a first work function layer; and a second work function layer surrounding the first work function layer, wherein all layers in the bottom layer have a first total number; and a plurality of upper portions between adjacent semiconductor nanostructures, wherein the upper portions have a plurality of second heights less than the first height and have the same height, wherein the semiconductor nanostructures have the same third height, wherein the upper portion includes the second work function layer, wherein all layers in the upper portion have a second total number less than the first total number; and a semiconductor region adjacent to and in contact with the semiconductor nanostructures.

9. The structure as described in claim 8, wherein the upper portion of the gate stack does not include the second work function layer.

10. The structure as described in claim 8, wherein a first height at the bottom is higher than a second height at the top.

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