ADC device and method for converting an analog signal to a digital signal

Abstract

An analog-to-digital converter (ADC) device includes a first stage and a second stage. The first stage has an input for receiving an analog signal and an output for transmitting a first digital signal based on the analog signal. The first stage includes a successive approximation register that receives the analog signal and performs a successive approximation of the analog signal to provide the first digital signal. The successive approximation register includes a passive switched-capacitor integrator for filtering low-frequency white noise and integrating a residual signal based on a comparison controlled by the successive approximation of the analog signal to generate a filtered first-stage quantization error. The second stage receives and converts the filtered first-stage quantization error into a second digital signal, and a digital filter combines the first and second digital signals to provide a combined digital signal.

Description

Technical Field

[0001] This invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter having a noise-shifting successive approximation register and digitization of quantization error. Prior Technology

[0002] Analog-to-digital converters (ADCs) are used in various applications to convert analog input signals into digital output signals. Essentially, the digital output signal is a binary digit proportional to the analog input signal. Continuous analog input signals are periodically sampled, and each sample is converted into a discrete digital output signal. Converting continuous analog input signals to digital output signals requires quantizing the analog input signals, which can introduce quantization errors.

[0003] Analog-to-digital converter (ADC) architectures include piped, flash, delta-Sigma, integrating (sloping), and successive approximation register (SAR) architectures. Each architecture has its advantages and disadvantages. For example, delta-Sigma ADCs can achieve relatively high resolutions, such as 16 bits or higher, but bandwidth may be limited. SAR ADCs can operate with relatively low power consumption, but resolution may be limited. In some ADC architectures, it is difficult to achieve sufficiently high signal-to-noise ratios (SNR) and conversion bandwidth. Summary of the Invention

[0004] This disclosure provides an analog-to-digital converter device, including a first stage and a second stage. The first stage has a first input terminal for receiving a first analog input signal and an output terminal for transmitting a first digital output signal based on the first analog input signal. The first stage includes a successive approximation register for receiving the first analog input signal and performing a plurality of successive approximations on the first analog input signal to provide the first digital output signal. The successive approximation register includes a passive switched-capacitor integrator that filters out low-frequency white noise and integrates a first residual signal. The first residual signal generates a first-level quantization error based on the comparison of the successive approximations of the first analog input signal with the first analog input signal. The second stage receives the first-level quantization error and converts the first-level quantization error into a second digital output signal. The second stage also includes a digital filter that combines the first digital output signal and the second digital output signal to provide a combined digital output signal.

[0005] This disclosure provides an analog-to-digital converter device, including a first stage having a first input terminal for receiving a first analog signal, a second input terminal for receiving a second analog signal, and an output terminal for transmitting a first digital output signal based on the first and second analog signals. The first stage includes a successive approximation register, which performs a complex number of successive approximations on the first and second analog signals to provide the first digital output signal. The successive approximation register includes a passive switched-capacitor integrator, which integrates a first residual signal from the successive approximation based on the first analog input signal and a second residual signal from the successive approximation based on the second analog input signal to provide a first-stage quantization error. The passive switched-capacitor integrator includes a first sampling capacitor. The device is configured to sample a first residual signal during a first set of signals and provide a first sample of the first residual signal to a first integrating capacitor during a second set of signals, the second set of signals being different from and alternating with the first set of signals; a second sampling capacitor is configured to sample the first residual signal during the second set of signals and provide a second sample of the first residual signal to the first integrating capacitor during the first set of signals; a third sampling capacitor is configured to sample the second residual signal during the first set of signals and provide a first sample of the second residual signal to a second integrating capacitor during the second set of signals; and a fourth sampling capacitor is configured to sample the second residual signal during the second set of signals and provide a second sample of the second residual signal to the second integrating capacitor during the first set of signals.

[0006] This disclosure provides a method for converting an analog signal into a digital signal in an analog-to-digital converter device, comprising receiving a first analog signal at a first input of a successive approximation register; receiving a second analog signal at a second input of the successive approximation register; performing a plurality of successive approximations on the first analog signal and the second analog signal using the successive approximation register; generating a first digital output signal based on the successive approximations of the first analog signal and the second analog signal using the successive approximation register; integrating a first residual signal based on the successive approximation of the first analog signal using a passive switched-capacitor integrator; integrating a second residual signal based on the successive approximation of the second analog signal using a passive switched-capacitor integrator; and generating a filtered first-level quantization error based on the integration of the first residual signal and the second residual signal. Simple Explanation of the Diagram

[0007] The various aspects of this disclosure will be best understood by reading the following detailed description and referring to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced. Furthermore, these drawings are merely illustrative examples of embodiments of this disclosure and are not intended to limit the scope of this disclosure. Figure 1 is a schematic diagram illustrating a multi-level analog-to-digital converter device according to some embodiments. Figure 2 is a schematic diagram illustrating a first stage according to some embodiments. Figure 3 is a schematic diagram illustrating a passive switched capacitor integrator according to some embodiments. Figure 4 is a schematic diagram illustrating a second level according to some embodiments. Figure 5 is a schematic diagram illustrating a voltage / time converter according to some embodiments. Figure 6 is a schematic diagram illustrating a time-to-digital converter according to some embodiments. Figure 7 is a schematic diagram illustrating a digital filter according to some embodiments. Figure 8 is a schematic diagram illustrating the Fast Fourier Transform (FFT) spectrum of an analog-to-digital converter device according to some embodiments. Figure 9 is a schematic diagram illustrating a noise frequency shift successive approximation register according to some embodiments, the noise frequency shift successive approximation register being part of the first stage of one of the analog / digital converter devices. Figure 10 is a schematic diagram illustrating a noise frequency shift successive approximation register with a passive switched capacitor integrator according to some embodiments. Figure 11 is a timing diagram illustrating the operation of a noise frequency shift successive approximation register with a passive switched capacitor integrator according to some embodiments. Figure 12 is a schematic diagram illustrating a second level according to some embodiments. Figure 13 is a schematic diagram illustrating one method of converting an analog signal into a digital signal in an analog-to-digital converter device according to some embodiments. Implementation

[0008] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of apparatus and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, the description of a first feature being formed "on" or "on" a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. Such repetition is for the purpose of brevity and clarity and is not, in itself, an indication of a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, for ease of explanation, this document may use spatially relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature illustrated in the figures and another (other) element or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0010] Successive approximation registers (SARs) are commonly used in applications such as sensors, data acquisition systems, and battery-powered devices. A SAR SAR ADC performs a series of comparisons and approximations to determine a digital output signal that is proportional to and correlated with an analog input signal. The SAR ADC uses a binary search algorithm to acquire the digital output signal correlated with the analog input signal. In some embodiments, the analog input signal is sampled and retained, and the SAR ADC sets the most significant bit (MSB) of the digital output signal to 1, while the remaining bits are set to 0. A digital-to-analog converter (DAC) generates an analog output voltage based on the digital output signal. A comparator compares the analog output voltage of a digital-to-analog converter (DAC) with a sampled analog input voltage and outputs a high-level or low-level digital signal based on whether the sampled analog input voltage is higher or lower than the DAC's analog output voltage. The comparator's output determines whether a bit is set to 1 or 0. Next, the second most significant bit (e.g., MSB-1) is set to 1, and the DAC's analog output voltage is compared with the sampled analog input signal to determine whether the bit is set to 1 or 0. This process continues processing the remaining bits until the least significant bit (LSB) is reached to obtain the digital output signal associated with the sampled analog input signal. Furthermore, the DAC's analog output voltage is subtracted from the sampled analog input signal to obtain a residual voltage, also known as the residual error, which is a quantization error.

[0011] Analog-to-digital converters typically include high-performance analog circuitry, such as high-gain operational amplifiers, which consume significant power. This makes it challenging to implement successive approximation register analog-to-digital converters in advanced, deeply extended (nanoscale) process technologies with reduced supply voltages.

[0012] The disclosed embodiments provide a multi-stage analog-to-digital converter (ADC) including a noise-shaping successive approximation register and digitization of quantization error. The ADC device includes a first stage, a second stage, and a digital filter. The first stage includes a noise-shaping successive approximation register that receives one or more analog input signals and successively approximates the analog input signals to provide a first digital output signal. The successive approximation register includes a passive switched-capacitor integrator, which acts as a loop filter to filter out low-frequency white noise. The passive switched-capacitor integrator integrates the residual signals (also referred to herein as residual signals) generated by comparing the successive approximations of the analog input signals with the analog input signals to produce a first-stage quantization error. The second stage receives the quantization error from the first stage and converts it into a second digital output signal. A digital filter combines the first and second digital output signals to provide a combined final digital output signal. In some embodiments, the second stage digitizes the first-stage quantization error in the time domain and outputs the second digital output signal.

[0013] The disclosed embodiments also provide an analog-to-digital converter (ADC) device including a first stage. The first stage includes a successive approximation register that performs a successive approximation of an analog input signal to provide a first digital output signal. The successive approximation register includes a passive switched-capacitor integrator that integrates the residual signal based on the successive approximation of the analog signal to provide a first-stage quantization error. A passive switched-capacitor integrator includes a first sampling capacitor configured to sample a first residual signal during a first set of signals and provide a first sample of the first residual signal to the first integrating capacitor during a second set of signals, the second set of signals being different from and alternating with the first set of signals; a second sampling capacitor configured to sample the first residual signal during the second set of signals and provide a second sample of the first residual signal to the first integrating capacitor during the first set of signals; a third sampling capacitor configured to sample a second residual signal during the first set of signals and provide a first sample of the second residual signal to the second integrating capacitor during the second set of signals; and a fourth sampling capacitor configured to sample the second residual signal during the second set of signals and provide a second sample of the second residual signal to the second integrating capacitor during the first set of signals.

[0014] Further disclosed embodiments include a method of operating an analog-to-digital converter device. The method includes: performing a successive approximation of a first analog signal and a second analog signal via a successive approximation register; generating a first digital output signal from the successive approximation register based on the successive approximation of the first and second analog signals; integrating a first residual signal based on the successive approximation of the first analog signal via a passive switched-capacitor integrator; integrating a second residual signal based on the successive approximation of the second analog signal via a passive switched-capacitor integrator; and generating a first-level quantization error based on the integration of the first and second residual signals.

[0015] The disclosed embodiments offer scalability advantages in deep nanoscale processes, such as advanced FinFET technology. The disclosed embodiments can be implemented in low power supply voltage applications, such as those with a supply voltage equal to or below 1.0 volt (V), thereby utilizing advanced complementary metal-oxide-semiconductor (CMOS) process technologies. Furthermore, in some embodiments, low power supply voltage applications refer to the core power supply voltage used in advanced digital processes; for 5-nanometer (nm) or 3-nm technologies, the core power supply voltage may be between 0.75V and 0.96V. Additionally, the disclosed embodiments can be used in analog circuits without relying on input / output (IO) transistor devices with higher voltage ratings.

[0016] Figure 1 is a schematic diagram illustrating a multi-stage analog-to-digital converter (ADC) device 20 according to some embodiments. The ADC device 20 performs high-pass frequency noise shifting and quantization error digitization. The ADC device 20 is an electronic device. In some embodiments, the ADC device 20 includes one or more semiconductor devices. In some embodiments, the ADC device 20 includes one or more integrated circuit devices.

[0017] The analog-to-digital converter device 20 includes a first stage 22, a second stage 24, and a digital filter 26. The first stage 22 is electrically connected to the second stage 24 through a first conductive path 28 and to the digital filter 26 through a second conductive path 30. The second stage 24 is electrically connected to the digital filter 26 through a third conductive path 32.

[0018] The first stage 22 includes a noise frequency-shifted successive approximation register 34, which includes a passive switched-capacitor integrator 36. The noise frequency-shifted successive approximation register 34 is electrically connected to the second stage 24 via a first conductive path 28 and to the digital filter 26 via a second conductive path 30. The first stage 22 includes an input IN that receives an analog input signal. The noise frequency-shifted successive approximation register 34 performs a successive approximation of the analog input signal to generate a first digital output signal corresponding to the analog input signal on the second conductive path 30.

[0019] The passive switched-capacitor integrator 36 serves as a high-pass loop filter to filter out low-frequency white noise during the operation of the noise frequency-shifted successive approximation register 34. The passive switched-capacitor integrator 36 integrates the residual signal generated by comparing the analog signal from the noise frequency-shifted successive approximation register with the analog input signal from input IN. Based on the residual signal, the passive switched-capacitor integrator 36 generates a first-order quantization error transmitted along the first conductive path 28. In some embodiments, the passive switched-capacitor integrator 36 includes a plurality of sampling capacitors that alternately sample a residual signal and integrate the sampled residual signal onto an integrating capacitor, such that the output (i.e., sampling rate) of the analog-to-digital converter device 20 is not reduced.

[0020] The second stage 24 receives the first-stage quantization error on the first conductive path 28 and converts it into a second digital output signal. The second digital output signal is transmitted to the digital filter 26 on the third conductive path 32. The second stage 24 digitizes the first-stage quantization error in the time domain and outputs the second digital output signal on the third conductive path 32.

[0021] The second stage 24 includes a voltage-to-time converter (VTC) 38, which is electrically connected to a time-to-digital converter (TDC) 40 via a fourth conductive path 42. The VTC 38 receives the first-stage quantization error and converts it from voltage to the corresponding time. The TDC 40 converts the time to a second digital output signal. Therefore, the first-stage quantization error is passively connected or coupled to the VTC 38 of the second stage 24 without requiring an active amplifier circuit. In some embodiments, the VTC 38 includes a zero-crossing detector (ZCD) that receives the first-stage quantization error and converts the voltage to the corresponding time.

[0022] The digital filter 26 receives a first digital output signal and a second digital output signal, and in the digital domain, the digital filter combines the first digital output signal and the second digital output signal to provide a final combined digital output signal at the output terminal DOUT44 of the digital filter 26.

[0023] The analog-to-digital converter device 20 includes a noise-shifting successive approximation register 34 in a first stage 22 and a time-domain quantizer in a second stage 24. Advantages of the analog-to-digital converter device 20 include that the noise-shifting successive approximation register 34 not only suppresses first-stage quantization errors but also suppresses comparator noise in the noise-shifting successive approximation register 34, which could otherwise significantly impact overall noise and power consumption. Furthermore, when used in conjunction with oversampling, noise shifting can significantly reduce in-band quantization and comparator noise, thereby improving the signal-to-noise ratio (SNR). Similarly, through oversampling, the sampling in-band thermal noise (referred to as kT / C noise) on the capacitive digital-to-analog converter (CDAC) of the noise-shifting successive approximation register 34 is reduced. Furthermore, the passive switched-capacitor integrator 36 uses only passive components and requires no active amplifier, thus consuming no active power and saving power. Therefore, the analog-to-digital converter device 20 can be used in deep nanoscale technologies with low supply voltages. In this case, low supply voltage refers to the low core supply voltage used in advanced digital process technologies, such as between 0.75V and 0.96V in 5nm or 3nm technologies. Additionally, in some embodiments, noise and nonlinearity in the second stage 24 are high-pass filtered through a noise frequency-shifting function, which increases the signal-to-noise ratio (SNDR).

[0024] Figure 2 is a schematic diagram illustrating a first stage 50 according to some embodiments. The first stage 50 includes a noise frequency-shifted successive approximation register, which includes a passive switched-capacitor integrator. In some embodiments, Figure 2 is a signal flow diagram of the first stage 50 in the z-conversion domain. In some embodiments, Figure 2 is a functional diagram of the noise frequency-shifted successive approximation register 34 (as shown in Figure 1). In some embodiments, the first stage 50 is similar to the first stage 22 (as shown in Figure 1).

[0025] The first stage 50 includes a first adder 52, a passive switched-capacitor integrator 54, a first gain stage 56, a comparator 58, and a digital-to-analog converter 60. The first stage 50 has an input terminal 62 that receives a sampled and held analog input signal X(z). The sampled analog input signal is received at a positive input terminal of the first adder 52 and a positive input terminal of the comparator 58. The first adder 52 compares the sampled analog input signal with an analog output signal at an output terminal 64 of the digital-to-analog converter 60, the analog output signal of which is received at a negative input terminal of the first adder 52. The digital-to-analog converter 60 receives a digital output signal at an output terminal 66 of the first stage 50 and converts the digital output signal into an analog output signal for the digital-to-analog converter 60. The analog output signal of the digital-to-analog converter 60 approximates the sampled analog input signal. The difference between the sampled analog input signal and the analog output signal of the digital-to-analog converter 60 is a residual signal VRES(z) at the output terminal 68 of the first adder 52. The residual signal VRES(z) is received and integrated by the passive switched-capacitor integrator 54.

[0026] The passive switched-capacitor integrator 54 includes a second gain stage 70, a second adder 72, a delay 74, and a feedback signal 76. The second gain stage 70 receives the residual signal VRES(z) and applies a gain factor a less than 1. The result is received by the second adder 72, which also receives the feedback signal 76 from a previous summation of (1-a)z⁻¹. The second adder adds the results from the second gain stage 70 and the feedback signal 76 to provide a summed result, which is delayed by one clock cycle in the z-conversion domain Z⁻¹ by the delay 74. The first gain stage 56 receives the delayed summed result from the delay 74 and has a gain factor g with a quantization error applied to the delayed summed result to provide a first-stage quantization error to the second stage, such as the second stage 24 (as shown in Figure 1), on the conductive path 78.

[0027] Comparator 58 adds the first-stage quantization error to the sampled analog input signal and feeds it forward, combining it with the quantization error q1(z) introduced by comparator 58 to produce a first output signal Y1(z) of the first stage 50. The digital output signal of the first stage 50 is fed back to the digital-to-analog converter 60, which transmits its analog output signal to the first adder 52. This process is repeated. The first output signal Y1(z) of the first stage 50 is:

[0028] ,

[0029] Where NTF1 is the noise conversion function of the first stage 50, and the first stage quantization error, including the quantization error q1(z) introduced by comparator 58, is:

[0030] .

[0031] Figure 3 is a schematic diagram illustrating a passive switched-capacitor integrator 80 according to some embodiments. The passive switched-capacitor integrator 80 includes a sampling capacitor Cs82, an integrating capacitor Cint84, two phi1 switches (switches 86 and 88) activated by a first clock signal φ1, and two phi2 switches (switches 90 and 92) activated by a second clock signal φ2. The passive switched-capacitor integrator 80 has a gain factor of:

[0032] .

[0033] In operation, clock signal φ1 is activated to close the two phi1 switches (switches 86 and 88), and clock signal φ2 is deactivated to activate the two phi2 switches (switches 90 and 92) to sample the input signal Vin using sampling capacitor Cs82. Next, clock signal φ1 is deactivated to activate the two phi1 switches (switches 86 and 88), and clock signal φ2 is activated to close the two phi2 switches (switches 90 and 92) to integrate the sampled voltage on sampling capacitor Cs82 onto integrating capacitor Cint84. The integrated voltage on integrating capacitor Cint84 can be obtained from the output signal Vout. This process is repeated to continue sampling and integrating the input signal Vin.

[0034] Compared to the first stage 50 in Figure 2, the passive switched capacitor integrator 80 has a transition function:

[0035] ,

[0036] And the first level 50 has a first-level output as follows:

[0037] ,

[0038] in,

[0039] In this way

[0040] ,

[0041] Where Vn,CMP are the inputs called comparator noise.

[0042] For example, in some embodiments, a=0.5 and g=2, such that the output of the first stage 50 is:

[0043] .

[0044] The passive switched-capacitor integrator 80 is used to implement a high-pass filter noise conversion function, as shown in the equation in paragraph

[0043] above, which filters out low-frequency white noise. Therefore, the successive approximation register is a noise frequency-shifting successive approximation register.

[0045] Figure 4 is a schematic diagram illustrating a second stage 100 according to some embodiments. The second stage 100 includes a time-domain quantizer that digitizes the first-stage quantization error in the time domain and outputs a second digital output signal. In some embodiments, the second stage 100 is similar to the second stage 24 (as shown in Figure 1).

[0046] The second stage 100 includes an input terminal 102 for receiving the filtered first-stage quantization error and an output terminal 104 for transmitting the second digital output signal. The second stage 100 converts the first-stage quantization error into a second digital output signal, which is transmitted via output terminal 104 to a digital filter, such as digital filter 26 (as shown in Figure 1). The first-stage quantization error, including the quantization error q1(z) introduced by comparator 58, is:

[0047] .

[0048] The output of level 100 is:

[0049] ,

[0050] Where q2(z) is the second-level quantization error of 100.

[0051] The second stage 100 includes a voltage-to-time converter 106 electrically connected to a time-to-digital converter 108 via a conductive path 110. The voltage-to-time converter 106 receives a first-stage quantization error (as shown in FIG. 2) at its input terminal 102 on the conductive path 78 and converts the first-stage quantization error from voltage to a corresponding time. The time-to-digital converter 108 receives the corresponding time and the quantization error q2(z) 112 of the second stage 100 and converts the corresponding time to a second digital output signal. The time-to-digital converter 108 outputs the second digital output signal at its output terminal 104. Therefore, the first-stage quantization error is passively connected or coupled to the voltage-to-time converter 106 of the second stage 100 without the need for an active amplifier circuit. In some embodiments, the voltage-to-time converter 106 includes a zero-crossing detector that receives the first-stage quantization error and converts the voltage to a corresponding time.

[0052] Figure 5 is a schematic diagram illustrating a voltage / time converter 120 according to some embodiments. The voltage / time converter 120 includes a zero-crossing detector 122, a discharge current source 124, and a discharge switch 126. In some embodiments, the voltage / time converter 120 is similar to a voltage / time converter 38 (as shown in Figure 1). In some embodiments, the voltage / time converter 120 is similar to a voltage / time converter 106 (as shown in Figure 4).

[0053] Zero-crossing detector 122 receives the first-stage quantization error generated by the first stage, such as first stage 22 (as shown in Figure 1) or first stage 50 (as shown in Figure 2). In this example, a differential signal received by zero-crossing detector 122 at a first input 128 is a high residual voltage VRESP, and a differential signal received at a second input 130 is a low residual voltage VRESM.

[0054] One end of the discharge current source 124 is electrically coupled to an analog power supply voltage AVDD, and the other end is electrically coupled to one end of the discharge switch 126. The other end of the discharge switch 126 is electrically coupled to the first input terminal 128.

[0055] In operation, the first input terminal 128 receives the high residual voltage VRESP, and the second input terminal 130 receives the low residual voltage VRESM. Discharge switch 126 is activated by a switch signal φDIS to close discharge switch 126 and set the output 132 of zero-crossing detector 122 to a high voltage. Discharge current source 124 provides a discharge current IDIS, which discharges the high residual voltage VRESP until it is equal to or lower than the low residual voltage VRESM. This sets the output 132 of zero-crossing detector 122 to a low voltage, generating a discharge pulse Tp with a width proportional to the difference between the high residual voltage VRESP and the low residual voltage VRESM. Therefore, voltage / time converter 120 performs a voltage-to-time conversion.

[0056] In a system with a single residual voltage VRES:

[0057] ,

[0058] Where VIN is the sampled analog input voltage and VDAC is the analog output voltage of the digital-to-analog converter, for example, digital-to-analog converter 60 (as shown in Figure 2). The discharge time TDIS is:

[0059] ,

[0060] Where VOS is the offset voltage and CT is the total capacitance at the VRES node.

[0061] Figure 6 is a schematic diagram illustrating a time-to-digital converter 140 according to some embodiments. The time-to-digital converter 140 includes a digital delay line for measuring the time interval between a start event and a stop event, and for generating a corresponding digital output signal, namely a second digital output signal. A start event, such as the rising edge of the discharge pulse Tp of the zero-crossing detector 122 (as shown in Figure 5), is applied to the start of the digital delay line, while a stop event, such as the falling edge of the discharge pulse Tp of the zero-crossing detector 122, locks the state of the digital delay line. Therefore, the time-to-digital converter 140 converts the time interval between the start event and the stop event (e.g., the width of the discharge pulse Tp of the zero-crossing detector 120) into a digital output signal. In some embodiments, the time-to-digital converter 140 is similar to the time-to-digital converter 40 (as shown in Figure 1). In some embodiments, the time-to-digital converter 140 is similar to the time-to-digital converter 108 (as shown in Figure 4).

[0062] The time-to-digital converter 140 includes delay units 142a-142n and D-type flip-flops 144a-144n. In some embodiments, the delay units 142a-142n are voltage-controlled delay units. In some embodiments, one or more delay units 142a-142n include a delay-locked loop (DLL) for stabilizing the delay of the delay units 142a-142n to resist process, power supply, and temperature variations.

[0063] Each delay unit 142a-142n has a signal delay time td, such that delay unit 142a outputs a delayed signal D1 at output terminal 146a, delay unit 142b outputs a delayed signal D2 at output terminal 146b, and so on, until delay unit 142n outputs a delayed signal DN at output terminal 146n. Delay units 142a-142n are connected in series, such that output terminal 146a is connected to the input terminal of delay unit 142b, and so on.

[0064] Each D-type flip-flop 144a-144n includes a data input D, a clock input Clk, and an output Q. The data input D of the D-type flip-flop 144a is electrically coupled to the output 146a of the delay unit 142a and receives the delay signal D1; the data input D of the D-type flip-flop 144b is electrically coupled to the output 146b of the delay unit 142b and receives the delay signal D2, and so on, until the data input D of the D-type flip-flop 144n is electrically coupled to the output 146n of the delay unit 142n and receives the delay signal DN. In addition, each clock input Clk of the D-type flip-flops 144a-144n is electrically connected to the conductive path 148 that receives a stop event, such as the falling edge of the discharge pulse Tp (as shown in Figure 5).

[0065] In operation, a start event, such as the rising edge of the discharge pulse Tp of the zero-crossing detector 122, is applied to the input terminal 150 of the delay unit 142a and propagates through one or more delay units 142a-142n. A stop event, such as the falling edge of the discharge pulse Tp of the zero-crossing detector 122, latches the delay signals D1 to DN to the D-type flip-flops 144a-144n. The D-type flip-flops 144a-144n output the latched voltages at their output terminals Q1, Q2 to QN, respectively, to generate corresponding digital output signals, i.e., the second digital output signal. Therefore, the time / digital converter 140 converts the width of the discharge pulse Tp of the zero-crossing detector 122 into a digital output signal, i.e., the second digital output signal.

[0066] Figure 7 is a schematic diagram illustrating a digital filter 160 according to some embodiments. The digital filter 160 receives a first digital output signal Y1(z) from a first stage and a second digital output signal Y2(z) from a second stage, and combines the signals in the digital domain to provide a final combined digital output signal Yo(z). In some embodiments, the first stage is similar to first stage 22 (as shown in Figure 1). In some embodiments, the first stage is similar to first stage 50 (as shown in Figure 2). In some embodiments, the second stage is similar to second stage 24 (as shown in Figure 1). In some embodiments, the second stage is similar to second stage 100 (as shown in Figure 4). In some embodiments, the digital filter 160 is similar to digital filter 26 (as shown in Figure 1).

[0067] The digital filter 160 includes an adder 162, a delay 164, and a filter function 166. The delay 164 is electrically connected to a first input 168 of the adder 162, and the filter function 166 is electrically connected to a second input 170 of the adder 162. The delay 164 receives a first digital output signal Y1(z) and delays it by one clock cycle in the z-transformation domain Z-1. The filter function 166 receives a second digital output signal Y2(z) and applies the function 1-(1-a)Z-1 to the second digital output signal Y2(z). The adder 162 receives the result from the delay 164 and the filter function 166 and outputs the final combined digital output signal Yo(z) at its output 172.

[0068] In this example, the first digital output signal Y1(z) from the first stage is:

[0069] ,

[0070] The second digital output signal Y2(z) of the second stage is:

[0071] .

[0072] The final combined digital output signal Yo(z) from adder 162 is:

[0073] ,

[0074] The quantization error q1 introduced by comparator 58 has been eliminated.

[0075] Furthermore, if a = 0.5 and g = 2, then:

[0076] .

[0077] Figure 8 is a schematic diagram illustrating the fast Fourier transform (FFT) spectrum of an analog-to-digital converter device 180 according to some embodiments. The FFT spectrum includes an analog FFT spectrum of an analog-to-digital converter device with a noise-shift successive approximation register 182, and an analog FFT spectrum of an analog-to-digital converter device without a noise-shift successive approximation register 184. The analog-to-digital converter device including a noise-shift successive approximation register includes a passive switched-capacitor integrator, which acts as a high-pass filter to filter out low-frequency white noise. Therefore, the analog-to-digital converter device including a noise-shift successive approximation register can perform high-pass frequency noise shifting and digitization of quantization errors, thereby improving the in-band signal-to-noise ratio (SNR).

[0078] In some embodiments, the analog-to-digital converter (ADC) device includes a first stage, a second stage, and a digital filter. In some embodiments, the analog-to-digital converter device is similar to the analog-to-digital converter device 20 in FIG1. ​​In some embodiments, the first stage is similar to first stage 22, the second stage is similar to second stage 24, and the digital filter is similar to digital filter 26. In some embodiments, the first stage is similar to first stage 50 in FIG2, the second stage is similar to second stage 100 in FIG4, and the digital filter is similar to digital filter 160 in FIG7. In some embodiments, the noise shift successive approximation register is similar to a noise shift successive approximation register 34 including a passive switched-capacitor integrator 36.

[0079] The Fast Fourier Transform (FFT) spectrum is presented graphically, with x-axis 186 representing frequency in Hertz (Hz) and y-axis 188 representing power spectral density in decibels (dB). At frequencies below approximately 90,000,000 Hz, the power spectral density of the analog-to-digital converter (ADC) device including a noise-shifting successive approximation register 182 is less than that of the ADC device excluding a noise-shifting successive approximation register 184. Specifically, the power spectral density of the ADC device including the noise-shifting successive approximation register 182 is approximately -60 dB to -45 dB at frequencies below approximately 90,000,000 Hz. The power spectral density of the ADC device excluding the noise-shifting successive approximation register 184 remains relatively constant at -45 dB. The noise shift successive approximation register includes a passive switched-capacitor integrator, which acts as a high-pass filter to filter out low-frequency white noise.

[0080] Analog-to-digital converters (ADCs) that include a noise-shifting successive approximation register can produce a higher signal-to-noise ratio (SNR). For example, an ADC with a sampling rate of 320 mega-samples per second (MSPS), an input tone of 7.5 MHz, a signal bandwidth of 40 MHz, and an oversampling rate (OSR) of 4, provides an SNR of 64.5 dB without a noise-shifting successive approximation register, while an ADC that includes a noise-shifting successive approximation register provides an even higher SNR of 73.4 dB.

[0081] Figure 9 is a schematic diagram illustrating a noise-shifted successive approximation register 200 according to some embodiments, which is part of a first stage of an analog-to-digital converter device. The noise-shifted successive approximation register 200 includes a sample-and-hold circuit 202, a passive switched-capacitor integrator 204, a comparator 206, and successive approximation register logic 208. The noise-shifted successive approximation register 200 uses the comparator 206 to successively narrow down a range including an input voltage. In each successive step, the noise-shifted successive approximation register 200 compares the input voltage with an analog output of the digital-to-analog converter. In some embodiments, the noise-shifted successive approximation register 200 is similar to a noise-shifted successive approximation register 34 (as shown in Figure 1). In some embodiments, the passive switched-capacitor integrator 204 is similar to a passive switched-capacitor integrator 36 (as shown in Figure 1).

[0082] The sample-and-hold circuit 202 includes a set of capacitors 210a and a set of switches 212a, corresponding to the differential residual voltage RESP. One side of each of the capacitors 210a is electrically connected to the residual voltage conductor 214, and the other side of each of the capacitors 210a is electrically connected to a switch of the set of switches 212a. The other side of the set of switches 212a is configured to switch to an analog input voltage VIP, a high reference voltage VREFP, and a low reference voltage VREFM. Furthermore, the sample-and-hold circuit 202 includes a set of capacitors 210b and a set of switches 212b, corresponding to the differential residual voltage REM. One side of each of the capacitors 210b is electrically connected to the residual voltage conductor 216, and the other side of each of the capacitors 210b is electrically connected to a switch of the set of switches 212b. The other side of the set of switches 212b is configured to switch to an analog input voltage VEM, a high reference voltage VREFP, and a low reference voltage VREFM. Furthermore, the sample-and-hold circuit 202 includes switches 222a and 222b, which connect the common-mode voltage VCM to residual voltage conductors 214 and 216, respectively. Each of the sets of capacitors 210a and 210b includes multiple capacitors 1C and multiple capacitors 2C, 4C, 8C, etc., up to a maximum of capacitor 2NC, where N may correspond to the number of bits to be digitized. In some embodiments, the two sets of capacitors (one set of capacitors 210a and one set of capacitors 210b) are binary-weighted.

[0083] In operation, the sample-and-hold circuit 202 includes two sets of switches (one set of switches 212a and one set of switches 212b) receiving successive approximation register control signals from successive approximation register logic 208 on conductive paths 218 and 220. The control signals control the two sets of switches (one set of switches 212a and one set of switches 212b) to selectively connect two sets of capacitors (one set of capacitors 210a and one set of capacitors 210b) to the analog input voltage VIP, analog input voltage VIM, high reference voltage VREFP, and low reference voltage VREFM. Furthermore, the control signals control switches 222a and 222b to selectively connect the common-mode voltage VCM to residual voltage conductors 214 and 216.

[0084] In some embodiments, during a first clock phase or pulse, clock signal PHI_1 is enabled to sample and hold analog input voltages VIP and VIM. Control signals connect analog input voltage VIP to the top plate of capacitor 210a and analog input voltage VIM to the top plate of capacitor 210b. Approximately at the same time, clock signal PHI_1E is enabled to turn off switches 222a and 222b and connect the bottom plates of capacitors 210a and 210b to the common-mode voltage VCM. During the next clock phase or pulse, clock signal PHI_2 is enabled, for example for comparator 206, to control a binary search algorithm implemented by successive approximation register logic 208 to generate a corresponding digital output signal representing the differential analog input voltage. Next, during the third clock phase or pulse, a clock signal PHI_3 (not shown) is activated to initiate the second stage of the analog-to-digital converter to digitize the first stage quantization error and output a second digital output signal. Successive approximation register logic 208 is electrically connected to the second stage via conductive path 224 to control the output of the second digital output signal. Furthermore, a noise-shifted successive approximation register 200 is electrically connected to the second stage via conductive path 226 to receive signals from the second stage.

[0085] The passive switched-capacitor integrator 204 acts as a high-pass loop filter to filter out low-frequency white noise during the operation of the noise frequency-shifted successive approximation register 200. The passive switched-capacitor integrator 204 integrates the differential residual voltages RESP and RSM, which are based on a comparison of the analog signal from the noise frequency-shifted successive approximation register 200 with the analog input voltages VIP and VIM. Based on the differential residual voltages RESP and RSM, the passive switched-capacitor integrator 200 generates a first-stage quantization error, which is propagated to a second stage. The passive switched-capacitor integrator 200 includes multiple sampling capacitors that alternately sample the residual signal and integrate the sampled signal onto the integrating capacitor, thus maintaining the output (i.e., sampling rate) of the analog-to-digital converter device.

[0086] The sample-and-hold circuit 202 is electrically coupled to the passive switched-capacitor integrator 204 through residual voltage conductors 214 and 216. The passive switched-capacitor integrator 204 is electrically coupled to the comparator 206 and the second stage through differential input paths 228 and 230. The comparator 206 is electrically coupled to the successive approximation register logic 208 through differential output paths 232 and 234. The successive approximation register logic 208 is electrically coupled to the second stage through differential input paths 228 and 230.

[0087] The passive switched-capacitor integrator 204 includes six capacitors: CRP1236, CRP2238, CINTP240, CRM1242, CRM2244, and CINTM246. Capacitors CRP1236, CRP2238, and CINTP240 are used to sample and integrate the differential residual voltage RESP. Capacitors CRM1242, CRM2244, and CINTM246 are used to sample and integrate the differential residual voltage RESS.

[0088] As shown in Figure 9, during a set of clock signals PHI_1, PHI_2, and PHI_3, capacitor CRP1236 samples the differential residual voltage RESP, and capacitor CRM1242 samples the differential residual voltage RESS. Simultaneously, capacitor CRP2238 integrates the previously obtained sample of differential residual voltage RESP onto capacitor CINTP240, and capacitor CRM2244 integrates the previously obtained sample of differential residual voltage RESS onto capacitor CINTM246. During the next set of clock signals PHI_1, PHI_2, and PHI_3, the capacitor arrangement, including capacitors CRP1236, CRP2238, CINTP240, CRM1242, CRM2244, and CINTM246, is changed or switched to another arrangement, as shown in Figure 10.

[0089] Figure 10 is a schematic diagram illustrating a noise frequency shift successive approximation register 200 with a passive switched-capacitor integrator 204 according to some embodiments. The passive switched-capacitor integrator 204 has six capacitors, including capacitors CRP1236, CRP2238, CINTP240, CRM1242, CRM2244, and CINTM246, which switch to another arrangement to process the next group of clock signals PHI_1, PHI_2, and PHI_3. Other components of the noise frequency shift successive approximation register 200 are similar to those in the noise frequency shift successive approximation register 200 in Figure 9, and therefore will not be described again here.

[0090] As shown in Figure 10, in the next group of clock signals (clock signal PHI_1, clock signal PHI_2, and clock signal PHI_3), capacitor CRP2238 samples the differential residual voltage RESP, and capacitor CRM2244 samples the differential residual voltage RESS. Simultaneously, capacitor CRP1236 integrates the previously obtained sample of differential residual voltage RESP onto capacitor CINTP240, and capacitor CRM1242 integrates the previously obtained sample of differential residual voltage RESS onto capacitor CINTM246.

[0091] Therefore, during a set of clock signals (clock signal PHI_1, clock signal PHI_2, and clock signal PHI_3), the sampling capacitor and the integrating capacitor are set in one configuration, while in the next set of clock signals (clock signal PHI_1, clock signal PHI_2, and clock signal PHI_3), the sampling capacitor and the integrating capacitor are set in another configuration, and this alternating process is repeated continuously.

[0092] While one capacitor (e.g., capacitor CRP1236) completes sampling, another capacitor (e.g., capacitor CRP2238) is integrating the sample, and so on alternately. The capacitors switch back and forth, with one capacitor sampling during a set of clock signals (clock signals PHI_1, PHI_2, and PHI_3), while the other capacitor performs integration during the next set of clock signals (clock signals PHI_1, PHI_2, and PHI_3). This saves time because no additional clock cycles are needed to sample and integrate the residual voltages RESP and RSM between the sets of clock signals (clock signals PHI_1, PHI_2, and PHI_3). Furthermore, the output (i.e., the sampling rate) of the analog-to-digital converter device is not reduced.

[0093] Figure 11 is a timing diagram 260 illustrating the operation of a noise frequency shift successive approximation register 200 with a passive switched-capacitor integrator 204 according to some embodiments. Timing diagram 260 includes a first set of clock signals 262 and a second set of clock signals 264, which operate alternately during analog-to-digital conversion.

[0094] During the first set of clock signals 262, clock signal PHI_1 266 rises to a high voltage level 268 to sample and hold analog input voltages VIP and VIM. The high voltage level 268 of clock signal PHI_1 266 connects analog input voltage VIP to the top plate of capacitor 210a and analog input voltage VIM to the top plate of capacitor 210b. Furthermore, clock signal PHI_1E 270 rises to a high voltage level 272 to turn off switches 222a and 222b and connects the bottom plates of capacitors 210a and 210b to the common-mode voltage VCM. Clock signal PHI_1E 270 returns to a low voltage level 274, and shortly thereafter, clock signal PHI_1 266 returns to a low voltage level 276.

[0095] After the clock signal PHI_1 266 returns to the low voltage level 276, the clock signal PHI_2 278 rises to the high voltage level 280, and the binary search algorithm is implemented by the successive approximation register logic 208 to generate a first digital output signal corresponding to the analog input voltages VIP and VIM. Then the clock signal PHI_2 278 returns to a low voltage level 282.

[0096] After clock signal PHI_2 278 returns to low voltage level 282, clock signal PHI_3 284 rises to a high voltage level 286 to initiate the second stage of the analog-to-digital converter. The second stage receives and digitizes the quantization error of the first stage and outputs the second stage digital output signal. Clock signal PHI_3 284 returns to low voltage level 288 at the end of the first set of clock signals 262.

[0097] During the first set of clock signals 262, clock signal PHI_R1 290 rises to a high voltage level 292, and clock signal PHI_R2 294 is at a low voltage level 296. At low voltage level 296, capacitor CRP1236 samples the differential residual voltage RESP, and capacitor CRM1242 samples the differential residual voltage RESS. Capacitor CRP2238 is connected to integrate the previously obtained sample of differential residual voltage RESP onto capacitor CINTP240, and capacitor CRM2244 is connected to integrate the previously obtained sample of differential residual voltage RESS onto capacitor CINTM246. During the second set of clock signals 264, the configuration or arrangement of the capacitors (including capacitors CRP1236, CRP2238, CINTP240, CRM1242, CRM2244, and CINTM246) is changed to another configuration or arrangement.

[0098] During the second set of clock signals 264, clock signals PHI_1 266, PHI_1E 270, PHI_2 278, and PHI_3 284 are identical to those clock signals during the first set of clock signals 262. Clock signal PHI_1 266 rises to a high voltage level 298 to sample and hold analog input voltages VIP and VIM. The high voltage level 298 of clock signal PHI_1 266 connects analog input voltage VIP to the top plate of capacitor 210a and analog input voltage VIM to the top plate of capacitor 210b. Furthermore, clock signal PHI_1E 270 rises to a high voltage level 300 to turn off switches 222a and 222b and connects the bottom plates of capacitors 210a and 210b to the common-mode voltage VCM. The clock signal PHI_1E 270 returns to a low voltage level 302, and shortly thereafter, the clock signal PHI_1 266 returns to a low voltage level 304.

[0099] After the clock signal PHI_1 266 returns to a low voltage level 304, the clock signal PHI_2 278 rises to a high voltage level 306. The binary search algorithm is implemented using the successive approximation register logic 208 to generate a first digital output signal corresponding to the analog input voltages VIP and VIM. Then, the clock signal PHI_2 278 returns to a low voltage level 308.

[0100] After clock signal PHI_2 278 returns to low voltage level 308, clock signal PHI_3 284 rises to a high voltage level 310 to initiate the second stage of the analog-to-digital converter. The second stage receives and digitizes the first stage quantization error and outputs a second digital output signal. Clock signal PHI_3 284 returns to a low voltage level 312 at the end of the second set of clock signals 264.

[0101] During the second set of clock signals 264, clock signal PHI_R1 290 is at a low voltage level 314, while clock signal PHI_R2 294 rises to a high voltage level 316. This connects capacitor CRP2238 to sample the differential residual voltage RESP, capacitor CRM2244 to sample the differential residual voltage RESS, capacitor CRP1236 to integrate the previously obtained differential residual voltage RESP sample onto capacitor CINTP240, and capacitor CRM1242 to integrate the previously obtained differential residual voltage RESS sample onto capacitor CINTM246.

[0102] Therefore, in the first set of clock signals 262, the sampling capacitor and the integrating capacitor are connected in one configuration, and in the second set of clock signals 264, the sampling capacitor and the integrating capacitor are connected in another configuration. These two configurations alternate during the analog-to-digital conversion process. This alternating capacitor configuration saves time because no additional clock cycle is required between the first set of clock signals 262 and the second set of clock signals 264 to sample and integrate the differential residual voltage RESP and differential residual voltage RSM. Furthermore, the output (i.e., the sampling rate) of the analog-to-digital converter device increases or at least does not decrease.

[0103] Figure 12 is a schematic diagram illustrating a second stage 330 according to some embodiments. The second stage 330 receives the first-stage quantization error and converts it into a second digital output signal, which is transmitted to a digital filter, such as digital filter 26 (as shown in Figure 1). In some embodiments, the second stage 330 is similar to the second stage 24 (as shown in Figure 1). In some embodiments, the second stage 330 is similar to the second stage 100 of Figure 4.

[0104] The second stage 330 is electrically coupled to the noise frequency shift successive approximation register 200 of Figures 9 and 10. The second stage 330 is electrically coupled to the comparator 206 and the successive approximation register logic 208 via differential input paths 228 and 230. Furthermore, the second stage 330 is electrically coupled to the successive approximation register logic 208 via conductive path 224, and in some embodiments, the second stage 330 is electrically coupled to the noise frequency shift successive approximation register 200 via conductive path 226 to enable the noise frequency shift successive approximation register 200 to operate.

[0105] The second stage 330 receives and digitizes the filtered first-stage quantization error, and outputs a second digital output signal. The second stage 330 is activated when the clock signal PHI_3 284 (as shown in Figure 11) is at high voltage level 286 and high voltage level 310. The clock signal of PHI_3 284 returns to low voltage level 288 and low voltage level 312 at the end of each clock signal group.

[0106] The second stage 330 includes a zero-crossing detector 332, a time-to-digital converter 334, and an output register 336. The zero-crossing detector 332 is electrically coupled to the differential input of comparator 206 and successive approximation register logic 208 via differential input paths 228 and 230. Furthermore, the zero-crossing detector 332 is electrically coupled to the time-to-digital converter 334 via conductive path 338. The successive approximation register logic 208 is electrically coupled to the output register 336 via conductive path 224 to control the operation of the output register 336. In some embodiments, the zero-crossing detector 332 is similar to the zero-crossing detector 122 (as shown in FIG. 5). In some embodiments, the zero-crossing detector 332 is part of the voltage-to-time converter 120 of FIG. 5, which includes the zero-crossing detector 122, a discharge current source 124, and a discharge switch 126.

[0107] Zero-crossing detector 332 receives a differential input signal, one of the first-stage filtering quantization errors, through differential input paths 228 and 230. The differential input signal includes a high residual voltage and a low residual voltage. Zero-crossing detector 332 performs a voltage-to-time conversion on the differential input signal and outputs a pulse TP, the width of which is proportional to the difference between the high and low residual voltages. In some embodiments, zero-crossing detector 332 is part of the voltage / time converter 120 of FIG. 5, such that the function of zero-crossing detector 332 is related to the voltage / time converter 120 of FIG. 5.

[0108] The time-to-digital converter 334 receives the pulse TP and converts the pulse TP into a second digital output signal. In some embodiments, the time-to-digital converter 334 is similar to the time-to-digital converter 140 of FIG. 6. In some embodiments, the time-to-digital converter 334 is similar to the time-to-digital converter 40 (as shown in FIG. 1).

[0109] In some embodiments, the second stage 330 further includes a time-to-digital converter (TD-SCDMA) logic 340, an encoder logic 342, and a latch array 344. The TD-SCDMA 334 is electrically coupled to the TD-SCDMA logic 340 via conductive path 346 and to the latch array 344 via conductive path 348. The TD-SCDMA logic 340 is electrically coupled to the encoder logic 342 via conductive path 350, and to the noise frequency shift successive approximation register 200 via conductive path 226, providing a signal for the operation of the noise frequency shift successive approximation register 200. The latch array 344 is electrically coupled to the encoder logic 342 via conductive path 352, and the encoder logic 342 is electrically coupled to the output register 336 via conductive path 354.

[0110] In operation, the time / digital converter 334 receives the pulse TP and outputs the signal to the time / digital converter logic 340 and the latch array 344, which in turn outputs the signal to the encoder logic 342. The encoder logic 342 encodes the received signal and outputs a second digital output signal to the output register 336, which outputs the second digital output signal on the output path DOUT 356.

[0111] Therefore, the second stage 330 receives the quantization error from the first stage and converts it into a second digital output signal. This second digital output signal is transmitted on the output path DOUT to a digital filter, such as digital filter 26. The digital filter receives the first digital output signal from the first stage and the second digital output signal from the second stage, and combines them to provide a final combined digital output signal at the output of the digital filter.

[0112] Figure 13 is a schematic diagram illustrating one method of converting an analog signal to a digital signal in an analog-to-digital converter device according to some embodiments. The analog-to-digital converter device includes a noise-shifting successive approximation register, which includes a passive switched-capacitor integrator. In some embodiments, the analog-to-digital converter device is similar to analog-to-digital converter device 20 in Figure 1. In some embodiments, the noise-shifting successive approximation register is similar to noise-shifting successive approximation register 34 (as shown in Figure 1). In some embodiments, the noise-shifting successive approximation register is similar to noise-shifting successive approximation register 200 (as shown in Figures 9 and 10). In some embodiments, the passive switched-capacitor integrator is similar to passive switched-capacitor integrator 36 (as shown in Figure 1). In some embodiments, the passive switched-capacitor integrator is similar to passive switched-capacitor integrator 204 (as shown in Figures 9 and 10).

[0113] In operation 370, the method includes receiving a first analog signal at a first input of a successive approximation register; and in operation 372, the method includes receiving a second analog signal at a second input of the successive approximation register. In operation 374, the method includes performing a successive approximation of the first analog signal and the second analog signal through the successive approximation register; and in operation 376, the method includes generating a first digital output signal based on the successive approximation of the first analog signal and the second analog signal through the successive approximation register.

[0114] In operation 378, the method includes integrating a first residual signal based on a successive approximation of a first analog signal by a passive switched-capacitor integrator. In some embodiments, integrating the first residual signal includes sampling the first residual signal by a first sampling capacitor during a first set of signals, and providing a first sample of the first residual signal to a first integrating capacitor during a second set of signals, the second set of signals being different from the first set of signals and alternating with the first set of signals, sampling the first residual signal by a second sampling capacitor during the second set of signals, and providing a second sample of the first residual signal to the first integrating capacitor during the first set of signals.

[0115] In operation 380, the method includes integrating a second residual signal based on a successive approximation of a second analog signal by a passive switched-capacitor integrator. In some embodiments, integrating the second residual signal includes sampling the second residual signal by a third sampling capacitor during a first set of signals and providing a first sample of the second residual signal to a second integrating capacitor during a second set of signals, and sampling the second residual signal by a fourth sampling capacitor during the second set of signals and providing a second sample of the second residual signal to the second integrating capacitor during the first set of signals.

[0116] In operation 382, ​​the method includes generating a first-order quantization error based on the integration of the first residual signal and the second residual signal.

[0117] In some embodiments, the method includes: during a first set of signals and a second set of signals, sampling and holding a first analog signal and a second analog signal by a successive approximation register during a first time period, performing a successive approximation on the first analog signal and the second analog signal during a second time period, and converting a first-level quantization error from a voltage to a corresponding time during a third time period, and triggering a conversion from the corresponding time to a second digital output signal. In some embodiments, the method includes receiving the first-level quantization error at a second stage, converting the first-level quantization error to a second digital output signal, and combining the first digital output signal and the second digital output signal to provide a combined digital output signal.

[0118] Therefore, the disclosed embodiments provide an analog-to-digital converter device including a noise-shifted successive approximation register with a passive switched-capacitor integrator. A first stage includes the noise-shifted successive approximation register, which successively approximates an analog input signal to provide a first digital output signal. The noise-shifted successive approximation register with the passive switched-capacitor integrator acts as a high-pass filter to filter out low-frequency white noise. The passive switched-capacitor integrator integrates the residual signal and generates a first-stage quantization error. A second stage converts the first-stage quantization error into a second digital output signal, and a digital filter combines the first and second digital output signals to provide a combined final digital output signal.

[0119] The disclosed embodiments further provide an analog-to-digital converter device including a passive switched-capacitor integrator. The passive switched-capacitor integrator includes a first sampling capacitor configured to sample a first residual signal during a first set of signals and provide a first sample of the first residual signal to the first integrating capacitor during a second set of signals, the second set of signals being different from and alternating with the first set of signals; a second sampling capacitor configured to sample the first residual signal during the second set of signals and provide a second sample of the first residual signal to the first integrating capacitor during the first set of signals; a third sampling capacitor configured to sample a second residual signal during the first set of signals and provide a first sample of the second residual signal to the second integrating capacitor during the second set of signals; and a fourth sampling capacitor configured to sample the second residual signal during the second set of signals and provide a second sample of the second residual signal to the second integrating capacitor during the first set of signals.

[0120] Further disclosed embodiments include a method for converting an analog signal into a digital signal in an analog-to-digital converter device. The method includes: performing a successive approximation of a first analog signal and a second analog signal via a successive approximation register; generating a first digital output signal from the successive approximation register based on the successive approximation of the first and second analog signals; integrating a first residual signal based on the successive approximation of the first analog signal via a passive switched-capacitor integrator; integrating a second residual signal based on the successive approximation of the second analog signal via a passive switched-capacitor integrator; and generating a first-level quantization error based on the integration of the first and second residual signals.

[0121] The advantages of the disclosed embodiments include scalability in deep nanoscale processes, implementation in low supply voltage applications, and use in analog circuits without relying on I / O devices with higher rated voltages.

[0122] According to some embodiments, an analog-to-digital converter (ADC) device includes a first stage, a second stage, and a digital filter. The first stage has a first input terminal for receiving a first analog input signal and an output terminal for transmitting a first digital output signal based on the first analog input signal. The first stage includes a successive approximation register that receives the first analog input signal and performs a successive approximation on the first analog input signal to provide the first digital output signal. The successive approximation register includes a passive switched-capacitor integrator for filtering low-frequency white noise and integrates a first residual signal generated by comparing the successive approximation based on the first analog input signal with the first analog input signal to generate a first-stage quantization error. The second stage receives the first-stage quantization error and converts it into a second digital output signal. The digital filter combines the first digital output signal and the second digital output signal to provide a combined digital output signal.

[0123] In some embodiments, a successive approximation register generates an analog signal based on a successive approximation controlled by the successive approximation register, and compares the analog signal with a first analog input signal to generate a first residual signal. In some embodiments, the first stage includes receiving a second analog input signal and a second input terminal for the successive approximation register to sample and hold the first and second analog input signals. In some embodiments, the passive switched-capacitor integrator includes a first sampling capacitor configured to sample the first residual signal during a first set of signals and provide a first sample of the first residual signal to a first integrating capacitor during a second set of signals, the second set of signals being different from and alternating with the first set of signals, and a second sampling capacitor configured to sample the first residual signal during the second set of signals and provide a second sample of the first residual signal to the first integrating capacitor during the first set of signals. In some embodiments, the passive switched-capacitor integrator includes a third sampling capacitor configured to sample a second residual signal during a first set of signals and provide a first sample of the second residual signal to a second integrating capacitor during a second set of signals, and a fourth sampling capacitor configured to sample the second residual signal during the second set of signals and provide a second sample of the second residual signal to the second integrating capacitor during the first set of signals. In some embodiments, a second stage receives an integrated first residual voltage from a first integrating capacitor and an integrated second residual voltage from a second integrating capacitor. In some embodiments, the second stage includes a voltage-to-time converter that receives the integrated first residual voltage from the first integrating capacitor and the integrated second residual voltage from the second integrating capacitor. In some embodiments, the voltage-to-time converter includes a zero-crossing detector that receives the integrated first residual voltage from the first integrating capacitor and the integrated second residual voltage from the second integrating capacitor. In some embodiments, the second stage includes a time-to-digital converter connected to a voltage-to-time converter, the time-to-digital converter being configured to provide a second digital output signal. In some embodiments, during the first and second sets of signals, the first stage samples and holds a first analog input signal during a first pulse, performs a complex number of successive approximations on the first analog input signal during a second pulse, and converts the first stage quantization error from a voltage to a corresponding time during a third pulse, triggering a conversion from the corresponding time to the second digital output signal.

[0124] According to a further embodiment, an analog-to-digital converter device includes a first stage having a first input for receiving a first analog signal, a second input for receiving a second analog signal, and an output for transmitting a first digital output signal based on the first and second analog signals. The first stage includes a successive approximation register that successively approximates the first and second analog signals to provide the first digital output signal. The successive approximation register includes a passive switched-capacitor integrator that integrates a first residual signal based on the successive approximation of the first analog signal and a second residual signal based on the successive approximation of the second analog signal to provide a first-stage quantization error. A passive switched-capacitor integrator includes a first sampling capacitor configured to sample a first residual signal during a first set of signals and provide a first sample of the first residual signal to the first integrating capacitor during a second set of signals, the second set of signals being different from and alternating with the first set of signals; a second sampling capacitor configured to sample the first residual signal during the second set of signals and provide a second sample of the first residual signal to the first integrating capacitor during the first set of signals; a third sampling capacitor configured to sample the second residual signal during the first set of signals and provide a first sample of the second residual signal to the second integrating capacitor during the second set of signals; and a fourth sampling capacitor configured to sample the second residual signal during the second set of signals and provide a second sample of the second residual signal to the second integrating capacitor during the first set of signals.

[0125] In some embodiments, during the first and second sets of signals, a successive approximation register is configured to sample and hold the first and second analog signals during a first pulse, perform a complex number of successive approximations on the first and second analog signals during a second pulse, and convert the first-level quantization error from a voltage to a corresponding time during a third pulse, triggering a conversion from the corresponding time to a second digital output signal. In some embodiments, a second stage receives the first-level quantization error and converts it to a second digital output signal; and a digital filter combines the first and second digital output signals to provide a combined digital output signal. In some embodiments, the second stage includes a voltage-to-time converter connected to a time-to-digital converter, wherein the voltage-to-time converter includes a zero-crossing detector that receives an integrated first residual voltage from a first integrating capacitor and an integrated second residual voltage from a second integrating capacitor, and the time-to-digital converter generates the second digital output signal. In some embodiments, the digital filter reduces or eliminates the first-stage quantization error.

[0126] According to a further disclosed embodiment, a method for converting an analog signal into a digital signal in an analog-to-digital converter device includes: receiving a first analog signal at a first input of a successive approximation register; receiving a second analog signal at a second input of the successive approximation register; performing successive approximation on the first analog signal and the second analog signal through the successive approximation register; generating a first digital output signal based on the successive approximation of the first analog signal and the second analog signal through the successive approximation register; integrating a first residual signal based on the successive approximation of the first analog signal by a passive switched-capacitor integrator; integrating a second residual signal based on the successive approximation of the second analog signal by a passive switched-capacitor integrator; and generating a first-level quantization error based on the integration of the first residual signal and the second residual signal.

[0127] In some embodiments, integrating the first residual signal includes: sampling the first residual signal via a first sampling capacitor during a first set of signals, and providing a first sample of the first residual signal to a first integrating capacitor during a second set of signals, the second set of signals being different from and alternating with the first set of signals; and sampling the first residual signal via a second sampling capacitor during the second set of signals, and providing a second sample of the first residual signal to the first integrating capacitor during the first set of signals. In some embodiments, integrating the second residual signal includes: sampling the second residual signal via a third sampling capacitor during the first set of signals, and providing a first sample of the second residual signal to a second integrating capacitor during the second set of signals; and sampling the second residual signal via a fourth sampling capacitor during the second set of signals, and providing a second sample of the second residual signal to the second integrating capacitor during the first set of signals. In some embodiments, during the first set of signals and the second set of signals, the process includes: sampling and holding the first analog signal and the second analog signal via a successive approximation register during a first time period; performing a plurality of successive approximations on the first analog signal and the second analog signal during a second time period; and converting a filtered first-stage quantization error from a voltage to a corresponding time during a third time period, and triggering a conversion from the corresponding time to a second digital output signal. In some embodiments, the filtered first-stage quantization error is received at a second stage; the filtered first-stage quantization error is converted to a second digital output signal; and the first digital output signal and the second digital output signal are combined to provide a combined digital output signal.

[0128] This disclosure outlines various embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will recognize that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and adjustments without departing from the spirit and scope of this disclosure.

[0129] 20: Analog / Digital Converter Device 22: Level 1 24: Level Two 26: Digital Filter 28, 30, 32, 42: Conductive paths IN: Input 34: Noise Shift Successive Approximation Register 36: Passive switched capacitor integrator 38: Voltage / Time Converter 40: Time / Digital Converter 44, DOUT: Output terminal 50: Level 1 52: Adder 54: Passive switched capacitor integrator 56: Gain Stage g: Gain factor q1(z): Quantization error 58: Comparator 60: Digital-to-Analog Converter 62, X(z): Input terminal 64, 66, 68: Output terminals VRES(z): Residual signal 70: Gain Stage a: Gain factor 72: Adder 74,Z-1: Delay 76: Feedback signal (1-a)z-1: function 78: Conductive path 80: Passive switched capacitor integrator 82: Sampling capacitor 84: Integrating Capacitor 86,88,90,92: Switches phi1, phi2: Switches Cs, Cint: Capacitors Vin: Input signal Vout: Output signal 100: Level 2 102: Input terminal 104: Output terminal 106: Voltage / Time Converter 108: Time / Digital Converter 110: Conductive path 112,q2(z): Quantization error 120: Voltage / Time Converter 122: Zero-crossing detector AVDD: Analog power supply voltage 124: Discharge Current Source IDIS: Discharge Current 126: Discharge switch φDIS: Switch signal 128: Input terminal VRESP: High Residual Voltage 130: Input terminal VRESM: Low residual voltage 132: Output Tp: Discharge pulse 140: Time / Digital Converter 142a, 142b, 142n: Delay units D1, D2, DN: Delayed signal td: Signal delay time 144a, 144b, 144n: Type D flip-flops D: Data Input Clk: Clock Input Q: Output Q1, Q2, QN: Output terminals 146a, 146b, 146n: Output terminals 148: Conductive path 150: Input terminal 160: Digital Filter 162: Adder 164, Z-1: Delay 166,1-(1-a)Z-1: Function 168: Input terminal 170: Input terminal 172: Output terminal Y1(z), Y2(z), Yo(z): Output signals 180: Analog / Digital Converter Device 182, 184: Power spectral density 186: x-axis 188: y-axis 200: Noise Shift Successive Approximation Register 202: Sample and Hold Circuit 204: Passive switched capacitor integrator 206: Comparator 208: Successive Approximation Register Logic 210a, 210b: Capacitors 212a, 212b: Switches 214, 216: Residual voltage conductors 218: Conductive path 220: Conductive path 222a, 222b: Switches 224, 226: Conductive paths 228, 230, 232, 234: Differential input paths 236, 238, 240, 242, 244, 246: Capacitors VIP, VIM: Analog Input Voltage VIM: Analog Input Voltage VCM: Common-mode voltage VREFP: High Reference Voltage VREFM: Low reference voltage RESP, RESM: Differential Residual Voltage PHI_1, PHI_1E, PHI_2, PHI_3, PHI_R1, PHI_R2: Clock signals 1C, 2C, 4C, 8C, 2NC: Capacitors 260: Time Series Diagram 266,270,278,284,290,294: Clock signal 268,272,298,300,280,306,286,310,292,316: High voltage level 276,304,274,302,282,308,288,312,314,296: Low voltage level 262, 264: Clock signal 330: Level Two 224,226,338,346,348,350,352,354: Conductive paths 228, 230: Differential Input Path 332: Zero-crossing detector 334: Time / Digital Converter 336: Output register 340: Time / Digital Converter Logic 342: Encoder Logic 344: Latch Array 356, DOUT: Output path 370, 372, 374, 376, 378, 380, 382: Operations

Claims

1. An analog-to-digital converter device, comprising: A first stage having a first input terminal for receiving a first analog input signal and an output terminal for transmitting a first digital output signal based on the first analog input signal, the first stage including a successive approximation register for receiving the first analog input signal and performing a plurality of successive approximations on the first analog input signal to provide the first digital output signal, the successive approximation register including a passive switched-capacitor integrator that filters out low-frequency white noise and integrates a first residual signal based on the comparison of the successive approximations of the first analog input signal with the first analog input signal to generate a first-level quantization error; a second stage receiving the first-level quantization error and converting the first-level quantization error into a second digital output signal; and a digital filter combining the first digital output signal and the second digital output signal to provide a combined digital output signal. The passive switched-capacitor integrator includes a first sampling capacitor and a second sampling capacitor; wherein the first sampling capacitor is configured to sample the first residual signal during a first set of signals and provide a first sample of the first residual signal to the first integrating capacitor during a second set of signals, the second set of signals being different from and alternating with the first set of signals; and wherein the second sampling capacitor is configured to sample the first residual signal during the second set of signals and provide a second sample of the first residual signal to the first integrating capacitor during the first set of signals.

2. The analog-to-digital converter device as claimed in claim 1, wherein the successive approximation register generates an analog signal based on the successive approximations controlled by the successive approximation register, and compares the analog signal with the first analog input signal to generate the first residual signal, wherein the first stage includes a second input receiving a second analog input signal and the successive approximation register sampling and holding the first analog input signal and the second analog input signal.

3. The analog-to-digital converter device as claimed in claim 1, wherein the passive switched-capacitor integrator further includes a third sampling capacitor and a fourth sampling capacitor, the third sampling capacitor being configured to sample a second residual signal during the first set of signals and provide a first sample of the second residual signal to a second integrating capacitor during the second set of signals; and the fourth sampling capacitor being configured to sample the second residual signal during the second set of signals and provide a second sample of the second residual signal to the second integrating capacitor during the first set of signals.

4. The analog-to-digital converter device as claimed in claim 3, wherein the second stage receives an integrated first residual voltage from the first integrating capacitor and an integrated second residual voltage from the second integrating capacitor; wherein the second stage includes a voltage-to-time converter that receives the integrated first residual voltage from the first integrating capacitor and the integrated second residual voltage from the second integrating capacitor; wherein the voltage-to-time converter includes a zero-crossing detector that receives the integrated first residual voltage from the first integrating capacitor and the integrated second residual voltage from the second integrating capacitor; wherein the second stage includes a time-to-digital converter connected to the voltage-to-time converter, the time-to-digital converter being configured to provide the second digital output signal.

5. An analog-to-digital converter device, comprising: A first stage has a first input terminal for receiving a first analog signal, a second input terminal for receiving a second analog signal, and an output terminal for transmitting a first digital output signal based on the first analog signal and the second analog signal. The first stage includes a successive approximation register that performs a complex number of successive approximations on the first analog signal and the second analog signal to provide the first digital output signal. The successive approximation register includes a passive switched-capacitor integrator that integrates a first residual signal based on the first analog signal and a second residual signal based on the second analog signal to provide a first-stage quantization error. The passive switched-capacitor integrator includes a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, and a fourth sampling capacitor. The first sampling capacitor is configured to sample the first residual signal during a first set of signals and provide a first sample of the first residual signal to a first integrating capacitor during a second set of signals, the second set of signals being different from and alternating with the first set of signals; the second sampling capacitor is configured to sample the first residual signal in the second set of signals and provide a second sample of the first residual signal to the first integrating capacitor during the first set of signals; the third sampling capacitor is configured to sample the second residual signal during the first set of signals and provide a first sample of the second residual signal to a second integrating capacitor during the second set of signals; and the fourth sampling capacitor is configured to sample the second residual signal during the second set of signals and provide a second sample of the second residual signal to the second integrating capacitor during the first set of signals.

6. The analog-to-digital converter device as claimed in claim 5, wherein during the first set of signals and the second set of signals, the successive approximation register is configured to sample and hold the first analog signal and the second analog signal during a first pulse, perform a plurality of successive approximations on the first analog signal and the second analog signal during a second pulse, and convert the first-stage quantization error from a voltage to a corresponding time during a third pulse, and trigger a conversion from the corresponding time to the second digital output signal.

7. The analog-to-digital converter device as described in claim 5, comprising: A second stage receives the first-stage quantization error and converts it into a second digital output signal. The second stage includes a voltage-to-time converter connected to a time-to-digital converter. The voltage-to-time converter includes a zero-crossing detector that receives an integrated first residual voltage from a first integrating capacitor and an integrated second residual voltage from a second integrating capacitor. The time-to-digital converter generates the second digital output signal. A digital filter combines the first and second digital output signals to provide a combined digital output signal, wherein the digital filter reduces or eliminates the first-stage quantization error.

8. A method for converting an analog signal into a digital signal, applicable to an analog-to-digital converter device, the method comprising: A first analog signal is received at a first input of a successive approximation register; A second analog signal is received at a second input of the successive approximation register; a complex number of successive approximations are performed on the first analog signal and the second analog signal using the successive approximation register; a first digital output signal is generated based on the successive approximations of the first analog signal and the second analog signal using the successive approximation register; a first residual signal based on the successive approximations of the first analog signal is integrated using a passive switched-capacitor integrator; a second residual signal based on the successive approximations of the second analog signal is integrated using the passive switched-capacitor integrator; and a filtered first-level quantization error is generated based on the integration of the first residual signal and the second residual signal, wherein the operation of integrating the first residual signal includes: During a first set of signals, the first residual signal is sampled by a first sampling capacitor, and a first sample of the first residual signal is provided to a first integrating capacitor during a second set of signals, the second set of signals being different from and alternating with the first set of signals; and during the second set of signals, the first residual signal is sampled by a second sampling capacitor, and a second sample of the first residual signal is provided to the first integrating capacitor during the first set of signals.

9. The method as described in claim 8, wherein the operation of integrating the second residual signal includes: During the first set of signals, the second residual signal is sampled by a third sampling capacitor, and a first sample of the second residual signal is provided to a second integrating capacitor during the second set of signals; and during the second set of signals, the second residual signal is sampled by a fourth sampling capacitor, and a second sample of the second residual signal is provided to the second integrating capacitor during the first set of signals.

10. The method as described in claim 9, comprising the following during the first set of signals and the second set of signals: During a first time period, the first analog signal and the second analog signal are sampled and held by the successive approximation register; During a second time period, a complex number of successive approximations are performed on the first analog signal and the second analog signal; and during a third time period, the filtered first-level quantization error is converted from a voltage to a corresponding time, and a conversion from the corresponding time to a second digital output signal is triggered.

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