Semiconductor device and method of manufacturing the same

Abstract

One embodiment of this disclosure relates to a semiconductor device, the semiconductor device comprising a substrate and an epitaxial layer disposed on the substrate. The epitaxial layer has an active region and an insulating region adjacent to the active region and includes a buffer layer disposed on the substrate and doped with carbon, a channel layer disposed on the buffer layer, and a barrier layer disposed on the channel layer. The semiconductor device further includes a gate disposed on the epitaxial layer and located within the active region, a source and a drain respectively disposed on opposite sides of the gate and located within the active region, and an insulating structure penetrating the barrier layer and the channel layer and located within the insulating region. This disclosure further provides a method for manufacturing the semiconductor device.

Claims

1. A semiconductor device, comprising: One substrate; An epitaxial layer is disposed on the substrate, having an active region and an insulating region adjacent to the active region, and the epitaxial layer includes: a buffer layer disposed on the substrate and doped with carbon; and a channel layer disposed on the buffer layer. The device includes a barrier layer disposed on the channel layer; a gate disposed on the epitaxial layer and located within the active region; a source and a drain disposed on opposite sides of the gate and located within the active region; and an insulating structure penetrating the barrier layer and the channel layer and located within the insulating region, wherein the insulating structure includes a dielectric material having a refractive index (RI) greater than about 1.

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2. The semiconductor device as claimed in claim 1, wherein a bottom surface of the insulating structure and a top surface of the buffer layer are coplanar.

3. The semiconductor device as claimed in claim 1, wherein a bottom surface of the insulating structure is lower than a top surface of the buffer layer.

4. The semiconductor device as claimed in claim 1, wherein the insulating structure is further embedded in the buffer layer.

5. The semiconductor device as claimed in claim 1, wherein a bottom surface of the insulating structure is higher than a bottom surface of the buffer layer.

6. The semiconductor device as claimed in claim 1, wherein the insulating structure has a depth between about 206 nm and 925 nm.

7. The semiconductor device as claimed in claim 1, wherein the buffer layer comprises a carbon-doped gallium nitride (C-GaN) layer.

8. The semiconductor device as claimed in claim 1, wherein the channel layer includes an undoped gallium nitride (u-GaN) layer.

9. The semiconductor device as claimed in claim 1, wherein the barrier layer comprises an aluminum gallium nitride (AlxGa1-xN) layer, wherein 0 < x < 1.

10. The semiconductor device as claimed in claim 1, wherein the substrate comprises a silicon substrate or a QST substrate.

11. The semiconductor device as claimed in claim 1, wherein the epitaxial layer further comprises: A seed layer is disposed on the substrate; And a superlattice structure is disposed between the seed layer and the buffer layer.

12. A method for manufacturing a semiconductor device, comprising: Provide a substrate; An epitaxial layer is formed on the substrate, wherein the epitaxial layer has an active region and an insulating region adjacent to the active region, and includes: a buffer layer disposed on the substrate and doped with carbon; and a channel layer disposed on the buffer layer. A barrier layer is disposed on the channel layer; an insulating structure is formed through the barrier layer and the channel layer and located within the insulating region, wherein the insulating structure includes a dielectric material having a refractive index (RI) greater than about 1.5; a gate is formed on the epitaxial layer and located within the active region; and a source and a drain are respectively formed on opposite sides of the gate and located within the active region.

13. A method for manufacturing a semiconductor device as described in claim 12, wherein the step of forming the insulating structure includes: An etching process is performed to form a groove that penetrates the barrier layer and the channel layer; And perform a deposition process to form the insulating structure to fill the groove.

14. A method of manufacturing a semiconductor device as claimed in claim 13, wherein a bottom surface of the groove and a top surface of the buffer layer are coplanar.

15. A method of manufacturing a semiconductor device as claimed in claim 13, wherein a bottom surface of the groove is lower than a top surface of the buffer layer.

16. A method of manufacturing a semiconductor device as claimed in claim 13, wherein the etching process includes plasma etching.

17. A method for manufacturing a semiconductor device as claimed in claim 13, wherein the deposition process includes plasma-enhanced chemical vapor deposition (PECVD).

18. A method of manufacturing a semiconductor device as claimed in claim 13, wherein a bottom surface of the groove has an average roughness (Ra) of less than 1.5 nm.

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