Complementary field effect transistor

Abstract

A complementary field-effect transistor includes: a first source / drain region of a first conductivity type; an insulating layer located on the first source / drain region; a second source / drain region of a second conductivity type located on the insulating layer, the second conductivity type being different from the first conductivity type; a vertical connection structure extending through the insulating layer and electrically connecting the first and second source / drain regions, the first and second source / drain regions being used to receive the same first reference voltage; a first channel region corresponding to the first source / drain region; a second channel region corresponding to the second source / drain region; and a gate structure shared by the first and second channel regions and at least partially surrounding the first and second channel regions, the gate structure being used to receive a second reference voltage, the second reference voltage being different from the first reference voltage.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] Advances in integrated circuit (IC) technology have enabled devices to be smaller, consume less power, have more functions, and be faster. The demand for more functions in modern devices has led to greater device complexity and has posed challenges to continued miniaturization. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," "above," "on," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] Embodiments relate to decoupling capacitor (DCAP) cells and CFET structures for providing capacitance to other circuitry or circuitry elements useful to the DCAP cells and / or capacitor devices. Embodiments may provide one or more of high capacitance, small footprint (e.g., cell area or die area), and / or simple wiring (e.g., in-cell wiring). Embodiments may employ n-type metal oxide semiconductor (NMOS) transistors and / or p-type metal oxide semiconductor (PMOS) transistors to provide capacitance while helping to minimize or avoid excessive leakage (e.g., gate oxide leakage or well leakage).

[0008] In some embodiments, the CFET is used as a capacitor, for example, a decoupling capacitor. In some embodiments, both the NMOS and PMOS transistors of the CFET are used to provide capacitance. In some embodiments, some portions of one of the transistors (e.g., an NMOS transistor (or a PMOS transistor)) are omitted, while other portions of the transistor are retained to provide capacitance for the capacitor.

[0009] In some embodiments, the CFET includes vertically arranged NMOS transistors and PMOS transistors, with one transistor stacked on top of the other. In some embodiments, a PMOS transistor is formed on a substrate, and an NMOS transistor is formed on the PMOS transistor. In some embodiments, an NMOS transistor is formed on a substrate, and a PMOS transistor is formed on the NMOS transistor. Embodiments are not limited to a specific stacking order. In some embodiments, forming a CFET includes forming transistors one after another sequentially, while in other embodiments, forming a CFET includes simultaneously forming one or more features of two transistors. In some embodiments, the NMOS transistor is wellless.

[0010] Figure 1 is a schematic diagram of a decoupling capacitor (DCAP) unit 100 according to some embodiments.

[0011] In some embodiments, the DCAP unit 100 corresponds to a decoupling circuit included in an integrated circuit device comprising a plurality of units. In Figure 1, the DCAP unit 100 according to some embodiments includes, for example, four CFET devices 100a-100d. In other embodiments, the number of CFET devices varies, for example, one, two, three, or more than four. The first CFET device 100a includes a first PMOS transistor P01 and a first NMOS transistor N01 having a common gate G01. The second to fourth CFET devices 100b-100d also include NMOS transistors and PMOS transistors having corresponding common gates, respectively. The source / drain (s / d) region P01s / d of the first PMOS transistor P01 and the s / d region N01s / d of the first NMOS transistor N01 are supplied with a first reference voltage, such as a constant voltage, such as VDD, while the common gate G01 is supplied with a second reference voltage different from the first reference voltage, such as VSS. This configuration effectively reverse-bias the NMOS transistor N01. The second to fourth CFET devices 100b-100d are coupled in parallel with the first CFET device 100a, therefore the NMOS transistors of the second to fourth CFET devices 100b-100d are also reverse-biased. As described in further detail below with reference to Figures 2A to 2D, the DCAP cell 100 used to reverse-bias the NMOS transistor provides additional capacitance compared to a DCAP cell using CFETs. This DCAP cell uses only one transistor (e.g., a PMOS transistor) per CFET to provide capacitance, while maintaining low gate leakage across the gate oxide layer in the NMOS transistor. Furthermore, the increased capacitance provided by the DCAP cell 100 is achieved without increasing the cell size compared to a DCAP cell using CFETs, as the DCAP cell uses only one transistor (e.g., a PMOS transistor) per CFET to provide capacitance. In some embodiments, the DCAP cell 100 is implemented using a split-gate configuration, which uses reverse charge on the channel to increase capacitance.

[0012] Figure 2A is a cross-sectional view of the structure of CFET 200 according to some embodiments. Figure 2B is a cross-sectional view along line I-I' in Figure 2A. Figure 2C is a cross-sectional view along line II-II' in Figure 2A.

[0013] In Figure 2A, the CFET 200 according to some embodiments includes a first transistor 200a (e.g., a PMOS transistor on substrate 210) and a second transistor 200b (e.g., an NMOS transistor on the first transistor 200a) arranged vertically, such that the first transistor 200a is located between substrate 210 and the second transistor 200b relative to the Z-axis direction (it should be understood that the positioning of the PMOS and NMOS transistors is flexible, and the description of the PMOS transistor being located between substrate 210 and the NMOS transistor also applies to the CFET 200 including the NMOS transistor located between substrate 210 and the PMOS transistor). In some embodiments, the CFET 200 serves as a CFET decoupling capacitor device and corresponds to any of the CFET devices 100a to 100d in Figure 1.

[0014] In Figure 2A, the CFET 200 includes a pair of first conductive structures 214 laterally spaced along the X-axis on a substrate 210, a pair of first source / drain structures 218 (e.g., p-type epitaxial (PEPI) structures or n-type EPI (NEPI) structures) on the respective first conductive structures 214, a pair of insulating structures 222 on the respective first source / drain structures 218, a pair of second source / drain structures 226 (e.g., NEPI or PEPI structures) on the respective insulating structures 222, and a pair of second conductive structures 230 on the respective second source / drain structures 226. It should be understood that, unless otherwise stated or obvious, references to insulators, insulating structures, etc., encompass the use of dielectric materials. The CFET 200 also includes a pair of vertical electrical connections 234 that extend along the Z-axis between and connect the respective first source / drain structures 218 and second conductive structures 230. The CFET 200 also includes: a first channel region 238 extending along the X-axis between the first source / drain structures 218; and a second channel region 242 extending along the X-axis between the second source / drain structures 226. A gate structure 246 extends along the Z-axis and at least partially surrounds the first channel region 238 and the second channel region 242. In some embodiments, the gate structure 246 completely surrounds each of the first channel region 238 and the second channel region 242. The gate structure 246 is located relative to the X-axis between one of the pair of first conductive structures 214 and between one of the pair of second conductive structures 230. Gate structure 246 is at least partially covered by gate isolation layer 250 (e.g., gate oxide layer). Gate isolation layer 250 is located between gate structure 246 and first channel region 238 and second channel region 242. Insulating structure 254 surrounds gate structure 246. In some embodiments, insulating structure 254 includes silicon oxide, silicon nitride, SiOCN, etc. In some embodiments, insulating structure 254 is formed by, for example, deposition or oxidation processes. In some embodiments, insulating structure 254 and insulating structure 222 are integral. In other embodiments, insulating structure 254 and insulating structure 222 are formed separately and / or formed of different insulating materials.

[0015] More specifically, in Figure 2A, the first conductive structure 214 is a conductive structure located between the substrate 210 and the CFET 200. This conductive structure is formed in the BMD layer (which may be referred to as the bottom metal diffusion layer or the top metal diffusion layer) on the substrate 210 or on wiring (not shown) on the substrate 210. The first conductive structure 214 may be referred to as a BMD structure.

[0016] In some embodiments, substrate 210 is a semiconductor substrate. In some embodiments, substrate 210 is a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, etc. In some embodiments, substrate 210 includes silicon and another elemental semiconductor, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. In some embodiments, substrate 210 is a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator substrate. In some embodiments, substrate 210 includes a doped epitaxial layer, a gradient semiconductor layer and / or a semiconductor layer covering another different type of semiconductor layer, such as a silicon layer on a silicon-germanium layer. In some embodiments, substrate 210 includes doped regions, such as p-wells, n-wells or both. In some embodiments, the substrate 210 is a dielectric substrate, a sapphire substrate, or the like.

[0017] The first conductive structure 214 forms the source / drain contact of the lower transistor (e.g., the first transistor 200a) in the CFET 200. The first conductive structure 214 includes one or more conductive materials, such as metals, metal compounds, doped semiconductors, etc. In some embodiments, the first conductive structure 214 includes one or more metals, such as Al, Co, Cu, Ru, W, etc. In some embodiments, the first conductive structure 214 includes one or more metal compounds, such as AlCu, NiSix, TaN, TiN, TiSix, WTiN, etc. In some embodiments, the first conductive structure 214 includes one or more doped semiconductors, such as doped Si, doped SiGe, etc.

[0018] In some embodiments, the first conductive structure 214 is located on a conductive segment (e.g., a metal segment) (not shown) in a first conductive layer (e.g., a metal layer), which may be referred to as BMO, and is located below the CFET 200. In some embodiments, the first conductive layer BMO is located between the CFET 200 and the substrate 210. In other embodiments, the first conductive layer BMO is a back-side conductive layer located on the back side of the substrate 210, such that the substrate 210 is located between the CFET 200 and the first conductive layer BMO. The conductive layers (e.g., metal layers) located below the first conductive layer BMO are referred to as BM1, BM2, etc., wherein BM1 is located between BM2 and BM0. Through-hole structures (not shown) extend between the conductive layers to couple the conductive segment, wherein BV0 is a bottom through-hole layer or a back-side through-hole layer disposed between the BMO layer and the BM1 layer and electrically coupling the BMO layer and the BM1 layer, and the through-hole layers BV1, BV2, etc. are used to couple the lower conductive layer.

[0019] A first source / drain structure 218 is located on and electrically contacts a corresponding first conductive structure 214. The first first source / drain structure 218 is located on a first side 246-1 of the gate structure 246, while the second first source / drain structure 218 is located on a second side 246-2 of the gate structure 246. In some embodiments, the PEPI structure includes one or more of GeSnB, SiGeB, etc. In some embodiments, the NEPI structure includes one or more of AlGaAs, GaAs, GaAsP, Ge, Si, SiGe, SiP, etc. In some embodiments, the first source / drain structure 218 is formed by epitaxial growth from the first channel region 238. In other embodiments, the first source / drain structure 218 is formed by epitaxial growth from another portion of the first transistor 200a or from an intermediate or sacrificial structure. Epitaxial processes that can be used to form the first source / drain structure 218 include, for example, chemical vapor deposition (CVD), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), selective epitaxial growth (SEG), vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In some embodiments, the PEPI structure is in-situ doped during the epitaxial process by introducing a p-type dopant such as boron or BF2. In some embodiments, the NEPI structure is in-situ doped during the epitaxial process by introducing an n-type dopant such as phosphorus or arsenic. In other embodiments, a planting process is performed to dope the first source / drain structure 218.

[0020] A first channel region 238 extends between corresponding first source / drain structures 218. In some embodiments, the first channel region 238 is an active region including nanostructures (such as nanosheets or nanowires). In Figure 2A, the first transistor 200a includes two first channel regions 238. In other embodiments, only one first channel region 238 is provided, while in other embodiments, more than two first channel regions 238 are provided. In some embodiments, each first channel region 238 includes a plurality of nanostructures. In some embodiments, the nanostructures are silicon nanostructures, such as silicon nanosheets. In some embodiments, forming a silicon nanostructure includes forming alternating SiGe layers and Si layers in a vertical stack, for example, by sequentially forming SiGe layers and Si layers using an epitaxial process (such as one of the epitaxial processes described above), and then selectively removing the SiGe layers (e.g., using selective etching) such that the Si layers remain as the first channel regions 238.

[0021] In some embodiments, the insulating structure 222 on the first source / drain structure 218 includes a middle dielectric isolation (MDI) layer. The insulating structure 222 and / or the MDI layer isolates the active structure of the second transistor 200b from the active structure of the first transistor 200a. In some embodiments, the insulating structure 222 includes silicon oxide, silicon nitride, SiOCN, etc. In some embodiments, the insulating structure 222 is formed by, for example, a deposition process or an oxidation process. In some embodiments, the second transistor 200b is formed on a substrate different from the substrate on which the first transistor 200a is formed, and the substrates are then bonded together, with the MDI layer being an exposed layer of one of the substrates, such that the MDI layer is located at the interface of the substrates after the substrates are bonded.

[0022] The second source / drain structure 226 is located above the insulating structure 222 and is in electrical contact with the corresponding overlying second conductive structure 230. The first second source / drain structure 226 is located on the first side of the gate structure 246, and the second second source / drain structure 226 is located on the second side of the gate structure 246. In some embodiments, the PEPI structure includes one or more of GeSnB, SiGeB, etc. In some embodiments, the NEPI structure includes one or more of AlGaAs, GaAs, GaAsP, Ge, Si, SiGe, SiP, etc. In some embodiments, the second source / drain structure 226 is formed by epitaxial growth of the second channel region 242. In other embodiments, the second source / drain structure 226 is formed by epitaxial growth from another portion of the second transistor 200b or from an intermediate or sacrificial structure. The epitaxial process that can be used to form the second source / drain structure 226 includes the process described above for forming the first source / drain structure 218. In some embodiments, the PEPI structure is in-situ doped during the epitaxial process by introducing a p-type dopant such as boron or BF2. In some embodiments, the NEPI structure is in-situ doped during the epitaxial process by introducing an n-type dopant such as phosphorus or arsenic. In other embodiments, a planting process is performed to dope the second source / drain structure 226.

[0023] The second channel region 242 extends between the second source / drain structures 226. In some embodiments, the second channel region 242 is an active region including nanostructures (such as nanosheets or nanowires). In Figure 2A, the second transistor 200b includes two second channel regions 242. In other embodiments, only one second channel region 242 is provided, while in other embodiments, more than two second channel regions 242 are provided. In Figure 2A, the number of first channel regions 238 is equal to the number of second channel regions 242. In other embodiments, the number of first channel regions 238 is different from the number of second channel regions 242, and / or the first channel regions 238 have different dimensions relative to the second channel regions 242. In some embodiments, each second channel region 242 includes a plurality of nanostructures. In some embodiments, the nanostructures are silicon nanostructures, such as silicon nanosheets, etc. In some embodiments, forming a silicon nanostructure includes forming alternating SiGe and Si layers in a vertical stack, for example by sequentially forming SiGe and Si layers using an epitaxial process (e.g., one of the epitaxial processes described above), and then selectively removing the SiGe layer (e.g., using selective etching) such that the Si layer remains as the second channel region 242.

[0024] The second conductive structure 230 forms the source / drain contact of the transistor (i.e., the second transistor 200b) in the CFET 200. The second conductive structure 230 is a conductive structure formed in the MD layer (which may be referred to as a metal-on-diffusion layer). The second conductive structure 230 may be referred to as an MD structure. The second conductive structure 230 is in electrical contact with the second source / drain structure 226. The second conductive structure 230 includes one or more conductive materials, such as metals, metal compounds, doped semiconductors, etc. In some embodiments, the second conductive structure 230 includes one or more metals, such as Al, Co, Cu, Ru, W, etc. In some embodiments, the second conductive structure 230 includes one or more metal compounds, such as AlCu, NiSix, TaN, TiN, TiSix, WTiN, etc. In some embodiments, the second conductive structure 230 includes one or more doped semiconductors, such as doped Si, doped SiGe, etc. In some embodiments, the second conductive structure 230 is formed of the same material as the first conductive structure 214. In other embodiments, the second conductive structure 230 is formed of a different material than the first conductive structure 214.

[0025] The vertical electrical connection 234 is formed of a conductive material that extends to connect the respective first source / drain structure 218 and the second conductive structure 230. The first vertical electrical connection 234 is located on a first side of the gate structure 246, while the second vertical electrical connection 234 is located on a second side of the gate structure 246. The vertical electrical connection 234 is in electrical contact with the second conductive structure 230. In some embodiments, the vertical electrical connection 234 is formed before the second conductive structure 230, and the top surface 234t of the vertical electrical connection 234 is exposed to make electrical contact with the bottom surface of the second conductive structure 230. In other embodiments, the vertical electrical connection 234 is formed to penetrate the second conductive structure 230 and makes electrical contact with the second conductive structure while penetrating the second conductive structure 230. The vertical electrical connection 234 penetrates the second source / drain structure 226. In some embodiments, the sidewalls 234s of the vertical electrical connection 234 are in electrical contact with the second source / drain structure 226, wherein the vertical electrical connection 234 passes through the second source / drain structure 226. In other embodiments, the sidewalls 234s are covered with an insulating layer or material, and the vertical electrical connection 234 is electrically connected to the second source / drain structure 226 via the second conductive structure 230. In Figure 2A, the vertical electrical connection 234 extends partially into the first source / drain structure 218. In some embodiments, the vertical electrical connection 234 extends through less than half the height of the first source / drain structure 218. In other embodiments, the vertical electrical connection 234 extends completely through the first source / drain structure 218 to connect to the first conductive structure 214.

[0026] In Figure 2A, CFET 200 is used as a capacitor, and both the first source / drain structure 218 and the second source / drain structure 226 are supplied with the same first reference voltage. Other CFETs that are not used as capacitors (e.g., in a logic gate adjacent to CFET 200) do not include the vertical electrical connection 234 connected to the first source / drain structure 218. For example, a cell layout according to some embodiments includes a first cell and a second cell adjacent to the first cell. The first cell is a DCAP cell, including one or more CFETs used as capacitors, and includes a vertical electrical connection 234 connecting all sources and drains of PMOS and NMOS transistors to the same reference voltage (e.g., VDD). The second cell is a logic cell, including CFETs without the vertical electrical connection 234.

[0027] Figure 2B is a cross-sectional view along line I-I' in Figure 2A, corresponding to the location of the vertical electrical connection 234 on the first side of the gate structure 246. In Figure 2B, the vertical electrical connection 234 penetrates the second source / drain structure 226 and extends partially into the first source / drain structure 218. The vertical electrical connection 234 electrically connects the second conductive structure 230 (e.g., MD contact) to the first source / drain structure 218, such that the second source / drain structure 226 and the first source / drain structure 218 are at the same voltage potential, e.g., VDD.

[0028] In Figure 2B, the center of the vertical electrical connection 234 is offset relative to the center line c / l of the first source / drain structure 218 and the second source / drain structure 226. In other embodiments, the vertical electrical connection 234 is substantially centered relative to the center line c / l of the first source / drain structure 218 and the second source / drain structure 226. In Figure 2B, the insulating structure 222 is shown extending from the top of the second source / drain structure 226 to the bottom of the first source / drain structure 218, and laterally between the first source / drain structure 218 and the second source / drain structure 226. In some embodiments, the insulating structure 222 is a monolithic structure. In other embodiments, the insulating structure 222 is formed by two or more insulating structures, such as an MDI layer between the first source / drain structure 218 and the second source / drain structure 226, and additional insulating structures above and below the MDI layer.

[0029] Figure 2C is a cross-sectional view along line II-II' in Figure 2A, corresponding to the location of gate structure 246. In some embodiments, gate structure 246 is a metal gate comprising one or more metal layers. In other embodiments, the gate structure comprises a conductive material, such as a semiconductor or doped semiconductor, such as polysilicon. In some embodiments, gate structure 246 is formed after removing intermediate or sacrificial structures (e.g., SiGe layers) between the first channel regions 238 and between the second channel regions 242. In some embodiments, gate structure 246 has the same construction or configuration at the first transistor 200a as it does at the second transistor 200b. In other embodiments, the structure or material of gate structure 246 varies along the height of the gate structure, for example, such that the material and / or layers of gate structure 246 are different in the first transistor 200a than in the second transistor 200b. Gate insulation layer 250 is located on the outer surface of gate structure 246 at the first channel region 238 and the second channel region 242, thereby isolating gate structure 246 from each of the first channel region 238 and the second channel region 242. Figure 2C shows gate insulation layer 250 extending along the surface of gate structure 246 in regions located away from the first and second channel regions 238, 242, but it should be understood that other insulation structures may be used instead of gate insulation layer 250 in regions located away from the first channel region 238 and the second channel region 242.

[0030] Although not shown in Figure 2A, in some embodiments, conductive segments (e.g., metal segments) in the first conductive layer (e.g., a metal layer) (may be referred to as M0) are located on the second conductive structure 230. Conductive layers (e.g., metal layers) located above the first conductive layer M0 are referred to as M1, M2, etc., wherein M1 is located between M2 and M0. Through-hole structures (not shown) extend between the conductive layers to couple the conductive segments, wherein V0 is a through-hole layer disposed between the M0 layer and the M1 layer and electrically couples the M0 layer and the M1 layer, and through-hole layers V1, V2, etc. are used to couple the upper conductive layers.

[0031] Additional structures and operations for forming the CFET 200 are described in U.S. Patent No. 10,977,417, U.S. Patent Application Publication No. 2024 / 0222429A1 and U.S. Patent Application Publication No. 2024 / 0341092A1, all of which are incorporated herein by reference.

[0032] In Figures 2A to 2C, a pair of first source / drain structures 218 and a pair of second source / drain structures 226 are each provided with the same first reference voltage or constant voltage by corresponding first conductive structures 214 and second conductive structures 230. In some embodiments, the first reference voltage applied to the first source / drain structures 218 and the second source / drain structures 226 is a first power supply voltage, such as VDD. The gate structure 246 is supplied with a second reference voltage or constant voltage, which is different from the first reference voltage. In some embodiments, the second reference voltage applied to the gate structure 246 is a second power supply voltage, such as VSS. In some embodiments, the CFET 200 is configured such that all four sources and drains of the first transistor 200a and the second transistor 200b are coupled to VDD, and the two gates of the first transistor 200a and the second transistor 200b are coupled to VSS. In some embodiments, the CFET 200 configured in this way improves the dynamic IR voltage drop in the circuit by providing a capacitor between VDD and VSS. In addition, the CFET 200 uses vertical electrical connection 234 to provide internal electrical connections, thus simplifying in-cell wiring compared to devices that use corresponding connections made outside the CFET.

[0033] Figure 2D is a schematic diagram of a CFET 200 demonstrating capacitive features according to some embodiments.

[0034] Referring to Figure 2D, the CFET 200, supplied with first and second reference voltages, provides capacitive characteristics in a plurality of regions. In the example of Figure 2D, the CFET 200 is used to couple all source / drain regions to VDD and to couple the common gate to VSS. Therefore, the CFET 200 is used to reverse bias the NMOS transistor, which helps to provide additional capacitance and helps to keep the gate leakage across the gate oxide layer in the NMOS transistor low. In some embodiments, the NMOS transistor of the CFET 200 has no well, which helps to avoid leakage that would occur when the NMOS transistor has a well and the source and drain of the NMOS transistor are coupled to VDD and the gate is coupled to VSS.

[0035] More specifically, in the 2D figure, the CFET 200 includes a plurality of capacitance features C01 to C12. Capacitance features C01 to C05 can be considered to be primarily associated with the first transistor 200a. Capacitance features C06 to C12 can be considered to be primarily associated with the reverse-biased second transistor 200b.

[0036] Referring to Figure 2D, capacitor feature C01 provides capacitance between the first side of the gate structure 246 and the first conductive structure 214a, and capacitor feature C02 provides capacitance between the second side of the gate structure 246 and the first conductive structure 214b. Capacitor feature C03 represents an oxide capacitor, which is the capacitance between the first channel region 238a and the gate structure 246. Capacitor feature C04 provides capacitance between the first side of the gate structure 246 and the first source / drain structure 218a, and capacitor feature C05 provides capacitance between the second side of the gate structure 246 and the second source / drain structure 218b. Capacitor feature C06 provides capacitance between the first side of the gate structure 246 and the insulating structure 222a, and capacitor feature C07 provides capacitance between the second side of the gate structure 246 and the insulating structure 222b. Capacitor feature C08 provides capacitance between the first side of the gate structure 246 and the first second source / drain structure 226a, and capacitor feature C09 provides capacitance between the second side of the gate structure 246 and the second second source / drain structure 226b. Capacitor feature C10 represents an oxide capacitor, which is the capacitance between the second channel region 242a and the gate structure 246. Capacitor feature C11 provides capacitance between the first side of the gate structure 246 and the second conductive structure 230a, and capacitor feature C12 provides capacitance between the second side of the gate structure 246 and the second conductive structure 230b.

[0037] Compared to a CFET that uses only one transistor (e.g., the first transistor 200a) to provide capacitance, the presence of capacitor features C06 to C12 significantly increases the total capacitance of the CFET 200 in a capacitor configuration. A CFET that uses only one transistor to provide capacitance is not sufficiently used for decoupling purposes. Instead, according to some embodiments, a CFET 200 used as a capacitor can significantly increase the capacitance used for decoupling while occupying the same layout area as a CFET that uses only one transistor to provide capacitance. Therefore, a CFET 200 used as a capacitor can help minimize the layout cell area used for decoupling capacitors.

[0038] Figure 2E is a cross-sectional view of the structure of CFET 200' according to some embodiments. Figure 2F is a cross-sectional view along line III-III' in Figure 2E.

[0039] The features discussed below in conjunction with Figures 2E and 2F generally correspond to the features with corresponding numbers or markings discussed above in conjunction with Figures 2A to 2C. Unless otherwise stated or obvious, the features in Figures 2E to 2F not specifically described below are the same as the corresponding features in Figures 2A to 2C with corresponding numbers or markings.

[0040] In some embodiments, CFET 200' is used to implement DCAP cell 100 using a split-gate configuration that employs reverse charge on the channel to increase capacitance. In Figures 2E and 2F, the common gate of CFET 200 in Figures 2A to 2C is replaced by a split-gate configuration, wherein the first transistor 200a has a gate structure 246a, and the second transistor 200b has a separate gate structure 246b. An insulating structure 258 is located between the gate structure 246a and the gate structure 246b, and isolates the gate structure 246a from the gate structure 246b.

[0041] In some embodiments, the vertical electrical connection 234 electrically connects the second conductive structure 230 to the first source / drain structure 218, and the second source / drain structure 226 and the first source / drain structure 218 are supplied with VDD, while the gate structure 246a of the first transistor 200a and the gate structure 246b of the second transistor 200b are supplied with VSS.

[0042] In Figure 2E, the height of insulating structure 258 (in the Z-axis direction) is less than the height of insulating structure 222. In other embodiments, insulating structure 258 and insulating structure 222 have the same height. In some embodiments, insulating structure 258 and insulating structure 222 are formed using separate processes and / or different materials, while in other embodiments, insulating structure 258 and insulating structure 222 are formed using the same process and / or the same materials. In some embodiments, insulating structure 258 is included in an MDI layer.

[0043] Figure 3 is a schematic diagram of a DCAP unit 300 according to some embodiments.

[0044] In Figure 3, the DCAP unit 300 according to some embodiments includes four CFET devices 300a-300d (for example). In other embodiments, the number of CFET devices is one, two, three, or more than four. The first CFET device 300a includes a first PMOS transistor P01 and a first NMOS transistor device NL01 having a common gate G01. The second to fourth CFET devices 300b-300d also include PMOS transistors and NMOS transistor devices having a common gate, respectively. The source / drain (s / d) region P01s / d of the first PMOS transistor P01 and the contact NL01c of the first NMOS transistor device NL01 are both provided with a first reference voltage, such as a constant voltage, such as VDD, while the common gate G01 is provided with a second reference voltage different from the first reference voltage, such as VSS. The channels of the first to fourth CFET devices 300a-300d are floating. As described in detail below with reference to Figures 4A to 4D, the DCAP cell 300 configured in this way provides additional capacitance compared to a DCAP cell using CFETs, which uses only one transistor (e.g., a PMOS transistor) per CFET to provide capacitance. Furthermore, compared to a DCAP cell using CFETs, the increased capacitance provided by the DCAP cell 300 is achieved without increasing the cell size, as the DCAP cell uses only one transistor (e.g., a PMOS transistor) per CFET to provide capacitance.

[0045] Figure 4A is a cross-sectional view of the structure of a CFET-type structure 400 according to some embodiments. Figure 4B is a cross-sectional view along line I-I' in Figure 4A. Figure 4C is a cross-sectional view along line II-II' in Figure 4A.

[0046] The features discussed below in conjunction with Figures 4A to 4C generally correspond to the features discussed above in conjunction with Figures 2A to 2C, wherein the numbering is increased by 200. In some embodiments, unless otherwise stated or obvious, the features of Figures 4A to 4C not specifically described below are the same as the corresponding features of Figures 2A to 2C.

[0047] In Figure 4A, the NMOS transistor-type structure 400c according to some embodiments does not include the second source / drain structure 226 of Figure 2A. In some embodiments, the CFET-type structure 400 corresponds to any CFET-type device 300a-300d in Figure 3.

[0048] In Figure 4A, the CFET-type structure 400 according to some embodiments includes a vertically arranged PMOS transistor 400a on a substrate 410 and an NMOS transistor-type structure 400c on the PMOS transistor 400a, such that the PMOS transistor 400a is located between the substrate 410 and the NMOS transistor-type structure 400c relative to the Z-axis direction.

[0049] In Figure 4A, the CFET-type structure 400 includes: a pair of first conductive structures 414 laterally spaced along the X-axis on the substrate 410; a pair of first source / drain structures 418 located on the respective first conductive structures 414; a pair of insulating structures 422 located on the respective first source / drain structures 418; a pair of insulating structures 428 located on the respective insulating structures 422; and a pair of second conductive structures 230 located on the respective insulating structures 428. The CFET-type structure 400 also includes a pair of vertical electrical connections 434 extending in the Z-axis direction between the first source / drain structures 418 and the second conductive structures 430 and connecting the respective first source / drain structures 418 and the second conductive structures 430. The CFET-type structure 400 also includes: a first channel region 438 extending along the X-axis between the first source / drain structures 418; and a second channel region 442 extending along the Z-axis between the insulating structures 428. In some embodiments, the second channel region 442 floats by omitting the NEPI (or PEPI) structure. A gate structure 446 extends in the Z-axis direction and at least partially surrounds the first channel region 438 and the second channel region 442. In some embodiments, the gate structure 446 completely surrounds the first channel region 438 and the second channel region 442. The gate structure 446 is located between a pair of first conductive structures 414 and a pair of second conductive structures 430 relative to the X-axis direction. The gate structure 446 is at least partially covered by a gate insulating layer 450 (e.g., a gate oxide). The gate insulating layer 450 is located between the gate structure 446 and the first channel region 438 and the second channel region 442. Figure 4C shows the gate insulating layer 450 extending along the surface of the gate structure 446 in the region outside the first channel region 438 and the second channel region 442; however, it should be understood that other insulating structures may be used instead of the gate insulating layer 450 in the region outside the first channel region 438 and the second channel region 442. An insulating structure 454 surrounds a gate structure 446. In some embodiments, the insulating structure 454 is integral with insulating structures 422 and 428. In other embodiments, the insulating structures 454, 422, and / or 428 are formed separately and / or made of different insulating materials. In some embodiments, the gate structure 446 is replaced by a split-gate structure, such as the split-gate structures described above in conjunction with gate structures 246a and 246b of Figures 2E and 2F.

[0050] The second channel region 442 extends between the insulating structures 428. In some embodiments, the second channel region 442 is an active region including nanostructures (such as nanosheets or nanowires). In Figure 4A, the NMOS transistor-type structure 400c includes two second channel regions 442. In other embodiments, only one second channel region 442 is provided, while in other embodiments, more than two second channel regions 442 are provided. In Figure 4A, the number of first channel regions 438 is equal to the number of second channel regions 442. In other embodiments, the number of first channel regions 438 is different from the number of second channel regions 442, or the first channel regions 438 have different dimensions relative to the second channel regions 442. In some embodiments, each second channel region 442 includes a plurality of nanostructures. In some embodiments, the nanostructures are silicon nanostructures, such as silicon nanosheets, etc. In some embodiments, forming a silicon nanostructure includes forming alternating SiGe and Si layers in a vertical stack, for example by sequentially forming SiGe and Si layers using an epitaxial process (such as one of the epitaxial processes described above), and then selectively removing the SiGe layer (e.g., using selective etching) such that the Si layer remains as the second channel region 442.

[0051] In some embodiments, the insulating structure 428 includes silicon oxide, silicon nitride, SiOCN, etc. In some embodiments, the insulating structure 428 is formed by, for example, a deposition process or an oxidation process.

[0052] The vertical electrical connection 434 is formed of a conductive material that extends through the insulating structure 428 to connect the respective first source / drain structure 418 and the second conductive structure 430. The first vertical electrical connection 434 is located on a first side of the gate structure 446, and the second vertical electrical connection 434 is located on a second side of the gate structure 446. In some embodiments, the vertical electrical connection 434 is formed before the second conductive structure 430. In other embodiments, the vertical electrical connection 434 is formed to penetrate the second conductive structure 430. In Figure 4A, the vertical electrical connection 434 extends partially into the first source / drain structure 418. In other embodiments, the vertical electrical connection 434 extends through the first source / drain structure 418 to connect to the first conductive structure 414. In Figure 4B, the vertical electrical connection 434 penetrates the insulating structure 428 and extends partially into the first source / drain structure 418. The vertical electrical connection 434 electrically connects the second conductive structure 430 to the first source / drain structure 418, such that the second conductive structure 430 and the first source / drain structure 418 are at the same voltage potential, for example, VDD.

[0053] In Figure 4A, the CFET-type structure 400 is used as a capacitor, and the first source / drain structure 418 and the second conductive structure 430 are both supplied with the same first reference voltage. Other CFETs that are not used as capacitors (e.g., in logic gates adjacent to the CFET-type structure 400) do not include the vertical electrical connection 434 connected to the first source / drain structure 418.

[0054] Figure 4D is a schematic diagram of a CFET-type structure 400 demonstrating capacitive features according to some embodiments.

[0055] Referring to Figure 4D, the CFET-type structure 400, supplied with first and second reference voltages, provides capacitive features in a plurality of regions. As described above, in some embodiments, the CFET-type structure 400 is used to couple the source and drain of the PMOS transistor 400a to VDD, the second conductive structure 430 to VDD, and the common gate to VSS. Therefore, the CFET-type structure 400 is used to provide additional capacitance relative to a CFET that uses only a single transistor to provide capacitance, and helps to keep the gate leakage across the gate oxide layer at the second channel region 442 low.

[0056] More specifically, in Figure 4D, the CFET-type structure 400 includes a plurality of capacitor features C01~C07, C11, and C12. Capacitor features C01~C05 can be considered to be primarily associated with the PMOS transistor 400a. Capacitor features C06, C07, C11, and C12 can be considered to be primarily associated with the NMOS transistor-type structure 400c.

[0057] Referring to Figure 4D, capacitor feature C01 provides capacitance between the first side of the gate structure 446 and the first conductive structure 414a, and capacitor feature C02 provides capacitance between the second side of the gate structure 446 and the first conductive structure 414b. Capacitor feature C03 represents an oxide capacitor, which is the capacitance between the first channel region 438a and the gate structure 446. Capacitor feature C04 provides capacitance between the first side of the gate structure 446 and the first first source / drain structure 418a, and capacitor feature C05 provides capacitance between the second side of the gate structure 446 and the second first source / drain structure 418b. Capacitor feature C06 provides capacitance between the first side of the gate structure 446 and the insulating structure 422a, and capacitor feature C07 provides capacitance between the second side of the gate structure 446 and the insulating structure 422b. Capacitor feature C10 represents an oxide capacitor, which is the capacitance between the second channel region 442a and the gate structure 446. Capacitor feature C11 provides capacitance between the first side of the gate structure 446 and the second conductive structure 430a, and capacitor feature C12 provides capacitance between the second side of the gate structure 446 and the second conductive structure 430b.

[0058] The presence of capacitor features C06, C07, C11, and C12 significantly increases the total capacitance of the CFET-type structure 400 with capacitor configuration compared to a CFET that uses only one transistor (e.g., the first transistor 200a) to provide capacitance. A CFET that uses only one transistor to provide capacitance is not sufficiently used for decoupling purposes. Instead, according to some embodiments, the CFET-type structure 400 used as a capacitor can significantly increase the capacitance used for decoupling while occupying the same layout area as a CFET that uses only one transistor to provide capacitance. Therefore, the CFET-type structure 400 used as a capacitor can help minimize the layout cell area used for decoupling capacitors. Furthermore, the CFET-type structure 400 can provide a larger capacitance compared to a CFET that uses only one transistor to provide capacitance, and the manufacturing process is simpler compared to CFET 200 due to the omission of the NEPI (or PEPI) structure.

[0059] Figure 5 is a flowchart of a method 500 for manufacturing a semiconductor device according to some embodiments.

[0060] Method 500 according to some embodiments includes operation 505: forming a source / drain contact structure. In some embodiments, the source / drain contact structure formed in operation 505 is a BMD structure, corresponding to a pair of first conductive structures 214 in Figures 2A to 2D and / or a pair of first conductive structures 414 in Figures 4A to 4D.

[0061] Method 500 includes operation 510: forming a first source / drain structure (e.g., a PEPI (or NEPI) structure) on a source / drain contact structure. In some embodiments, the PEPI (or NEPI) structure formed in operation 510 corresponds to the first source / drain structure 218 of Figures 2A to 2D and / or the first source / drain structure 418 of Figures 4A to 4D.

[0062] Method 500 includes operation 515: forming an insulator on a source / drain contact structure. In some embodiments, the insulator formed in operation 515 corresponds to the insulating structure 222 of Figures 2A to 2D and / or the insulating structure 422 of Figures 4A to 4D.

[0063] Method 500 includes operation 520: forming a second source / drain structure (e.g., an NEPI (or PEPI) structure) on the source / drain contact structure. In some embodiments, the NEPI (or PEPI) structure formed in operation 520 corresponds to the second source / drain structure 226 of Figures 2A to 2D. In modified embodiments, operation 520 is omitted and the NEPI (or PEPI) structure is not formed, for example, as shown in the CFET-type structure 400 of Figures 4A to 4D.

[0064] Method 500 includes operation 525: forming a vertical structure via an insulator to connect the first and second source / drain structures. In some embodiments, the vertical structure formed in operation 525 corresponds to the vertical electrical connection 234 in Figures 2A to 2D. In a modified embodiment, operation 525 forms a vertical structure via an insulator to connect the second conductive structure 430 and the first source / drain structure, thereby forming a vertical structure corresponding to the vertical electrical connection 434 in Figures 4A to 4D.

[0065] The embodiments and modified embodiments described above in conjunction with Figure 5 can be used to form CFET devices and CFET-type devices of the DCAP units 100 and 300 described above in conjunction with Figures 1 and 3.

[0066] Figure 6 is a flowchart of a method 600 for manufacturing a semiconductor device according to some embodiments.

[0067] According to some embodiments, method 600 may be implemented, for example, using EDA system 700 (Figure 7, discussed below) and integrated circuit (IC) manufacturing system 800 (Figure 8, discussed below). Examples of semiconductor devices that can be manufactured according to method 600 include CFET 200 of Figures 2A and 2D.

[0068] In Figure 6, method 600 includes blocks 602 and 604. At block 602, a layout diagram is generated, which, among other things, includes one or more layout diagrams disclosed herein. According to some embodiments, block 602 may be implemented using, for example, an EDA system 700 (Figure 7, discussed below). In some embodiments, block 602 includes generating a shape corresponding to a structure to be represented in the semiconductor diagram.

[0069] At block 604, based on the layout diagram, at least one of the following operations is performed: (A) performing one or more photolithography exposures, or (B) fabricating one or more semiconductor masks, or (C) fabricating one or more components in a layer of an integrated circuit (IC) device (e.g., a semiconductor device). See the discussion in Figure 8 below.

[0070] Figure 7 is a block diagram of an electronic design automation (EDA) system 700 according to some embodiments.

[0071] In some embodiments, the EDA system 700 includes an automatic placement and routing (APR) system. According to one or more embodiments, the design layout diagram layout method described herein can be implemented, for example, using the EDA system 700.

[0072] In some embodiments, the EDA system 700 is a general-purpose computing device, including a hardware processor 702 and a non-transitory computer-readable storage medium 704. Among other things, the computer-readable storage medium 704 is encoded with (i.e., stored) computer program code 706, i.e., a set of executable instructions. The processor 702 executes the instructions 706 (at least partially) to represent an EDA tool that implements part or all of the methods described herein according to one or more embodiments (hereinafter referred to as the processes and / or methods).

[0073] Processor 702 is electrically coupled to computer-readable storage medium 704 via bus 708. Processor 702 is also electrically coupled to I / O interface 710 via bus 708. Network interface 712 is also electrically connected to processor 702 via bus 708. Network interface 712 is connected to network 714, enabling processor 702 and computer-readable storage medium 704 to be connected to external components via network 714. Processor 702 is used to execute computer program code 706 encoded in computer-readable storage medium 704 to enable EDA system 700 to perform part or all of the process and / or method. In one or more embodiments, processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0074] In one or more embodiments, the computer-readable storage medium 704 is an electronic system, a magnetic system, an optical system, an electromagnetic system, an infrared system, and / or a semiconductor system (or device or apparatus). For example, the computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 704 includes compact disk-read-only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disc (DVD).

[0075] In one or more embodiments, computer-readable storage medium 704 stores computer program code 706 for enabling EDA system 700 (where such execution (at least partially) represents EDA tools) to perform part or all of the process and / or method. In one or more embodiments, computer-readable storage medium 704 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, computer-readable storage medium 704 stores a standard cell library 707, which includes the standard cells disclosed herein. In one or more embodiments, computer-readable storage medium 704 stores one or more layout figures 709 corresponding to one or more layouts disclosed herein.

[0076] The EDA system 700 includes an I / O interface 710. The I / O interface 710 is coupled to external circuitry. In one or more embodiments, the I / O interface 710 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to the processor 702.

[0077] The EDA system 700 also includes a network interface 712 coupled to the processor 702. The network interface 712 allows the EDA system 700 to communicate with a network 714, to which one or more other computer systems are connected. The network interface 712 includes a wireless network interface (such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA) or a wired network interface (such as Ethernet, USB, or IEEE-1364). In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 700.

[0078] The EDA system 700 receives information via the I / O interface 710. The information received via the I / O interface 710 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by the processor 702. The information is transmitted to the processor 702 via the bus 708. The EDA system 700 receives information related to the user interface (UI) via the I / O interface 710. The information is stored as UI 742 in the computer-readable medium 704.

[0079] In some embodiments, a portion or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, a portion or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, a portion or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, a portion or all of the process and / or method is implemented as a software application used by an EDA system 700. In some embodiments, a tool (such as VIRTUOSO® from CADENCE DESIGN SYSTEMS) or another suitable layout generation tool is used to generate a layout diagram including standard cells.

[0080] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of optical discs such as DVDs, magnetic disks such as hard disks, and semiconductor memories such as ROM, RAM, memory cards, etc.

[0081] Figure 8 is a block diagram of an integrated circuit (IC) manufacturing system 800 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on a layout diagram, the manufacturing system 800 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0082] In Figure 8, the IC manufacturing system 800 includes entities that interact with each other during the design, development, and manufacturing cycle and / or in connection with services related to the manufacture of IC devices 860, such as design room 820, mask room 830, and IC manufacturer / fabrication company (“fab”) 850. The entities in the IC manufacturing system 800 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 820, mask room 830, and IC fab 850 are owned by a single larger company. In some embodiments, two or more of the design room 820, mask room 830, and IC fab 850 coexist in a shared facility and use shared resources.

[0083] The design studio (or design team) 820 generates an IC design layout 822. The IC design layout 822 includes various geometric patterns designed for an IC device 860. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 860 to be manufactured. The various layers combine to form various IC features. For example, a portion of the IC design layout 822 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which will be formed on a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design studio 820 implements appropriate design procedures to form the IC design layout 822. These design procedures include logic design, physical design, or one or more of placement and routing. The IC design layout 822 is presented in one or more data files containing geometric pattern information. For example, the IC design layout 822 may be expressed in GDSII or DFII file format.

[0084] Mask chamber 830 includes mask data preparation 832 and mask fabrication 844. Mask chamber 830 uses IC design layout 822 to fabricate one or more masks 845 to fabricate various layers of IC device 860 according to IC design layout 822. Mask chamber 830 performs mask data preparation 830, in which IC design layout 822 is translated into a representative data file (RDF). Mask data preparation 832 provides RDF to mask fabrication 844. Mask fabrication 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) 845 or a wafer 853, such as a semiconductor wafer 853. IC design layout 822 is manipulated by mask data preparation 832 to conform to the specific characteristics of the mask writer and / or the requirements of IC wafer fab 850. In Figure 8, mask data preparation 832 and mask fabrication 844 are shown as separate components. In some embodiments, mask data preparation 832 and mask manufacturing 844 can be collectively referred to as mask data preparation.

[0085] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. OPC adjustment IC design layout diagram 822. In some embodiments, mask data preparation 832 includes other resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution aids, phase-transfer masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an anti-imaging problem.

[0086] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 822, which has been processed in the OPC, against certain geometric and / or connectivity constraints to ensure sufficient boundaries to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 822 to compensate for constraints during mask manufacturing 844, thereby canceling a portion of the modifications performed by the OPC to satisfy the mask creation rules.

[0087] In some embodiments, mask data preparation 832 includes lithography process checking (LPC), which simulates the process performed by IC wafer fab 850 to manufacture IC device 860. The LPC simulates this process based on IC design layout 822 to establish a simulated manufacturing apparatus, such as IC device 860. Processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after establishing the simulated manufacturing apparatus using LPC, if the simulated apparatus is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 822.

[0088] It should be understood that, for clarity, the above description of mask data preparation 832 has been simplified. In some embodiments, mask data preparation 832 includes additional features such as logic operations (LOPs) to modify the IC design layout 822 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 822 during mask data preparation 832 can be performed in various different sequences.

[0089] After mask data preparation 832 and during mask manufacturing 844, a mask 845 or a set of masks 845 is manufactured based on a modified IC design layout 822. In some embodiments, mask manufacturing 844 includes one or more photolithography exposures based on the IC design layout 822. In some embodiments, a pattern is formed on the mask (photomask or screen) 845 using an electron beam or a plurality of electron beams based on the modified IC design layout 822. The mask 845 can be formed using various techniques. In some embodiments, the mask 845 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams (such as ultraviolet (UV) beams) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of the mask 845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, a phase shift technique is used to form a mask 845. In the phase shift mask (PSM) version of mask 845, various features in the pattern formed on the phase shift mask are used to have appropriate phase difference to enhance resolution and image quality. In various examples, the phase shift mask can be a decaying PSM or an alternating PSM. The mask produced by mask fabrication 844 is used in various processes. For example, this mask is used in ion implantation processes to form various doped regions in semiconductor wafer 853, in etching processes to form various etched regions in semiconductor wafer 853, and / or in other suitable processes.

[0090] IC wafer fab 850 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC wafer fab 850 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end-of-line, FEOL) of a plurality of IC products, while a second manufacturing facility may provide back-end manufacturing (back-end-of-line, BEOL) for interconnection and packaging of IC products, and a third manufacturing facility may provide other services to the foundry.

[0091] IC wafer fab 850 includes manufacturing tools 852 for performing various manufacturing operations on semiconductor wafers 853 to manufacture IC devices 860 according to a mask (e.g., mask 845). In various embodiments, manufacturing tools 852 include one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as described herein.

[0092] IC wafer fab 850 uses a mask 845 manufactured by mask chamber 830 to manufacture IC device 860. Therefore, IC wafer fab 850 uses IC design layout 822 at least indirectly to manufacture IC device 860. In some embodiments, semiconductor wafer 853 is manufactured by IC wafer fab 850 using mask 845 to form IC device 860. In some embodiments, IC manufacturing includes one or more photolithography exposures based at least indirectly on IC design layout 822. Semiconductor wafer 853 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 853 further includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0093] Details relating to integrated circuit (IC) manufacturing systems (e.g., IC manufacturing system 800 of Figure 8) and associated IC manufacturing processes can be found, for example, in U.S. Patent No. 9,256,709, issued February 9, 2016; U.S. Pre-Grant Notice No. 2015 / 0278429, issued October 1, 2015; U.S. Pre-Grant Notice No. 2014 / 0040838, issued February 6, 2014; and U.S. Patent No. 7,260,442, issued August 21, 2007, the entire contents of which are incorporated herein by reference.

[0094] As used herein, terms such as “first,” “second,” and “third” describe various components, elements, regions, layers, and / or portions, but these components, elements, regions, layers, and / or portions should not be limited by these terms. These terms may be used only to distinguish one component, element, region, layer, or portion from another. Terms such as “first,” “second,” and “third” as used herein do not imply order or sequence unless the context clearly indicates otherwise.

[0095] Although the numerical ranges and parameters describing the broad scope of this disclosure are approximate, the values ​​listed in specific examples are reported as precisely as possible. However, any numerical value inherently contains some errors, which are necessarily caused by the standard deviations found in the various test measurements. Furthermore, as used herein, the terms "substantially," "approximately," and "about" generally mean values ​​or ranges that would be conceived by a person of ordinary skill. Alternatively, the terms "substantially," "approximately," and "about" mean within an acceptable standard error range of an average value considered by a person of ordinary skill. It will be understood by a person of ordinary skill that the acceptable standard error may vary depending on the technology. Except for operational / working examples, or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages (such as material quantity, duration, temperature, operating conditions, quantity ratios, etc.) disclosed herein should be understood to be modified in all cases by the terms "substantially," "approximately," or "about." Therefore, unless otherwise stated, the numerical parameters listed in this disclosure and the claims of the invention are approximate values ​​that may vary as needed. At a minimum, each numerical parameter should be interpreted based on the number of significant digits reported and using standard rounding techniques. Ranges can be expressed as a distance from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include the endpoints.

[0096] In some embodiments, a complementary field-effect transistor (CFET) includes: a first source / drain region of a first conductivity type; an insulating layer located on the first source / drain region; a second source / drain region of a second conductivity type located on the insulating layer, the second conductivity type being different from the first conductivity type; a vertical connection structure extending through the insulating layer and electrically connecting the first source / drain region and the second source / drain region, the first and second source / drain regions being used to receive the same first reference voltage; a first channel region corresponding to the first source / drain region; a second channel region corresponding to the second source / drain region; and a gate structure shared by the first channel region and the second channel region and at least partially surrounding the first channel region and the second channel region, the gate structure being used to receive a second reference voltage, the second reference voltage being different from the first reference voltage.

[0097] In some embodiments, the CFET further includes: a first conductive structure, wherein a first source / drain region is located on and electrically connected to the first conductive structure; and a second conductive structure, located on the second source / drain region, the second conductive structure being located on and electrically connected to the vertical connection structure. In some embodiments, the vertical connection structure includes a first vertical connection structure extending through the entire height of the first one in the second source / drain region, and the vertical connection structure includes a second vertical connection structure extending through the entire height of the second one in the second source / drain region. In some embodiments, the first vertical connection structure extends into the first one in the first source / drain region, and the second vertical connection structure extends into the second one in the first source / drain region. In some embodiments, the first vertical connection structure extends into the first one in the first source / drain region by a height less than half the height of the first one in the first source / drain region, and the second vertical connection structure extends into the second one in the first source / drain region by a height less than half the height of the second one in the first source / drain region. In some embodiments, the first and second source / drain regions are epitaxial regions. In some embodiments, the vertical connection structure is offset relative to the centerline of the epitaxial region. In some embodiments, the first reference voltage is VDD, the second reference voltage is VSS, the first conductivity type is p-type, and the second conductivity type is n-type. In some embodiments, the first reference voltage is VSS, the second reference voltage is VDD, the first conductivity type is n-type, and the second conductivity type is p-type. In some embodiments, a plurality of CFETs are coupled together in parallel in a decoupling capacitor (DCAP) circuit, wherein all source / drain regions of the CFETs in the DCAP circuit are used to receive VDD, and all gate structures of the CFETs in the DCAP circuit are used to receive VSS.

[0098] In some embodiments, the CFET includes: a first source / drain region of a first conductivity type; an insulating layer located on the first source / drain region; a second source / drain region of a second conductivity type located on the insulating layer, the second conductivity type being different from the first conductivity type; a vertical connection structure extending through the insulating layer and electrically connecting the first source / drain region and the second source / drain region, the first and second source / drain regions being configured to receive the same first reference voltage; a first channel region corresponding to the first source / drain region; a second channel region corresponding to the second source / drain region; a first gate structure at least partially surrounding the first channel region; and a second gate structure at least partially surrounding the second channel region, the first and second gate structures being configured to receive a second reference voltage different from the first reference voltage.

[0099] In some embodiments, the CFET further includes an insulating structure located between the first channel region and the second channel region. In some embodiments, the first and second source / drain regions are epitaxial regions. In some embodiments, the first reference voltage is VDD, and the second reference voltage is VSS, and the first conductivity type is p-type, and the second conductivity type is n-type. In some embodiments, the first reference voltage is VSS, and the second reference voltage is VDD, and the first conductivity type is n-type, and the second conductivity type is p-type. In some embodiments, a plurality of CFETs are coupled together in parallel in a decoupling capacitor (DCAP) circuit, wherein all source / drain regions of the CFETs in the DCAP circuit are used to receive VDD, and all gate structures of the CFETs in the DCAP circuit are used to receive VSS.

[0100] In some embodiments, the CFET includes: a first source / drain region; an insulating layer located on the first source / drain region; a conductive structure located on the insulating layer; a vertical connection structure extending through the insulating layer and electrically connecting the first source / drain region and the conductive structure, the first source / drain region and the conductive structure being used to receive the same first reference voltage; a first channel region corresponding to the first source / drain region; a second channel region located on the upper portion of the insulating layer near the conductive structure; and a gate structure shared by the first channel region and the second channel region and at least partially surrounding the first channel region and the second channel region, the gate structure being used to receive a second reference voltage different from the first reference voltage.

[0101] In some embodiments, the second channel region does not have a corresponding source / drain region. In some embodiments, the second channel region is used to float. In some embodiments, the first reference voltage is VDD, and the second reference voltage is VSS, and the first source / drain region is p-type. In some embodiments, the first reference voltage is VSS, and the second reference voltage is VDD, and the first source / drain region is n-type. In some embodiments, a plurality of CFETs are coupled together in parallel in a decoupling capacitor (DCAP) circuit, wherein all source / drain regions of the CFETs in the DCAP circuit are used to receive VDD, and all gate structures of the CFETs in the DCAP circuit are used to receive VSS.

[0102] The foregoing has outlined the structures of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The various aspects of this disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 is a schematic diagram of a decoupling capacitor (DCAP) unit according to some embodiments. Figure 2A is a cross-sectional view of the structure of a complementary field-effect transistor (CFET) according to some embodiments. Figure 2B is a cross-sectional view along line I-I' in Figure 2A. Figure 2C is a cross-sectional view along line II-II' in Figure 2A. Figure 2D is a schematic diagram of a CFET demonstrating capacitive features according to some embodiments. Figure 2E is a cross-sectional view of the structure of a CFET according to some embodiments. Figure 2F is a cross-sectional view along line III-III' in Figure 2E. Figure 3 is a schematic diagram of a DCAP unit according to some embodiments. Figure 4A is a cross-sectional view of a CFET-like structure according to some embodiments. Figure 4B is a cross-sectional view along line I-I' in Figure 4A. Figure 4C is a cross-sectional view along line II-II' in Figure 4A. Figure 4D is a schematic diagram of a CFET demonstrating capacitive features according to some embodiments. Figure 5 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments. Figure 6 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments. Figure 7 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Figure 8 is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. [Biomaterial Storage]

[0104] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A complementary field-effect transistor (FET) comprising: a plurality of first source / drain regions of a first conductivity type; an insulating layer located on the first source / drain regions; a plurality of second source / drain regions of a second conductivity type located on the insulating layer, the second conductivity type being different from the first conductivity type; a plurality of vertically connected structures extending through the insulating layer and electrically connecting the first source / drain regions and the second source / drain regions, the first and second source / drain regions being configured to receive the same first reference voltage; a first channel region corresponding to the first source / drain regions; a second channel region corresponding to the second source / drain regions; and a gate structure shared by the first channel region and the second channel region and at least partially surrounding the first channel region and the second channel region, the gate structure being configured to receive a second reference voltage, the second reference voltage being different from the first reference voltage. A plurality of complementary field-effect transistors are coupled together in parallel in a decoupling capacitor circuit, wherein all source / drain regions of the complementary field-effect transistors in the decoupling capacitor circuit are used to receive the first reference voltage, and all gate structures of the complementary field-effect transistors in the decoupling capacitor circuit are used to receive the second reference voltage.

2. The complementary field-effect transistor as claimed in claim 1, further comprising: a plurality of first conductive structures, the first source / drain regions being located on and electrically connected to the first conductive structures; and a plurality of second conductive structures being located on the second source / drain regions, the second conductive structures being located on and electrically connected to the vertical connection structures.

3. The complementary field-effect transistor as described in claim 1, wherein: The vertical connection structures include a first vertical connection structure extending through the entire height of the first one in the second source / drain regions, and the vertical connection structures include a second vertical connection structure extending through the entire height of the second one in the second source / drain regions.

4. The complementary field-effect transistor as described in claim 3, wherein: The first vertical connection structure extends into the first of the first source / drain regions, and the second vertical connection structure extends into the second of the first source / drain regions.

5. The complementary field-effect transistor as described in claim 3, wherein: The first vertical connection structure extends into the first of the first source / drain regions, with an extension height less than half the height of the first of the first source / drain regions, and the second vertical connection structure extends into the second of the first source / drain regions, with an extension height less than half the height of the second of the first source / drain regions.

6. The complementary field-effect transistor as claimed in claim 1, wherein: The first reference voltage is VDD, and the second reference voltage is VSS.

7. The complementary field-effect transistor as described in claim 6, wherein: The first conductivity type is p-type, and the second conductivity type is n-type.

8. The complementary field-effect transistor as described in claim 7, wherein: All source / drain regions of the complementary field-effect transistors in the decoupling capacitor circuit are used to receive the VDD, and all gate structures of the complementary field-effect transistors in the decoupling capacitor circuit are used to receive the VSS.

9. A complementary field-effect transistor (FET) comprising: a plurality of first source / drain regions of a first conductivity type; an insulating layer located on the first source / drain regions; a plurality of second source / drain regions of a second conductivity type located on the insulating layer, the second conductivity type being different from the first conductivity type; a plurality of vertical interconnect structures extending through the insulating layer and electrically connecting the first source / drain regions and the second source / drain regions, the first and second source / drain regions being configured to receive the same first reference voltage; a first channel region corresponding to the first source / drain regions; a second channel region corresponding to the second source / drain regions; a first gate structure at least partially surrounding the first channel region; and a second gate structure at least partially surrounding the second channel region, the first and second gate structures being configured to receive a second reference voltage different from the first reference voltage, wherein the vertical interconnect structures include a first vertical interconnect structure and a second vertical interconnect structure. The first vertical connection structure extends through the entire height of the first one in the second source / drain regions and into the first one in the first source / drain regions, and the second vertical connection structure extends through the entire height of the second one in the second source / drain regions and into the second one in the first source / drain regions.

10. A complementary field-effect transistor (FET) comprising: a plurality of first source / drain regions; an insulating layer located on the first source / drain regions; a plurality of conductive structures located on the insulating layer; a plurality of vertical connection structures extending through the insulating layer and electrically connecting the first source / drain regions and the conductive structures, the first source / drain regions and the conductive structures being configured to receive the same first reference voltage; a first channel region corresponding to the first source / drain regions; a second channel region located on an upper portion of the insulating layer near the conductive structures; and a gate structure shared by the first channel region and the second channel region and at least partially surrounding the first channel region and the second channel region, the gate structure being configured to receive a second reference voltage different from the first reference voltage, wherein the vertical connection structures include a first vertical connection structure and a second vertical connection structure. The first vertical connection structure extends into the first of the first source / drain regions, and the second vertical connection structure extends into the second of the first source / drain regions.

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