Cfet structure, semiconductor device structure, and method of forming the same

Abstract

The embodiments disclosed herein provide a CFET structure and a method for forming the same. The structure includes a first transistor comprising a first gate structure, the first gate structure comprising a first number of dielectric layers and a first conductivity type dipole dopant, wherein the peak concentration of the first conductivity type dipole dopant is located at the interface between a first interface layer and the first gate dielectric layer of the first number of dielectric layers. The structure further includes a second transistor disposed above the first transistor, and the second transistor comprising a second gate structure, the second gate structure comprising a second number of dielectric layers and a second conductivity type dipole dopant of the opposite conductivity type to the first conductivity type, the second number being different from the first number, and the peak concentration of the second conductivity type dipole dopant being located in the dipole layer of the second number of dielectric layers.

Description

Technical Field

[0001] none. Prior Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Advances in IC materials and design technologies have led to generation after generation of ICs, each smaller and more complex than the last. Throughout IC development, functional density (the number of interconnects per unit wafer area) has increased overall, while geometry (the smallest element (or line) that can be manufactured using a process) has decreased. This downsizing typically benefits production efficiency and reduces associated costs. However, the reduction in size also increases the complexity of IC fabrication and manufacturing.

[0003] Therefore, improvements are needed in IC processing and manufacturing. Summary of the Invention

[0004] none. Simple Explanation of the Diagram

[0005] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various parts are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various parts may be arbitrarily increased or decreased. Figures 1, 2, 3, 4, 5 and 6 are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments. Figure 7A is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments. Figure 7B is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line BB of Figure 6 according to some embodiments. Figure 7C is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments. Figure 8A is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments. Figure 8B is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line BB of Figure 6 according to some embodiments. Figure 8C is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments. Figure 9A is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments. Figure 9B is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line BB of Figure 6 according to some embodiments. Figure 9C is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments. Figure 10A is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments. Figure 10B is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line BB of Figure 6 according to some embodiments. Figure 10C is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments. Figure 11A is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments. Figure 11B is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line BB of Figure 6 according to some embodiments. Figure 11C is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments. Figure 12A is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments. Figure 12B is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line BB of Figure 6 according to some embodiments. Figure 12C is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments. Figure 13A is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments. Figure 13B is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line BB of Figure 6 according to some embodiments. Figure 13C is a cross-sectional side view of various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments. Figures 14, 15, 16, 17, 18, 19, 20, 21, and 22 are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments. Figure 23 is a cross-sectional side view of a portion of a gate structure according to an alternative embodiment. Implementation

[0006] This disclosure generally relates to integrated circuit (IC) devices, and more specifically, to IC devices having a stacked device structure, such as a stack of transistors having n-type transistors and p-type transistors (i.e., complementary field effect transistors (CFETs)).

[0007] The following disclosure provides numerous different embodiments or examples for implementing various components of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first component above or on a second component in the following description may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, for clarity in this disclosure regarding the relationship between one feature and another, spatially relative terms such as “down,” “above,” “horizontal,” “vertical,” “above,” “on top,” “below,” “under,” “up,” “down,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “downward,” etc.) are used. Spatially relative terms are intended to cover different orientations of the device, including features. Reference numerals and / or letters may also be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, when describing numbers or ranges of numbers using terms such as "about," "approximately," etc., the term is intended to encompass numbers within a reasonable range that takes into account variations inherent in the manufacturing process, as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics related to numbers, a number or range of numbers encompasses a reasonable range including said number, such as within + / - 10% of said number. For example, a material layer with a thickness of "about 5 nanometers" can encompass a size range of 4.5 nanometers to 5.5 nanometers, where a manufacturing tolerance associated with the deposited material layer is known to one of ordinary skill in the art to be + / - 10%. Additionally, considering any inherent variations in the manufacturing process, when a device feature is described as having "substantial" properties and / or characteristics, the term is intended to capture properties and / or characteristics within the tolerance range of the manufacturing process. For example, a feature that is "substantially vertical" or "substantially horizontal" is intended to capture features that are approximately vertical and horizontal within a given tolerance range of the manufacturing process used to manufacture such features—but not mathematically or perfectly vertical and horizontal.

[0009] Although the embodiments disclosed herein are discussed with respect to nanostructured channel FETs (field effect transistors) (e.g., gate all-around FETs, such as horizontal gate all-around FETs (HGAA) or vertical gate all-around FETs (VGAA), implementations of some aspects of this disclosure can be used with other processes and / or other devices, such as planar FETs, FinFETs, and other suitable devices. Those skilled in the art will readily understand that other modifications can be made within the scope of this disclosure. In the case of a gate all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes (including dual-patterning or multi-patterning processes). Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby enabling the creation of patterns, for example, with smaller spacing than those obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A spacer is formed alongside the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacers can be used to pattern the GAA structure.

[0010] Figures 1 through 22 illustrate exemplary processes for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure. It should be understood that, for additional embodiments of the method, additional operations may be provided before, during, and after the processes shown in Figures 1 through 22, and some operations described below may be replaced or eliminated. The order of operations / processes is not limited and can be interchanged.

[0011] Figures 1 to 6 are perspective views of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a semiconductor layer 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0012] The substrate 101 may include various regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus in an n-type field-effect transistor (NFET) and boron in a p-type field-effect transistor (PFET).

[0013] Semiconductor layer 104 comprises alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels in multi-gate devices, such as nanostructure channel FETs. In some embodiments, semiconductor layer 104 comprises a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, semiconductor layer 104 comprises alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0014] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the semiconductor layer 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0015] The first semiconductor layer 106, or a portion thereof, may form nanostructure channels of the semiconductor device structure 100 in subsequent manufacturing stages. The term nanostructure is used herein to refer to any material portion having nanometer- or even micrometer-scale dimensions and an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, as well as beam or rod-shaped material portions, such as those comprising cylindrical or substantially rectangular cross-sections. The nanostructure channels of the semiconductor device structure 100 may be surrounded by gates. The semiconductor device structure 100 may include nanostructure transistors. Nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, gate-around-a-loop (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gates surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0016] The thickness of each first semiconductor layer 106 can range from about 5 nm to about 30 nm. The thickness of each second semiconductor layer 108 can be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, the thickness of each second semiconductor layer 108 ranges from about 2 nm to about 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, as shown in FIG1, which is for illustrative purposes only and is not intended to limit the scope specifically described in the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in semiconductor layer 104, and the number of layers depends on the predetermined number of channels of semiconductor device structure 100.

[0017] In Figure 2, fin structures 112 are formed by stacking semiconductor layers 104. Each fin structure 112 has an upper portion including a first semiconductor layer 106, a second semiconductor layer 108, and a substrate portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layers 104 using a multi-patterning operation including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, the photoresist layer can be patterned using an electron beam lithography process to form the mask element. The etching process forms trenches 114 in the unprotected area, through the hard mask layer, through the stack of semiconductor layers 104, and into the substrate 101, thereby leaving a plurality of extending fin structures 112. The trenches 114 extend in the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or combinations thereof. In some embodiments, each fin structure 112 has a longitudinal axis in the X direction.

[0018] In Figure 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0019] In Figure 4, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes portions of fin structures 112, such as the stack of semiconductor layers 104. The recess in insulating material 118 exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using suitable processes, such as dry etching, wet etching, or combinations thereof. The top surface of insulating material 118 can be flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from substrate 101.

[0020] In Figure 5, one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate layer 134, and the masking layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate layer 134, and the masking layer 136, and then patterning these layers into the sacrificial gate structure 130. Gate spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. The gate spacers 138 may be formed by, for example, conformally depositing one or more layers of gate spacers 138 and anisotropically etching the one or more layers. In some embodiments, the gate spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be arranged along the X direction.

[0021] The sacrificial gate dielectric layer 132 may include one or more dielectric materials, such as silicon oxide-based materials. The sacrificial gate layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may include multiple layers, such as oxide layers and nitride layers. The gate spacer 138 may be made of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0022] The portion of the fin structure 112 covered by the sacrificial gate layer 134 of the sacrificial gate structure 130 is used as a channel region of the semiconductor device structure 100.

[0023] In Figure 6, the portion of fin structure 112 not covered by sacrificial gate structure 130 and gate spacer 138 is recessed to a level above, above, or below the top surface of isolation region 120. This partial recess of fin structure 112 can be achieved through an etching process, which can be either isotropic or anisotropic, and can be selected for one or more crystal planes of substrate 101. The etching process can be dry etching, such as RIE, NBE, etc., or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0024] Figures 7A, 7B, and 7C are cross-sectional side views of the semiconductor device structure 100 taken along lines AA, BB, and CC in Figure 6, respectively.

[0025] Figures 8A, 8B, and 8C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various stages of manufacturing a semiconductor device structure 100. As shown in Figure 8A, the edge portions of each second semiconductor layer 108 of semiconductor layer 104 are removed horizontally along the X direction. Removing the edge portions of the second semiconductor layer 108 creates cavities. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process. In cases where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine-o-phenylenediamine-catechol (EDP), or an hydroxide solution.

[0026] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 can be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), followed by anisotropic etching to remove the portion of the conformal dielectric layer except for the dielectric spacers 144. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layers 108 cover the spacers 144 along the X-direction.

[0027] In some embodiments, instead of removing the edge portions of each second semiconductor layer 108, the second semiconductor layer 108 is removed and replaced with a dielectric material (e.g., high-density SiN or SiO). The edge portions of the dielectric material are removed, and dielectric spacers 144 are formed to cover the dielectric material.

[0028] Figures 9A, 9B, and 9C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various stages of fabricating a semiconductor device structure 100. As shown in Figures 9A and 9C, a source / drain (S / D) region 146 is formed from a substrate portion 116. In some embodiments, the S / D region 146 may be grown vertically and horizontally to form a surface, which may correspond to a crystal plane of the material used for the substrate portion 116. In this disclosure, the source region and drain region are used interchangeably and their structures are substantially the same. Furthermore, the source / drain region may refer to either the source or the drain, individually or collectively, depending on the context. For an n-channel FET, the S / D region 146 may be made of one or more layers of Si, SiP, SiC, and SiCP, or for a p-channel FET, the S / D region 146 may be made of one or more layers of Si, SiGe, and Ge. For a p-channel FET, the S / D region 146 may also contain a p-type dopant, such as boron (B). The S / D region 146 can be formed using epitaxial growth methods such as CVD, ALD, or MBE.

[0029] According to some embodiments, Figures 10A, 10B, and 10C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, of one of the various stages of manufacturing the semiconductor device structure 100. In Figures 10A, 10B, and 10C, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D region 146. CESL 162 may include oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbonitride, silicon oxide, silicon carbide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric layer (ILD layer) 164 is formed on the CESL 162 above the semiconductor device structure 100. The material of ILD layer 164 may include compounds containing Si, O, C and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for ILD layer 164. ILD layer 164 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after ILD layer 164 is formed, the semiconductor device structure 100 may undergo heat treatment to cure ILD layer 164.

[0030] After the ILD layer 164 is formed, a planarization operation (e.g., CMP) is performed on the semiconductor device structure 100 until the sacrificial gate layer 134 is exposed, as shown in Figures 10A and 10B.

[0031] Figures 11A, 11B, and 11C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the stages of fabricating a semiconductor device structure 100. As shown in Figures 11A and 11B, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the second semiconductor layer 108 creates openings between the gate spacers 138 and between the first semiconductor layer 106. The dielectric materials of the ILD layer 164, the gate spacers 138, and the dielectric spacers 144 are substantially unaffected by the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate layer 134 can be removed first by any suitable process (e.g., dry etching, wet etching, or a combination thereof), followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process (e.g., dry etching, wet etching, or a combination thereof). In some embodiments, a wet etchant (e.g., a tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate layer 134, but not the gate spacer 138, dielectric material 166, dielectric layer 163, and CESL 162.

[0032] The second semiconductor layer 108 can be removed using a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe without significantly affecting the Si, the dielectric material of the gate spacer 138, the dielectric material 166, the dielectric layer 163, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant, such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant (e.g., fluorine-based (e.g., F2) or chlorine-based gas (e.g., Cl2)), or any suitable isotropic etchant.

[0033] According to some embodiments, Figures 12A, 12B, and 12C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, of one of the stages of manufacturing a semiconductor device structure 100. As shown in Figures 12A and 12B, after forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106. In some embodiments, an interfacial layer IL169 is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, IL169 is formed through the oxidation of the first semiconductor layer 106. The thickness of IL169 may range from about 1 nm to about 1.5 nm. In some embodiments, the gate dielectric layer 170 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed using CVD, ALD, or any suitable deposition technique.

[0034] Next, a dipole process is performed to adjust the threshold voltage of the transistor to be formed. In some embodiments, a dipole layer (not shown) is first deposited on the gate dielectric layer 170. The dipole layer can be formed by any suitable process, such as ALD or CVD. The dipole layer is a dielectric layer comprising an n-dipole dopant or a p-type dopant. In some embodiments, the n-dipole dopant or p-dipole dopant can comprise a metal, such as La, Sr, Er, or Mg for n-dipole dopant, or Al or Ti for p-dipole dopant. The dipole layer can comprise oxygen, nitrogen, carbon, or combinations thereof. In some embodiments, the dipole layer comprises an n-dipole dopant. After the dipole layer is deposited, a heat treatment is performed to drive the n-dipole dopant or p-dipole dopant into the gate dielectric layer 170. The heat treatment can be any suitable treatment, such as annealing, including rapid thermal annealing (RTA), millisecond annealing (MSA), microsecond annealing (pSA), microwave annealing, laser annealing, spike annealing, immersion annealing, furnace annealing, other suitable annealing treatments, or combinations thereof. The heat treatment temperature may reach 500 degrees Celsius or even higher. The heat treatment causes the n-dipole dopant or p-dipole dopant to diffuse into the gate dielectric layer 170. In some embodiments, the n-dipole dopant or p-dipole dopant also diffuses into IL169. Therefore, in some embodiments, the gate dielectric layer 170 includes an n-dipole dopant or a p-dipole dopant. In some embodiments, the peak n-dipole dopant concentration or peak p-dipole dopant concentration is located at the interface between the gate dielectric layer 170 and IL169.

[0035] After heat treatment, the dipole layer is removed. The dipole layer can be removed using any suitable process, such as dry etching, wet etching, or a combination thereof. The process for removing the dipole layer can be selective and will not substantially affect the gate dielectric layer 170 and the ILD layer 164.

[0036] Figures 13A, 13B, and 13C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the stages of fabricating a semiconductor device structure 100. As shown in Figures 13A and 13B, a gate layer 172 is formed on the gate dielectric layer 170. The gate layer 172 may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, alloys, other suitable combinations, and other combinations. The gate layer 172 may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. In some embodiments, the gate layer 172 includes one or more work function layers and a bulk fill layer. The gate layer 172 may also be deposited over the ILD layer 164. Then, the gate dielectric layer 170 and gate layer 172 formed above the ILD layer 164 are removed using, for example, CMP, until the ILD layer 164 is exposed. The gate dielectric layer 170 and gate layer 172 can be collectively referred to as gate structure 174.

[0037] As shown in Figures 13A, 13B, and 13C, the semiconductor device structure 100 includes at least one transistor, such as a GAAFET, comprising a gate structure 174, S / D regions 146 on opposite sides of the gate structure 174, and a first semiconductor layer 106 serving as a channel between the S / D regions 146. In some embodiments, the transistor may be a FinFET or a planar FET. This transistor may be an NFET or a PFET. In some embodiments, the semiconductor device structure 100 includes a plurality of transistors of a first conductivity type. For example, the plurality of transistors may all be NFETs or PFETs.

[0038] Figures 14, 15, 16, 17, 18, 19, 20, 21, and 22 are cross-sectional side views taken along line AA of Figure 6 according to some embodiments of a semiconductor device structure 100 being manufactured. Figures 14 through 22 illustrate the process of forming a complementary field-effect transistor (CFET), which can further reduce density for advanced IC technology nodes. As shown in Figure 14, a dielectric layer 202 is formed on an ILD layer 164 and a gate structure 174. The dielectric layer 202 may be an oxide layer. Next, as shown in Figure 15, structure 200 is bonded to the dielectric layer 202. In some embodiments, structure 200 includes a dielectric layer 203, a semiconductor layer 204, and a substrate 201. Structure 200 may be formed by forming a stack of semiconductor layers 204 on substrate 201 and depositing a dielectric layer 203 on the stack of semiconductor layers 204. Structure 200 is then flipped so that the dielectric layer 203 is bonded to the dielectric layer 202. In some embodiments, dielectric layer 203 is an oxide layer, and the bonding between dielectric layer 202 and dielectric layer 203 is a bonding process between dielectric layers, such as a bonding process between oxides. In some embodiments, the combined thickness of dielectric layer 202 and dielectric layer 203 ranges from about 10 nm to about 100 nm.

[0039] Semiconductor layer 204 includes alternating semiconductor layers 206 and 208. In some embodiments, semiconductor layer 206 comprises the same material as the first semiconductor layer 106, and semiconductor layer 208 comprises the same material as the second semiconductor layer 108. Substrate 201 may comprise the same material as substrate 101. Semiconductor layer 206 or portions thereof may form nanostructure channels for the upper transistors of a CFET in subsequent manufacturing stages. The alternating arrangement of three semiconductor layers 206 and three semiconductor layers 208, as shown in FIG15, is for illustrative purposes only and is not intended to limit the scope beyond that specifically described in the claims. It is understood that any number of semiconductor layers 206 or semiconductor layers 208 may be formed in semiconductor layer 104.

[0040] As shown in Figure 16, substrate 201 is removed, and one or more sacrificial gate structures 230 (only one shown) are formed over semiconductor layer 204. Substrate 201 can be removed using any suitable process. In some embodiments, a thinning process, such as a planarization process, can be performed to remove substrate 201. An etch stop layer (not shown) can be formed between the topmost semiconductor layer 206 and substrate 201. The etch stop layer is removed after substrate 201 is removed. Sacrificial gate structure 230 includes sacrificial gate dielectric layer 232 and sacrificial gate layer 234. In some embodiments, sacrificial gate dielectric layer 232 comprises the same material as sacrificial gate dielectric layer 132, and sacrificial gate layer 234 comprises the same material as sacrificial gate layer 134. A masking layer (not shown) can be formed on sacrificial gate layer 234. The masking layer may comprise the same material as masking layer 136. The sacrificial gate dielectric layer 232 and sacrificial gate layer 234 can be formed using the same process as the sacrificial gate dielectric layer 132 and sacrificial gate layer 134. After forming the sacrificial gate structure 230, a gate spacer 238 is formed on the sidewall of the sacrificial gate structure 230. The gate spacer 238 may include the same material as the gate spacer 138 and can be formed using the same process as the gate spacer 138.

[0041] As shown in Figure 17, the exposed portion of semiconductor layer 204 is removed. The exposed portion of semiconductor layer 204 can be removed using the process described in Figure 6 that recesses the exposed portion of fin structure 112. Next, the edge portion of semiconductor layer 208 is removed, and dielectric spacer 244 is formed, as shown in Figure 18. The edge portion of semiconductor layer 208 can be removed using the process described in Figure 8A that removes the edge portion of second semiconductor layer 108. Dielectric spacer 244 may comprise the same material as dielectric spacer 144 and can be formed using the same process as dielectric spacer 144.

[0042] As shown in Figure 19, the S / D region 246 is formed by the semiconductor layer 206. In some embodiments, the S / D region 246 can be grown vertically and horizontally to form surfaces, which may correspond to the crystal planes of the material used for the semiconductor layer 206. For an n-channel FET, the S / D region 246 may be made of one or more layers of Si, SiP, SiC, and SiCP, or for a p-channel FET, the S / D region 246 may be made of one or more layers of Si, SiGe, and Ge. For a p-channel FET, the S / D region 246 may also contain a p-type dopant, such as boron (B). The S / D region 246 can be formed using epitaxial growth methods such as CVD, ALD, or MBE. In some embodiments, the S / D region 146 is of a first conductivity type, while the S / D region 246 is of a second conductivity type opposite to the first conductivity type. For example, the S / D region 146 includes an n-type semiconductor material, while the S / D region 246 includes a p-type semiconductor material.

[0043] As shown in Figure 20, CESL 262 and ILD layer 264 are formed over S / D region 246. In some embodiments, CESL 262 comprises the same material as CESL 162 and is formed using the same process as CESL 262. ILD layer 264 may comprise the same material as ILD layer 164 and may be formed using the same process as ILD layer 164. A planarization process (e.g., CMP process) may be performed to remove portions of CESL 262 and ILD layer 264 formed over sacrificial gate layer 234. A masking layer may also be removed using a CMP process to expose sacrificial gate layer 234.

[0044] As shown in Figure 21, the sacrificial gate structure 230 and the semiconductor layer 208 are removed. The sacrificial gate structure 230 can be removed using the same process as the sacrificial gate structure 130, and the semiconductor layer 208 can be removed using the same process as the second semiconductor layer 108. Openings are formed between the gate spacers 238 and between the semiconductor layers 206, as shown in Figure 21.

[0045] As shown in Figure 22, a gate structure 274 is formed in the openings between the gate spacers 238 and between the semiconductor layers 206. The processing temperature for forming the gate structure 274 is below 400 degrees Celsius, for example, from about 20 degrees Celsius to about 350 degrees Celsius. If the processing temperature is above about 400 degrees Celsius, the material of the gate layer 172 may degrade.

[0046] In some embodiments, as shown in FIG22, an interface layer (IL) 250 is formed on the exposed surface of semiconductor layer 206. IL 250 may be an oxide. In some embodiments, IL 250 is formed through an oxide semiconductor layer 206. In some embodiments, the thickness of IL 250 ranges from about 1 nm to about 1.5 nm. Next, a first gate dielectric layer 252 is deposited on gate spacer 138 and IL 250. The first gate dielectric layer 252 may include the same material as gate dielectric layer 170. In some embodiments, gate dielectric layer 252 has a thickness ranging from about 3 angstroms to about 5 angstroms. In some embodiments, the thickness of gate dielectric layer 252 is just sufficient to form a continuous layer. Gate dielectric layer 252 may be deposited through any suitable process, such as ALD or CVD. In some embodiments, the subsequently formed dipole layer 256 is capable of generating a remote electric field during use, and a gate dielectric layer 252 is formed between the first semiconductor layer 106 and the subsequently formed dipole layer 256 to shield the first semiconductor layer 106 (i.e., the channel region) from the effects of the remote sublayer generated by the dipole layer 256. In some embodiments, the presence of the gate dielectric layer 252 can lead to a reduction in Dit. Next, another IL254 is deposited on the gate dielectric layer 252. In some embodiments, IL254 is an oxide, such as silicon oxide. IL254 can be deposited through any suitable process, such as ALD or CVD. In some embodiments, IL254 has a thickness in the range of about 3 angstroms to about 5 angstroms. In some embodiments, the thickness of IL254 is just sufficient to form a continuous layer. In some embodiments, the thickness of IL254 is significantly smaller than the thickness of IL250. For example, the ratio of the thickness of IL250 to the thickness of IL254 can be between 2 and 3. A dipole layer 256 is then deposited on IL254. The dipole layer 256 may be a dielectric layer comprising an n-dipole dopant or a p-dipole dopant. In some embodiments, the dipole layer 256 comprises a metal, such as La, Sr, Er, or Mg for an n-dipole dopant, or Al or Ti for a p-dipole dopant. The dipole layer 256 may comprise oxygen, nitrogen, carbon, or combinations thereof. In some embodiments, the dipole layer 256 comprises a p-dipole dopant. In some embodiments, the gate dielectric layer 170 comprises a dopant of a first conductivity type, and the dipole layer 256 comprises a second conductivity type opposite to the first conductivity type. In some embodiments, the dipole layer 256 has a thickness ranging from about 3 angstroms to about 5 angstroms. In some embodiments, the thickness of the dipole layer 256 is just sufficient to form a continuous layer.

[0047] The deposition of gate dielectric layer 252, IL254, and dipole layer 256 is performed at low temperatures, such as below 400 degrees Celsius, for example, from about 20 degrees Celsius to about 350 degrees Celsius. At low temperatures, n-dipole dopants or p-dipole dopants do not diffuse to adjacent layers. Therefore, IL254 and gate dielectric layer 252 are substantially free of n-dipole and p-dipole dopants. In some embodiments, the peak n-dipole dopant concentration or peak p-dipole dopant concentration is located within dipole layer 256. As described above, the peak n-dipole dopant concentration or peak p-dipole dopant concentration is located at the interface between gate dielectric layer 170 and IL169. Therefore, in some embodiments, in the CFET structure, the bottom transistor includes a first conductivity type dipole dopant, and the peak concentration of the first conductivity type dipole dopant is located at the interface between gate dielectric layer 170 and IL169. The top transistor of the CFET structure includes a second conductivity type dipole dopant opposite to the first conductivity type, and the peak concentration of the second conductivity type dipole dopant is located within the dipole layer 256. In some embodiments, the first conductivity type is p-type and the second conductivity type is n-type. In some embodiments, the first conductivity type is n-type and the second conductivity type is p-type. The gate dielectric layer 252, IL254, and dipole layer 256 can adjust the threshold voltage without diffusing dopants in the dipole layer 256 into the gate dielectric layer 252 or IL254. Furthermore, although the k-values ​​of IL254 and dipole layer 256 are smaller than the k-value of the gate dielectric layer 252, the thicknesses of IL254 and dipole layer 256 are smaller, so the parasitic capacitance is essentially not increased. In addition, the addition of IL254 and dipole layer 256 creates a discontinuous gate structure 274, thereby preventing the formation of penetration paths during device operation. In other words, leakage current during operation is reduced. Since the dipole layers 256 and IL250 are separated by the gate dielectric layers 252 and IL254, the density of interface trap charge (Dit) can be reduced, resulting in a reduction in leakage current.

[0048] In some embodiments, dipole layer 256 and IL254 are capable of bidirectional threshold voltage regulation. For example, if dipole layer 256 comprises an n-dipole dopant and is deposited on IL254 (or dipole layer 256 is located inside IL254), the threshold voltage can be adjusted to be more n-type. If IL254 is deposited on dipole layer 256 (or IL254 is located inside dipole layer 256), the threshold voltage can be adjusted to be more p-type. In other words, dipole layer 256 comprising a single conductivity type dopant (n-dipole dopant or p-dipole dopant) can be used for both PFETs and NFETs.

[0049] Next, a gate dielectric layer 258 is deposited on the dipole layer 256. The gate dielectric layer 258 may comprise the same material as the gate dielectric layer 170 and may be formed using the same process as the gate dielectric layer 170. The gate dielectric layer 258 is deposited at a low temperature, for example, below 400 degrees Celsius, such as from about 20 degrees Celsius to about 350 degrees Celsius. As mentioned above, at low temperatures, dopants in the dipole layer 256 do not diffuse into adjacent layers, such as IL254 or the gate dielectric layer 258. Therefore, in some embodiments, the gate dielectric layer 258 is substantially free of both n-dipole and p-dipole dopants. In some embodiments, the thickness of the gate dielectric layer 258 ranges from about 0.5 nm to about 1.0 nm. In some embodiments, the gate dielectric layer 258 and the gate dielectric layer 252 comprise the same material. The threshold voltage can be adjusted by inserting IL254 and dipole layer 256 between gate dielectric layer 252 and / or gate dielectric layer 258.

[0050] In some embodiments, the thickness of IL250 ranges from about 1 nm to about 1.5 nm, the thickness of gate dielectric layer 252 ranges from about 3 angstroms to about 5 angstroms, the thickness of IL254 ranges from about 3 angstroms to about 5 angstroms, the thickness of dipole layer 256 ranges from about 3 angstroms to about 5 angstroms, and the thickness of gate dielectric layer 258 ranges from about 0.5 nm to about 1.0 nm. In some embodiments, the total thickness of IL250, gate dielectric layer 252, IL254, dipole layer 256, and gate dielectric layer 258 ranges from about 2.4 nm to about 4 nm. In some embodiments, IL169 and IL250 have the same thickness, and the thickness of gate dielectric layer 170 is the same as the sum of the thicknesses of gate dielectric layer 252 and gate dielectric layer 258. In some embodiments, the total thickness of IL169 and gate dielectric layer 170 ranges from about 1.8 nm to about 3 nm, which is less than the total thickness of IL250, gate dielectric layer 252, IL254, dipole layer 256, and gate dielectric layer 258. In other words, in some embodiments, the thickness of the dielectric layer of gate structure 174 is less than the thickness of the dielectric layer of gate structure 274.

[0051] A gate layer 260 is formed on the gate dielectric layer 258. The gate layer 260 may include the same material as the gate layer 172. In some embodiments, the gate layer 260 includes one or more work function layers, and each work function layer includes Ti, Al, Ag, Mn, Zr, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, Ru, Mo, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, or TiAlN. The gate layer 260 also includes a bulk filling layer made of a conductive material, such as Al, W, Cu, Ti, Ta, TiN, TaN, polycrystalline silicon, other suitable metals and / or alloys thereof, or combinations thereof.

[0052] In some embodiments, the semiconductor device structure 100 includes a CFET having a first transistor 282 and a second transistor 284 disposed above the first transistor 282. The first transistor 282 includes a first gate structure 174 having a first number of layers, and the second transistor 284 includes a second gate structure 274 having a second number of layers greater than the first number of layers. For example, the second gate structure 274 includes three more layers than the first gate structure 174, namely a gate dielectric layer 252, an IL 254, and a dipole layer 256. The first gate structure 174 may include a gate dielectric layer 170 having an n-dipole dopant or a p-dipole dopant, and the second gate structure 174 may include a gate dielectric layer 252 and a gate dielectric layer 258 without n-dipole and p-dipole dopant. The second gate structure 174 is formed at a low temperature below about 400 degrees Celsius, for example, about 20 degrees Celsius to about 350 degrees Celsius. Therefore, the metal layer of the first gate structure 174 will not deteriorate.

[0053] Figure 23 is a cross-sectional side view of a portion of a gate structure 280 according to an alternative embodiment. As shown in Figure 23, the gate structure 280 includes a gate dielectric layer 252, a dipole layer 256 disposed on the gate dielectric layer 252, an IL 254 disposed on the dipole layer 256, a gate dielectric layer 258 disposed on the IL 254, and a gate layer 260 disposed on the gate dielectric layer 258.

[0054] The portion of the gate structure 280 shown in Figure 23 is the portion located between the gate spacers 138. The gate structure 280 also includes portions (not shown) located perpendicular to the first semiconductor layer 106 (or perpendicular to the semiconductor layer 206) (Figure 22). In some embodiments, in the CFET described above, the first transistor 282 is a FET of a first conductivity type and includes the gate structure 280. The second transistor 284 is a FET of a second conductivity type opposite to the first conductivity type and includes the gate structure 274. In such embodiments, the dipole layer 256 of the gate structure 280 and the dipole layer 256 of the gate structure 274 comprise the same material. Because the relative positions of the first transistor 282 and the dipole layer 256 in the gate structure 274 and the gate structure 280 are different, the conductivity types of the first transistor 282 and the second transistor 284 are different. In some embodiments, the first transistor 282 and the second transistor 284 are located in the same layer. For example, the first transistor 282 is located in the PMOS region, while the second transistor 284 is located in the NMOS region adjacent to the PMOS region along the X or Y direction. The first transistor includes a gate structure 280, and the second transistor includes a gate structure 274. The dipole layers 256 of the gate structures 280 and 274 are made of the same material.

[0055] This disclosure provides a semiconductor device structure and a method for forming the same. In some embodiments, the semiconductor device structure includes a first gate structure 174 and a second gate structure 274 disposed above the first gate structure 174. The first gate structure 174 and the second gate structure 274 are formed using different processes and include different numbers of layers. The second gate structure 274 is formed using a low-processing-temperature process. Some embodiments offer advantages. For example, at low processing temperatures, the material of the first gate structure 174 does not degrade because the second gate structure 274 is formed after the first gate structure 174 is formed.

[0056] One embodiment is a CFET structure. This structure includes a first transistor comprising a first gate structure, the first gate structure comprising a first number of dielectric layers and a first conductivity type dipole dopant, wherein the peak concentration of the first conductivity type dipole dopant is located at the interface between a first interface layer of the first number of dielectric layers and the first gate dielectric layer. The structure also includes a second transistor disposed above the first transistor, and the second transistor comprising a second gate structure comprising a second number of dielectric layers and a second conductivity type dipole dopant of the opposite type to the first conductivity type, the second number being different from the first number, and the peak concentration of the second conductivity type dipole dopant being located in the dipole layer of the second number of dielectric layers.

[0057] Another embodiment is a semiconductor device structure. This structure includes a semiconductor layer, a first source / drain region disposed on a first side of the semiconductor layer, a second source / drain region disposed on a second side of the semiconductor layer opposite to the first side, and a first gate structure disposed above the semiconductor layer. The first gate structure includes a first interface layer and a dipole layer adjacent to the first interface layer. The thickness of the dipole layer ranges from about 3 angstroms to about 5 angstroms.

[0058] A further embodiment is a method of forming a semiconductor device structure. This method includes forming a first gate structure over a semiconductor layer. The method of forming the first gate structure includes depositing a first gate dielectric layer, depositing a first dipole layer on the first gate dielectric layer, and performing a thermal treatment to diffuse a dopant from the first dipole layer into the first gate dielectric layer. The thermal treatment has a first processing temperature. The method of forming the first gate structure further includes removing the first dipole layer. The method further includes forming a second gate structure over the first gate structure. The method of forming the second gate structure includes depositing a first interface layer, depositing a second dipole layer, and depositing a second gate dielectric layer on the second dipole layer. The processes of depositing the first interface layer, depositing the second dipole layer, and depositing the second gate dielectric layer have a second processing temperature lower than the first processing temperature.

[0059] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the scope of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

[0060] 100: Semiconductor Device Structure 101:Substrate 104: Semiconductor layer 106: First semiconductor layer 108: Second semiconductor layer 112: Fin Structure 114: Trench 116: Substrate portion 118: Insulating materials 120: Isolation Zone 130: Gate structure 132: Gate dielectric layer 134: Sacrificial Gate Layer 136: Masking layer 138: Gate spacer 144: Dielectric spacer 146: Source / Drain Region (S / D Region) 162: Contact Etching Stop Layer (CESL) 163: Dielectric layer 164: ILD layer 166: Dielectric Materials 169:IL 170: Gate dielectric layer 172: Gate Layer 174: Gate Structure 200: Structure 201:Substrate 202: Dielectric layer 203: Dielectric layer 204: Semiconductor layer 206: Semiconductor layer 208: Semiconductor layer 230: Sacrificial gate structure 232: Gate dielectric layer 234: Sacrificial Gate Layer 238: Gate spacer 244: Dielectric spacer 246: S / D area 250: Interface Layer (IL) 252: Gate dielectric layer 254:IL 256: Dipole Layer 258: Gate dielectric layer 260: Gate layer 262:CESL 264: ILD layer 274: Gate Structure 280: Gate structure 282: First Transistor 284: Second transistor AA: Line BB: Line CC: Line

[0061] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A complementary field-effect transistor structure, comprising: A first transistor includes a first gate structure, wherein the first gate structure includes a first number of dielectric layers and a dipole dopant of a first conductivity type, wherein a peak concentration of the dipole dopant of the first conductivity type is located at an interface between a first interface layer and a first gate dielectric layer of the first number of dielectric layers, wherein the first gate structure includes the first interface layer, the first gate dielectric layer, and a first gate layer; and a second transistor is disposed above the first transistor and includes a second gate structure, wherein the second gate structure includes a second number of dielectric layers and a first conductivity type. A second type of dipole dopant with opposite conductivity, wherein the second quantity is different from the first quantity, wherein the second gate structure includes a second interface layer, a second gate dielectric layer surrounded by the second interface layer, a third interface layer surrounded by the second gate dielectric layer, a dipole layer surrounded by the third interface layer, a third gate dielectric layer surrounded by the dipole layer, and a second gate layer surrounded by the third gate dielectric layer, wherein the dipole layer is in contact with the third interface layer, and a peak concentration of the second type of dipole dopant is located in the dipole layer of the second quantity of dielectric layers.

2. The complementary field-effect transistor structure as described in claim 1, wherein, The second interface layer and the third interface layer are formed using different processes.

3. The complementary field-effect transistor structure as described in claim 1, wherein the second gate dielectric layer and the third gate dielectric layer substantially do not contain dipole dopants of the second conductivity type.

4. The complementary field-effect transistor structure as described in claim 1, wherein, The first interface layer and the second interface layer have the same thickness, and the thickness of the first interface layer is greater than the thickness of the third interface layer.

5. The complementary field-effect transistor structure as described in claim 4, wherein, The total thickness of the second gate dielectric layer and the third gate dielectric layer is the same as the thickness of the first gate dielectric layer.

6. A semiconductor device structure, comprising: A semiconductor layer; A first source / drain region is disposed on a first side of the semiconductor layer; A second source / drain region is disposed on a second side of the semiconductor layer opposite to the first side; A first gate structure is disposed above the semiconductor layer, wherein the first gate structure includes: a first interface layer; and a first gate dielectric layer surrounded by the first interface layer; a second interface layer surrounded by the first gate dielectric layer; a dipole layer surrounded by the second interface layer and in contact with the second interface layer, wherein the thickness of the dipole layer is in the range of about 3 angstroms to about 5 angstroms; a second gate dielectric layer surrounded by the dipole layer; and a gate layer surrounded by the second gate dielectric layer.

7. The semiconductor device structure as described in claim 6 further includes a second gate structure disposed below the first gate structure.

8. The semiconductor device structure as claimed in claim 6, wherein the dipole layer comprises a metal and oxygen, nitrogen, carbon, or a combination thereof.

9. A method for forming a semiconductor device structure, comprising: Forming a first gate structure over a semiconductor layer includes: depositing a first gate dielectric layer; depositing a first dipole layer on the first gate dielectric layer; performing a thermal process to diffuse a dopant from the first dipole layer into the first gate dielectric layer, wherein the thermal process has a first process temperature; and removing the first dipole layer; and forming a second gate structure over the first gate structure includes: depositing a first interface layer; depositing a second dipole layer; and depositing a second gate dielectric layer on the second dipole layer, wherein the processes of depositing the first interface layer, depositing the second dipole layer, and depositing the second gate dielectric layer have a second process temperature lower than the first process temperature.

10. The method as described in claim 9, wherein forming the first gate structure further includes forming a second interface layer through a first process different from a second process for depositing the first interface layer.

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