Semiconductor structures and methods for fabricating the same

Abstract

A method of manufacturing a semiconductor structure includes: providing a structure including a substrate and a fin-like structure protruding from the substrate; forming an isolation structure on the substrate and adjacent to the sidewalls of the fin-like structure; forming a protective layer on the isolation structure; growing source / drain components on the source / drain regions of the fin-like structure; depositing a contact etch stop layer (CESL) on the source / drain components; depositing a first interlayer dielectric (ILD) layer, a capping layer, and a second ILD layer on the CESL; forming source / drain contact plugs in the first ILD layer to electrically couple the source / drain components; forming a metal silicon layer between the source / drain components and the source / drain contact plugs; thinning the substrate from the bottom of the structure; forming an opening to expose the bottom surface of the source / drain contact plugs and the bottom surface of the protective layer; and depositing a back-side conductive component in the opening.

Description

Technical Field

[0001] The present invention relates to a structure and a method for manufacturing the same, and particularly to a semiconductor structure and a method for manufacturing the same. Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to several generations of ICs, each featuring smaller and more complex circuits than the previous generation. During the evolution of ICs, functional density (i.e., the number of interconnects per unit wafer area) typically increases while geometry (i.e., the smallest component (or line) that can be manufactured using a process) decreases. This miniaturization process usually benefits by increasing production efficiency and reducing associated costs.

[0003] This miniaturization also increases the complexity of integrated circuit fabrication and manufacturing. To achieve these advancements, similar progress is needed in integrated circuit fabrication and manufacturing. While existing structures and methods generally meet the intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0004] Some embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising: forming a stack on a substrate, the stack including an interleaved plurality of first semiconductor layers and a plurality of second semiconductor layers; patterning the stack and the top of the substrate to form a first active region and a second active region protruding from the bottom of the substrate and extending longitudinally in one direction, the first active region including a first fin substrate and a first stack of semiconductor layers on the first fin substrate, the second active region including a second fin substrate and a second stack of semiconductor layers on the second fin substrate; forming an isolation structure between the first active region and the second active region; depositing a protective layer on the isolation structure; forming a dummy gate stack across the first active region and the second active region, the dummy gate stack intersecting with the top surface of the protective layer; depositing gate spacers on the sidewalls of the dummy gate stack; etching the first active region and the second active region outside the dummy gate stack and the gate spacers to form a first trench and a second trench, respectively; and in the first trench... A first source / drain component is formed in a trench, and a second source / drain component is formed in a second trench, wherein a portion of the first source / drain component is overhanged on an isolation structure, and a portion of the second source / drain component is overhanged on an isolation structure; a dummy gate stack is removed to form a gate trench, the gate trench exposing a protective layer; a second semiconductor layer is removed from the gate trench; a gate structure is deposited in the gate trench, the gate structure intersecting the top surface of the protective layer; source / drain contacts are formed on the first source / drain component, the source / drain contacts being connected to the first source / drain component; the substrate is thinned to expose the back side of the isolation structure; a back-side dielectric structure is formed on the back side of the isolation structure; a back-side opening is formed through the back-side dielectric structure, exposing the bottom surface of the protective layer, the bottom surface of the source / drain contacts, and the sidewalls of the gate spacers; and a conductive component is formed in the back-side opening, the conductive component being electrically connected to the source / drain contacts.

[0005] Other embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising: providing a structure including a substrate and a fin-like structure protruding from the substrate; forming an isolation structure on the substrate and adjacent to the sidewalls of the fin-like structure; forming a protective layer on the isolation structure; epitaxially growing source / drain components on the source / drain regions of the fin-like structure; depositing a contact etch stop layer (CESL) on the source / drain components; and depositing a first interlayer dielectric on the CESL. ILD layer; deposit capping layer on the top surface of CESL and the top surface of the first ILD layer; deposit second ILD layer on the capping layer; form source / drain contact plugs disposed in the first ILD layer for electrical coupling to source / drain components; form a metal silicate layer disposed between the source / drain components and the source / drain contact plugs, wherein the conductivity of the metal silicate layer is between the conductivity of the source / drain components and the conductivity of the source / drain contact plugs, wherein the metal silicate layer includes a curved profile; thin the substrate from the bottom of the structure until the isolation structure is exposed; form an opening to expose the bottom surface of the source / drain contact plugs and the bottom surface of the protective layer; and deposit back-side conductive components in the opening.

[0006] Some embodiments of the present invention provide a semiconductor structure, including: one or more nanostructures disposed on a semiconductor fin substrate; an isolation structure disposed on one side of the semiconductor fin substrate; a protective layer disposed on the isolation structure and below the bottom surface of the one or more nanostructures; a first source / drain component and a second source / drain component connected by the one or more nanostructures; a gate structure disposed on the one or more nanostructures and intersecting with the top surface of the protective layer; a gate spacer extending along the sidewall of the gate structure and intersecting with the top surface of the protective layer; a source / drain contact disposed on and electrically coupled to the first source / drain component, wherein the conductivity of the source / drain contact is greater than the conductivity of the first source / drain component; and a back-side conductive component landing on the bottom surface of the protective layer and the bottom surface of the source / drain contact, wherein the back-side conductive component is electrically isolated from the gate structure by the gate spacer and the protective layer. Simple Explanation of the Diagram

[0007] The various aspects of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only used for illustrative purposes. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of this disclosure. According to one or more aspects of this disclosure, Figure 1 illustrates a flowchart of a method for forming a semiconductor structure. According to one or more aspects of this disclosure, Figure 2 illustrates a partial top view of an example semiconductor structure during various manufacturing stages of the method in Figure 1. According to one or more aspects of this disclosure, Figures 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43 and 44 illustrate partial cross-sectional views of example semiconductor structures during various manufacturing stages in the method of Figure 1. Implementation

[0008] The following provides many different embodiments or examples to implement different features of the embodiments disclosed herein. Specific examples of components and configurations are described below to simplify the embodiments disclosed herein. Of course, these are merely examples and are not intended to limit the embodiments disclosed herein. For example, the following description, referring to the formation of a first component above or on a second component, may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component is formed between the first and second components, such that the first and second components do not need to be in direct contact.

[0009] Furthermore, the embodiments of the present invention may repeat element symbols and / or letters in many examples. These repetitions are for simplification and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed. Moreover, the following disclosure of forming, connecting to, and / or coupling to one component on another may include embodiments where the components are formed in direct contact, and may also include embodiments where additional components may be formed to insert into the component so that the components are not in direct contact. In addition, spatially relative terms, such as “lower,” “higher,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “up,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.), are used to describe the relationship between one component and another in this disclosure. Spatially relative terms are used to include different orientations of the device (including components). Furthermore, when using terms such as "approximately" or "around" to describe a number or range of numbers, this terminology is intended to cover a reasonable range of numbers that takes into account the inherent variations in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing parts with the characteristics associated with that number, the number or range of numbers covers a reasonable range that includes the number, such as within + / - 10% of the number. For example, those skilled in the art know that the manufacturing tolerance associated with a deposited material layer is + / - 15%, and a material layer with a thickness of "approximately 5 nanometers" can cover a size range of 4.25 nanometers to 5.75 nanometers.

[0010] As integrated circuit dimensions continue to shrink, so do power rails. This inevitably leads to an increase in voltage drop across the power rails and increased power consumption of the integrated circuit. One area of ​​interest is how to form power rails and vias with lower resistance and lower coupling capacitance on the back side of the IC. The size of the back-side power rails can be wider than the first metal layer (M0) rails on the front side of the structure, which helps to reduce power rail resistance.

[0011] Feedthrough vias (FTVs) are used to connect signals from the front side of a wafer to the back side. This allows for flexibility in forming semiconductor components on both the front and back sides of a semiconductor structure. However, forming feedthrough vias presents challenges when surrounded by components such as active regions, metal gates, and conductive parts. Therefore, while existing semiconductor structures generally meet their intended uses, they are not satisfactory in all aspects.

[0012] This disclosure generally relates to semiconductor structures and manufacturing processes, and more specifically to semiconductors having feedthrough vias (FTVs) and protective layers for isolating the FTVs from adjacent gate structures. In some embodiments, the structure disclosed includes a first active region and a second active region, an isolation structure disposed between the first and second active regions, a protective layer disposed on the isolation structure, a gate structure disposed above and across the first and second active regions and intersecting the top surface of the protective layer, and a gate spacer disposed along the sidewall of the gate structure. In some embodiments, the source / drain regions of the first and second active regions include source / drain components adjacent to the gate spacer. In some embodiments, the structure further includes source / drain contacts disposed above and electrically connected to the source / drain components, and an FTV disposed below and connected to the source / drain contacts. The FTV is separated from the gate structure by the gate spacer and the protective layer. By providing the protective layer, the etching control of the gate trench for the gate structure can be improved, the direct contact between the gate structure and the FTV can be reduced, and the leakage current margin between the gate structure and the FTV can be increased.

[0013] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, according to an embodiment of the disclosure, Figure 1 shows a flowchart of a method 100 for forming a semiconductor structure. The method 100 is described below in conjunction with Figures 2 through 44. Figure 2 is a partial top view of a structure 200 manufactured according to an embodiment of the method 100 of Figure 1. Figures 3 through 44 are partial cross-sectional views of the structure 200 at different stages of an embodiment of the method 100 of Figure 1. Figures 3 to 6, 19, 23, 25, 29, 31, 34, 38, 41, 43, and 44 are partial cross-sectional views taken along line AA of Figure 2; Figures 7, 8, 12 to 14, 18, 22, 26, 30, and 32 are partial cross-sectional views taken along line BB of Figure 2; Figures 9, 15, 28, 36, and 39 are partial cross-sectional views taken along line CC of Figure 2; and Figures 10, 11, 16, 17, 20, 21, 24, 27, 33, 35, 37, 40, and 42 are partial cross-sectional views taken along line DD of Figure 2. Method 100 is merely an example and is not intended to limit this disclosure to what is explicitly described in Method 100. Additional steps may be provided before, during, and after Method 100, and some described steps may be replaced, eliminated, or moved in additional embodiments of Method 100. For simplicity, not all steps are described in detail here. Since structure 200 will be fabricated as a semiconductor structure, it may be referred to as semiconductor structure 200 or semiconductor device 200, depending on the context. To avoid ambiguity, the X, Y, and Z directions in Figures 2 through 44 are perpendicular to each other and are used consistently throughout this disclosure. In this disclosure, unless otherwise stated, the same designations denote the same parts. That is, the material properties of the various numbered elements described in relation to a method or drawing, and their comparisons, apply to the same numbered elements described in relation to different methods or different drawings.

[0014] Referring to Figures 1 and 3, method 100 includes step 102, forming or providing structure 200. Structure 200 includes a stack 204 of alternating semiconductor layers formed on substrate 202.

[0015] In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include various doping configurations known in the art, depending on design requirements. In embodiments where the semiconductor device is p-type, an n-type doping distribution (i.e., an n-type well or n-well) may be formed on substrate 202. In some embodiments, the n-type dopant used to form the n-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor device is n-type, a p-type doping distribution (i.e., a p-type well or p-well) may be formed on substrate 202. In some embodiments, the p-type dopant used to form the p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of the dopant. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Alternatively, substrate 202 may include compound semiconductors and / or alloy semiconductors. In addition, the substrate 202 may optionally include an epi-layer, which may be strained to enhance performance, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable reinforcing components.

[0016] In some embodiments, the stack 204 on top of the substrate 202 includes staggered channel layers 208 of a first semiconductor combination and sacrificial layers 206 of a second semiconductor combination. Alternatively, the sacrificial layers 206 and channel layers 208 may be staggered. The first and second semiconductor compositions are different. In some embodiments, the sacrificial layer 206 comprises silicon germanium (SiGe) or germanium tin (GeSn), and the channel layers 208 comprise silicon (Si). It should be understood that the alternating arrangement of three (3) sacrificial layers 206 and three (3) channel layers 208, as shown in Figure 3, is for illustrative purposes only and is not intended to limit the scope specifically described in the claim. It should be understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the performance requirements of the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0017] The sacrificial layer 206 and channel layer 208 in stack 204 can be deposited using molecular beam epitaxy (MBE), vapor deposition (VPE), and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, and the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the Ge% in the sacrificial layer 206 may be not less than about 20%, for example, about 30% or more. In some embodiments, the sacrificial layer 206 and channel layer 208 are substantially dopant-free (i.e., have an intrinsic dopant concentration from about 0 atoms / cm³ to about 1 x 10¹⁷ atoms / cm³), wherein, for example, no intentional doping is performed during the epitaxial growth process of stack 204.

[0018] Referring to Figures 1, 2 and 4, method 100 includes step 104, forming a fin structure 212 from the stack 204 and the substrate 202.

[0019] To pattern the stack 204, a hard mask layer can be deposited over the stack 204 to form an etch mask. The hard mask layer can be a single layer or multiple layers. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer disposed above the pad oxide layer. The fin structure 212 can be patterned from the stack 204 and the substrate 202 using lithography and etching processes. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. As shown in Figure 4, the etching process of step 104 forms trenches that extend vertically through the stack 204 and a portion of the substrate 202. The trenches define the fin structure 212. In some embodiments, a dual-patterning or multi-patterning process can be used to define the fin structure, for example, with a pitch smaller than that achievable using a single direct lithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a lithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the fin structure 212 can then be patterned using the remaining spacers or mandrel through etching the stack 204 and a portion of the substrate 202. As shown in Figure 4, the fin structure 212 extends vertically along the Z-direction and longitudinally along the Y-direction. The fin structure 212 provides an active region (also referred to as active region 212) for the subsequently formed transistor, which includes a channel region (labeled 212C, as shown in Figure 7) and a source / drain region (labeled 212SD, as shown in Figure 7). As shown in Figure 4, the fin structure 212 includes a fin substrate 212B patterned by the substrate 202 and a patterned stack 204 disposed directly above the fin substrate 212B. In the embodiment shown in Figure 4, the top of the patterned stack 204 and the fin substrate 212B has generally straight sidewalls; while the bottom of the fin substrate 212B has tapered sidewalls due to the load effect in the patterning process.

[0020] Referring to Figures 1 and 4, method 100 includes step 106, forming an isolation structure 214 (or isolation member 214) around the fin base 212B of the fin structure 212, and forming a protective layer 215 over the isolation structure 214. The layer B214 on the bottom surface of the isolation structure 214 can be shown by dashed lines.

[0021] In some embodiments shown in Figure 4, an isolation structure 214 is disposed on the sidewall of the fin substrate 212B. In some embodiments, the isolation structure 214 may be formed in a trench to isolate adjacent active regions located in the fin structure 212. In some embodiments, the isolation structure 214 is a shallow trench isolation (STI) component 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202, and the trench is filled with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In some embodiments, the dielectric layer includes silicon oxide. In various examples, the dielectric layer may be deposited via chemical vapor deposition (CVD), subatmospheric pressure CVD (SACVD), flow CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, through a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further etched or pulled back using dry etching, wet etching, and / or a combination thereof to form the isolation structure 214 shown in Figure 4. In the illustrated embodiment, the top surface of the isolation structure 214 has a recessed profile due to the loading effect during the etching process. After etching, the fin structure 212 rises above the isolation structure 214, while the fin substrate 212B is at least partially embedded in or masked within the isolation structure 214. In the illustrated embodiment, the top edge of the recessed profile of the isolation structure 214 intersects with the sidewall of the fin substrate 212B.

[0022] Referring again to Figures 1 and 4, a protective layer 215 is formed over the isolation structure 214 and around the top of the fin-like substrate 212B. The composition of the protective layer 215 differs from that of the isolation structure 214. In some embodiments, the isolation structure 214 comprises silicon oxide (SiOx, e.g., SiO2), and the protective layer 215 comprises silicon nitride (SixNy, e.g., SiN, Si3N4), silicon carbide nitride (SiCN), or silicon oxynitride (SiON). The protective layer 215 may have a nitrogen concentration of about 50% to about 70%. For example, in some embodiments, a nitride-containing material is first deposited over the isolation structure 214 to fill the trenches. In various examples, the nitride-containing material can be deposited using CVD processes, subatmospheric pressure CVD (SACVD) processes, flow CVD processes, spin coating processes, and / or other suitable processes. The deposited nitride-containing material is then thinned and planarized, for example, through a chemical mechanical polishing (CMP) process. A protective layer 215 is formed by further etching or pulling back the planarized nitride-containing material using dry etching, wet etching, and / or a combination thereof. In the illustrated embodiment, the top surface of the protective layer 215 has a recessed profile due to the loading effect during the etching process. After etching, the fin structure 212 is higher than the protective layer 215. In the illustrated embodiment, the top edge of the recessed profile of the protective layer 215 intersects with the sidewall of the fin substrate 212B. Alternatively, the top edge of the recessed profile of the protective layer 215 may intersect with the sidewall of the bottommost sacrificial layer 206, such that the fin substrate 212B is completely embedded or buried in the combination of the isolation structure 214 and the protective layer 215. The midpoint of the recessed profile of the protective layer 215 (e.g., the lowest point of the top surface) may be located below or above the bottom surface of the bottommost sacrificial layer 206. The fin substrate 212B is embedded or buried in the combination of the isolation structure 214 and the protective layer 215. The thickness T1 of the protective layer 215 can be from about 10 nm to about 50 nm, or from about 30 nm to about 50 nm. This range is not arbitrary or irrelevant. If T1 is less than about 10 nm, the protective layer 215 itself may be etched during subsequent etching processes due to limited etching contrast, thereby reducing its protective effect on the isolation structure 214. If T1 is greater than about 50 nm, the bottom sacrificial layer 206 may be buried underneath and difficult to remove in subsequent gate replacement processes.

[0023] Referring to Figure 5, in some alternative embodiments, a low-nitrogen layer 211 and / or an oxide layer 213 may be formed along the sidewalls of the finned substrate 212B prior to the formation of the isolation structure 214 and the protective layer 215. The low-nitrogen layer 211 and the oxide layer 213 may each have a different composition than the protective layer 215 and the isolation structure 214. In some embodiments, the low-nitrogen layer 211 comprises silicon nitride (e.g., SixNy) and has a nitrogen concentration of less than about 10%, for example, from about 2% to about 10%. In some embodiments, the oxide layer 213 comprises a high-temperature oxide material. In some embodiments, the oxide layer 213 comprises silicon oxide (SiOx, e.g., SiO2), and its oxygen concentration is different from (e.g., greater than) the oxygen concentration in the isolation structure 214. In some embodiments, the SiO2 concentration included in the oxide layer 213 is greater than the SiO2 concentration in the isolation structure 214. For example, the low-nitrogen layer 211 can be formed by blanketing a dielectric material layer over the structure 200 in a compliant manner, using processes such as chemical vapor deposition (CVD), subatmospheric pressure CVD (SACVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable processes. In the illustrated embodiment, an etch-back process (e.g., anisotropic) is performed after the dielectric material layer is deposited to remove the dielectric material layer from the horizontal surface and the sidewalls of the patterned stack 204. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. In some embodiments, the etch-back process includes a directional etching process (e.g., tilted plasma etching), in which an ion beam may be directed at a tilt angle relative to the Z-direction to the surface of the structure 200. In some embodiments, the top surface and sidewalls of the patterned stack 204 and the top surface of the substrate 202 in the trench are exposed after the etch-back process. A dielectric material layer may be retained on the sidewalls of the fin substrate 212B as a low-NOx layer 211. An oxide layer 213 may be similarly formed by conformally depositing another dielectric material layer on the structure 200 and performing an etch-back process. The low-NOx layer 211 and oxide layer 213 may each have a thickness of about 3 nm to about 7 nm. In some embodiments, the top edge of the recessed profile of the protective layer 215 intersects the sidewalls of the oxide layer 213. The low-NOx layer 211 and oxide layer 213 may protect the fin substrate 212B and the isolation structure 214 in subsequent processes (e.g., when removing the dummy gate stack and sacrificial layer 206). The low-NOx layer 211 and oxide layer 213 are not shown in subsequent figures, but it will be understood that they may be included in the structure 200 of the subsequent figures.

[0024] Referring to Figures 1, 2, 6, and 7, method 100 includes step 108, forming a dummy gate stack 220 and a gate spacer 226 above the channel region 212C of the fin structure 212. The dummy gate stack 220 serves as a placeholder for various processes and will be removed to be replaced by a functional gate structure. Other processes and configurations are also possible. The dummy gate stack 220 extends longitudinally along the Y direction as shown in Figure 2. As shown in Figure 7, the dummy gate stack 220 and the gate spacer 226 are formed above the fin structure 212, and the fin structure 212 can be divided into the channel region 212C located below the dummy gate stack 220 and the gate spacer 226, and the source / drain region 212SD not located below the dummy gate stack 220 and the gate spacer 226. The channel region 212C is adjacent to the source / drain region 212SD. As shown in Figure 7, the channel region 212C is disposed along the X direction between the two source / drain regions 212SD. As used in this disclosure, the source / drain region or "S / D region" may refer to a region that provides a source and / or drain for one or more devices. It may also refer to the source or drain of one or more devices.

[0025] The formation of the dummy gate stack 220 may include depositing layers in the dummy gate stack 220 and patterning these layers. Referring to Figure 6, a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 may be deposited over the semiconductor device 200. The dummy dielectric layer 216 may be deposited compliantly on the fin structure 212 using chemical vapor deposition (CVD), atomic layer deposition (ALD), oxygen plasma oxidation, or other suitable processes. This disclosure conveniently describes layers having a generally uniform thickness over various regions using the term "compliantly." In some cases, the dummy dielectric layer 216 may include silicon oxide. Subsequently, a dummy electrode layer 218 may be deposited over the dummy dielectric layer 216 using CVD, ALD, or other suitable processes. In some cases, the dummy electrode layer 218 may include polycrystalline silicon. For patterning purposes, a gate-top hard mask layer 222 can be deposited on the dummy electrode layer 218 using CVD, ALD, or other suitable processes. The gate-top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, as shown in Figure 7. For example, the patterning process can include lithography (e.g., lithography or electron beam lithography) and etching processes. The lithography process can also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The lithography process forms a patterned photoresist layer. Then, in the etching process, the patterned photoresist layer is used as an etching mask to pattern the gate-top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 is a two-layer structure, which may include a silicon oxide layer and a silicon nitride layer located above the silicon oxide layer.

[0026] The formation of the gate spacer 226 may include the deposition of a gate spacer layer and the etch-back of the gate spacer layer. In some embodiments, the gate spacer layer is compliantly deposited over the semiconductor device 200, including over the top surface and sidewalls of the dummy gate stack 220. The gate spacer layer may be a single layer or multiple layers. At least one of the gate spacer layers may include silicon carbide, silicon oxide, silicon carbide, or silicon nitride. The gate spacer layer may be deposited over the dummy gate stack 220 using, for example, a CVD process, a subatmospheric pressure CVD (SACVD) process, an ALD process, or other suitable processes. Subsequently, an anisotropic etching process may be performed to remove the horizontal portion of the gate spacer layer from the top surface of the semiconductor device 200 (including the top surface of the dummy gate stack 220). The remaining vertical portion of the gate spacer layer covers the sidewalls of the dummy gate stack 220 as gate spacer 226.

[0027] Referring to Figures 1 and 8 through 11, method 100 includes step 110, anisotropically etching the source / drain region 212SD of the fin structure 212 to form a source / drain groove 228. The anisotropic etching may include dry etching or a suitable etching process that etches the source / drain region 212SD and a portion of the substrate 202. The resulting source / drain groove 228 extends vertically through the depth of the stack 204 and partially into the substrate 202 (i.e., the fin substrate 212B is partially etched). An example dry etching process for step 110 may employ oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. As shown in Figure 8, the source / drain region 212SD of the fin structure 212 is etched to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain groove 228 extends below the stack 204 into the substrate 202, the source / drain groove 228 includes a bottom surface and a lower sidewall defined in the substrate 202.

[0028] As shown in Figure 9, above the source / drain region 212SD, most of the fin structure 212 is etched, exposing the top surface of the fin substrate 212B within the source / drain region 212SD. Furthermore, the recessed top surface of the fin substrate 212B may be lower than the top surface of the protective layer 215. Since the etching rate of the gate spacer 226 is lower than that of the fin structure 212, the gate spacer 226 in the source / drain region 212SD is higher than the top surface of the fin substrate 212B. The remaining gate spacer 226 in the source / drain region 212SD is also referred to as a fin spacer. The fin spacer protects a portion of the protective layer 215 directly beneath it from being removed during the etching process of the source / drain region 212SD.

[0029] As shown in Figure 10, between adjacent fin structures 212, the bottom surface of the dummy gate stack 220 and the gate spacers 226 fall directly above the top surface of the protective layer 215. In the embodiment shown in Figure 10, the etching process performed during the etching process of the source / drain region 212SD also etches through the protective layer 215 between the opposing gate spacers 226. Therefore, due to limited etching contrast, the top of the exposed isolation structure 214 may also suffer some etching loss. This etching process expands the cavity below the protective layer 215 (i.e., the bottom of the trench 228), making the cavity width exceed the lateral spacing between the opposing gate spacers 226. In other words, a portion of the cavity may extend directly below the gate spacers 226. Furthermore, the bottom of the protective layer 215 may be etched laterally, giving the segments of the protective layer 215 an inverted trapezoidal appearance. In some embodiments, the anisotropic etching process that removes the horizontal portion of the gate spacer layer in step 108 may also etch at least a portion of the protective layer 215 between opposing gate spacers 226. In the illustrated embodiment, the trench 228 may have a width W1 between opposing gate spacer layers 226, a width W2 between opposing protective layers 215, and a width W3 between opposing sidewalls of the isolation structure 214. In some embodiments, the width W3 is greater than the width W2, and the width W2 is greater than the width W1. Referring to Figure 11, in some alternative embodiments, the bottom of the protective layer 215 is not etched laterally. The trench 228 may have a width W2' between opposing protective layers 215, the width W2' being the same as the width W1 and less than the width W3. In some embodiments, the bottom surface of the trench 228 is curved.

[0030] Referring to Figures 1 and 12, method 100 includes step 112, forming an inner spacer recess 232. The sacrificial layer 206 is selectively and partially etched to form the inner spacer recess 232. The inner spacer recess 232 may have a rectangular profile as shown. Alternatively, the inner spacer recess 232 may have a concave profile curved away from the source / drain recess 228. Different compositions allow the sacrificial layer 206 of the stack 204 exposed in the source / drain recess 228 to be selectively and partially etched to form the inner spacer recess 232, while the exposed channel layer 208 is largely unetched. In embodiments where the channel layer 208 is largely composed of Si and the sacrificial layer 206 is largely composed of SiGe, the selective etching of the sacrificial layer 206 may include a SiGe oxidation process followed by removal of the SiGe oxide. In these embodiments, the SiGe oxidation process may include the use of ozone. In some embodiments, selective etching may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent of etching of the sacrificial layer 206 is controlled by the duration of the etching process. In some embodiments, a selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The inner spacer recess may extend inward in the X direction from the source / drain recess 228. In some embodiments, a selective wet etching process may include hydrofluoric acid (HF) or NH4OH etchant.

[0031] Referring to Figures 1 and 13, method 100 includes step 114, forming an inner spacer 236 in an inner spacer recess 232. Forming the inner spacer 236 may include depositing an inner spacer layer on the exposed surface of the source / drain recess 228, including filling the inner spacer recess 232. In some embodiments, the inner spacer layer may include silicon carbide (SiCN), silicon oxycarbonate (SiOCN), silicon nitride (SiN), silicon carbon oxyoxide (SiOC), or silicon oxynitride (SiON). In some embodiments, the inner spacer layer may be deposited using CVD or ALD. Subsequently, the inner spacer layer is etched back to form the inner spacer 236 in the inner spacer recess 232. In some embodiments, the etching back of the inner spacer layer may include using a dry etching process, such as a reactive ion etching (RIE) process using plasma. Example dry etching processes may include the use of boron trichloride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), methane (CH4), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen (N2), or combinations thereof. In the illustrated embodiment, the inner spacer 236 is generally retained below the gate spacer 226 and does not extend directly below the dummy gate stack 220. Alternatively, the inner spacer 236 may extend laterally directly below the dummy gate stack 220.

[0032] Referring to Figures 1, 14, and 15, method 100 includes step 116, forming a source / drain component 244 over the source / drain region 212SD. Although not explicitly shown, method 100 may include a cleaning process to clean the surface of structure 200 before forming any epitaxial layer. The cleaning process may include dry cleaning, wet cleaning, or a combination of dry and wet cleaning. In some examples, wet cleaning may include using deionized (DI) water, a mixture of ammonium hydroxide and hydrogen peroxide, a mixture of DI water, hydrochloric acid and hydrogen peroxide, SPM (sulfur peroxide mixture), and / or hydrofluoric acid to remove oxides. Dry cleaning processes may include helium (He) and hydrogen (H2) treatment.

[0033] Depending on the context, source / drain component 244 may refer individually or collectively to a source or drain. Source / drain component 244 is connected to channel region 212C. Each source / drain component 244 may be selectively epitaxially formed from an exposed semiconductor surface using epitaxial processes such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Example n-type source / drain components may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped during the epitaxial process by introducing an n-type dopant (e.g., phosphorus, arsenic, or antimony), or ex-situ doped using a junction implantation process. Example p-type source / drain components may include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and may be in-situ doped during the epitaxial process by introducing a p-type dopant (e.g., boron or gallium), or out-of-situ doped using a junction placement process. In some embodiments, each of the n-type and p-type source / drain components may include multiple semiconductor layers with different doping concentrations (e.g., as shown). The n-type and p-type source / drain components may be formed in any suitable order. One or more annealing processes may be performed to activate the dopants in the source / drain components 244. Annealing processes may include rapid thermal annealing (RTA) and / or laser annealing processes. As shown in Figure 15, in some embodiments, each source / drain component 244 may include a portion overhanging over the isolation structure 214 and the protective layer 215 in the YZ plane.

[0034] Referring to Figures 1 and 14 through 17, method 100 includes step 118, depositing a contact etch stop layer (CESL) 246 and a first interlayer dielectric (ILD) layer 248 in the source / drain region 212SD. As shown in Figures 14 and 15, CESL 246 is deposited over the source / drain component 244. As shown in Figure 15, fin spacers 226 are also covered by CESL 246. CESL 246 may comprise silicon nitride or aluminum nitride. In some embodiments, CVD or ALD may be used to deposit CESL 246. The first ILD layer 248 is then deposited over CESL 246. In some embodiments, the first ILD layer 248 comprises, for example, an oxide-based dielectric material, SiOx, SiON, SiC, tetraethylorthosilicate (TES) oxide, undoped silicate glass, or doped silica oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG)) and / or other suitable dielectric materials. The first ILD layer 248 can be deposited using CVD, flow CVD (FCVD), spin coating, or a suitable deposition technique. As shown in Figures 16 and 17, structures 200 fabricated according to the embodiments shown in Figures 10 and 11 are illustrated, with CESL 246 also lining the cavity beneath the protective layer 215. The bottom of CESL 246 and the first ILD layer 248 extends directly beneath the gate spacer 226 and is partially embedded in the isolation structure 214. After depositing the first ILD layer 248, the structure 200 can be planarized through a planarization process to remove the gate top hard mask layer 222 and expose the dummy electrode layer 218. For example, the planarization process may include a chemical mechanical planarization (CMP) process. After planarization, the top surfaces of CESL 246, the first ILD layer 248, the gate spacer 226, and the dummy electrode layer 218 are coplanar.

[0035] Referring to Figures 1 and 18-21, method 100 includes step 120, selectively removing the dummy gate stack 220 and subsequently selectively removing the sacrificial layer 206. At the end of the operation in step 118, the exposure of the dummy gate stack 220 allows for its removal. Removal of the dummy gate stack 220 may include one or more etching processes selectively targeting the material of the dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof selectively targeting the dummy gate stack 220 may be used to remove the dummy gate stack 220. Removal of the dummy gate stack 220 forms a gate trench 250 that exposes the stack of channel layer 208 and sacrificial layer 206. After removing the dummy gate stack 220, the sacrificial layer 206 in channel region 212C is exposed and then removed in a separate etching process. For example, a selective wet etching process or a selective dry etching process may be performed to remove the sacrificial layer 206. Example selective wet etching processes may include using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Example selective dry etching processes may include using anhydrous hydrogen fluoride (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or combinations thereof. After removing the sacrificial layer 206, the channel layer 208 is released as a channel component (hereinafter also referred to as channel component 208).

[0036] As shown in Figures 19 and 20, due to limited etching contrast, the etching process may partially etch the protective layer 215 to form trenches, causing the bottom surface of the gate trench 250 to extend below the original top surface of the protective layer 215 (shown as dashed lines). In some embodiments, the top of the protective layer 215 in the gate trench 250 may have a recessed profile. Nevertheless, the protective layer 215 prevents the gate trench 250 from extending through, thereby ensuring that the isolation structure 214 beneath the gate trench 250 remains intact. The protective layer 215 may have a thickness T2 in the gate trench 250. T2 may be from about 8 nm to about 50 nm. In some embodiments, the ratio of T2 to T1 is from about 1:4 to about 1:1. If the thickness T2 is too small or the ratio is too small, the protective layer 215 may be too thin to serve as a stop layer in subsequent processes. In some alternative embodiments, as shown in Figure 21, the protective layer 215 remains unetched during the etching process, and the thickness T2 is the same as the thickness T1.

[0037] Referring to Figures 1, 2, and 22-24, method 100 includes step 122, forming a gate structure 260 in a gate trench 250 to wrap around each channel member 208. The gate structure 260 is also referred to as a metal gate structure 260 due to its metal layer. In the illustrated embodiment, the gate structure 260 includes an interface layer 262 intersecting with the channel member 208, a high-k dielectric layer 264 above the interface layer 262, and a gate electrode layer 266 above the high-k dielectric layer 264. The interface layer 262 and the high-k dielectric layer 264 are collectively referred to as the gate dielectric layer.

[0038] Interface layer 262 may comprise a dielectric material of silicon oxide, hafnium silicate, or silicon oxynitride. Interface layer 262 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In the illustrated embodiment, interface layer 262 is formed by thermally oxidizing the semiconductor material exposed in the gate trench 250. Thus, interface layer 262 is formed on semiconductor surfaces, such as the exposed surface of channel member 208 and the top surface of fin substrate 212B, but not on dielectric surfaces, such as the sidewalls of inner spacer 236, the sidewalls of gate spacer 226, and the top surface of protective layer 215 (Figures 23 and 24). High-k dielectric layer 264 may comprise a high-k dielectric material, such as hafnium oxide. Alternatively, the high-k dielectric layer 264 may comprise other high-k dielectric materials, such as titanium dioxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The dielectric constant of the high-k dielectric layer 264 is greater than the dielectric constant of the gate spacer 226. The high-k dielectric layer 264 can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation and / or other suitable methods. As shown in Figures 23 and 24, the high-k dielectric layer 264 can be compliantly deposited on the dielectric surface exposed in the gate trench 250.

[0039] The gate electrode layer 266 includes a work function metal layer and a metal filler layer above the work function metal layer. The work function metal layer is a p-type work function metal layer in a p-type transistor or an n-type work function metal layer in an n-type transistor. The p-type work function metal layer includes, but is not limited to, metals selected from titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. The n-type work function metal layer includes, but is not limited to, metals selected from, titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. In some embodiments, the p-type or n-type work function metal layer includes a plurality of layers deposited through CVD, PVD, and / or other suitable processes. The metal filler layer includes aluminum, tungsten, cobalt, copper, and / or other suitable materials, and is formed through CVD, PVD, electroplating, and / or other suitable processes.

[0040] Referring to Figures 1, 2, and 25, method 100 includes an optional step 124, forming a gate isolation structure 270. The gate isolation structure 270 divides the originally continuous gate structure 260 into multiple segments, and may also be referred to as a cut-metal-gate (CMG) component 270. In some embodiments, the gate isolation structure 270 provides additional isolation between the FTV (to be formed) and the gate structure 260. The gate isolation structure 270 may be a single-layer or multi-layer structure. For a multi-layer structure, the gate isolation structure 270 may include a dielectric liner 272 and a dielectric filler layer 274. In the example process flow, forming the gate isolation structure 270 includes: etching the gate structure 260 to form a CMG trench that extends through the protective layer 215 and into the isolation structure 214 for better isolation; conformally depositing a dielectric liner 272 on the sidewalls and bottom surface of the CMG trench; depositing a dielectric filler layer 274 to fill the CMG trench; and performing a planarization process (e.g., CMP) to remove excess dielectric material portions. In some embodiments, the dielectric filler layer 274 is an oxide (e.g., silicon oxide), and the dielectric liner 272 is oxygen-free, such as a nitride (e.g., silicon nitride or silicon carbide nitride). The dielectric filler layer 274 can be deposited via ALD, CVD, PVD, or other suitable processes. The dielectric liner 272 and the dielectric filler layer 274 together define the gate isolation structure 270.

[0041] Referring to Figures 1, 2, and 26-28, method 100 includes step 126, forming a source / drain contact plug 280 and an optional silicon component 282 located between the source / drain contact plug 280 and the source / drain component 244 in the source / drain region 212SD. In the example process, a capping layer 276 (also referred to as an etch stop layer (ESL) 276) and a second ILD layer 278 are deposited on structure 200. In some embodiments, the thickness of the first ILD layer 248 is greater than the thickness of the second ILD layer 278. Subsequently, contact holes are formed by etching the second ILD layer 278, capping layer 276, first ILD layer 248, and ESL 246. The etching process can be a self-aligned process, such that a portion of the first ILD layer 248 on the source / drain component 244 is removed using the vertical sidewalls of the ESL 246 as an etch stop layer (e.g., as shown in Figures 26 and 27). Optionally, the upper portion of the source / drain component 244 can be etched to have a concave bottom as the contact hole, as shown in Figure 26. A silicide component 282 is formed at the bottom of the contact hole. The silicide component 282 may include titanium silicon silicide (TiSi), nickel silicon silicide (NiSi), tungsten silicon silicide (WSi), nickel platinum silicon silicide (NiPtSi), nickel platinum germanium silicon silicide (NiPtGeSi), nickel germanium silicon silicide (NiGeSi), ytterbium silicon silicide (YbSi), platinum silicon silicide (PtSi), iridium silicon silicide (IrSi), erbium silicon silicide (ErSi), cobalt silicon silicide (CoSi), or other suitable compounds. Subsequently, source / drain contact plugs 280 are formed on the silicide component 282. Each source / drain contact plug 280 may include a conductive barrier layer and a bulk metal layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The bulk metal layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes. The conductivity of the silicon component 282 is between that of the source / drain component 244 and the source / drain contact plug 280, and the conductivity of the source / drain contact plug 280 is greater than that of the source / drain component 244. The silicon component 282 and the source / drain contact plug 280 can be collectively referred to as the source / drain contact. As shown in Figure 27, in the DD cross-sectional view, the source / drain contact plug 280 extends further than in the BB cross-sectional view and rests directly at the bottom of the first ILD layer 248, without the silicon component 282 in between.Referring to Figures 2 and 28, in some embodiments, the source / drain contact plug 280 extends longitudinally along the Y direction. The source / drain contact plug 280 may be disposed above and connected to one or more source / drain components 244.

[0042] In some embodiments, referring to Figures 2 and 26, a gate via 284 is formed above and electrically connected to a source / drain contact plug 280, similar to a source / drain contact plug 280. The number, location, and size of the source / drain contact plug 280 and the gate via 284 in Figure 2 are merely examples and are not intended to limit the scope of this disclosure.

[0043] Referring to Figure 27, the source / drain recess 228 (as shown in Figures 10 and 11) is now filled with CESL 246, the first ILD layer 248, and a portion of the source / drain contact plug 280. The source / drain recess 228 has a depth D1 measured horizontally from the top surface of the gate structure 260, as shown. The gate structure 260 may have a height D2 as shown. In some embodiments, the ratio of height D2 to depth D1 is about 0.6 to about 0.8. If the ratio is too small (e.g., less than about 0.6), the depth D1 may be too large, and CESL 246 and the first ILD layer 248 may penetrate excessively into the isolation structure 214, meaning that too much etching is performed when etching the source / drain recess 228, and this may affect the performance of structure 200. If the ratio is too large (e.g., greater than about 0.8), the protective layer 215 may be penetrated by the gate structure 260, or it may be too thin to serve as a stop layer in subsequent processes. Gate spacer 226 may have a height D3. In some embodiments, height D2 is greater than height D3. In some other embodiments, height D2 is the same as height D3 when the protective layer 215 remains unetched at step 120 (e.g., as shown in Figure 21).

[0044] Referring to Figures 29 and 30, structure 200 can be flipped. This allows for further processing from the back side of structure 200. Structure 200 can be placed and attached to a carrier (not shown) using any suitable attachment process (e.g., direct bonding, hybrid bonding, adhesive bonding, or other bonding methods). The operations disclosed herein may also include alignment, annealing, and / or other processes. In some embodiments, the carrier may be a silicon wafer.

[0045] Referring to Figures 1 and 31-33, method 100 includes step 128, thinning structure 200 from the back side. In some embodiments, the thinning process may involve mechanical polishing and / or chemical thinning. First, a significant amount of substrate material is removed from substrate 202 by mechanical polishing. Subsequently, a chemical thinning process is employed, applying etching chemicals to the back side of substrate 202 for further thinning. In the illustrated embodiment, thinning is performed until isolation structure 214 is exposed. In such an embodiment, the thinning process utilizes isolation structure 214 as a thinning stop layer, ensuring that the process stops at the bottom surface of isolation structure 214 (e.g., at layer B214). In the illustrated embodiment, once isolation structure 214 is exposed, additional components, such as fin substrate 212B (Figures 31 and 32) and gate isolation structure 270 (Figure 31), are also exposed on the back side of structure 200. In other embodiments, thinning continues until protective layer 215 is exposed. In such an embodiment, the thinning process utilizes the protective layer 215 as a thinning stop layer to ensure that the process stops at the bottom surface of the protective layer 215. In some embodiments, thinning is performed such that a portion of the isolation structure 214 is removed while a portion of the isolation structure is retained, and the protective layer 215 is not exposed.

[0046] Referring to Figures 1, 34, and 35, method 100 includes step 130, forming a back-side dielectric layer on the back side of structure 200. The back-side dielectric layer may include a back-side etch stop layer (ESL) 286 and a back-side ILD layer 288. The composition and formation method of the back-side ESL 286 and the back-side ILD layer 288 may be similar to the composition and formation method of the capping layer 276 and the second ILD layer 278.

[0047] Referring to Figures 1 and 36 to 38, method 100 includes step 132, forming an FTV opening 290 from the back side of structure 200 to expose protective layer 215 and source / drain contact plug 280.

[0048] As shown in Figures 36 and 38, the FTV opening 290 is designed to penetrate the back-side ILD layer 288, the back-side ESL 286, the isolation structure 214, the CESL 246, and the first ILD layer 248 to expose the bottom surface of the source / drain contact plug 280 and the bottom surface of the guard layer 215. As shown in Figure 37, the FTV opening 290 may include a first partial opening 290a located below layer B215 on the bottom surface of the guard layer 215 and a second partial opening 290b located between the opposing gate spacer 226 and the guard layer 215.

[0049] The FTV opening 290 can be formed using lithography and etching processes. In an example process, a patterned mask (not explicitly shown) is formed on the back-side ILD layer 288, and then a first etching process is performed to use the patterned mask as an etching mask to form the first partial opening 290a. The first etching process can include any suitable process using any suitable etchant (e.g., dry etching, wet etching, or a combination thereof). An example dry etching process may employ oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, C4F8 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. The first etching process may use a protective layer 215 as a stop layer. After the first etching process is completed, the bottom surface of the protective layer 215 is exposed, and the first ILD layer 248 (as shown in Figure 35) between layer B215 and the source / drain contact plug 280 is exposed. A second etching process can be performed to form a second partial opening 290b. As described above, the first ILD layer 248 may include an oxide-based dielectric material, and the protective layer 215 may include a nitride-based material. The second etching process can be configured to etch the oxide-based dielectric material (e.g., silicon oxide) at a faster rate than etching silicon or nitride-based materials. In some embodiments, the second etching process uses the protective layer 215 as an etching mask. In some embodiments, the second etching process may include the use of fluorine-containing gases (e.g., carbon tetrafluoride (CF4), octafluorocyclobutane (C4F8), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), or sulfur hexafluoride (SF6)), chlorine-containing gases (e.g., chlorine (Cl2), oxygen (O2), or hydrogen (H2)). In some embodiments, a portion of CESL 246 and gate spacer 226 are also etched in the second etching process. The FTV opening 290 may have tapered sidewalls resulting from the etching process as shown in Figures 36-38, such that the width of the first portion opening 290a and the width of the second portion opening 290b gradually decrease from the back side to the front side (e.g., in the positive Z direction). By providing the protective layer 215, the bottom surface of the gate structure 260 is controlled above layer B215, and the first portion opening 290a stops at layer B215, thereby preventing the gate structure 260 from being exposed during the etching process that forms the FTV opening 290.

[0050] Referring to Figures 1, 2, and 39-41, method 100 includes step 134, forming an FTV 292 in the FTV opening 290. In some embodiments, the FTV 292 may include a metal, such as cobalt (Co), nickel (Ni), ruthenium (Ru), tungsten (W), copper (Cu), or a combination thereof. In some embodiments, the aforementioned metal may be deposited to fill the FTV opening 290 to form the FTV 292 by methods such as physical vapor deposition (PVD), metal-organic chemical vapor deposition (MOCVD), electroplating, or electroless plating. After depositing the metal filler, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove excess metal from the back-side ILD layer 288 to form the FTV 292. The FTV 292 is located on and electrically connected to the source / drain contact plug 280. A protective layer 215 prevents the FTV 292 from directly contacting the gate structure 260, thereby increasing the leakage current margin between the FTV 292 and the gate structure 260. The leakage current margin between FTV 292 and gate structure 260 is defined as the ability to prevent leakage current from occurring between gate structure 260 (metal gate) and FTV 292. Referring to Figure 40, gate spacer 226 and CESL 246 can also isolate FTV 292 and gate structure 260. Figure 42 shows an alternative view of Figure 40, and the structure 200 of Figure 42 can be made from the structure 200 of the embodiment shown in Figure 21.

[0051] Referring to Figure 43, the FTV 292 in the CC section of Figure 39 is projected onto the AA section. The source / drain contact plug 280 shown as a dashed trapezoid in Figure 43 is a schematic projection for simplicity, showing its connection to the FTV 292. It should be understood that the shape of the source / drain contact plug 280 in Figure 39 is different. The width W4 of layer B260 on the bottom surface of gate structure 260 (e.g., the interface between gate structure 260 and protective layer 215) of FTV 292 in the Y direction can be referred to as the critical dimension of FTV 292 (or the gate structure-related critical dimension). The critical dimension of FTV 292 may affect the leakage current margin between FTV 292 and gate structure 260. Due to the tapered sidewalls of FTV 292, the width of FTV 292 in the Y direction decreases along the positive Z direction. For example, the width W4 at layer B260 is smaller than the width W5 below layer B260. Therefore, the distance between FTV 292 and fin substrate 212B in the Y direction increases along the positive Z direction. For example, the distance S1 at layer B260 is greater than the distance S2 below layer B260. By providing the protective layer 215, the control of layer B260 can be improved (e.g., keeping layer B260 above the isolation structure 214), thereby reducing the critical size of FTV 292, increasing the distance between FTV 292 and fin substrate 212B in the Y direction, and increasing the leakage current margin between FTV 292 and gate structure 260.

[0052] In some embodiments, as the leakage current margin between FTV 292 and gate structure 260 increases, at least one gate isolation structure 270 of Figure 43 can be omitted without causing leakage current between FTV 292 and gate structure 260. Figure 44 shows an example structure 200 with both gate isolation structures 270 of Figure 43 omitted. This can reduce the footprint of structure 200 and reduce the associated cost and time.

[0053] Structure 200 can be fabricated using additional processes to form various components and regions known in the art. For example, additional processes can form additional front and / or back interlayer dielectric (ILD) layers, front and / or back contacts / vias / lines, and front and / or back multilayer interconnect components (e.g., metal layers and interlayer dielectric layers) configured to connect various components to form functional circuitry, which may include one or more devices (including semiconductor device 200). The additional front-side components may be formed prior to flipping structure 200. In a further example, the multilayer interconnects may include vertical interconnects (e.g., vias or contacts) and horizontal interconnects (e.g., metal lines). Various interconnect components can be made of various conductive materials, including copper, tungsten, and / or silicates. In one example, a damascene and / or dual damascene process is used to form the copper-associated multilayer interconnect structure. In some embodiments, back-side metal lines (e.g., back-side power rails) may be formed below and connected to FTV 292.

[0054] Although Figures 3 through 42 illustrate GAA transistors, other examples of semiconductor devices (e.g., FinFETs, other multi-gate devices) may also benefit from aspects of this disclosure.

[0055] While not intended to be limiting, one or more embodiments disclosed herein offer numerous benefits to semiconductor structures. For example, the protective layer can serve as a stop layer for forming the FTV opening and can isolate the FTV from the gate structure. Furthermore, by providing the protective layer, the gate trench can be prevented from penetrating into the isolation structure, thereby raising the bottom surface of the gate structure and reducing the critical size of the FTV, increasing the leakage current margin between the FTV and the gate structure. This can thus improve the overall performance of the semiconductor device. Additionally, the gate isolation structure used to isolate the FTV and the gate structure can be omitted, reducing the structural footprint and associated costs and time.

[0056] In one example aspect, this disclosure provides a method for manufacturing a semiconductor structure, comprising: forming a stack on a substrate, the stack including an interleaved plurality of first semiconductor layers and a plurality of second semiconductor layers; patterning the stack and the top of the substrate to form a first active region and a second active region protruding from the bottom of the substrate and extending longitudinally in one direction, the first active region including a first fin substrate and a first stack of semiconductor layers on the first fin substrate, the second active region including a second fin substrate and a second stack of semiconductor layers on the second fin substrate; forming an isolation structure between the first active region and the second active region; depositing a protective layer on the isolation structure; forming a dummy gate stack across the first active region and the second active region, the dummy gate stack intersecting with the top surface of the protective layer; depositing gate spacers on the sidewalls of the dummy gate stack; and etching a first active region outside the dummy gate stack and the gate spacers. An active region and a second active region are formed to form a first trench and a second trench, respectively; a first source / drain component is formed in the first trench, and a second source / drain component is formed in the second trench; a dummy gate stack is removed to form a gate trench, exposing a protective layer; a second semiconductor layer is removed from the gate trench; a gate structure is deposited in the gate trench, intersecting with the top surface of the protective layer; source / drain contacts are formed on the first source / drain component, and the source / drain contacts are connected to the first source / drain component; a substrate is thinned to expose the back side of an isolation structure; a back-side dielectric structure is formed on the back side of the isolation structure; a back-side opening is formed through the back-side dielectric structure, exposing the bottom surface of the protective layer, the bottom surface of the source / drain contacts, and the sidewalls of the gate spacers; and a conductive component is formed in the back-side opening, electrically connected to the source / drain contacts. A portion of the first source / drain component is suspended on the isolation structure, wherein a portion of the second source / drain component is suspended on the isolation structure.

[0057] In some embodiments, the isolation structure intersects with the sidewalls of the first fin base and the sidewalls of the second fin base.

[0058] In some embodiments, source / drain contacts are disposed on and connected to the second source / drain component.

[0059] In some embodiments, the method further includes: forming a first dielectric layer along the sidewall of the first fin substrate; and forming a second dielectric layer along the sidewall of the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are between the isolation structure and the first fin substrate, wherein the first dielectric layer comprises less than about 10% nitrogen, and wherein the second dielectric layer comprises oxide.

[0060] In some embodiments, removing the dummy gate stack also removes the top of the protective layer while retaining the bottom of the protective layer.

[0061] In some embodiments, the first and second trenches extend through the protective layer and expose the isolation structure.

[0062] In some embodiments, the top of the first trench of the adjacent gate spacer has a first width along the aforementioned direction, and the bottom of the first trench spanning the sidewall of the isolation structure has a second width along the aforementioned direction, the second width being greater than the first width.

[0063] In some embodiments, the middle portion of the first groove between the top and bottom of the adjacent protective layer has a third width along the aforementioned direction, the third width being smaller than the second width.

[0064] In some embodiments, the substrate is thinned to remove at least one bottom of the isolation structure.

[0065] In another example aspect, this disclosure provides a method of manufacturing a semiconductor structure, comprising: providing a structure including a substrate and a fin structure protruding from the substrate; forming an isolation structure on the substrate and adjacent to the sidewalls of the fin structure; forming a protective layer on the isolation structure; epitaxially growing source / drain components on the source / drain regions of the fin structure; depositing a contact etch stop layer (CESL) on the source / drain components; depositing a first interlayer dielectric (ILD) layer on the CESL; depositing a capping layer on the top surface of the CESL and the top surface of the first ILD layer; depositing a second ILD layer on the capping layer; forming source / drain contact plugs disposed in the first ILD layer for electrical coupling to the source / drain components; forming a metal silicate layer disposed between the source / drain components and the source / drain contact plugs; thinning the substrate from the bottom of the structure until the isolation structure is exposed; forming an opening to expose the bottom surface of the source / drain contact plugs and the bottom surface of the protective layer; and depositing a back-side conductive component in the opening. The conductivity of the metal silicate layer is between that of the source / drain component and the source / drain contact plug, and the metal silicate layer includes a curved profile.

[0066] In other embodiments, the fin structure includes a fin substrate and a stack of channel layers and sacrificial layers; and the method of manufacturing the semiconductor structure further includes: forming a dummy gate structure on the channel region of the fin structure, removing the dummy gate structure and sacrificial layer after depositing a first ILD layer to form a gate trench, and forming a gate structure in the gate trench, the gate structure surrounding the stack of channel layers, wherein the gate structure is disposed on the top surface of the protective layer relative to the bottom surface of the protective layer.

[0067] In other embodiments, the fin structure extends longitudinally along a direction, and a portion of the back-side conductive component is separated from the gate structure along the aforementioned direction by a gate spacer.

[0068] In other embodiments, removing the dummy gate structure and the sacrificial layer also removes the top of the protective layer in the gate trench, so that the top of the protective layer has a recessed profile.

[0069] In other embodiments, epitaxial growth of source / drain components includes: forming source / drain grooves in the source / drain regions of a fin-like structure; and epitaxial growth of source / drain components in the source / drain grooves, wherein a portion of the source / drain grooves is formed to remove the protective layer, thereby exposing the isolation structure.

[0070] In other embodiments, the opening is formed to remove portions of the isolation structure, portions of the CESL, and portions of the first ILD layer.

[0071] In other embodiments, prior to thinning the substrate, the first ILD layer includes a bottom embedded in the isolation structure and a top above the bottom, wherein the bottom is wider than the top along a longitudinal extension direction of the fin structure.

[0072] In another example, this disclosure provides a semiconductor structure comprising: one or more nanostructures disposed on a semiconductor fin substrate; an isolation structure disposed on one side of the semiconductor fin substrate; a protective layer disposed on the isolation structure and below the bottom surface of the one or more nanostructures; a first source / drain component and a second source / drain component connected by the one or more nanostructures; a gate structure disposed on the one or more nanostructures and intersecting the top surface of the protective layer; a gate spacer extending along the sidewall of the gate structure and intersecting the top surface of the protective layer; a source / drain contact disposed on and electrically coupled to the first source / drain component; and a back-side conductive component landing on the bottom surface of the protective layer and the bottom surface of the source / drain contact. The conductivity of the source / drain contact is greater than that of the first source / drain component, and the back-side conductive component is electrically isolated from the gate structure by the gate spacer and the protective layer.

[0073] In some other embodiments, it further includes: a low-nitrogen dielectric layer disposed on the sidewall of the semiconductor fin substrate; and an oxide layer disposed on the sidewall of the low-nitrogen dielectric layer, wherein the isolation structure and the protective layer intersect with the sidewall of the oxide layer, and wherein the nitrogen concentration of the protective layer is greater than the nitrogen concentration of the low-nitrogen dielectric layer.

[0074] In some other embodiments, the first boundary between the gate structure and the protective layer is lower than the second boundary between the gate spacer and the protective layer.

[0075] In some other embodiments, in a top view, the semiconductor fin substrate and the back-side conductive component extend longitudinally in the same direction.

[0076] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0077] 100: Method 102: Steps 104: Steps 106: Steps 108: Steps 110: Steps 112: Steps 114: Steps 116: Steps 118: Steps 120: Steps 122: Steps 124: Steps 126: Steps 128: Steps 130: Steps 132: Steps 134: Steps 200: Structure / Device 202:Substrate 204: Stacking 206: Sacrifice Layer 208: Channel Layer / Channel Components 211: Low-nitrogen layer 212: Fin-like structure / active region 213: Oxide layer 214: Isolation structure / isolation component 215: Protective layer 216: Dummy Dielectric Layer 218: Dummy Electrode Layer 220: Dummy gate stack 222: Gate top hard shielding layer 226: Gate spacer / fin spacer 228: Groove / Groove 232: Groove 236: Internal spacer 244: Source / Drain Components 246: Contact Etching Stop Layer / CESL 248: Interlayer dielectric layer / ILD layer 250: Trench 260: Gate structure 262: Interface Layer 264: Dielectric layer 266: Electrode layer 270: Gate isolation structure / Cut metal gate components 272: Dielectric sheath 274: Dielectric filling layer 276: Capping Layer / Etching Stop Layer / ESL 278: ILD layer 280: Contact plug 282: Silicone components 284: Through hole 286: Backside Etching Stop Layer / ESL 288: Dorsal ILD layer 290: Opening 292:FTV 212B: Fin-like base 212C: Passage Area 212SD: Source / Drain Region 290a: First part opening 290b: Second part opening AA: Line / Section B214: Floor B215: Floor B260: Floor BB: Line / Section CC: Line / Section D1: Depth D2: Height D3: height DD: Line / Section S1: Distance S2: Distance T1: Thickness T2: Thickness W1: Width W2: Width W2': Width W3: Width W4: Width W5: Width

Claims

1. A method for manufacturing a semiconductor structure, comprising: A stack is formed on a substrate, the stack comprising an interleaved plurality of first semiconductor layers and a plurality of second semiconductor layers; The stack and a top of the substrate are patterned to form a first active region and a second active region protruding from a bottom of the substrate and extending longitudinally in one direction. The first active region includes a first fin substrate and a first stack of multiple semiconductor layers on the first fin substrate. The second active region includes a second fin substrate and a second stack of multiple semiconductor layers on the second fin substrate. An isolation structure is formed between the first active region and the second active region. A protective layer is deposited on the isolation structure. A dummy gate stack is formed across the first active region and the second active region, intersecting a top surface of the protective layer. Multiple gate spacers are deposited on multiple sidewalls of the dummy gate stack. The first active region and the second active region outside the dummy gate stack and the gate spacers are etched to form a first trench and a second trench, respectively. A first source / drain component is formed in the first trench, and a second source / drain component is formed in the second trench, wherein a portion of the first source / drain component is suspended on the isolation structure, and a portion of the second source / drain component is suspended on the isolation structure; the dummy gate stack is removed to form a gate trench, the gate trench exposing the protective layer; the second semiconductor layers are removed from the gate trench; a gate structure is deposited in the gate trench, the gate structure intersecting the top surface of the protective layer; a source / drain contact is formed on the first source / drain component, the source / drain contact being connected to the first source / drain component; the substrate is thinned to expose a back side of the isolation structure; a back-side dielectric structure is formed on the back side of the isolation structure; A back-side opening is formed through the back-side dielectric structure, exposing a bottom surface of the protective layer, a bottom surface of the source / drain contact, and the sidewalls of the gate spacers; and a conductive member is formed in the back-side opening, the conductive member being electrically connected to the source / drain contact, wherein a top of a first trench adjacent to the gate spacers has a first width along the direction, wherein a bottom of the first trench spanning multiple sidewalls of the isolation structure has a second width along the direction, and wherein a middle portion of the first trench adjacent to the protective layer and between the top and the bottom has a third width along the direction, the third width being smaller than the second width.

2. The method of manufacturing a semiconductor structure as described in claim 1, wherein the source / drain contact is disposed on the second source / drain component and connected to the second source / drain component.

3. The method for manufacturing a semiconductor structure as described in claim 1 further includes: A first dielectric layer is formed along one sidewall of the first fin-shaped substrate; A second dielectric layer is formed along one sidewall of the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are between the isolation structure and the first fin substrate, wherein the first dielectric layer comprises less than about 10% nitrogen, and wherein the second dielectric layer comprises an oxide.

4. The method of manufacturing a semiconductor structure as described in any one of claims 1 to 3, wherein removing the dummy gate stack also removes a top of the protective layer, while retaining a bottom of the protective layer.

5. A method of manufacturing a semiconductor structure as described in any one of claims 1 to 3, wherein the first trench and the second trench extend through the protective layer and expose the isolation structure.

6. The method of manufacturing a semiconductor structure as described in claim 5, wherein the second width is greater than the first width.

7. A method for manufacturing a semiconductor structure, comprising: A structure is provided, including a substrate and a fin-like structure protruding from the substrate; An isolation structure is formed on the substrate and adjacent to one sidewall of the fin structure; a protective layer is formed on the isolation structure; a source / drain component is epitaxially grown on a source / drain region of the fin structure; a contact etch stop layer (CESL) is deposited on the source / drain component; a first interlayer dielectric (ILD) layer is deposited on the CESL; a capping layer is deposited on a top surface of the CESL and a top surface of the first ILD layer; a second ILD layer is deposited on the capping layer; a source / drain contact plug is formed and disposed in the first ILD layer for electrical coupling to the source / drain component; A metal silicate layer is formed and disposed between the source / drain component and the source / drain contact plug, wherein the conductivity of the metal silicate layer is between the conductivity of the source / drain component and the conductivity of the source / drain contact plug, wherein the metal silicate layer includes a curved profile; the substrate is thinned from a bottom of the structure until the isolation structure is exposed; an opening is formed to expose a bottom surface of the source / drain contact plug and a bottom surface of the protective layer; and a back-side conductive component is deposited in the opening, wherein before thinning the substrate, the first ILD layer includes a bottom embedded in the isolation structure and a top above the bottom, wherein the bottom is wider than the top along a longitudinal extension direction of the fin structure.

8. The method of manufacturing a semiconductor structure as described in claim 7, wherein the fin structure comprises a fin substrate and a stack of a plurality of channel layers and a plurality of sacrificial layers; and wherein the method of manufacturing the semiconductor structure further comprises: A dummy gate structure is formed on a channel region of the fin structure. After the first ILD layer is deposited, the dummy gate structure and the sacrificial layers are removed to form a gate trench, and a gate structure is formed in the gate trench. The gate structure surrounds the stack of the channel layers, wherein the gate structure is disposed on a top surface of the protective layer, relative to the bottom surface of the protective layer.

9. The method of manufacturing a semiconductor structure as claimed in claim 8, wherein the fin structure extends longitudinally along a direction, and wherein a portion of the back-side conductive member is separated from the gate structure along the direction by a gate spacer.

10. A method of manufacturing a semiconductor structure as described in any one of claims 7 to 9, wherein epitaxial growth of the source / drain component comprises: A source / drain groove is formed in the source / drain region of the fin-like structure; And epitaxial growth of the source / drain component in the source / drain groove, wherein forming the source / drain groove removes a portion of the protective layer to expose the isolation structure.

11. A semiconductor structure, comprising: One or more nanostructures are disposed on a semiconductor fin substrate; An isolation structure is disposed on one side of the semiconductor fin substrate; a protective layer is disposed on the isolation structure and below a bottom surface of the one or more nanostructures; a first source / drain component and a second source / drain component are connected via the one or more nanostructures; a gate structure is disposed on the one or more nanostructures and intersects a top surface of the protective layer; a plurality of gate spacers extend along a plurality of sidewalls of the gate structure and intersect the top surface of the protective layer; a source / drain contact is disposed on and electrically coupled to the first source / drain component, wherein the conductivity of the source / drain contact is greater than the conductivity of the first source / drain component; and a back-side conductive component rests on a bottom surface of the protective layer and a bottom surface of the source / drain contact. The back-side conductive component is electrically isolated from the gate structure by the gate spacers and the protective layer. A top of a first trench adjacent to the gate spacers has a first width. A bottom of the first trench spanning multiple sidewalls of the isolation structure has a second width. A middle portion of the first trench adjacent to the protective layer and between the top and the bottom has a third width, which is smaller than the second width.

12. The semiconductor structure as described in claim 11, further comprising: A low-nitrogen dielectric layer is disposed on one sidewall of the semiconductor fin substrate; An oxide layer is disposed on one sidewall of the low-nitrogen dielectric layer, wherein the isolation structure and the protective layer intersect with one sidewall of the oxide layer, and wherein the nitrogen concentration of the protective layer is greater than the nitrogen concentration of the low-nitrogen dielectric layer.

13. The semiconductor structure as claimed in claim 11 or 12, wherein a first boundary between the gate structure and the protective layer is lower than a second boundary between the gate spacers and the protective layer.

Images