Electronic module and half bridge circuit for integrated iii-nitride devices

Abstract

An electronic module for a half-bridge circuit includes a substrate with an insulating layer between a first metal layer and a second metal layer. Trenches formed through the first metal layer electrically isolate first, second, and third portions of the first metal layer from each other. A high-side switch includes an enhancement-mode transistor and a depletion-mode transistor. The depletion-mode transistor comprises a III-N material structure on a conductive substrate. The drain electrode of the depletion-mode transistor is electrically connected to the first portion, the source electrode of the enhancement-mode transistor is electrically connected to the second portion, the drain electrode of the enhancement-mode transistor is electrically connected to the source electrode of the depletion-mode transistor, and the gate electrode of the depletion-mode transistor is connected to the conductive substrate, which is connected to the second portion.

Description

[Technical Field]

[0001] The disclosed technology relates to semiconductor electronic modules designed to achieve improved performance and reliability. [Previous Technology]

[0002] Currently, typical power semiconductor devices, including transistors, diodes, power MOSFETs, and insulated-gate bipolar transistors (IGBTs), are all manufactured using silicon (Si) semiconductor materials. Recently, wide-bandgap materials (SiC, III-N, III-O, diamond) have been considered for use in power devices due to their excellent properties. Type III nitride (or III-N) semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates for carrying high currents, supporting high voltages, and providing extremely low on-resistance and fast switching times.

[0003] Figure 1A shows a schematic diagram 100 of a half-bridge circuit including a high-side switch 102 and a low-side switch 103. The half-bridge circuit has a high-voltage node 111 and a low-voltage or ground node 113. The output node 112 of the half-bridge, between the source of the high-side switch 102 and the drain of the low-side switch 103, is connected to the load motor (inductor 104). To ensure proper operation of the circuit in Figure 1A, the DC high-voltage node 111 must remain AC grounded. That is, node 111 can be capacitively coupled to DC ground 113 by connecting one end of a first capacitor 106 to the high-voltage node 111 and the other end of the capacitor to ground 113. Therefore, when either the high-side switch 102 or the low-side switch 103 is turned on or off, the first capacitor 106 can be charged or discharged as needed to provide the current required to maintain a substantially constant voltage on the high-voltage side and the low-voltage side of the circuit.

[0004] Figure 1B shows a circuit diagram of a three-phase full-bridge circuit 120 configured to drive a three-phase motor. Each of the three half-bridges 122, 124, and 126 in circuit 120 includes two transistors (141-146), such as the half-bridge in Figure 1A. Each of the three half-bridges has an output node 137, 138, or 139. Each transistor in this circuit is capable of blocking voltage in a first direction and is capable of conducting current in the first direction or optionally in both directions.

[0005] One type of transistor that shows promising benefits when used in the circuits of Figures 1A and 1B is the III-N high electron mobility transistor (HEMT), which can be used as the high-side switch 102 and / or low-side switch 103 in the half-bridge of Figure 1A, or as any transistor in the bridge circuit of Figure 1B. Most known III-N HEMTs and related transistor devices are typically in the on state (i.e., with a negative threshold voltage), meaning they conduct current at zero gate voltage. These devices with negative threshold voltages are called depletion-mode (D-mode) devices. In power electronic devices, it is preferable to have normally off devices (i.e., devices with a positive threshold voltage) that are in the off state when zero volts are applied to the gate relative to the source to prevent accidental activation that could damage the device or other circuit components. Normally off devices are often called enhancement-mode (E-mode) devices.

[0006] To date, the reliable manufacture and operation of high-voltage III-N enhancement-mode transistors have proven extremely difficult. An alternative to a single high-voltage enhancement-mode transistor is to combine a high-voltage depletion-mode III-N transistor with a low-voltage silicon enhancement-mode FET in a cascode configuration. As seen in Figure 2, the cascode switch 200 includes a high-voltage depletion-mode transistor 223 and a low-voltage enhancement-mode transistor 222 packaged in a package 205. The source 234 of the high-voltage depletion-mode transistor 223 is connected to the drain 213 of the low-voltage enhancement-mode transistor 222. The gate 235 of the high-voltage depletion-mode transistor 223 and the source 211 of the low-voltage enhancement-mode transistor 222 are interconnected and connected to the source lead 207 of the package 205. The gate 212 of the low-voltage enhancement-mode transistor 222 is connected to the gate lead 208 of the package 205. The drain electrode 236 of the high-voltage depletion transistor 223 is connected to the drain lead 209 of the package 205. The low-voltage enhancement-mode transistor 222 includes an intrinsic body diode 237 formed between the source electrode 211 and the drain electrode 213. The device configured in the common-source common-gate switch 200 of FIG2 can operate in the same manner as a single high-voltage enhancement-mode transistor, wherein leads 207, 208, and 209 serve as the source, gate, and drain of the device, respectively, and in many cases achieve the same or similar output characteristics as a single high-voltage enhancement-mode transistor.

[0007] The common operating methods of the circuits in Figures 1A and 1B involve hard switching of the switches (i.e., transistors or common-source common-gate switches). In a hard-switching circuit configuration, the switches have a high current (e.g., greater than 10A) flowing through them when they are turned on, and a high voltage across them when they are turned off. Switches that switch under these conditions are called "hard switches". Alternative circuit configurations use additional passive and / or active components, or signal timing techniques, to allow the switches to be "soft-switched". In a soft-switching circuit configuration, the switches are turned on under zero current (or near-zero current) conditions and turned off under zero voltage (or near-zero voltage) conditions. Soft-switching methods and configurations have been developed to address the high-level electromagnetic interference (EMI) and associated ringing observed in hard-switching circuits, especially in high-current and / or high-voltage applications. While soft switching can mitigate these problems in many cases, the circuitry required for soft switching typically includes many additional components, leading to increased overall cost and complexity. Soft switching typically requires configuring the circuit to switch only at specific times when zero current or zero voltage conditions are met, thus limiting the control signals that can be applied and reducing circuit efficiency in many cases. Therefore, hard switching power supply circuits require alternative configurations and methods to maintain sufficiently low EMI levels, reduce circuit inductance, and improve switching speed stability. [Summary of the Invention]

[0008] This document describes a module configuration integrating III-N devices, wherein low-voltage enhancement-mode devices and high-voltage depletion-mode III-N devices are integrated into a single electronic component module to form half-bridge and full-bridge power switching circuits. When there is no need to distinguish between them, the term "device" is generally used for any transistor or switch or diode.

[0009] In the first embodiment, an electronic module is described. The electronic module includes a substrate, which includes an insulating layer between a first metal layer and a second metal layer. The first metal layer includes a first portion, a second portion, and a third portion, and a trench is formed through the first metal layer, the trench electrically isolating the first, second, and third portions of the first metal layer from each other. The electronic module also includes a high-side switch, which includes an enhancement-mode transistor and a depletion-mode transistor, wherein the depletion-mode transistor includes a III-N material structure on a conductive substrate. The electronic module also includes a low-side switch. The drain electrode of the depletion-mode transistor is electrically connected to the first portion of the first metal layer, the source electrode of the enhancement-mode transistor is electrically connected to the second portion of the first metal layer, the drain electrode of the enhancement-mode transistor is electrically connected to the source electrode of the depletion-mode transistor, the gate electrode of the depletion-mode transistor is electrically connected to the conductive substrate, and the conductive substrate is electrically connected to the second portion of the first metal layer.

[0010] In the second embodiment, a half-bridge circuit is described. The half-bridge circuit includes a high-side switch and a low-side switch, each packaged in a single electronic package, wherein the package includes a high-voltage terminal, an output terminal, and a ground terminal. The high-side switch includes a first enhancement-mode transistor and a first depletion-mode transistor arranged in a common-source, common-gate configuration. The low-side switch includes a second enhancement-mode transistor and a second depletion-mode transistor arranged in a common-source, common-gate configuration. The drain electrode of the first III-N transistor is electrically connected to the high-voltage terminal, the conductive substrate of the first depletion-mode III-N transistor is electrically connected to the output terminal, the drain electrode of the second III-N transistor is electrically connected to the output terminal, and the conductive substrate of the second depletion-mode III-N transistor is electrically connected to the ground terminal.

[0011] In the third state, a half-bridge circuit is described. The half-bridge circuit includes a high-side switch and a low-side switch, each of which is packaged in a single electronic package. The high-side switch is connected to a high-voltage node, the low-side switch is connected to a ground node, and an inductor is connected to the output of the package, the output being configured between the high-side switch and the low-side switch. The low-side switch includes a low-voltage enhancement-mode transistor and a high-voltage III-N depletion-mode transistor arranged in a common-source, common-gate configuration. The half-bridge circuit is configured such that in a first operating mode, current flows through the high-side switch and the inductor in a first direction, while the high-side switch is biased to be on and the low-side switch is biased to be off. In a second operating mode, current flows through the low-side switch and the inductor in a second direction, while the high-side switch is biased to be off and the low-side switch is biased to be off. In the third operating mode, current flows along the second direction through the low-side switch and through the inductor, while the high-side switch is biased to turn off and the low-side switch is biased to turn on. During the second operating mode, the low-side switch is configured to conduct a reverse DC current greater than 50A, and during the third operating mode, the on-resistance of the III-N depleted transistor increases by less than 5% relative to the first mode.

[0012] Each of the electronic modules and / or transistors described herein may include one or more of the following features: The high-side switch and the low-side switch may form a half-bridge circuit. The depletion transistor may be configured to block at least 600V when the high-side switch is biased off and to conduct a current greater than 30A when the high-side switch is biased on. The electronic module may include a capacitor, wherein a first terminal of the capacitor is electrically connected to a first portion of a first metal layer, and a second terminal of the capacitor is electrically connected to a third portion of the first metal layer. The capacitor may be formed vertically above a trench. The capacitor may be a hybrid capacitor including a resistor and a capacitor component connected in series. The resistor component may be greater than 0.1 ohm, and the capacitor component may be greater than 0.1 nF. The gate electrode, source electrode, and drain electrode may be located on opposite sides of a III-N material structure forming a conductive substrate. The III-N material structure may include a via formed through the substrate, and the gate electrode of the depletion transistor is electrically connected to the substrate through the via. The electronic module may include a package in which the substrate, the high-side switch, and the low-side switch are packaged. The electronic module may include a gate driver packaged within a package, wherein a first terminal of the gate driver is connected to the gate electrode of a high-side switch, and a second terminal of the gate driver is connected to the gate electrode of a low-side switch. The gate driver may be integrated with the enhancement transistors of the high-side and low-side switches. A second high-side switch may be connected in parallel with the high-side switch, and a second low-side switch may be connected in parallel with the low-side switch. A second portion of a first metal layer is connected to the output node of the electronic module. The module is configured such that during operation, a first portion of the first metal layer is connected to a DC voltage source and a third portion of the first metal layer is connected to DC ground. A ferrite bead has a first terminal and a second terminal, the first terminal of which is connected to the second portion of the first metal layer, and the second terminal is connected to the output terminal. The substrate of the first and / or second depleted III-N transistor is a silicon-doped p-type substrate having a hole concentration greater than 1 x 10¹⁹ holes / cm³. During a second operating mode, a reverse DC current flows through the parasitic diode of the enhancement transistor and the device channel of the III-N depleted transistor. During the third operating mode, reverse DC current flows through the channel of the enhancement transistor and the device channel of the III-N depleted transistor.

[0013] The "hybrid enhancement electronic device or component" described herein, or simply "hybrid device or component," is an electronic device or component formed of a depletion-type transistor and an enhancement-type transistor, wherein the depletion-type transistor is capable of withstanding a higher operating and / or breakdown voltage compared to the enhancement-type transistor, and the hybrid device or component is configured to operate similarly to a single enhancement-type transistor, while its breakdown and / or operating voltage is approximately as high as that of the depletion-type transistor. That is, the hybrid enhancement device or component includes at least three nodes having the following characteristics: When the first node (source node) and the second node (gate node) are held at the same voltage, the hybrid enhancement device or component can block a positive high voltage (i.e., greater than the maximum voltage that the enhancement-type transistor can block) applied relative to the source node to the third node (drain node). Current flows from the source node to the drain node when the gate node is held at a sufficiently positive voltage (i.e., greater than the threshold voltage of the enhancement-type transistor), or current flows from the drain node to the source node when a sufficiently positive voltage is applied relative to the source node to the drain node. When the enhancement-mode transistor is a low-voltage device and the depletion-mode transistor is a high-voltage device, the hybrid component can operate similarly to a single high-voltage enhancement-mode transistor. The breakdown voltage and / or maximum operating voltage of the depletion-mode transistor can be at least two, at least three, at least five, at least ten, or at least twenty times that of the breakdown voltage and / or maximum operating voltage of the enhancement-mode transistor.

[0014] As used herein, the terms group III nitride (or III-N) materials, layers, devices, etc., refer to materials or devices made of compound semiconductor materials according to the stoichiometric formula BwAlxInyGazN, where w+x+y+z is approximately 1, and 0 ≤ w ≤ 1, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ z ≤ 1. III-N materials, layers, or devices can be grown directly on a suitable substrate (e.g., by metal-organic chemical vapor deposition), or grown on a suitable substrate, separated from the original substrate, and then bonded to other substrates.

[0015] As used herein, two or more contacts or other objects (such as conductive channels or components) are referred to as “electrically connected” if they are connected by a sufficiently conductive material to ensure that the potential of each contact or other object is intended to remain the same (e.g., substantially the same) under any bias conditions.

[0016] The "blocking voltage" as used herein refers to the ability of a transistor, device, or component to prevent a large current (e.g., a current greater than 0.001 times the average operating current during normal conduction) from flowing through it when a voltage is applied across it. In other words, when a transistor, device, or component blocks a voltage applied across it, the total current flowing through it will not exceed 0.001 times the operating current during normal conduction. Devices with a blocking current greater than this value exhibit high losses and low efficiency and are generally unsuitable for many applications, especially power switching applications.

[0017] The "high-voltage device" described herein, such as a high-voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS), is an electronic device optimized for high-voltage applications. In other words, when the device is off, it can block high voltages, such as approximately 300V or higher, approximately 600V or higher, or approximately 1200V or higher, while when the device is on, it has a sufficiently low on-resistance (RON) for the application using it, for example, it experiences sufficiently low conduction losses when a large current flows through the device. The high-voltage device is at least able to block a voltage equal to the high-voltage power supply or the maximum voltage in the circuit using it. The high-voltage device may be able to block 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. In other words, a high-voltage device can block all voltages between 0V and at least Vmax, where Vmax is the maximum voltage that the circuit or power supply can provide. Vmax can be, for example, 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltage required by the application. For bidirectional or four-quadrant switches, the blocking voltage can be of any polarity less than a certain maximum value (±Vmax such as ±300V, ±600V, ±1200V, etc.) when the switch is off, and the current can flow in either direction when the switch is on.

[0018] The "III-N device" described herein is a device having a conductive path formed in a III-N material. The III-N device can be designed as a transistor or switch, wherein the state of the device is controlled by a gate terminal, or as a two-terminal device that, in the absence of a gate terminal, prevents current flow in one direction and conducts it in the other. The III-N device can be a high-voltage device suitable for high-voltage applications. In such a high-voltage device, when the device is biased off (e.g., the voltage at the gate relative to the source is less than the device threshold voltage), it is capable of supporting at least all high voltages less than or equal to those in applications using this device, such as 100V, 300V, 600V, 1200V, 1700V, 2500V, or higher. When the high-voltage device is biased on (e.g., the voltage at the gate relative to the source or associated power supply terminal is greater than the device threshold voltage), it is capable of conducting a large current at a low on-state voltage (i.e., a low voltage between the source and drain terminals or between the opposite power supply terminals). The maximum permissible on-state voltage is the maximum on-state voltage that can be withstood in applications using this device.

[0019] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of a layer with respect to other layers. Thus, for example, a layer disposed above or below another layer may be in direct contact with that other layer or may have one or more intermediate layers. Furthermore, a layer disposed between two layers may be in direct contact with both layers or may have one or more intermediate layers. Conversely, a first layer "on" a second layer is in contact with this second layer. Additionally, assuming the operation is performed relative to the substrate without considering the absolute orientation of the substrate, the relative position of a layer with respect to other layers is provided.

[0020] In typical power switching applications using high-voltage switching transistors, the transistor is in one of two states most of the time. In the first state (often called the "ON state"), the voltage between the gate and source is higher than the transistor's threshold voltage, and a large current flows through the transistor. In this state, the voltage difference between the source and drain is typically low, usually not exceeding a few volts, for example, about 0.1-5 volts. In the second state (often called the "OFF state"), the voltage between the gate and source electrodes is lower than the transistor's threshold voltage, and no large current flows through the transistor except for the off-state leakage current. In the second state, the voltage between the source and drain can range from about 0V to the value of the circuit's high-voltage supply, and in some cases can be as high as 100V, 300V, 600V, 1200V, 1700V or higher, but can be lower than the transistor's breakdown voltage. In some applications, inductive elements in the circuit cause the voltage between the source and drain to be even higher than the circuit's high-voltage supply. Furthermore, immediately after the gate is turned on or off, the transistor transitions between these two states for a very short time. When the transistor is in the off state, it is referred to as the "blocking voltage between the source and drain." The "blocking voltage" as described herein refers to the ability of a transistor, device, or component to prevent a large current (e.g., a current greater than 0.001 times the average operating current during normal conduction) from flowing through a circuit when a voltage is applied across it. In other words, when a transistor, device, or component blocks a voltage applied across it, the total current through the transistor, device, or component will not exceed 0.001 times the average operating current during normal conduction.

[0021] Details of one or more embodiments of the technical subject matter described herein are disclosed in the accompanying drawings and the following description. Additional features and variations may also be included in the embodiments. Other morphologies, features, and advantages will be apparent from the specification, drawings, and claims.

Implementation Method

[0041] This document describes electronic modules and their operation methods suitable for maintaining low EMI levels, thereby allowing for higher circuit stability and improved performance. The design of the module, combined with the design of the switches used in the module, can lead to a reduction in inductors and other parasitic effects, resulting in the aforementioned performance improvements. The electronic modules can also have a reduced size and can be assembled more easily than conventional modules, thus allowing for lower production costs.

[0042] Figures 3A and 3B show a plan view and a cross-sectional view of the integrated electronic module 300, respectively. The integrated electronic module 300 includes a common-source common-gate high-side switch 382 and a low-side switch 383 connected in a half-bridge configuration as shown in Figure 1A. Plan views and cross-sectional views of a common-source common-gate switch 400 that can be used for each of the high-side switch 382 and the low-side switch 383 are shown in Figures 4A and 4B, respectively (other common-source common-gate configurations may be used instead of the common-source common-gate switch 400).

[0043] Referring to Figures 4A and 4B, the common-source common-gate switch 400 includes a low-voltage enhancement-mode transistor 422 directly mounted on the source electrode 434 of a high-voltage depletion transistor 423. The FET drain electrode 453 of the low-voltage enhancement-mode transistor 422 is directly coupled to the source electrode 434 of the high-voltage depletion transistor 423. The low-voltage enhancement-mode transistor 422 may be, for example, a silicon FET, and the depletion transistor may be, for example, a III-N HEMT. The common-source common-gate switch 400 can operate in the same manner as a single high-voltage enhancement-mode III-N transistor and, in many cases, achieves the same or similar output characteristics as a single high-voltage enhancement-mode III-N transistor. The high-voltage depletion transistor 423 has a larger breakdown voltage than the low-voltage enhancement-mode transistor 422 (e.g., at least three times larger). The maximum voltage that the common-source common-gate switch 400 can block when the bias is in the off state is at least as large as the maximum blocking voltage or breakdown voltage of the high-voltage depletion transistor 423.

[0044] The low-voltage enhancement-mode transistor 422 includes a semiconductor body layer 455. The low-voltage enhancement-mode transistor 422 also includes a FET source electrode 451 and a FET gate electrode 452 on a first side of the semiconductor body layer 455, and a FET drain electrode 453 on a second side of the semiconductor body layer 455 opposite to the FET source electrode 451.

[0045] The high-voltage depletion transistor 423 includes a III-N material structure 418, such as a combination of GaN and AlGaN, grown on a suitable substrate 411, which may be a conductive semiconductor such as silicon (e.g., p-type or n-type silicon), GaN (e.g., p-type or n-type GaN), or any other sufficiently conductive substrate, or an insulating (e.g., sapphire) substrate, or a semi-insulating (e.g., semi-insulating silicon carbide) substrate.

[0046] The III-N material structure 418 may include a III-N buffer layer 412, such as GaN or AlGaN, grown over a substrate 411. The buffer layer 412 may be insulating or substantially free of unintentional n-type charge carriers. The buffer layer 412 may have a substantially uniform composition, or the composition may vary. The thickness and composition of the buffer layer 412 may be optimized for high-voltage applications. That is, the buffer layer is capable of blocking voltages equal to or greater than the voltage of the high-voltage power supply or the maximum voltage in the circuit using it. For example, the buffer layer 412 is capable of blocking voltages greater than 600V or greater than 900V. The thickness of the buffer layer 412 may be greater than 2μm. For example, the III-N buffer layer may have a thickness between 5μm and 10μm.

[0047] The III-N material structure may further include a III-N channel layer 413 (e.g., GaN) above the III-N buffer layer 412, and a III-N barrier layer 414 (e.g., AlGaN, AlInN, or AlGaInN) above the III-N channel layer 413. The band gap of the III-N barrier layer 414 is larger than that of the III-N channel layer 413. The III-N channel layer 413 has a different composition than the III-N barrier layer 414, and the thickness and composition of the III-N barrier layer 414 are chosen such that a two-dimensional electron gas (2DEG) channel 419 (indicated by the dashed line in FIG. 4B) is adjacent to the interface between layers 414 and 413 in the III-N channel layer 413.

[0048] Typically, III-N high electron mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown in a reactor by molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). The III-N material structure can be grown in a group III polar (e.g., Ga polar) orientation, such as a [0 0 0 1] (C-plane) orientation, as shown in Figure 4B. Alternatively, a III-N HEMT can be formed on a III-N material structure grown in an N polar (i.e., N-plane) orientation (e.g., a [0 0 0 -1] orientation, not shown). In an N polar device, a III-N barrier layer can be placed on top of a III-N buffer layer, and a III-N channel layer can be placed on top of the III-N barrier layer. N polar III-N materials have a polarization field in the opposite direction to that of group III polar III-N materials, thus enabling the realization of III-N device structures that cannot be formed using group III polar structures.

[0049] An insulating layer 415 (e.g., a dielectric layer) is grown or deposited over the top surface of the III-N material structure 418. The insulating layer 415 may be formed, for example, of alumina (Al2O3), silicon dioxide (SiO2), SixNy, Al1-xSixN, Al1-xSixO, Al1-xSixON, or any other wide-bandgap insulator, or include one or more of the above. Although the insulating layer 415 is shown as a single layer, it may also be formed from multiple layers and / or materials deposited during different processing steps to form a single combined insulating layer.

[0050] Source electrode 434 and drain electrode 436 are formed on the side of the high-voltage depletion transistor 423 opposite to the substrate, such that the high-voltage depletion transistor 423 is characterized as a lateral III-N device (i.e., the source and drain are on the same side of the device, and current flows laterally through the device between the source electrode 434 and the drain electrode 436). The source electrode 434 and drain electrode 436 are ohmic contacts and electrically connected to the device 2DEG channel 419 formed in layer 413. The source electrode 434 and drain electrode 436 can each be formed from a stack of multiple metal layers. For example, each metal stack can be a Ti / Al / Ni / Au, Ti / Al, or other suitable metal layer stack.

[0051] The high-voltage depletion transistor 423 further includes a gate electrode 435. The gate electrode 435 may be formed such that an insulating layer 415 extends between the gate electrodes 435 and separates the gate electrodes 435 from the III-N material structure 418, as shown in FIG4B. Alternatively, the gate electrode 435 may be formed to contact the III-N material structure 418 (not shown). The gate electrode 435 may be formed of a suitable conductive material, such as a metal stack, such as titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au). The gate electrode 435 may alternatively be another conductive material or material stack, including one or more materials with a high work function, such as semiconductor materials with a high work function (e.g., p-type polysilicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride).

[0052] The low-voltage enhancement-mode transistor 422 is electrically connected to the high-voltage depletion-mode transistor 423 to form a common-source common-gate switch 400, which may be a hybrid III-N device. Here, the FET drain electrode 453 of the low-voltage enhancement-mode transistor 422 directly contacts (e.g., is mounted on) the source electrode 434 of the high-voltage depletion-mode transistor 423 and is electrically connected to the source electrode 434 of the high-voltage depletion-mode transistor 423. The FET drain electrode 453 of the low-voltage enhancement-mode transistor 422 can be connected to the source electrode 434 of the high-voltage depletion-mode transistor 423, for example, using solder, solder paste, conductive epoxy, conductive tape, or other suitable attachment methods, which allows for a high-quality mechanical, thermal, and electrical connection between the FET drain electrode 453 and the source electrode 434 of the depletion-mode transistor. The low-voltage enhancement-mode transistor 422 can be mounted above the device's 2DEG channel 419, as shown in Figure 4B, or it can be partially or completely mounted in a region outside the device's active region, such that it is not above the 2DEG channel layer. The gate node of the common-source common-gate switch 400 can be connected to the FET gate electrode 452 of the low-voltage enhancement-mode transistor 422. In conventional common-source common-gate switches, the depletion and enhancement-mode transistors are typically packaged side-by-side on a ceramic insulating substrate (e.g., an AlN pad) and require external lead-in connectors to connect the FET drain to the HEMT source, as required in a common-source common-gate configuration. However, as shown in Figures 4A and 4B, mounting the low-voltage enhancement-mode transistor 422 directly on the high-voltage depletion transistor 423 eliminates the need for external lead-in connectors and a ceramic substrate. This significantly reduces the parasitic inductance of the circuit, resulting in higher rated current and faster switching speeds.

[0053] Although the gate electrode 435 of the high-voltage depletion transistor 423 is not shown connected to the FET source electrode 451 of the low-voltage enhancement-type transistor 422 in Figures 4A or 4B (as required for normal operation of the common-source common-gate switch), these two electrodes are actually electrically connected once the common-source common-gate switch 400 is mounted onto the integrated electronics module 300 of Figures 3A and 3B, because the two electrodes are wire-bonded to a common metal layer. This can be seen in Figures 3A and 3B and is described in more detail below.

[0054] Referring now back to Figures 3A and 3B, the integrated electronic module 300 includes a direct-bonded copper (DBC) substrate 310 (best visible in Figure 3B), which can be the base substrate of the module. The DBC substrate is formed by directly bonding pure copper to a ceramic insulator (e.g., AlN or Al2O3) during a high-temperature melting and diffusion process. The DBC substrate 310 includes an insulating (e.g., ceramic or AlN) substrate 315, on which a top metal layer (e.g., copper or nickel) is patterned at least as a first portion serving as a high-voltage board 311, a second portion serving as an output board 312, and a third portion serving as a ground plane 313. The high-voltage board 311, the output board 312, and the ground plane 313 are each electrically isolated from each other by through-holes 314 formed through the top metal layer. As shown in Figure 3B, the DBC substrate may include a back metal layer 316 (e.g., copper or nickel) on the side of the insulating substrate 315 opposite to the top metal layer (high voltage board 311 / output board 312 / grounding plate 313). The grounding plate 313 may optionally be electrically connected to the back metal layer 316 by forming metal vias 317 through the insulating substrate 315. As shown in Figures 4A and 4B, both the high-side switch 382 and the low-side switch 383 are common-source, common-gate switches. The high-side switch 382 is directly mounted on the output board 312, and the low-side switch 383 is directly mounted on the grounding plate 313.

[0055] For the high-side switch 382, ​​the drain electrode 436 of the depletion-type transistor is electrically connected to the high-voltage board 311 via connector 341, and the gate electrode 435 of the depletion-type transistor and the FET source electrode 451 of the enhancement-type transistor are electrically connected to the output board 312 via wire connectors 340 and 342, respectively. For the low-side switch 383, the drain electrode 436' of the depletion-type transistor is electrically connected to the output board 312 via connector 343, and the gate electrode 435' of the depletion-type transistor and the FET source electrode 451' of the enhancement-type transistor are electrically connected to the ground plane 313 via wire connectors 346 and 348, respectively.

[0056] The integrated electronic module 300 may optionally include a package for packaging electronic components, the package including a first input lead 372, a second input lead 373, a high-voltage lead 391, a ground lead 393, and an output lead 392. The first input lead 372 is connected to the FET gate electrode 452 of the enhancement transistor of the high-side switch 382, ​​the second input lead 373 is connected to the FET gate electrode 452' of the enhancement transistor of the low-side switch 383, the high-voltage lead 391 is connected to the high-voltage board 311, the ground lead 393 is connected to the ground plane 313, and the output lead 392 is connected to the output board 312.

[0057] To ensure the correct operation of the half-bridge circuit formed by the integrated electronic module 300 of Figures 3A and 3B, the high-voltage lead 391 should be kept AC grounded. In other words, the high-voltage lead 391 can be capacitively coupled to the ground lead 393 by connecting the first end of the capacitor 375 to the high-voltage plate 311 and the second end of the capacitor 375 to the ground lead 393. As shown in Figure 3A, the capacitor 375 can be located directly on a portion of the via 314. When the high-side switch 382 or the low-side switch 383 is turned on or off, the capacitor 375 can be charged or discharged as needed to provide the current required to maintain a substantially constant voltage on the high-voltage and low-voltage sides of the circuit. Furthermore, the capacitor 375 can also be a hybrid capacitor including both capacitive and resistive components. For example, the capacitor 375 can be constructed as a capacitor and a resistor connected in series. Due to the large di / dt required under high-current operation, ringing effects and voltage surges may occur during the off period of the high-side switch or the low-side switch. Typically, ringing frequencies can be observed in the range of 100 MHz. In contrast to using only a decoupling capacitor, a series resistor and capacitor can effectively suppress this ringing effect. At an operating current of around 30A, capacitor values ​​can range from 0.01nF to 100nF, and resistor values ​​from 0.1 ohms to 100 ohms. Designers can also choose higher resistor and capacitor values ​​to bias towards under-damped conditions.

[0058] Figures 5A and 5B respectively show plan and cross-sectional views of another electronic module 500 that provides improved performance and reliability as well as reduced complexity compared to the integrated electronic module 300. The electronic module 500 utilizes the common-source switch 600 shown in Figure 6 as its high-side switch 582 and / or low-side switch 583. As described in more detail below, the design of the common-source switch 600 for the high-side switch 582 and low-side switch 583 allows for the elimination of certain external connectors in the electronic module 500, resulting in reduced complexity and improved performance and reliability of the module 500.

[0059] As shown in Figure 6, the common-source switch 600 used in the electronic module 500 is similar to the common-source switch 400 used in the integrated electronic module 300, but with some added features. First, the substrate 611 on which the III-N material structure 618 is formed is a conductive substrate (e.g., formed of p-type silicon, n-type silicon, p-type GaN, n-type GaN, or n-type SiC), so that the substrate is electrically connected (i.e., short-circuited) to the top metal layer of the electronic module 500 on which the substrate is mounted.

[0060] Furthermore, the gate electrode 635 of the high-voltage depletion transistor 623 is electrically connected to the conductive substrate 611 via a via 638 (e.g., a through-epi-epi-epitaxy via or TEV), the via 638 being formed through a portion of the III-N material structure 618. The via 638 may be formed to extend through the entire thickness of the III-N material structure 618 and all the way to the substrate 611, as shown by the dashed area in FIG6. The metal of the gate electrode 635 is at least partially formed in the via 638 and makes ohmic contact with the conductive substrate 611, such that the gate electrode 635 of the high-voltage depletion transistor 623 is electrically connected to the conductive substrate 611. Although the dashed area in FIG6 shows a via 638 through the 2DEG channel 619, the via 638 is formed in such a manner that the 2DEG channel 619 is continuous between the source electrode 634 and the drain electrode 636 of the depletion-type device (e.g., the via may be formed in a portion of the III-N material outside the active region of the III-N transistor).

[0061] Finally, a back metal layer 617 (e.g., Ti / Ni / Ag) may be optionally formed on the back side of the conductive substrate 611 opposite to the III-N material structure 618. The back metal layer 617 may serve as a bonding layer to allow the substrate 611 to be attached to the underside metal plane in the module 500 via solder, solder paste, conductive epoxy resin, conductive tape, or other suitable attachment methods that allow the device substrate 611 to be connected to the metal layer with high-quality mechanical, thermal, and electrical connections.

[0062] Referring back to Figures 5A and 5B, in order to form the half-bridge module 500, a first common-source common-gate switch (e.g., common-source common-gate switch 600) is directly mounted on the output board 512 to form a high-side switch 582, and a second common-source common-gate switch (e.g., common-source common-gate switch 600) is directly mounted on the ground plane 513 to form a low-side switch 583. For the high-side switch 582, since the gate electrode 635 of the depletion transistor is electrically connected to the conductive substrate 611 through the through-hole 638, and the conductive substrate is directly mounted on the output board 512, the gate electrode 635 is electrically connected to the output board 512 without the need for an external connector (e.g., the wire connector 340 in Figures 3A and 3B). Similarly, for the low-side switch 583, since the gate electrode 635' of the depletion transistor is electrically connected to the conductive substrate via a via, and the conductive substrate is directly mounted on the ground plane 513, the gate electrode 635' is electrically connected to the ground plane 513 without the need for external connectors (e.g., wire connector 346 in Figures 3A and 3B). Therefore, the assembly of the module 500 is simplified, and the circuit inductance is reduced, thereby reducing switching noise and EMI.

[0063] For completeness, other features and characteristics of module 500 and the common-source switch 600 used in module 500 are as follows. Referring to FIG6, the common-source switch 600 includes a low-voltage enhancement-mode transistor 622 directly mounted on the source electrode 634 of the high-voltage depletion transistor 623, the FET drain electrode 653 of the low-voltage enhancement-mode transistor 622 being directly bonded to the source electrode 634 of the high-voltage depletion transistor 623. The low-voltage enhancement-mode transistor 622 may be, for example, a silicon FET, and the depletion transistor may be, for example, a III-N HEMT. The common-source switch 600 may operate in the same manner as a single high-voltage enhancement-mode III-N transistor and, in many cases, achieve the same or similar output characteristics as a single high-voltage enhancement-mode III-N transistor. The high-voltage depletion transistor 623 has a larger breakdown voltage than the low-voltage enhancement-mode transistor 622 (e.g., at least three times larger). The common-source common-gate switch 600 can block a maximum voltage that is at least as large as the maximum blocking voltage or breakdown voltage of the high-voltage depletion transistor 623 when the bias is in the off state.

[0064] The low-voltage enhancement-mode transistor 622 includes a semiconductor body layer 655. The low-voltage enhancement-mode transistor 622 also includes a FET source electrode 651 and a FET gate electrode 652 on a first side of the semiconductor body layer 655, and a FET drain electrode 653 on a second side of the semiconductor body layer 655 opposite to the FET source electrode 651.

[0065] The high-voltage depletion transistor 623 includes a III-N material structure 618, such as a combination of GaN and AlGaN, grown on a conductive substrate 611, which may be silicon (e.g., p-type silicon or n-type silicon), GaN (e.g., p-type GaN or n-type GaN), n-type SiC, or any other sufficiently conductive substrate.

[0066] The III-N material structure 618 may include a III-N buffer layer 612, such as GaN or AlGaN, grown over a substrate 611. The buffer layer 612 may be insulating or substantially free of unintentional n-type charge carriers. The buffer layer 612 may have a substantially uniform composition, or the composition may vary. The thickness and composition of the buffer layer 612 may be optimized for high-voltage applications. That is, the buffer layer is capable of blocking voltages equal to or greater than the voltage of the high-voltage power supply or the maximum voltage in the circuit using it. For example, the buffer layer 612 is capable of blocking voltages greater than 600V or greater than 900V. The thickness of the buffer layer 612 may be greater than 2μm. For example, the III-N buffer layer may have a thickness between 5μm and 10μm.

[0067] The III-N material structure may further include a III-N channel layer 613 (e.g., GaN) above the III-N buffer layer 612, and a III-N barrier layer 614 (e.g., AlGaN, AlInN, or AlGaInN) above the III-N channel layer 613. The band gap of the III-N barrier layer 614 is larger than that of the III-N channel layer 613. The III-N channel layer 613 has a different composition than the III-N barrier layer 614, and the thickness and composition of the III-N barrier layer 614 are chosen such that a two-dimensional electron gas (2DEG) channel 619 (represented by the dashed line in FIG. 6) is adjacent to the interface between layers 614 and 613 in the III-N channel layer 613.

[0068] Typically, III-N high electron mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown in a reactor by molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD). The III-N material structure can be grown in a group III polar (e.g., Ga polar) orientation, such as a [0 0 0 1] (C-plane) orientation, as shown in Figure 6. Alternatively, a III-N HEMT can be formed on a III-N material structure grown in an N polar (i.e., N-plane) orientation (e.g., a [0 0 0 -1] orientation, not shown). In an N polar device, a III-N barrier layer can be placed on top of a III-N buffer layer, and a III-N channel layer can be placed on top of the III-N barrier layer. N polar III-N materials have a polarization field in the opposite direction to that of group III polar III-N materials, thus enabling the realization of III-N device structures that cannot be formed using group III polar structures.

[0069] An insulating layer 615 (e.g., a dielectric layer) is grown or deposited over the top surface of the III-N material structure 618. The insulating layer 615 may be formed, for example, of alumina (Al2O3), silicon dioxide (SiO2), SixNy, Al1-xSixN, Al1-xSixO, Al1-xSixON, or any other wide-bandgap insulator, or include one or more of the above. Although the insulating layer 615 is shown as a single layer, it may also be formed from multiple layers and / or materials deposited during different processing steps to form a single combined insulating layer.

[0070] The source electrode 634 and drain electrode 636 are formed on the side of the high-voltage depletion transistor 623 opposite to the substrate, such that the high-voltage depletion transistor 623 is characterized as a lateral III-N device (i.e., the source and drain electrodes are on the same side of the device, and current flows laterally through the device between the source electrode 634 and the drain electrode 636). The source electrode 634 and drain electrode 636 can each be formed by stacking multiple metal layers. For example, each metal stack can be a Ti / Al / Ni / Au, Ti / Al, or other suitable metal layer stack.

[0071] The high-voltage depletion transistor 623 further includes a gate electrode 635. The gate electrode 635 may be formed such that the insulating layer 615 is at least partially located between the gate electrode and the III-N material structure 618, as shown in FIG6. The gate electrode 435 may be formed of a suitable conductive material, such as a metal stack, such as titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au).

[0072] The low-voltage enhancement-mode transistor 622 is electrically connected to the high-voltage depletion-mode transistor 623 to form a common-source, common-gate switch 600. Here, the FET drain electrode 653 of the low-voltage enhancement-mode transistor 622 directly contacts (e.g., is mounted on) the source electrode 634 of the high-voltage depletion-mode transistor 623 and is electrically connected to the source electrode 634 of the high-voltage depletion-mode transistor 623. The FET drain electrode 653 of the low-voltage enhancement-mode transistor 622 can be connected to the source electrode 634 of the high-voltage depletion-mode transistor 623, for example, using solder, solder paste, conductive epoxy, conductive tape, or other suitable attachment methods, which allows for a high-quality mechanical, thermal, and electrical connection between the FET drain electrode 653 and the source electrode 634 of the high-voltage depletion-mode transistor. The low-voltage enhancement transistor 622 can be mounted above the 2DEG channel 619, as shown in Figure 6, or the low-voltage enhancement transistor 622 can be partially or completely mounted in a region outside the active region of the device, so that the low-voltage enhancement transistor 622 is not above the 2DEG channel layer.

[0073] Referring now back to Figures 5A and 5B, module 500 includes a direct bonding copper (DBC) substrate 510 (best visible in Figure 5B), which may serve as the base substrate of the module. The DBC substrate 510 includes an insulating (e.g., ceramic) substrate 515 on which a top metal layer (e.g., copper) is patterned at least as a first portion serving as a high-voltage board 511, a second portion serving as an output board 512, and a third portion serving as a ground plane 513. The high-voltage board 511, the output board 512, and the ground plane 513 are each electrically isolated from each other by trenches 514 formed through the top metal layer. Optionally, the DBC substrate 510 includes a back metal layer 516 on the side of the insulating substrate 515 opposite to the top metal layer (high-voltage board 511 / output board 512 / ground plane 513). The ground plane 513 may optionally be electrically connected to the back metal layer 516 by forming metal vias 517 through the insulating substrate 515. As shown in Figure 6, both the high-side switch 582 and the low-side switch 583 are common-source, common-gate switches. The high-side switch 582 is directly mounted on the output board 512, and the low-side switch 583 is directly mounted on the ground plane 513.

[0074] For the high-side switch 582, the drain electrode 636 of the depletion-type transistor is electrically connected to the high-voltage board 511 via a wire connector 541, and the FET source electrode 651 of the enhancement-type transistor is electrically connected to the output board 512 via a wire connector 542. For the low-side switch 583, the drain electrode 636' of the depletion-type transistor is electrically connected to the output board 512 via a wire connector 543, and the FET source electrode 651' of the enhancement-type transistor is electrically connected to the ground plane 513 via a wire connector 544. The wire connectors 541-544 may include a single bonding lead (as shown) or multiple parallel bonding leads, strips, conductive metal clips, or other connectors including conductive materials (such as aluminum (Al), gold (Au), copper (Cu), or other suitable materials).

[0075] The electronic module 500 may optionally include a package for packaging electronic components, the package including a first input lead 572, a second input lead 573, a high-voltage lead 591, a ground lead 593, and an output lead 592. The first input lead 572 is connected to the FET gate electrode 652 of the enhancement transistor of the high-side switch 582, the second input lead 573 is connected to the FET gate electrode 652' of the enhancement transistor of the low-side switch 583, the high-voltage lead 591 is connected to the high-voltage board 511, the ground lead 593 is connected to the ground plane 513, and the output lead 592 is connected to the output board 512.

[0076] To ensure the correct operation of the half-bridge circuit formed by the electronic modules 500 of Figures 5A and 5B, the high-voltage lead 591 should be kept AC grounded. In other words, the high-voltage lead 591 can be capacitively coupled to the ground lead 593 by connecting the first end of the capacitor 575 to the high-voltage plate 511 and the second end of the capacitor 575 to the ground lead 593. As shown in Figure 5A, the capacitor 575 can be located directly on a portion of the trench 514. When the high-side switch 582 or the low-side switch 583 is turned on or off, the capacitor 575 can be charged or discharged as needed to provide the current required to maintain a substantially constant voltage on the high-voltage and low-voltage sides of the circuit. Furthermore, the capacitor 575 can also be a hybrid capacitor including both capacitive and resistive components. For example, the capacitor 575 can be constructed as a capacitor and a resistor connected in series. Due to the need for a large di / dt under high-current operation, ringing effects and voltage surges may occur during the off period of the high-side switch or the low-side switch. Typically, ringing frequencies can be observed in the range of 100 MHz. In contrast to using only a decoupling capacitor, a series resistor and capacitor can effectively suppress this ringing effect. At an operating current of around 30A, capacitance values ​​can be greater than 0.1nF (e.g., in the range of 0.1nF to 100nF), and resistance values ​​can be greater than 0.1 ohms (e.g., in the range of 0.1 ohms to 100 ohms). Designers can also choose higher resistor and capacitor values ​​to bias towards under-damped conditions.

[0077] Figures 7A, 7B, and 7C show three different modes of operating a half-bridge buck converter circuit (similar to the half-bridge in Figure 1A). The half-bridge circuit includes a high-side switch 102 connected to high-voltage node 111 and a low-side switch 103 connected to ground node 113. An inductor 104 is connected between node 112 (between low-side switch 103 and high-side switch 102) and the circuit's output node VOUT. A first capacitor 106 is connected between high-voltage node 111 and DC ground 113. A second capacitor 107 is connected between the circuit's output node VOUT and DC ground 113. Low-side switch 103 and high-side switch 102 are selected to have characteristics that improve the efficiency of the buck converter circuit. Specifically, high-side switch 102 and low-side switch 103 should have low on-resistance (RDS(ON)) and low switching losses. The high-side switch 102 and / or the low-side switch 103 can be formed together, for example, with the common-source switch 200 of FIG2. Alternatively, the high-side switch 102 and / or the low-side switch 103 can be implemented as the common-source switch 600 of FIG6 assembled in the half-bridge module 500 of FIG5A.

[0078] The buck converter half-bridge of Figures 7A-7C can operate as follows: Referring to Figure 7A, in the first operating mode, the gate of the high-side switch 102 is biased to conduct (i.e., VGS102 > VTH) and the low-side switch 103 is biased to turn off (i.e., VGS103 < VTH). Current 97 flows forward from high-voltage node 111 through high-side switch 102 to node 112. The current is blocked by low-side switch 103 and flows through inductor 104, as shown by current path 97. When the device operates in the first operating mode, if the gate-to-source voltage of high-side switch 102 switches to low or off (i.e., switches to VGS102 < VTH), causing the gates of both high-side switches 102 and low-side switch 103 to be biased to turn off, the half-bridge switches to the second operating mode shown in Figure 7B. Current continues to flow through inductor 104.

[0079] Figures 7D and 7E show circuit diagrams of a common-source common-gate switch (e.g., the common-source common-gate switch 200 of Figure 2), and also show the various parasitic inductors and capacitors inherent in the common-source common-gate configuration. The parasitic gate-to-drain capacitance (CGD) of the high-voltage depletion transistor 223 is represented as parasitic gate-to-drain capacitor 57. The intrinsic body diode of the low-voltage enhancement-type transistor 222 is represented by diode 237. The parasitic inductor connected to the source of the low-voltage enhancement-type transistor 222 is represented as parasitic inductor 254, while the parasitic inductor connected to the gate of the high-voltage depletion transistor 223 is represented as parasitic inductor 253. When the circuits of Figures 7D and 7E are implemented as the low-side switch 383 in a half-bridge module, similar to the integrated electronics module 300 of Figure 3A, the parasitic inductor 254 represents the inductance value of the wire (e.g., wire connector 348 in Figure 3A) that connects the FET source electrode 451' of the enhancement transistor to the ground plane 313. To connect the gate electrode 435' of the depleted transistor of the low-side switch 383 to the FET source electrode 451' of the enhancement transistor of the low-side switch 383, an external gate wire connector 346 is used to connect the gate electrode 435' of the depleted transistor to the ground plane 313. This gate wire connector 346 creates a significant inductance between the gate electrode 435' of the depleted transistor and the ground plane 313 (represented by parasitic inductor 253 in Figure 7D). Parasitic inductors 253 and 254 slow down the turn-on and turn-off times of the module, increase switching losses, and thus reduce the efficiency of the circuit.

[0080] Figure 7D illustrates the detailed current path of the common-source, common-gate configuration of the low-side switch 103 during the transition time T1 between the first and second operating modes shown in Figures 7A and 7B. During the transition time T1, the voltage at node 112 (shown in Figures 7A-7B) is pulled down until it becomes negative, and displacement current flows through the parasitic gate-drain capacitor 57 of the high-voltage depletion transistor 223, as shown by the current path IAC in Figure 7D. When the voltage at node 112 becomes sufficiently negative, although the gate of the low-side switch 103 is biased to be off (i.e., VGS < VTH), the intrinsic body diode 237 of the low-voltage enhancement-mode transistor 222 is switched on, and the low-side switch 103 becomes reverse-conducting. This is referred to as the reverse-conducting mode (i.e., freewheeling diode mode). At the end of transition time T1, the low-side switch 103 transitions from off to reverse conduction, and the current suddenly changes from the displacement current of the parasitic gate-drain capacitor 57 of the high-voltage depletion transistor 223 (shown in FIG. 7D) to a reverse DC current. The reverse DC current flows through the intrinsic body diode 237 of the low-voltage enhancement-mode transistor 222 and the channel of the high-voltage depletion transistor 223, as shown by the current path IDC in FIG. 7E.

[0081] When the operating current of inductor 104 is high, the current path change causes voltage spikes and ringing at the gate of the high-voltage depletion transistor 223. This voltage surge injects charge into the gate dielectric of the depletion transistor (e.g., insulating layer 415 or 615) and causes an increase in the on-resistance (RON) of the depletion transistor, thereby increasing the on-resistance of the low-side switch 383. Even though the gate of the low-side switch 103 is biased to turn off because the current in inductor 104 must be continuous, reverse conduction of the low-side switch 103 also occurs in the circuit of FIG. 7B.

[0082] Returning to Figure 7C, after the gate of the high-side switch 102 is turned off, as shown in Figure 7B, the low-side switch 103 is switched on (i.e., switched to VGS > VTH), causing the buck converter to operate in the third operating mode, in which current 98 continues to flow through the low-side switch 103 in the same direction (reverse direction) as in the second mode, but the low-side switch 103 is biased to conduct. Compared to the second operating mode, biasing the low-side switch to conduct during the third operating mode reduces the voltage drop across the low-voltage enhancement transistor 222 in the reverse direction and allows for higher efficiency compared to the second operating mode. Sufficient dead time is provided between turning off the high-side switch 102 and turning on the low-side switch 103 to prevent accidental short-circuiting of the high-voltage node 111 to the ground node 113.

[0083] The design of the common-source common-gate switch and related modules can be a key factor determining the performance of the low-side switch 103 during reverse conduction mode. By implementing the common-source common-gate switch 600 into the half-bridge module 500 as the low-side switch 103, the need for an external gate wire connection (e.g., wire connector 346 in FIG. 3A) between the depletion transistor of the low-side switch 583 and the ground plane 513 in the module 500 is eliminated (because the gate of the depletion transistor is connected to the ground plane 513 through via 638), and the parasitic inductance in the half-bridge module (shown by parasitic inductor 253 in FIG. 7D) is reduced. This correspondingly reduces the voltage surge and ringing effects experienced at the gate of the depletion transistor of the low-side switch 583 during the current path transition between the first and second operating modes. Surprisingly, this shows a significant reduction in the degradation (i.e., increase) of the switch's path on-resistance compared to conventional modules with external gate leads when operating under very high reverse DC currents. This result is unexpected. The inventors believed that the contribution of the gate lead inductor of the depletion transistor to the module's switching performance was negligible because no DC current flows in this path, and the gate voltage of the depletion transistor of the low-side switch is typically grounded. This degradation of on-resistance is often referred to as current-collapse or dispersion, a major problem in implementing III-N devices in half-bridge circuits. When the common-source common-gate switch 600 is implemented as a low-side switch 583 in the half-bridge module 500, the low-side switch 583 is able to operate with reverse DC currents greater than 50A or even greater than 70A during the second and third operating modes with almost no increase in on-resistance. For example, the increase in on-resistance relative to the first operating mode can be less than 5%. Even when operating at a reverse DC current of 30A or lower, conventional modules with external gate lead connections typically exhibit an increase in on-resistance of more than 30%. The low-side switch 583 is capable of blocking voltages greater than 600V during the first operating mode.

[0084] Furthermore, the high-side switch 582 can operate in reverse conduction mode during certain switching sequences. Here, the gate connection between the depletion-type III-N transistor of the high-side switch 582 and the output board 512 is connected through via 638, further reducing parasitic inductance in the electronic module. This further reduces voltage surges and ringing effects experienced by the high-side switch 582 during current path transitions when switching to reverse conduction mode.

[0085] Figure 8 is a top view of the integrated electronic module 800, which forms a half-bridge circuit similar to the integrated electronic half-bridge module 500 of Figure 5A, with an alternative DBC 810 layout, which enables a more compact orientation of the high-voltage board 811, output board 812, and ground plane 813 compared to the module 500 of Figure 5A. This reduces the size and footprint of the electronic module and lowers costs. The module 800 also includes a high-side source sensing node 896 and a low-side source sensing node 897. Although not shown in Figure 5A, the module 500 may also include sensing nodes 896 and 897. The high-side source sensing node 896 is connected to the output board 812, and the low-side source sensing node 897 is connected to the ground plane 813. A first input lead 872, a high-side source sensing node 896, a second input lead 873, and a low-side source sensing node 897 (collectively referred to as gate nodes) extend from a first side of module 800 such that all gate nodes extend from the same side of the module and are configured to connect to an external gate driver. In some cases, the high-side gate node may be connected to a high-side gate driver, and the low-side gate node may be connected to a low-side gate driver. A high-voltage node 891, a ground node 893, and an output node 892 extend from a second side of module 800 opposite to the first side, wherein the high-voltage node 891 is configured to connect to a circuit high-voltage power supply, the ground node 893 is configured to connect to circuit ground, and the output node 892 is configured to connect to an inductor component or a circuit load. Compared to the low-side switch 883 in module 800, the high-side switch 882 is oriented with a 90° rotation to allow for a more compact module component arrangement and allows for shorter connection leads to the DBC 810. Specifically, in the high-side switch 882, the source electrode 634 and the drain electrode 636 are arranged along a first axis, while in the low-side switch 883, the source electrode 634' and the drain electrode 636' are arranged along a second axis, which is perpendicular to the first axis.

[0086] Figure 9 is a top view of an integrated electronic module 900, which forms a half-bridge circuit integrated into a surface mount power device (SMPD) type package. The half-bridge circuit configured in the integrated electronic module 900 is similar to the electronic module 500 of Figure 5A, but includes additional metal wiring layers on the DBC 910 and connector leads to accommodate source sensing pins and ferrite beads connecting the gate. The integrated electronic module 900 includes a high-side switch 582 and a low-side switch 583, which may be the same as those in the module 500 of Figure 5A. The integrated electronic module 900 includes a DBC 910, which includes a high-voltage board 911, an output board 912, and a ground plane 913, wherein each board is separated by a trench 914 formed in the top metal layer of the DBC 910. DBC 910 can be constructed in a similar manner to DBC substrate 510 of Figures 5A and 5B, but the separation pattern with trench 914 results in an alternating top metal layer configuration. The integrated electronic module 900 further includes a high-voltage lead 991 connected to high-voltage board 911, an output lead 992 connected to output board 912, and a ground lead 993 connected to ground plane 913. The integrated electronic module 900 further includes a first input lead 961 (which may be multiple leads), a high-side source detection lead 962, a second input lead 963 (which may be multiple leads), and a low-side source detection lead 964. The integrated electronic module 900 includes a hybrid capacitor 575 connected between high-voltage board 911 and ground plane 913, similar to module 500 of Figure 5A.

[0087] FIG9 further includes an optional high-side ferrite bead 68 and an optional low-side ferrite bead 69. The high-side ferrite bead 68 includes a first end electrically coupled to a first input lead 961 and a second end electrically coupled to a first side of a high-side gate connector 65. The high-side gate connector 65 includes a second side of a gate electrode connected to an enhancement transistor of the high-side switch 582. The low-side ferrite bead 69 includes a first end electrically coupled to a second input lead 963 and a second end electrically coupled to a first side of a low-side gate connector 67. The low-side gate connector 67 includes a second side of a gate electrode connected to an enhancement transistor of the low-side switch 583. The integrated electronic module 900 further includes a source detection connector 66, which has a first side electrically connected to the high-side source detection lead 962 and a second side electrically connected to the output board 912. The source detection connector 66 is used to bridge the ground plane 913 and allow the high-side source detection lead 962 to be at the same potential as the source of the high-side switch 582. The high-side gate connector 65, the source detection connector 66, and the low-side gate connector 67 may include a single bonding lead (as shown) or multiple parallel bonding leads, a strip, a conductive metal clip, or other connectors including conductive materials (such as aluminum (Al), gold (Au), copper (Cu), or other suitable materials).

[0088] As shown in Figure 9, the high-side switch 582 is directly mounted to the output board 912, which results in the gate of the depleted III-N transistor of the high-side switch 582 being directly electrically connected to the output board 912 through the substrate of the high-side switch 582 without the need for external lead connectors. Furthermore, the low-side switch 583 is directly mounted to the ground plane 913, which results in the gate of the depleted III-N transistor of the low-side switch 583 being electrically connected to the ground plane 913 through the substrate of the low-side switch 583 without the need for external lead connectors. A hybrid capacitor 575 is connected between the first input lead 931 on the input side of the integrated electronic module 900 and the high-side switch 582. Integrating the high-side switch 582 and the low-side switch 583 into an SMPD-type package allows for simplified and efficient integration of the half-bridge circuit into an industry-standard power device package.

[0089] FIG10 is a top view of an integrated electronic module 1000 similar to the integrated electronic module 900 of FIG9, but the integrated electronic module 1000 connects a hybrid capacitor 1075 between a high-voltage board 1011 and a ground plane 1013 on the output side of the integrated electronic module 1000, whereas it is connected on the input side of the module as shown in FIG9. The integrated electronic module 1000 includes a DBC 1010, which includes a high-voltage board 1011, an output board 1012, and a ground plane 1013, wherein each board is separated by a trench 1014 formed in the top metal layer of the DBC 1010. The DBC 1010 can be constructed in a similar manner to the DBC substrate 510 of FIG5A and FIG5B, but the separation pattern of the trench 1014 results in an alternating top metal layer configuration. Here, both the high-side switch 582 and the high-side source detection lead 962 are directly connected to the first output board 1012, and the source detection connector 66 of FIG. 6 is removed. The connector 66' of the integrated electronic module 1000 has a first side connected to the output board 1012 and a second side connected to the second output board 1012'. The output lead 992 directly contacts the second output board 1012', such that the output lead 992 and the source of the high-side switch 582 are at the same potential.

[0090] Figure 11 is a top view of an integrated electronic module 1100 similar to the integrated electronic module 1000 of Figure 10. However, the integrated electronic module 1100 includes a capacitor 1174 and a resistor 1175 as two separate discrete components connected in series (as opposed to the integrated electronic module 1000 which uses a single hybrid capacitor 1075) to connect the high-voltage board 1111 to the ground plane 1113, so as to keep the high-voltage board 1111 to AC ground on the DBC 1110. Using two separate discrete components allows circuit designers to modify package performance with additional component selection. Furthermore, the relative order of the capacitor 1174 and the resistor 1175 in the series circuit can be interchanged.

[0091] Figure 12 is a top view of an integrated electronic module 1200 similar to the integrated electronic module 1000 in Figure 10, but the integrated electronic module 1200 is implemented using a source ferrite bead 1266, which has a first terminal electrically coupled to the source voltage of the high-side switch 582 and a second terminal electrically coupled to the output lead 992. The source ferrite bead 1266 can be implemented such that the ferrite bead bridges the high-voltage board 1011, similar to connector 66' in Figure 10. Using the source ferrite bead 1266 instead of connector 66' to implement the integrated electronic module 1200 can reduce voltage ringing and other switching noise at the output node, which can further improve the operation of the half-bridge module.

[0092] Figures 13A and 13B show side and top views, respectively, of an external schematic diagram of a fully packaged SMPD-type package that can be used for integrated electronic modules 900-1200. The fully packaged package includes a molding compound 1311, which can be a plastic, epoxy resin, metal, or other suitable material to hermetically seal and electrically package the components of the integrated electronic module.

[0093] Integrated electronic modules 900, 1000, 1100, and 1200 show a surface mount power device (SMPD) package type, but alternative module packages, such as quad flat no-lead (QFN) or lossless package (LFPAK) or other suitable types of module packages, can be used to adequately accommodate the high-side switch 582 and the low-side switch 583 to form a half-bridge circuit. Furthermore, the components of integrated electronic modules 900-1200 can be oriented or arranged in a manner best suited to the needs of the designer and package type.

[0094] Figure 14 is a top view of an integrated electronic module 1400 similar to the integrated electronic module 500 in Figure 5A, but the integrated electronic module 1400 uses two high-side switches (582 and 582a) and two low-side switches (583 and 583a) connected in parallel. Connector 41a connects the high-voltage board 11 to the drain electrode 36a of the depletion transistor of the high-side switch 582a. Connector 42a connects the source electrode 51a of the enhancement transistor of the high-side switch 582a to the output board 12. Connector 43a connects the output board 12 to the drain electrode 36a' of the depletion transistor of the low-side switch 583a, and connector 44a connects the source electrode 51a' of the enhancement transistor of the low-side switch 583a to the ground plane 13. The first input lead 572 is connected to the gate electrode of the enhancement transistor of each high-side switch 582 and 82a, and the second input lead 573 is connected to the gate electrode of the enhancement transistor of each low-side switch 583 and 583a. Here, the substrates of the high-side switch 582 and 582a are both in contact with and electrically connected to the same portion of the top metal layer of the DBC 1410 forming the output board 12. Similarly, the substrates of the low-side switch 583 and 583a are both in contact with and electrically connected to the same portion of the top metal layer of the DBC 1410 forming the ground plane 13. By mounting the switches to the same portion of the top metal layer, the integrated electronic module 1400 with multiple parallel switches can be configured, improving the module's operating efficiency and achieving a higher total rated power.

[0095] During the operation of the integrated electronic module 1400, when the first input lead 572 is turned on or off, both the high-side switch 582 and the high-side switch 582a are simultaneously turned on or off. Similarly, when the second input lead 573 is turned on or off, both the low-side switch 583 and the low-side switch 583a are simultaneously turned on or off. Typically, when a half-bridge circuit uses multiple discrete components in parallel, external wiring is used, which can cause circuit mismatch problems during high-speed switching. Integrating the switching transistors into the same electronic module can reduce switching mismatch problems and improve overall circuit performance. Although two high-side and two low-side switches are shown in Figure 14, there can be, for example, three or four high-side and low-side switches connected in parallel. Theoretically, there is no limit to the number of switches that can be connected in parallel in this way.

[0096] Referring back to Figure 1B, a circuit diagram of a three-phase full-bridge circuit 120 is shown. Each of the three half-bridges 122, 124, and 126 in circuit 120 can be implemented using an integrated electronic module, such as the integrated electronic modules 300 to 1400 described in this specification.

[0097] Figure 15 is a top view of an electronic module 1500, which includes an integrated three-phase full-bridge circuit, such as circuit 120 of Figure 1B, in a single package. The first phase half-bridge circuit includes a high-side switch 82 and a low-side switch 83. The second phase half-bridge circuit includes a high-side switch 82' and a low-side switch 83'. The third phase half-bridge circuit includes a high-side switch 82" and a low-side switch 83". All high-side and low-side switches can be implemented using the common-source switch 600 of Figure 6. The electronic module 1500 includes a DBC layer 1510, wherein the top metal layer of the DBC layer 1510 is patterned into at least five sections separated by trenches 1514 formed through the top metal layer of the DBC layer 1510. The first section serves as a high-voltage board 14, which is configured to be connected to a DC high-voltage input via a high-voltage lead 91. The second section serves as an output board 15 connected to the output node of the first phase 92. The third part serves as the output board 16 connected to the output node of the second phase 92'. The fourth part serves as the output board 17 connected to the output node of the third phase 92". The fifth part serves as the ground plane 18, which is configured to be connected to the DC ground via the ground lead 93.

[0098] The substrates of high-side switches 82, 82', and 82" are respectively contacted and electrically connected to output boards 15, 16, and 17. The substrates of low-side switches 83, 83', and 83" are contacted and electrically connected to ground plane 18, such that all low-side switches are contacted and electrically connected to the same metal portion of DBC layer 1510. The substrates of high-side switches 82, 82', and 82" are electrically isolated from each other. The drain electrode 36 of the depletion transistor node of high-side switch 82 is connected to high-voltage board 14 via connector 41, the drain electrode 36' of the depletion transistor of high-side switch 82' is connected to high-voltage board 14 with connector 41', and the drain electrode 36" of the depletion transistor of high-side switch 82" is connected to high-voltage board 14 via connector 41". The source electrode 34 of the enhanced transistor node of the high-side switch 82 is connected to the output board 15 via connector 42, the source electrode 34' of the enhanced transistor of the high-side switch 82' is connected to the output board 16 with connector 42', and the source electrode 34" of the enhanced transistor of the high-side switch 82" is connected to the output board 17 via connector 42". The drain electrode 56 of the depletion transistor of the low-side switch 83 is connected to the first phase output board 15 via connector 43, the drain electrode 56' of the depletion transistor of the low-side switch 83' is connected to the second phase output board 16 via connector 43', and the drain electrode 56" of the depletion transistor of the low-side switch 83" is connected to the third phase output board 17 via connector 43". The source electrode 54 of the enhanced transistor node of the low-side switch 83 is connected to the ground plane 18 via connector 44, the source electrode 54' of the enhanced transistor of the low-side switch 83' is connected to the ground plane 18 via connector 44', and the source electrode 54" of the enhanced transistor of the low-side switch 83" is connected to the ground plane 18 via connector 44".

[0099] The gate driver uses three independent gate signals to operate the high-side switch and three independent gate signals to operate the low-side switch to operate module 1500. Each independent high-side gate signal from the gate driver can be connected to gate input nodes 94, 94', and 94" and each independent low-side gate signal from the gate driver can be connected to gate input nodes 95, 95', and 95" respectively. Integrating the three-phase full-bridge circuit 120 of FIG. 1B into a single integrated electronic device module 1500 can significantly improve switching efficiency while reducing circuit complexity. Although not shown for simplicity, module 1500 may include a gate driver integrated in the same package as the components of module 1500. The gate driver can be configured in a similar manner to that described below with respect to FIG. 16.

[0100] Figure 16 is a top view of an integrated electronic module 1600 forming a half-bridge circuit similar to the integrated electronic half-bridge module 500 of Figure 5A. However, the integrated electronic module 1600 also includes a gate driver 1620 integrated within the same module package as the high-side switch 582 and the low-side switch 583. Components with the same number include the same or similar features as those in the module 500. The integrated electronic module 1600 includes a DBC 1610. The DBC 1610 includes a high-voltage board 511, an output board 512, and a ground plane 513, and optionally a driver board 515, all separated by a trench 514. The gate driver 1620 can be mounted to the driver board 515, or the gate driver 1620 can be directly mounted to the structural package base of the module, such as a copper or nickel lead frame (not shown). Driver board 515 can be configured in multiple portions to accommodate and attach multiple leads extending from or connected to gate driver 1620. Gate driver 1620 includes at least a first terminal 1622 (VIN of high-side switch 582) of the FET gate electrode 652 of the enhancement transistor connected to high-side switch 582. Gate driver 1620 includes a second terminal 1623, which is a high-side source current sensing node and is connected to output board 512, or optionally directly connected to the FET source electrode 651 of the enhancement transistor of high-side switch 582 (not shown). Gate driver 1620 includes a third terminal 1624 (VIN of low-side switch 583) of the FET gate electrode 652' of the enhancement transistor connected to low-side switch 583. Gate driver 1620 includes a fourth terminal 1626 serving as a low-side source current sensing node and is connected to a ground plane 513, or optionally directly to the FET source electrode 651' of an enhancement transistor in a low-side switch 583 (not shown). While integrating gate driver 1620 into integrated electronic module 1600 increases cost and complexity compared to module 500, the overall performance of integrated electronic module 1600 can be superior to that of integrated electronic module 500 operating with an external gate driver. Furthermore, the overall size of the electronic circuitry components that can be incorporated into integrated electronic module 1600 can be reduced, resulting in cost savings and other advantages. Although not shown, gate driver 1620 can alternatively be two discrete gate drivers, such that a first gate driver is connected to a high-side switch and a second gate driver is connected to a low-side switch.

[0101] FIG17 is a top view of an integrated electronic module 1700 forming a half-bridge circuit similar to the integrated electronic module 1600 of FIG16. However, the integrated electronic module 1700 includes a gate driver 1720, in which the enhancement transistor of the high-side switch 582 and the enhancement transistor of the low-side switch 583 are integrated. The high-side depleted III-N transistor 1782 is mounted to the output board 512, and the low-side depleted III-N transistor 1783 is mounted to the ground plane 513. The gate driver 1720 includes at least a first terminal 1721 that connects the source of the integrated enhancement transistor of the high-side switch to the output board 512. This connection couples the source of the enhancement transistor to the output terminal 592 and the conductive substrate of the high-side depleted III-N transistor 1782. Gate driver 1720 includes a second terminal 1722 that connects the drain of the integrated enhancement transistor of the high-side switch to the source electrode 634 of the high-side depleted III-N transistor 1782. Gate driver 1720 includes a third terminal 1724 that connects to the source of the integrated enhancement transistor of the low-side switch and ground plane 513. This connection couples the source of the enhancement transistor to ground lead 593 and the conductive substrate of the low-side depleted III-N transistor 1783. Gate driver 1720 includes a fourth terminal 1725 that connects the drain of the integrated enhancement transistor of the low-side switch to the source electrode 634' of the low-side depleted III-N transistor 1783. Compared to the integrated electronic module 1600, integrating the enhanced transistors of the high-side and low-side switches into the gate driver 1720 reduces the complexity of the integrated electronic module 1700 and lowers the overall assembly cost. Although not shown, the gate driver 1720 can alternatively be two discrete gate drivers, such that the first gate driver is connected to the high-side switch and the second gate driver is connected to the low-side switch.

[0102] Several specific embodiments have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of the technology and apparatus described herein. Therefore, other embodiments exist within the scope of the following claims. [Simplified Explanation of the Diagram]

[0022] Figure 1A is a circuit diagram of a half-bridge circuit.

[0023] Figure 1B is a circuit diagram of a three-phase bridge circuit.

[0024] Figure 2 is a schematic diagram of a hybrid normally closed device arranged in a common source and common gate configuration.

[0025] Figure 3A is a plan view of an electronic module with a half-bridge.

[0026] Figure 3B is a cross-sectional view of a portion of the electronic module in Figure 3A.

[0027] Figure 4A is a plan view of a low-voltage enhancement-type transistor coupled to a high-voltage depleted III-N transistor to form a common-source common-gate switch.

[0028] Figure 4B is a cross-sectional view of a portion of the common source and common gate switch along Figure 4A.

[0029] Figure 5A is a plan view of an electronic module characterized by a half-bridge.

[0030] Figure 5B is a cross-sectional view of a portion of the electronic module along Figure 5A.

[0031] Figure 6 is a plan view of a low-voltage enhancement-type transistor coupled to a high-voltage depleted III-N transistor to form a common-source common-gate switch.

[0032] Figures 7A to 7E are circuit diagrams of different modes of operating the half-bridge.

[0033] Figure 8 is a plan view of an electronic module with a half-bridge.

[0034] Figures 9 to 12 are plan views of the electronic modules, each module having a half-bridge in an SMPD type package.

[0035] Figures 13A and 13B show the side view and top view of the packaged SMPD type package, respectively.

[0036] Figure 14 is a plan view of an electronic module with two half-bridges in parallel configuration.

[0037] Figure 15 is a plan view of an electronic module with a three-phase bridge circuit.

[0038] Figure 16 is a plan view of an electronic module with an integrated gate driver for a half-bridge.

[0039] Figure 17 is a plan view of an electronic module with an integrated gate driver for a half-bridge.

[0040] In various diagrams, similar element symbols indicate similar elements.

Claims

1. An electronic module, comprising: A package and a conductive lead frame; The conductive leadframe includes a first portion, a second portion, and a third portion. The first portion is configured to connect to a high-voltage node, the second portion is configured to connect to an output node, and the third portion is configured to connect to a ground node, wherein each of the first, second, and third portions is electrically isolated from each other. A first high-side switch includes an enhancement-mode transistor and a III-N depletion-mode transistor in a cascode configuration, wherein the III-N depletion-mode transistor includes a III-N material structure on a conductive substrate. A first low-side switch is also included. A drain electrode of the III-N depletion-mode transistor is electrically connected to the first portion of the leadframe, a source electrode of the enhancement-mode transistor is electrically connected to the second portion of the leadframe, a gate electrode of the depletion-mode transistor is electrically connected to the conductive substrate of the depletion-mode transistor, and the substrate of the depletion-mode transistor is electrically connected to the second portion of the leadframe.

2. The electronic module as claimed in claim 1, wherein the first low-side switch includes a second enhancement-mode transistor and a second III-N depletion-mode transistor, the second III-N depletion-mode transistor comprising a second III-N material structure on a second conductive substrate; wherein a drain electrode of the second III-N depletion-mode transistor is electrically connected to the second portion of the lead frame, a source electrode of the second enhancement-mode transistor is connected to the third portion of the lead frame, a gate electrode of the second III-N depletion-mode transistor is electrically connected to the second conductive substrate, and the second conductive substrate is electrically connected to the third portion of the lead frame.

3. The electronic module as claimed in claim 2, wherein the first high-side switch and the first low-side switch form a half-bridge circuit.

4. The electronic module as claimed in claim 3, wherein the depletion transistor is configured to block at least 600V when the first high-side switch bias is off and to conduct a current greater than 30A when the first high-side switch bias is on.

5. The electronic module as claimed in claim 3, the electronic module further comprising a capacitor, wherein a first terminal of the capacitor is electrically connected to the first portion of the lead frame, and a second terminal of the capacitor is electrically connected to the third portion of the lead frame.

6. The electronic module as claimed in claim 1, the electronic module further comprising a second high-side switch and a second low-side switch, wherein the first high-side switch and the second high-side switch are electrically connected in parallel, and the first low-side switch and the second low-side switch are electrically connected in parallel.

7. The electronic module as claimed in claim 5, wherein the capacitor is a hybrid capacitor comprising a resistive component and a capacitive component connected in series.

8. The electronic module as described in claim 1, wherein: The gate electrode, source electrode, and drain electrode of the first III-N depleted transistor are located on the side of the III-N material structure opposite to the conductive substrate; and the III-N material structure includes a through hole formed therein, and a metal layer forming the gate electrode is electrically connected to the conductive substrate through the through hole.

9. The electronic module as claimed in claim 2, the electronic module further comprising a gate driver packaged within the package, wherein a first terminal of the gate driver is connected to a gate electrode of the enhancement transistor, and a second terminal of the gate driver is connected to a gate electrode of the second enhancement transistor.

10. The electronic module as claimed in claim 9, wherein the first enhanced transistor or the second enhanced transistor is internally integrated within the gate driver.

11. A half-bridge circuit, comprising: a first high-side switch and a first low-side switch, each packaged in a single electronic package, the package including a high-voltage terminal, an output terminal, and a ground terminal; the first high-side switch including a first enhancement-mode transistor and a first depletion-mode III-N transistor arranged in a common-source, common-gate configuration; and the first low-side switch including a second enhancement-mode transistor and a second depletion-mode III-N transistor arranged in a common-source, common-gate configuration; wherein a first drain electrode of the first III-N transistor is electrically connected to the high-voltage terminal, a first gate electrode of the first depletion-mode III-N transistor is electrically connected to the output terminal, a second drain electrode of the second III-N transistor is electrically connected to the output terminal, and a second gate electrode of the second depletion-mode III-N transistor is electrically connected to the ground terminal.

12. The circuit as claimed in claim 11, wherein the first gate electrode of the first depleted III-N transistor is electrically connected to a substrate of the first depleted III-N transistor, and the substrate of the first depleted III-N transistor is electrically connected to the output terminal.

13. The circuit as claimed in claim 12, wherein the second gate electrode of the second depleted III-N transistor is electrically connected to the substrate of the second depleted III-N transistor, and the substrate of the second depleted III-N transistor is electrically connected to the output terminal.

14. The circuit as claimed in claim 13, the circuit further comprising a capacitor having a first terminal and a second terminal, wherein the first terminal of the capacitor is connected to the high voltage terminal and the second terminal of the capacitor is connected to the ground terminal.

15. The circuit as claimed in claim 14, further comprising a gate driver packaged within the package, wherein a first terminal of the gate driver is connected to a gate electrode of the first enhancement-mode transistor, and a second terminal of the gate driver is connected to a gate electrode of the second enhancement-mode transistor.

16. The circuit as claimed in claim 15, wherein the first enhancement transistor or the second enhancement transistor is internally integrated within the gate driver.

17. The circuit as claimed in claim 14, further comprising a second high-side switch and a second low-side switch, wherein the first high-side switch and the second high-side switch are electrically connected in parallel, and the first low-side switch and the second low-side switch are electrically connected in parallel.

18. The circuit as claimed in claim 11, wherein the circuit comprises ŋ high-side switches and ŋ low-side switches connected in parallel.

19. An electronic module comprising: a first high-side switch; a second high-side switch; and a third high-side switch; a first low-side switch; a second low-side switch; and a third low-side switch; and a single common electronic package that packages the first high-side switch, the second high-side switch, and the third high-side switch, and each of the first low-side switch, the second low-side switch, and the third low-side switch, wherein the electronic package includes a first metal layer and a second metal layer, the first metal layer being electrically connected to a high-voltage terminal, and the second metal layer being electrically connected to a ground terminal; Each of the first low-side switch, the second low-side switch, and the third low-side switch includes an enhancement-mode transistor and a depleted III-N transistor arranged in a common-source, common-gate configuration. Each individual depleted III-N transistor includes a separate III-N material structure formed on a separate conductive substrate. Each conductive substrate of the first low-side switch, the second low-side switch, and the third low-side switch is electrically connected to the second metal layer of the electronic package, and the gate electrode of each of the first, second, and third depleted III-N transistors is electrically connected to its respective conductive substrate. The first high-side switch, the second high-side switch, and the third high-side switch together with the first low-side switch, the second low-side switch, and the third low-side switch form a three-phase bridge circuit.

20. The electronic module as claimed in claim 19, the package further comprising a third metal layer, a fourth metal layer and a fifth metal layer, wherein a substrate of the first high-side switch is connected to the third metal layer, a substrate of the second high-side switch is connected to the fourth metal layer, and a substrate of the third high-side switch is connected to the fifth metal layer, and wherein the first metal layer, the second metal layer, the third metal layer, the fourth metal layer and the fifth metal layer are all electrically isolated from each other.

21. The electronic module as claimed in claim 20, the electronic module further comprising a first output terminal, a second output terminal and a third output terminal, wherein the first output terminal is electrically connected to the third metal layer, the second output terminal is electrically connected to the fourth metal layer, and the third output terminal is electrically connected to the fifth metal layer.

22. The electronic module as claimed in claim 21, wherein in the first low-side switch, the gate electrode of the III-N depletion transistor is located on the side of the III-N material structure opposite to the conductive substrate, and the III-N material structure includes a via formed therein, and a metal layer forming the gate electrode is electrically connected to the conductive substrate through the via.

23. The electronic module as claimed in claim 19, the electronic module further comprising a capacitor, wherein a first terminal of the capacitor is electrically connected to the first metal layer, and a second terminal of the capacitor is electrically connected to the second metal layer.

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