Semiconductor devices

Abstract

According to an embodiment, the semiconductor device of the present invention includes a memory circuit, a first FIFO, a second FIFO, and an input / output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input / output circuit outputs data from the second FIFO. The second FIFO is configured closer to the input / output circuit than the first FIFO.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Previous Technology]

[0002] In recent years, semiconductor devices have been processing increasingly larger volumes of data, thus requiring high-speed data transmission. The data transmitted from the core circuit to the input / output circuits is asynchronous with the external readout clock. Therefore, in semiconductor devices, FIFO (first-in first-out) circuits (hereinafter referred to as "FIFO") are used to synchronize data transmission with the external readout clock. The FIFO is positioned as equidistant as possible from each input / output circuit to distribute and transmit data synchronized with the readout clock to each input / output circuit. [Summary of the Invention]

[0003] An embodiment of the present invention provides a semiconductor device that can reduce the synchronization offset between the readout clock and the output data.

[0004] An embodiment of the semiconductor device includes a memory circuit, a first FIFO, a second FIFO, and an input / output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input / output circuit outputs data from the second FIFO. The second FIFO is configured closer to the input / output circuit than the first FIFO.

Implementation Method

[0006] [Related Applications] This application enjoys priority to U.S. Provisional Patent Application No. 62 / 167703 (filed May 28, 2015). This application includes all contents of the basic application by reference to that basic application.

[0007] Hereinafter, a semiconductor device according to an embodiment will be described with reference to the drawings. In the following description, constituent elements having the same function and structure are marked with the same symbols. Furthermore, each embodiment shown below is an example of a device or method used to concretize the technical concept of that embodiment, and the material, shape, structure, and arrangement of the constituent parts are not specific to those described below. 1. First Embodiment

[0008] A semiconductor device according to the first embodiment will be described. 1.1 Structure of the semiconductor device

[0009] Figure 1 is a layout diagram showing the circuit configuration of the semiconductor device according to the first embodiment. The semiconductor device 100 includes a core circuit 10, a first FIFO (first-in first-out) 20, a second FIFO (first-in first-out) 30-0, 30-1, 30-2, ..., 30-7, input / output pads 40-0, 40-1, 40-2, ..., 40-7, and other pads 40-8, 40-9, ..., 40-n. The semiconductor device 100 includes one semiconductor chip. Here, n is a natural number of 9 or more.

[0010] The core circuit 10 includes, for example, a memory circuit 11 and a buffer circuit 12, such as NAND (Not And) flash memory. The memory circuit 11 has a plurality of memory cells for storing data. The buffer circuit 12 temporarily stores data read from or written to the memory circuit 11. The buffer circuit 12 outputs the stored data to the FIFO 20. At this time, the buffer circuit 12 transmits data to the FIFO 20 with a bus width of 1 bit (e.g., 64 bits).

[0011] FIFO20 stores the data output from the self-buffered circuit 12. Furthermore, FIFO20 synchronously outputs the stored data to FIFO30-0 to 30-7, in conjunction with the readout enable signals REn and BREn supplied from the outside to the pads 40-8 and 40-9 respectively. At this time, FIFO20 transmits data to FIFO30-0 to 30-7 using a bus width of the aforementioned first bit number (e.g., 64 bits). That is, the data transmission from FIFO20 to FIFO30-0 to 30-7 is performed using the same bus width as the data transmission from the core circuit 10 to FIFO20.

[0012] FIFO30-0 to 30-7 store the data output from FIFO20. Then, FIFO30-0 to 30-7 synchronously output the stored data to the input / output pads 40-0 to 40-7, respectively, in conjunction with the readout enable signals REn and BREn.

[0013] Input / output pads 40-0 to 40-7 output data to the outside or input data from the outside. As described above, pads 40-8 and 40-9 are pads that supply readout enable signals REn and BREn from the outside. The readout enable signal BREn is the phase inversion signal of the readout enable signal REn. Pads 40-8 to 40-n are pads for inputting and outputting other power supplies or signals, such as power supply voltage VCC, reference voltage (e.g., ground voltage VSS), or commands. 1.2 Configuration of another semiconductor device

[0014] Another semiconductor device in the first embodiment is an example of one that is applied to a multi-chip package in order to ensure a larger memory capacity.

[0015] Figure 2 is a cross-sectional view showing the multi-chip package of the first embodiment. The multi-chip package 200 is packaged by disposing an interface chip (semiconductor chip) 220 and a stacked core chip 230 on a package substrate 210. The stacked core chip 230 has a plurality of stacked core chips (semiconductor chips) 230a, 230b, ..., 230h. An interface chip 220 is disposed between the package substrate 210 and the stacked core chip 230. The plurality of core chips 230a to 230h are stacked using a TSV (Through Silicon Via) method.

[0016] The structure of the multi-chip package 200 will be described in detail below. An interface chip 220 is disposed on the upper surface of the package substrate 210. A multilayer core chip 230 is disposed above the interface chip 220 and the upper surface of the package substrate 210.

[0017] The stacked core chip 230 includes a plurality of core chips 230a to 230h. The plurality of core chips 230a to 230h are stacked sequentially from the bottom side (the side of the package substrate 210). At least on each core chip 230a to 230h except for the topmost core chip 230h, a TSV (through electrode) 231 extending from its upper surface to its lower surface is provided. The TSV 231 is a via electrically connecting the upper surface of each core chip to its lower surface. A bump 232 is provided between each TSV 231. The TSV 231 and the bump 232 electrically connect each core chip 230a to 230h to the interface chip 220.

[0018] A wiring 233 is provided on the lower surface of the core chip 220a at the bottom layer. A bump 221 is provided between the wiring 233 and the interface chip 220. On the other hand, a bump 211 is provided between the wiring 233 and the package substrate 210. For example, the core chip 230a is electrically connected to the interface chip 220 via TSV 231 and bump 221. Also, the core chip 230b is electrically connected to the interface chip 220 via a first TSV 231, bump 232, a second TSV 231, and bump 221.

[0019] Bumps 212 are provided on the lower surface of the package substrate 210. In the case of a BGA (Ball grid array) package for semiconductor devices, the bumps 212 are solder balls. The package substrate 210 is electrically connected to the outside via the bumps 212.

[0020] The multilayer core chip 230 includes core circuitry such as NAND flash memory and memory controllers that control the memory circuitry. The memory circuitry stores data and outputs the stored data. That is, the multilayer core chip 230 stores data from external sources and outputs the stored data to the interface chip 220.

[0021] Interface chip 220 includes interface circuitry. Interface circuitry includes logic circuitry and analog circuitry, etc. Interface chip 220 transmits data and other power or signals, such as power supply voltage VCC, reference voltage (e.g., ground voltage VSS), or instructions, between package substrate 210 and multilayer core chip 230.

[0022] The packaging substrate 210 outputs data from the interface chip 220 to the outside. Furthermore, data and other power or signals, such as power supply voltage VCC, ground voltage VSS, or commands, are supplied to the packaging substrate 210 from the outside. The packaging substrate 210 supplies data to the multilayer core chip 230 via the interface chip 220. The packaging substrate 210 supplies power supply voltage VCC or ground voltage VSS to the multilayer core chip 230 either via the interface chip 220 or directly.

[0023] Figure 3 is a layout diagram showing the configuration of the interface chip 220 of the multi-chip package 200 shown in Figure 2. The interface chip 220 includes bumps 221, a first FIFO 20, a second FIFO 30-0, 30-1, 30-2, ..., 30-7, input / output pads 40-0, 40-1, 40-2, ..., 40-7, and other pads 40-8, 40-9, ..., 40-(n-1), 40-n.

[0024] Bump 221 is connected to the memory circuit of the multilayer core chip 230. Furthermore, bump 221 is connected to FIFO 20. The layout of other FIFOs 30-0 to 30-7, input / output pads 40-0 to 40-7, and pads 40-8 to 40-n on the interface chip 220 is different, but their connections and functions are the same as those of the semiconductor device shown in the above figure.

[0025] The FIFO 20 within the interface chip 220 receives data from the memory circuits of the core chips 230a to 230h within the stacked core chip 230, and transmits the received data to FIFOs 30-0 to 30-7. One interface chip 220 is provided for each of the multiple core chips 230a to 230h. The interface chip 220 is a chip shared by the multiple core chips 230a to 230h. 1.3 Structure of Core Circuit to Input / Output Pads

[0026] Figure 4 is a schematic diagram showing the configuration of the core circuit 10 to the input / output pads 40-0 to 40-9 in the multichip package 200 of the first embodiment. The core circuit 10 in the multilayer core chip 230 outputs the stored data to the FIFO 20 in the interface chip 220. At this time, the core circuit 10 transmits data to the FIFO 20 with a bus width of 1 bit number (e.g., 64 bits). That is, the multilayer core chip 230 transmits data to the interface chip 220 via the TSV 231 with a bus width of 1 bit number (e.g., 64 bits). The FIFO 20 holds the data output from the core circuit 10. From the outside, readout enable signals REn and BREn are supplied to the FIFO 20 via pads 40-8 and 40-9 as readout clock signals. Either the readout enable signal REn or BREn can be used, but here the readout enable signal REn is used.

[0027] FIFO20 outputs the held data to FIFO30-0 to 30-7 synchronously with the readout enable signal REn. At this time, FIFO20 transmits data to FIFO30-0 to 30-7 using a bus width of the first bit number mentioned above (e.g., 64 bits). That is, the data transmission from FIFO20 within the interface chip 220 to FIFO30-0 to 30-7 is performed with the same bus width as the data transmission from the stacked core chip 230 to the interface chip 220. FIFO30-0 to 30-7 hold the data output from FIFO20.

[0028] Readout enable signals REn and BREn are supplied to FIFOs 30-0 to 30-7 as readout clock signals. FIFOs 30-0 to 30-7 synchronously output the held data to input / output pads 40-0 to 40-7, respectively, in sync with the readout enable signal REn. Each of FIFOs 30-0 to 30-7 is positioned closer to the input / output pads 40-0 to 40-7 than the midpoint of the wiring between FIFO 20 and each of the input / output pads 40-0 to 40-7. Furthermore, a multiplexer and input / output circuitry are disposed between FIFOs 30-0 to 30-7 and the input / output pads 40-0 to 40-7, but these are omitted here.

[0029] Next, the configuration of the core circuit 10 to the input / output pads 40-0 shown in Figures 1 and 4 will be described in detail. The configuration of the core circuit 10 to the other input / output pads 40-1, 40-2, ..., 40-7 is the same as that of the core circuit 10 to the input / output pads 40-0. Data is transmitted from the core circuit 10 to FIFO 20, and from FIFO 20 to FIFO 30-0 to 30-7, using a 64-bit bus width. Here, FIFO 30-0 to 30-7 contain 8 FIFOs, so the bus width between FIFO 20 and FIFO 30-0 is 1 / 8, and data is transmitted using an 8-bit bus width. Similarly, between FIFO 20 and each of FIFO 30-1 to FIFO 30-7, the bus width is also 1 / 8, and data is transmitted using an 8-bit bus width.

[0030] Figure 5 is a diagram showing the detailed circuit configuration of the core circuit 10 to the input / output pads 40-0. Here, the bus width between FIFO20 and FIFO30-0 is 8 bits, so the amount of the 8-bit bus width corresponding to FIFO30-0 is used to represent the core circuit 10 to FIFO20.

[0031] As shown in the figure, the core circuit 10 and FIFO 20 are connected via data buses DB10-0, DB10-1, DB10-2, ..., DB10-7. FIFO 20 and FIFO 30-0 are connected via data buses DB20-0, DB20-1, DB20-2, ..., DB20-7.

[0032] Multiplexers 31e and 31o are configured between FIFO 30-0 and input / output pads 40-0. Multiplexer 32 is configured between multiplexers 31e and 31o and input / output pads 40-0. That is, multiplexers 31e and 31o are configured in parallel after FIFO 30-0, and multiplexer 32 is configured after multiplexers 31e and 31o.

[0033] FIFO 30-0 and multiplexer 31e are connected via data buses DB30-0, DB30-1, DB30-2, and DB30-3. FIFO 30-0 and multiplexer 31o are connected via data buses DB30-4, DB30-5, DB30-6, and DB30-7. Multiplexers 31e and 31o are connected to multiplexer 32 via data buses DB31-e and DB31-o, respectively. Furthermore, multiplexer 32 is connected to input / output pads 40-0 via data bus DB32.

[0034] Multiplexer 31e uses four input data buses DB30-0, DB30-1, DB30-2, and DB30-3 to select one data for output. Multiplexer 31o uses four input data buses DB30-4, DB30-5, DB30-6, and DB30-7 to select one data for output. Multiplexer 32 uses two input data buses DB31-e and DB31-o to select one data for output.

[0035] Furthermore, a readout enable signal REn is supplied from the outside to the pad 40-8. The readout enable signal REn supplied to the pad 40-8 is then supplied to the multiplexer 32.

[0036] A frequency divider circuit 33 and a pulse width adjustment circuit 34 are sequentially connected to the wiring connected to the pad 40-8 and transmitting the readout enable signal REn. The frequency divider circuit 33 divides the readout enable signal REn by 4, for example, and supplies the divided clock signal CLKB to the multiplexers 31e and 31o. The pulse width adjustment circuit 34 adjusts the pulse width of the clock signal CLKB after being divided by the frequency divider circuit 33, and supplies the adjusted clock signal CLKB to FIFO20 and FIFO30-0. Specifically, the pulse width adjustment circuit 34 adjusts the pulse width in such a way that by lengthening the "H (High)" portion of the pulse of the clock signal CLKB, FIFO20 and FIFO30-0 can operate normally even when the pulse waveform is slightly distorted. 1.4 Circuit Operation from Core Circuit to Input / Output Pads

[0037] Figure 6 is a timing diagram of clock signals and data input / output in the circuit shown in Figure 5. Figure 7 is a diagram showing the data transmission status in accordance with the timing diagram shown in Figure 6.

[0038] The core circuit 10 maintains the data on the even side and the odd side. The data on the even side is output from data buses DB10-0 to DB10-3. The data on the odd side is output from data buses DB10-4 to DB10-7. Here, the output of the data on the even side will be explained. The output of the data on the odd side is the same as that on the even side, so it is omitted from the description.

[0039] The core circuit 10 outputs data to the FIFO20 via data buses DB10-0 to DB10-3. The FIFO20 is supplied with a clock signal PICLK and clock signals CLKA-0 to CLKA-3 after being divided by 4.

[0040] FIFO20, synchronized with the clock signal PICLK, sequentially holds the data output from the core circuit 10. Specifically, FIFO20, synchronized with the first clock of the clock signal PICLK, holds data a, b, c, d (DATA-0). Next, FIFO20, synchronized with the second clock of the clock signal PICLK, holds data 0, 1, 2, 3 (DATA-1). Then, FIFO20, synchronized with the third clock of the clock signal PICLK, holds data 4, 5, 6, 7 (DATA-2). Similarly, FIFO20, synchronized with the eighth clock of the clock signal PICLK, holds data W, X, Y, Z (DATA-7). In this way, FIFO20 holds, for example, 4 bits of data on the even side. If data from the odd side input via data buses DB10-4 to DB10-7 is added, FIFO20 holds, for example, 8 bits of data. Furthermore, this only refers to 8 bits of the 64-bit bus width of FIFO20. Therefore, although the data retention capacity is 8 bits, the overall data retention capacity of FIFO20 is 64 bits.

[0041] Furthermore, the readout enable signal (clock signal) REn input from the outside is supplied to the frequency divider circuit 33 and the multiplexer 32. The frequency divider circuit 33 divides the readout enable signal REn to generate four clock signals CLKB-0, CLKB-1, CLKB-2, and CLKB-3. These clock signals CLKB-0 to CLKB-3 are supplied to the pulse width adjustment circuit 34, the FIFO 30-0, and the multiplexers 31e and 31o. Hereafter, the clock signal containing the clock signals CLKB-0 to CLKB-3 will be denoted as CLKB.

[0042] The pulse width adjustment circuit 34 adjusts the pulse width of the clock signals CLKB-0 to CLKB-3, generating clock signals CLKA-0, CLKA-1, CLKA-2, and CLKA-3 respectively. These clock signals CLKA-0 to CLKA-3 are supplied to FIFO20 and FIFO30-0. Furthermore, in Figure 6, for ease of explanation, the clock signals CLKA-0 to CLKA-3 are represented with the same waveform as the clock signals CLKB-0 to CLKB-3, but in reality, different waveforms are used. Hereinafter, the clock signal containing the clock signals CLKA-0 to CLKA-3 will be referred to as CLKA.

[0043] Next, FIFO20 outputs the held data to FIFO30-0 in sequence, synchronously with the clock signal CLKA. Specifically, FIFO20 outputs data "0" (DATA0) in sync with the rising of the clock (0) of the first cycle of the clock signal CLKA-0. Then, FIFO20 outputs data "1" (DATA1) in sync with the rising of the clock (1) of the first cycle of the clock signal CLKA-1. Subsequently, FIFO20 outputs data "2" (DATA2) in sync with the rising of the clock (2) of the first cycle of the clock signal CLKA-2. Furthermore, FIFO20 outputs data "3" (DATA3) in sync with the rising of the clock (3) of the first cycle of the clock signal CLKA-3. Furthermore, this is an example where FIFO20 has already output data a, b, c, d before outputting the aforementioned data 0, 1, 2, 3.

[0044] Next, the data output from FIFO20 is stored in FIFO30-0. FIFO30-0 stores data 0, 1, 2, and 3 synchronously with the clock signal CLKA. Specifically, FIFO30-0 stores data "0" (DATA0) synchronously with the rise of the clock (0) in the first cycle of the clock signal CLKA-0. Then, FIFO30-0 stores data "1" (DATA1) synchronously with the rise of the clock (1) in the first cycle of the clock signal CLKA-1. Next, FIFO30-0 stores data "2" (DATA2) synchronously with the rise of the clock (2) in the first cycle of the clock signal CLKA-2. Furthermore, FIFO30-0 stores data "3" (DATA3) synchronously with the rise of the clock (3) in the first cycle of the clock signal CLKA-3.

[0045] On the other hand, the data on the odd side is input to FIFO30-0 through the same input / output operation as the data on the even side. Furthermore, FIFO30-0, for example, holds the 4-bit data from the even side and the 4-bit data from the odd side, and merges them to hold 8 bits (1 byte) of data. If all FIFOs 30-0 to 30-7 are merged, then 8 bytes of data are held.

[0046] Next, FIFO 30-0 and multiplexers 31e and 31o, synchronized with the clock signal CLKB, output the data held in FIFO 30-0, and select one data from these data and output it. In this way, multiplexer 31e, synchronized with the clock signal CLKB, outputs the data on the even side (DATA-e). On the other hand, multiplexer 31o, synchronized with the clock signal CLKB, outputs the data on the odd side (DATA-o).

[0047] Specifically, the multiplexer 31e outputs data "a" (DATA-e) in sync with the rising edge of the clock (a) of the first cycle of the clock signal CLKB-0. Next, the multiplexer 31e outputs data "b" (DATA-e) in sync with the rising edge of the clock (b) of the first cycle of the clock signal CLKB-1. Then, the multiplexer 31e outputs data "c" (DATA-e) in sync with the rising edge of the clock (c) of the first cycle of the clock signal CLKB-2. Furthermore, the multiplexer 31e outputs data "d" (DATA-e) in sync with the rising edge of the clock (d) of the first cycle of the clock signal CLKB-3.

[0048] On the other hand, the multiplexer 31o outputs data "a" (DATA-o) synchronously with the rising of the clock (a) of the first cycle of the clock signal CLKB-0. Next, the multiplexer 31o outputs data "b" (DATA-o) synchronously with the rising of the clock (b) of the first cycle of the clock signal CLKB-1. Then, the multiplexer 31o outputs data "c" (DATA-o) synchronously with the rising of the clock (c) of the first cycle of the clock signal CLKB-2. Furthermore, the multiplexer 31o outputs data "d" (DATA-o) synchronously with the rising of the clock (d) of the first cycle of the clock signal CLKB-3.

[0049] Next, the data from the even side output from multiplexer 31e is input to multiplexer 32. On the other hand, the data from the odd side output from multiplexer 31o is also input to multiplexer 32.

[0050] The multiplexer 32 outputs the data input to the multiplexer 32 to the input / output pad 40-0 synchronously with the readout enable signal REn. Specifically, the multiplexer 32 outputs the data "a" (DATA-e) on the even side synchronously with the rising of the clock (a) of the readout enable signal REn. The multiplexer 32 outputs the data "a" (DATA-o) on the odd side synchronously with the falling of the clock (a) of the readout enable signal REn.

[0051] Subsequently, the multiplexer 32 outputs the data "b" (DATA-e) on the even side in sync with the rising of the clock (b) of the readout enable signal REn. The multiplexer 32 outputs the data "b" (DATA-o) on the odd side in sync with the falling of the clock (b) of the readout enable signal REn. Similarly, the multiplexer 32 outputs the data "c", "d", ..., "3", ... on the even side and the odd side in sync with the rising and falling of the clocks (c), (d), ..., (3), ... of the readout enable signal REn. Furthermore, the same symbols "a", "b", "c", ... are used to represent the data on the even side and the odd side, but the data on the even side and the odd side can also be different values.

[0052] Furthermore, although it is stated that the bus width between the core circuit 10 and FIFO20, and between FIFO20 and FIFO30-0 to 30-7 is set to 64 bits, and the bus width between each of FIFO20 and FIFO30-0 to 30-7 is set to 8 bits, it is not limited to this, and such bus widths can be freely changed according to the package form.

[0053] Furthermore, although examples are shown where the data retention capacity of FIFO20 in Figure 7 is 8 bytes, the data retention capacity of FIFO30-0 is 1 byte, the data retention size of FIFO20 in Figures 1 and 4 is 64 bytes, and the data retention size of FIFO30-0 to FIFO30-7 combined is 8 bytes, this is not limited to these examples. The data retention capacity of the first FIFO20 and the second FIFO30 can be freely changed according to the packaging form. 1.5 Effects of the First Embodiment

[0054] In the first embodiment, a first FIFO 20 and a second FIFO 30 are configured between the memory circuit for output data and the input / output pads (or input / output circuit). The first FIFO 20 synchronizes the output data of the memory circuit with respect to the readout clock (output clock), and the second FIFO 30 resynchronizes the output data of the first FIFO 20 with respect to the readout clock. This reduces the synchronization deviation between the readout clock and the output data.

[0055] Furthermore, a second FIFO 30 is disposed near each of the input / output pads (or input / output circuits) to synchronize the output data of the input / output pads with the readout clock. This can more effectively reduce the synchronization deviation between the output data of the input / output pads and the readout clock.

[0056] Hereinafter, the effects of the first embodiment will be described in detail using the comparative example shown in FIG8. In this comparative example, the data held in FIFO20 is output to multiplexers 31e and 31o in sync with the clock signal CLKA. Furthermore, the data input to multiplexers 31e and 31o is selected by multiplexers 31e and 31o and output to multiplexer 32.

[0057] In this comparative example, the distance between multiplexers 31e, 31o and multiplexer 32 is very long compared to the first embodiment. Therefore, during the data transmission from multiplexers 31e, 31o to multiplexer 32, the synchronization offset between the readout clock and the output data increases due to wiring resistance and capacitance, the increased number of pre-driver segments, or power supply noise. In circuits performing high-speed data transmission, this synchronization offset is required to be as small as possible.

[0058] According to the first embodiment, after synchronizing the output data of the memory circuit using the first FIFO, the output data of the first FIFO is synchronized again using the second FIFO located near the input / output pads. This reduces the synchronization deviation between the readout clock and the output data.

[0059] Furthermore, since the distance between the second FIFO and the input / output pads is extremely short, the resistance and capacitance of the wiring can be reduced, the number of segments of the readout clock and the pre-driver for data output can be reduced, and power supply noise can be decreased. Furthermore, since the distance between the second FIFO and the input / output pads can be shortened, jitter in the data transmission and readout clock can be reduced, and duty cycle unevenness can be reduced. 2. Second Embodiment

[0060] A semiconductor device according to the second embodiment will be described. In the first embodiment, a second FIFO is arranged near the input / output pads after the first FIFO; however, in the second embodiment, it is an example where the first FIFO is arranged near the input / output pads. 2.1 Structure from the core circuit to the input / output circuit

[0061] Figure 9 is a diagram showing the detailed configuration of the core circuit to one input / output pad in the second embodiment. In this semiconductor device, FIFO 20 is disposed near the input / output pad (or input / output circuit) 40-0. Data output from the core circuit 10 is input to FIFO 20 near the input / output pad 40-0 and held in FIFO 20. Subsequently, FIFO 20 outputs the held data to multiplexers 31e and 31o synchronously with the clock signal CLKB. The data input to multiplexers 31e and 31o is selected by multiplexers 31e, 31o and multiplexer 32 and output to the input / output pad 40-0.

[0062] The data output from the core circuit 10 is directly stored in FIFO 20, therefore the data storage capacity of FIFO 20 is 64 bits or more. Other configurations and operations are the same as in the first embodiment. 2.2 Effects of the Second Embodiment

[0063] In the second embodiment, the output data of the memory circuit is synchronized by a FIFO 20 disposed near the input / output pads (or input / output circuit). This reduces the synchronization deviation between the readout clock and the output data.

[0064] In this case, the data output from the core circuit 10 is synchronized with the readout clock by means of FIFO 20, and thus, similar to the first FIFO 20 used in the first embodiment, data retention of 64 bits or more can be achieved, for example. Furthermore, since FIFO 20 is located near the input / output pads, there is no need to adjust the pulse width of the clock signal CLKB. Therefore, the pulse width adjustment circuit 34 used in the first embodiment is deleted. Other configurations and effects are the same as those in the first embodiment described above. 3. Variations, etc.

[0065] In the first embodiment, the memory circuit 11 is described as including NAND flash memory, but it is not limited to this. Whether it is volatile memory or non-volatile memory, it can be applied to various types of semiconductor memory devices. For example, it can also be applied to MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), PCRAM (Phase-Change Random Access Memory), etc.

[0066] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents. [Simplified Explanation of the Diagram]

[0005] Figure 1 is a layout diagram showing the circuit configuration of the semiconductor device of the first embodiment. Figure 2 is a cross-sectional view showing the multi-chip package of the first embodiment. Figure 3 is a layout diagram showing the configuration of the interface chip of the multi-chip package shown in Figure 2. Figure 4 is a schematic diagram showing the configuration of the core circuit to the input / output pads in the semiconductor device of the first embodiment. Figure 5 is a detailed diagram showing the configuration of the core circuit to the input / output pads in the first embodiment. Figure 6 is a timing diagram of the clock signal and data input / output in the circuit shown in Figure 5. Figure 7 is a diagram showing the data transmission status according to the timing diagram shown in Figure 6. Figure 8 is a diagram showing the configuration of the core circuit to the input / output pads in a comparative example. Figure 9 is a detailed diagram showing the configuration of the core circuit to the input / output pads in the second embodiment.

Claims

1. A semiconductor device comprising: The system comprises: a memory circuit configured to output data; a first FIFO configured to receive data from the memory circuit and output data synchronously with a first clock signal; a second FIFO configured to receive data output from the first FIFO and output data synchronously with the first clock signal; a third FIFO configured to receive data output from the first FIFO and output data synchronously with the first clock signal; a signal circuit configured to receive the first clock signal; a first input / output circuit configured to output first data from the second FIFO; and a second input / output circuit configured to output second data from the third FIFO; wherein the signal circuit includes: a pad sandwiched between the first input / output circuit and the second input / output circuit in a first direction, wherein data output from the first input / output circuit and the second input / output circuit is synchronized with the second clock signal; The semiconductor device further includes a frequency divider circuit that divides the second clock signal and generates the first clock signal.

2. The semiconductor device of claim 1, wherein the second FIFO is disposed between the first FIFO and the first input / output circuit, and the third FIFO is disposed between the first FIFO and the second input / output circuit.

3. The semiconductor device of claim 1, wherein the second FIFO is located closer to one side of the first input / output circuit than the middle point of the interconnect connecting the first FIFO and the first input / output circuit; and the third FIFO is located closer to one side of the second input / output circuit than the middle point of the interconnect connecting the first FIFO and the second input / output circuit.

4. The semiconductor device of claim 1, wherein the data retention capacity of the second FIFO is lower than the data retention capacity of the first FIFO; and the data retention capacity of the third FIFO is lower than the data retention capacity of the first FIFO.

5. The semiconductor device as claimed in claim 1, further comprising: A multiplexer is disposed between the second FIFO and the first input / output circuit, and the multiplexer outputs data when the second clock signal rises and falls.

6. The semiconductor device of claim 1, further comprising: The first semiconductor chip includes the memory circuit described above; and the second semiconductor chip includes the first FIFO, the second FIFO, the third FIFO, the signal circuit, the first input / output circuit, and the second input / output circuit described above.

7. The semiconductor device of claim 6, wherein the first semiconductor chip includes: a first via extending from its upper surface to its lower surface, the first via being interconnected with the second semiconductor chip via a first bump; and data output from the first semiconductor chip is input to the first FIFO of the second semiconductor chip via the first via and the first bump.

8. The semiconductor device as claimed in claim 7, further comprising: The third semiconductor chip, its output data; The first FIFO receives data from the third semiconductor chip and outputs data synchronously with the first clock signal.

9. The semiconductor device of claim 8, wherein the third semiconductor chip is disposed on the first semiconductor chip and includes a second via that extends from its upper surface to its lower surface; the second via and the first via are interconnected by a second bump; and data output from the third semiconductor chip is input to the first FIFO of the second semiconductor chip via the second via, the second bump, the first via, and the first bump.

10. The semiconductor device of claim 6, wherein the bus width between the first semiconductor wafer and the first FIFO is the same as the bus width between the first FIFO and the second FIFO.

11. The semiconductor device of claim 8, wherein the bus width between the third semiconductor wafer and the first FIFO is the same as the bus width between the first FIFO and the second FIFO.

12. The semiconductor device of claim 6, wherein each of the second FIFO and the third FIFO receives at least a portion of the data output from the first FIFO in a divided form, and outputs the data received from the first input / output circuit and the second input / output circuit synchronously with the first clock signal.

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