Atomic layer etching for subtractive metal etch

Abstract

A method for atomic-layer etching of a metal-containing layer is provided. At least one region of the surface of the metal-containing layer is modified by exposing it to a modifying gas to form a modified metal-containing region, wherein an unmodified metal-containing region remains adjacent to the modified metal-containing region. The modified metal-containing region is selectively removed relative to the unmodified metal-containing region by exposing the surface of the metal-containing layer to an inert bombardment plasma generated from an inert gas.

Description

[Technical Field]

[0001] [Cross-reference to related applications] This application claims priority to the following: U.S. Patent Application No. 62 / 840523, filed on April 29, 2019, the entire contents of which are incorporated herein by reference.

[0002] This disclosure relates to a method of etching a metal layer using atomic layers. [Previous Technology]

[0003] Semiconductor manufacturing processes often involve the formation of metal-containing structures (including logic gates and memory). Subtractive etching processes are used to manufacture aluminum-containing structures, and as the industry shifted to the use of copper, damascene processes were created to address the difficulties of copper etching in subtractive etching processes. However, as devices shrink, it becomes more difficult to form small copper features using damascene processes.

[0004] Other metals such as molybdenum (Mo) or ruthenium (Ru) may be used for such small features. Etching such metals may have the following problems: wider features may be etched faster than narrower features, and the sidewalls of the metal features may be too rough.

[0005] The background description provided herein is intended to generally present the context of this disclosure. Within the scope described in this prior art section, the work of the inventors specified in this invention, and the descriptions in this description that may not be considered prior art at the time of application, are neither express nor implied as an admission that they are prior art against this disclosure. [Summary of the Invention]

[0006] To achieve the foregoing objectives and according to the purposes of this disclosure, this disclosure provides a method for atomic layer etching of a metal-containing layer. At least one region of the surface of the metal-containing layer is modified by exposing it to a modifying gas to form a modified metal-containing region, wherein an unmodified metal-containing region remains adjacent to the modified metal-containing region. The modified metal-containing region is selectively removed relative to the unmodified metal-containing region by exposing the surface of the metal-containing layer to an inert bombardment plasma generated from an inert gas.

[0007] These and other features of this disclosure will be described in more detail below with reference to the accompanying illustrations.

Implementation Method

[0030] In the following description, several specific details are set forth in order to provide a complete understanding of the present embodiments. This disclosure may be practiced without some or all of these specific details. In other instances, conventional processing steps and / or structures have not been described in detail to avoid unnecessarily obscuring the disclosed embodiments. Although the disclosed embodiments are described in conjunction with specific embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

[0031] In the decade beginning in 2000, copper damascene processes became the dominant integrated circuit manufacturing technology for forming metal interconnects. The method used to manufacture copper interconnects is the damascene process. The damascene process involves the following general operations: (1) depositing a dielectric layer on a substrate; (2) etching the dielectric layer to form trenches or dielectric windows; (3) optionally, depositing a barrier layer into the trenches or dielectric windows; and (4) filling the trenches or dielectric windows with a metal such as copper. An example barrier layer includes tantalum / tantalum nitride (Ta / TaN). In an illustrative damascene process, after the copper dielectric windows are formed, a subsequent dielectric layer such as silicon carbonitride (SiCN) is deposited on the dielectric layer.

[0032] Copper inlay interconnect fabrication may not be suitable for technology nodes below 22 nanometers (e.g., 15 or 16 nanometer nodes). As devices shrink, feature sizes become smaller, aspect ratios increase, and the trenches and vias in which metal must be deposited become narrower. Deposition of barrier layers or liner layers may be used to reduce electromigration, but the thickness of the barrier layers or liner layers reduces the remaining space in the trenches or vias available for copper deposition.

[0033] Several of these issues relate to reliability, such as damage from electromigration and high dielectric window resistance. Reliability issues are associated with increased current density, partly due to a corresponding reduction in linewidth. High dielectric window resistance is associated with the minimum copper diffusion barrier thickness required for reliable device performance (line leakage, interlayer dielectric (ILD) leakage, electromigration, and stress migration). These considerations have led the industry to alternative metallization methods. For example, some techniques involve forming tungsten (W) in the dielectric window and trenches via chemical vapor deposition (CVD); however, due to the conformal nature of CVD tungsten deposition, these techniques limit the grain size to approximately half the critical size. Physical vapor deposition (PVD) may not be used because PVD is not sufficiently conformal and creates voids in the dielectric window filling. However, CVD-deposited tungsten conformally follows the contour of the dielectric window and thus limits the tungsten grain size. Therefore, the size of the metal grains formed in the resulting metallic features is limited by the relatively small size of the trenches. Because smaller metal grains generally have higher resistivity, the metal interconnects formed by the damascene process in these smaller critical size trenches have higher resistivity and therefore do not perform as well as expected.

[0034] Transistor technology is approaching a critical point where the use of copper interconnects limits further miniaturization, a challenge known as the "RC challenge," where R represents resistivity and C represents conductivity. For example, in copper interconnect circuits, the resistivity of a 10 nm wide circuit is approximately an order of magnitude higher than that of bulk copper. This increase in resistivity is due to electron-photon scattering at the surface and grain boundaries. In the case of slender wires and / or small grain sizes, the resistivity of the wire, in addition to the bulk resistivity, depends on the mean free path of electron scattering. As size reduction increases, the resistivity is empirically proportional to:

[0035] Linear resistivity = ρλ / d where ρ is the volume resistivity, λ is the mean free path, and d is the relevant length scale determined by the wire width or grain size.

[0036] Using pλ as a guide, few materials have been identified as potential candidates to replace the metals currently used in logic gates and memory technology nodes. Even though their bulk resistivity is several times higher, they show competitive or superior conductivity in the sub-10 nanometer range. For example, Ru has the potential to replace copper as interconnect lines and / or interposer windows. For word lines and bit lines in memory applications, molybdenum shows potential advantages over tungsten. Other possible materials include: osmium, rhodium, iridium, cobalt; or binary / ternary compounds such as CoSi and AlSiC.

[0037] One method of forming non-copper metal circuits is by performing subtractive etching. Subtractive etching can be used with materials such as aluminum and tungsten by depositing a metal blanket and etching portions of the metal layer to form dielectric-filled areas, thereby leaving metal circuits or dielectric windows defined by an overlaid patterned mask. Subtractive etching has been used in etching processes, such as active ion etching, and in some cases for directly delivering etching chemicals to a metal blanket with a patterned mask on it to etch metal. The dielectric window layer is then completed by filling the voids around the metal dielectric window with an insulating material. Depending on the metal used, subtractive etching may not necessarily involve forming a barrier layer on the metal before depositing the dielectric.

[0038] While subtractive etching may be performed on other metals, such as refractory metals and high surface bonding energy materials (e.g., molybdenum and ruthenium), etching such materials is carried out using active ion etching (RIE). The difference in etching behavior between grain boundaries and the metal grains themselves leads to uneven etching and rough surfaces. As feature sizes continue to shrink, the critical size of metal circuits reaches below 10 nm. However, metals have a crystalline grain structure. Active ion etching typically has a faster reaction rate at grain boundaries compared to on the crystalline grains themselves. That is, grain boundaries tend to have weaker bonds, thus etching is faster than on the grains themselves. This preferential etching at metal grain boundaries produces circuit edge roughness, causing deviations and increasing the resistivity of metal contact lines. Therefore, metal regions with specific grain boundaries tend to be etched to the shape of the grain boundaries, and when etching is not finely controlled, it results in a rough surface after etching. Although some active ion etching (RIE) methods can improve the linewidth roughness (LWR) of sidewalls, achieving a linewidth roughness of less than 2 nm remains difficult. In addition, the etch front in RIE, with its random behavior, can form a selvage layer that tends to roughen the surface at a scale of approximately 5 nm. While random effects, ion scattering, and micromasking can be used to address these issues, these mechanisms kinetically hinder surface planarization (which is thermodynamically favorable due to lower surface tension).

[0039] An example of the prior art is provided in Figures 1, 2A, and 2B. In Figure 1, a substrate includes a bottom layer 101, a barrier layer 103, a metal layer 105, and a patterned mask layer 107. In Figure 2A, a patterned metal layer 115 with a rough surface 150 is formed by etching the metal layer using active ion etching (RIE) with the patterned mask layer 107 as a mask. Such roughness may occur because etching at grain boundaries has a faster etching rate than etching on the grains themselves. Figure 2B is a top view of the patterned metal layer 115 alone, showing the rough surface 150 along all etched metal.

[0040] The present invention provides a method for performing subtractive etching on a refractory metal by means of atomic layer etching (ALE) technology to form a smooth surface on a patterned refractory metal.

[0041] Not limited to logic gates, subtractive metal etching has strong miniaturization potential for advanced memory applications. In addition to interconnects, subtractive metal etching has key applications in word line and bit line processes in memory (DRAM and 3D NAND). In addition to ideal line roughness, it can also achieve uniform metal recesses that do not generate loading between features.

[0042] In addition to subtractive metal etching, ALE can be applied to DRAM buried word line recess etching applications, resulting in a smooth surface morphology and good uniformity between trenches and recesses. The metallization includes trench fillers of W, Mo, and Ru, with various substrate options such as titanium nitride (TiN), tungsten carbonitride (WCN), or no substrate.

[0043] Specific disclosed embodiments allow ruthenium and / or molybdenum interlayer windows to be formed without the use of a liner.

[0044] Figure 3 shows an example of metal grain 305a and grain boundary 305b. When active ion etching is formed, the surface is rough due to the etching of the grain as shown in 3-A (see 305c). In contrast, when atomic layer etching is performed, the substrate in 3-B shows that the surface is smooth (see 305d).

[0045] ALE is a multi-step process in advanced semiconductor manufacturing (e.g., technology nodes <10nm) used for pattern-defining etching or blanket removal of ultrathin layers of material with atomic-scale depth resolution and control. ALE is a technique that uses continuous self-limiting reactions to remove thin layers of material. Examples of atomic layer etching techniques are described in U.S. Patent Nos. 8,883,028 and 8,808,561, which are incorporated herein by reference for the purpose of describing illustrative atomic layer etching and etching techniques.

[0046] The concept of an "ALE cycle" is related to the various embodiments discussed herein. Generally, an ALE cycle is a minimal combination of operations used to perform an etching process once, for example, etching a monolayer. The result of a cycle is that at least some portions of a film layer on a substrate surface are etched. Typically, an ALE cycle includes a modification operation to form a modified layer, followed by a removal operation to remove or etch only the modified layer. The cycle may include specific auxiliary operations, such as scavenging or purging of reactants or byproducts. Generally, a cycle includes a unique sequence of operations. For example, an ALE cycle may include the following operations: (1) delivery of a modification gas, (2) purging of the reactive gas from the chamber, (3) delivery of a removal gas and an optional plasma, and (4) purging of the chamber. In some embodiments, etching may be performed nonconformally, including such that the resulting surface may be smoother than the starting surface, including much smoother.

[0047] Figure 4A shows two schematic diagrams of an ALE cycle. Figures 471a to 471e show a general ALE cycle. In 471a, a substrate is provided. In 471b, the surface of the substrate is modified to form a modified region of modified metal. Below the modified region is an unmodified region containing unmodified metal. In 471c, preparation for the next step is made. In 471d, the modified layer of the modified region is being etched. In 471e, the modified layer is removed, leaving the unmodified region containing unmodified metal. Similarly, Figures 472a to 472e show an example of an ALE cycle for etching a ruthenium film. In 472a, a silicon substrate is provided, which contains a number of ruthenium atoms. In 472b, modified oxygen gas is introduced into the substrate, modifying the surface of the substrate. The schematic diagram in 472b illustrates that some oxygen is adsorbed onto the surface of the substrate. Although oxygen is depicted in Figure 4B, any oxygen-containing compound or suitable reactant may be used. In 472c, the modified gas (oxygen) is purged from the chamber. In 472d, a removal gas, argon, is introduced via a plasma (indicated by Ar+ plasma type and arrows), and ion bombardment is performed to remove the modified surface of the substrate. During this operation, a bias voltage is applied to the substrate to attract ions toward it. In 472e, the chamber is purged and byproducts are removed.

[0048] ALE process conditions, such as chamber pressure, substrate temperature, plasma power, frequency and type, and bias power, depend on: the material to be etched, the composition of the gas used to modify the material to be etched, the material below the material to be etched, and the composition of the gas used to remove the modified material.

[0049] ALE involves separating the etching process into two (or more) separate operations: modification (operation A) and removal (operation B). For example, a modification operation modifies the surface layer so that it can be easily removed during the removal operation. Each cycle removes a thin layer of material, where one cycle includes modification and removal, and the cycle can be repeated until the desired depth is reached. Synergy refers to the beneficial etching that occurs due to the interaction of operations A and B. In ALE, operations A and B are separated spatially or temporally.

[0050] Favorable atomic layer etching occurs due to the interaction of operations A and B, and the "ALE synergy" metric below is used to quantify the strength and impact of the synergy. The ALE synergy is calculated as follows: (Equation 1) where EPC ("etch per cycle") is the thickness of substrate material removed in one ALE cycle (usually averaged over many cycles), and A and B are the contributions of these operations to EPC, measured by independently performing separate modification and removal operations as reference points.

[0051] Synergistic effects are a test that captures many aspects of ALE behavior and are well-suited for comparing different ALE conditions or systems. This is the underlying mechanism why etching in job B stops after the reactants from job A are exhausted. Therefore, this results in self-limiting behavior in ALE that benefits, for example, aspect ratio independence, uniformity, smoothness, and selectivity.

[0052] ALE is associated with at least two applications: defining metal lines and / or other features by transferring features from a mask, and etching back metal after trench / mesh window deposition.

[0053] The specific ALE process described herein is particularly associated with ruthenium and molybdenum subtractive etching, but it will be understood that other potential metals may be used.

[0054] FIG4B provides a process flow diagram of a method that may be implemented according to a particular disclosed embodiment. Although FIG4B is described below with respect to etching ruthenium and molybdenum in a subtractive patterning application, it will be understood that other suitable metals may be used instead of ruthenium and molybdenum.

[0055] In operation 402, a substrate with a patterned mask on a blanket coating of ruthenium or molybdenum is provided to a chamber. This chamber may be one chamber in a multi-chamber instrument or a single-chamber instrument. The substrate may be a semiconductor substrate in various embodiments. The substrate may be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, comprising a wafer having one or more layers of material (e.g., dielectric, conductor, or semiconductor material deposited thereon).

[0056] The patterned mask may include patterned mask features. Features may be formed in one or more of the aforementioned layers. An example of a feature is a hole or interlayer window in a layer on a semiconductor substrate or substrate. The feature may also be etched to form memory character lines. Another example of a feature is a trench in a substrate or layer. In various embodiments, the feature may have a lower layer, such as a barrier layer or adhesive layer. Non-limiting examples of the lower layer include dielectric and conductive layers, such as silicon oxide, silicon nitride, silicon carbide, metal oxide, metal nitride, metal carbide, and metal layers. In several embodiments, the aspect ratio of the feature may be at least about 2:1, at least about 4:1, at least about 5:1, at least about 6:1, at least about 10:1, at least about 30:1, or higher. Protection of the feature sidewalls may be desirable at a high aspect ratio. This disclosed method may be implemented on a substrate having an opening of less than about 150 nm or less than about 10 nm on a feature portion. A feature interlayer window or trench may refer to an unfilled feature portion or a feature portion. A feature portion may have a concave profile that narrows from the bottom, closed end, or interior of the feature portion toward the feature portion opening. In several embodiments, the method described herein may be used to form a feature portion having these properties.

[0057] In operation 404, the substrate is exposed to a modifying gas to form a ruthenium-containing material layer or a molybdenum-containing material layer. The modification operation forms a thin, active surface layer that forms a modified metal region having a thickness that is easier to remove than the unmodified metal in a subsequent removal operation.

[0058] The etching gas may be selected depending on the type and chemical properties of the substrate to be etched. Suitable modifier gases may include: oxygen (O2), chlorine (Cl2), boron trichloride (BCl3), hydrogen (H2), carbon tetrafluoride (CF4), and combinations thereof. For example, O2 has been shown to be effective for etching and smoothing ruthenium; Cl2 has been shown to be effective for etching and smoothing tantalum; and a mixture of Cl2 and O2 has been shown to be effective for etching and smoothing molybdenum.

[0059] During operation 404, the chamber pressure may be between approximately 50 mTorr and approximately 100 mTorr, for example: approximately 50 mTorr, approximately 60 mTorr, approximately 70 mTorr, approximately 80 mTorr, approximately 90 mTorr, or approximately 100 mTorr. In various embodiments, a modified gas is introduced into the chamber and a plasma is ignited. In several embodiments, no plasma is generated. In the case of plasma generation, the power supply may be set to a power between approximately 100 watts (W) and approximately 1000 W, for example: approximately 100 W, or approximately 200 W, or approximately 300 W, or approximately 400 W, or approximately 500 W, or approximately 600 W, or approximately 700 W, or approximately 800 W, or approximately 900 W, or approximately 1000 W. In various embodiments, when a plasma is ignited, a bias voltage is applied. A bias voltage may be applied at any suitable power. During operation 404, a base supporting the substrate may be set at a suitable temperature to prevent spontaneous etching. This temperature depends on the material to be etched, the layers present on the substrate, the modifier gas, and other process conditions. In several embodiments, this temperature is between approximately -70 and 150°C, for example, -70, -60, -50, -40, -30, -20, -10, 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, or 150°C. The duration of operation 404 depends on the surface configuration of the substrate, the modifier chemicals and surface chemicals, and the process conditions. In several embodiments, the duration of operation 404 is between approximately 0.1 and 5 seconds (s), for example, 0.1, 0.2, 0.5, 1, 2, 3, 4, or 5 seconds.

[0060] For ruthenium ALE, operation 404 involves exposure to an oxygen-containing gas and optionally the generation of a plasma. In various embodiments, oxygen plasma (O2 plasma) is used. In various embodiments, the oxygen plasma is adsorbed to form a Ru-O modified surface, and the process is self-limiting. This process converts a metal-metal surface into a modified layer in which covalent bonds can be formed.

[0061] For molybdenum ALE, operation 404 involves exposure to a chlorine-containing gas and optionally the generation of a plasma. In various embodiments, chlorine gas is used. In various embodiments, a mixture of chlorine and oxygen gas is used. A self-limiting Cl- or Cl- / O- adsorbed layer is formed on the surface of molybdenum, which is Mo-Cl or O-Mo-Cl.

[0062] In operation 406, the chamber can be selectively purged to remove excess modified gaseous chemicals from the processing space. During a purging operation, non-surface-bonded modified gaseous and / or modified plasma species may be removed from the processing chamber. This can be accomplished by purging and / or venting the processing chamber to remove modified gaseous and / or modified plasma species without removing the adsorbed layer. Species generated in a modified gas plasma can be removed by simply stopping the plasma and allowing the remaining species to recede (optionally combined with purging and / or venting the chamber). Purging can be accomplished using any inert gas, such as nitrogen (N2), argon (Ar), neon (Ne), helium (He), and combinations thereof.

[0063] In operation 408, the modified layer formed in operation 404 is exposed to a directional inert gas. The removal operation may be carried out by continuously (continuous ALE) or pulsedly (pulsed ALE) exposing the modified layer to the directional inert gas. Pulsed ALE may allow the use of higher plasma power and bias power.

[0064] Regardless of whether the directional inert gas system is delivered continuously or in pulses, during a removal operation, the substrate is exposed to an energy source (e.g., an activating or sputtering gas or a chemically active species that induces removal), such as argon or helium, to etch the substrate by directional sputtering. In some embodiments, the removal operation may be performed by ion bombardment. During removal, a bias voltage may be selectively activated to promote directional sputtering. In some embodiments, the ALE may be isotropic.

[0065] The amount of sputtering gas may be controlled to (e.g.) etch only a target amount of material. In various embodiments, the chamber pressure may vary between the modification and removal operations. The gas pressure may depend on the chamber size, gas flow rate, reactor temperature, substrate type, and the size of the substrate to be etched.

[0066] In various embodiments, operation 408 may be carried out at a chamber pressure of about 0.5 mTorr to about 20 mTorr, such as 0.5 mTorr, 1 mTorr, 2 mTorr, 5 mTorr, 10 mTorr, 15 mTorr, or 20 mTorr.

[0067] The temperature of the base is set at a specific temperature to avoid spontaneous etching, and this temperature may (in several embodiments) depend on the material on the substrate. In various different embodiments, this temperature is between approximately -70 and 150˚C, for example, -70, -60, -50, -40, -30, -20, -10, 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, or 150°C.

[0068] The duration of operation 408, at 50 eV and with an ion flux of approximately 2 x 10¹⁶ / cm²*S, may be between approximately 0.1 seconds and approximately 10 seconds, for example, 0.1, 0.2, 0.5, 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 seconds.

[0069] In various embodiments, operation 408 includes applying a bias voltage to the base supporting the substrate while exposing the substrate to the removal gas. The bias voltage may be applied at a power between approximately 10 (volts) V and approximately 150 V, such as 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 11, 120, 130, 140, or 150 V. In various embodiments, the power supply is set to a power between approximately 100 W and approximately 1500 W, such as 100, 200, 300, 400, 500, 600, 700, 800, 900, or 1000 W.

[0070] For ruthenium ALE, Operation 408 involves exposing the modified surface to inert ions (e.g., Ar+) to remove the modified layer, thus forming volatile RuOx as a byproduct.

[0071] In continuous ALE of ruthenium, in various embodiments, a bias voltage may be set at approximately 80 V. In various embodiments, during exposure of the metal-containing surface to an inert bombardment plasma, a continuous bias is applied with a bias power between approximately 60 V and approximately 100 V to allow a plasma formed from the inert gas to provide ion bombardment to the metal-containing surface. In pulsed ALE of ruthenium, the bias is pulsed at 10% duty cycles between 0 V and a peak bias power (between approximately 600 V and approximately 1200 V). It will be understood that other duty cycles may be used and the bias power may be adjusted accordingly depending on the duty cycle used.

[0072] For the ALE of molybdenum, operation 408 involves exposing the modified surface to inert ions (e.g., Ar+) to remove the modified layer, thereby forming volatile MoCl and / or MoClOx as a byproduct.

[0073] In continuous ALE of molybdenum, a bias voltage may be set between approximately 50 V and approximately 80 V. In several embodiments of pulsed ALE of molybdenum, the bias voltage is pulsed at 10% duty cycles between 0 V and a bias power between approximately 600 V and approximately 1200 V. The critical bias voltage of the bias range depends on the nature of the material being etched. For example, some metals used for hard masks may have a higher critical bias voltage, and the process window will therefore increase as the bias power range may be higher or wider.

[0074] It will be understood that other duty cycles may be used, and the bias power may be adjusted accordingly depending on the duty cycle used.

[0075] In operation 410, the chamber is purged to remove byproducts from the chamber. In operation 412, operations 404-410 may be selectively repeated cyclically to etch metal according to a desired subtractive etching application.

[0076] Operations 404 and 408, or alternatively 404-410, may construct an ALE cycle. The concept of an "ALE cycle" is relevant to the discussion of the various embodiments herein. Generally, an ALE cycle is the minimum combination of operations used to perform an etching process, such as etching a single atomic layer. The result of a cycle is that at least some portions of a film layer on a substrate surface are etched. Typically, an ALE cycle includes a modification operation to form an active layer, followed by a removal operation to remove or etch only this modification layer. The cycle may include specific auxiliary operations, such as scavenging one of the reactants or byproducts. Generally, a cycle includes a unique sequence of operations. For example, an ALE cycle may include the following operations: (1) delivery of reactive gases, (2) purging of reactive gases from the chamber, (3) delivery of a removal gas and an optional plasma, and (4) purging of the chamber.

[0077] The specific disclosed embodiments have three specific advantages: forming a smooth etched front on a horizontal surface, forming a smooth sidewall and linewidth roughness on a vertical surface, and reducing load effects.

[0078] Regarding the formation of a smooth etched surface, in a specific example of subtractive etching of ruthenium using ALE, ALE involves forming a self-limiting surface ruthenium layer in an O2 plasma, thereby uniformly converting the ruthenium surface into a modified layer with only negligible spontaneous chemical etching. During removal, ion bombardment is used to selectively remove the modified layer. Within one cycle of adsorption and desorption steps, the process equalizes the reaction rate on the surface without distinguishing between grain boundaries and grains. In various embodiments, ALE can produce a surface even smoother than the input film to be etched. By the self-limiting layer-by-layer ALE process, the surface morphology of the initial film is maintained without increasing roughness. For protrusions on a flat surface, the convex bends contribute additional surface energy to the surface atoms, making them more active than atoms on a flat surface. For recesses or pits, atoms on the convex bends are less active because they have less surface energy compared to flat areas. During exposure to O2 plasma, the protrusion surface is more reactive, with the potential to form a higher proportion of MO bonds while leaving fewer MM bonds. During the ion bombardment step, inert ions can smooth the surface through amorphization of the top approximately 1 nm of the surface. In summary, the faster reaction rate at the tip and the diffusion tendency from the tip to the foot of a protrusion result in a smooth ALE etched surface without inducing roughness from grain boundaries.

[0079] Regarding the formation of a smooth sidewall and linewidth roughness on a vertical surface, the sidewall can also be smoothed and the linewidth roughness reduced by subtractive etching of ALE. Unlike conventional active ion etching, ruthenium and molybdenum ALE results in atomic fidelity for pattern transfer towards smooth ruthenium and molybdenum lines. In addition to horizontally smooth etched surfaces, O2 / Ar or Cl2 / Ar ALE can produce smooth sidewalls in patterned structures. In several other processes, isotropic chemical etching results in lateral erosion of the vertical surface. Different etch rates caused by grain-to-grain boundary defects or non-uniform sidewall passivation form two-dimensional roughness along the vertical sidewall. In contrast, a layer-by-layer ALE process does not cause vertical or horizontal etching into the sidewall and can be a highly controlled etching mechanism. In the absence of a masking effect, ALE cycling and directional ion bombardment remove the modified layer. This limits the exposure of the sidewall surface to chemical or physical etching. Such a reaction mechanism in ALE thus improves the roughness of the line edges. While the linewidth roughness of ruthenium or molybdenum metal etched by active ions may be greater than 3 nm, the linewidth roughness of ruthenium or molybdenum metal etched by ALE may be less than about 2 nm. In various embodiments, the surface roughness is reduced by at least 30% compared to the metal surface etched by atomic layer etching prior to subtractive etching.

[0080] Figures 5, 6A, and 6B show exemplary schematic diagrams of a substrate during subtractive etching using ALE. In Figure 5, a substrate includes a base layer 501, a barrier layer 503, a metal layer 505, and a patterned mask layer 507 defining patterned mask features formed on the metal layer 505. In Figure 6A, the metal layer is etched using ALE with the patterned mask layer 507 as a mask to form a patterned metal layer 515 having a smooth surface 550. Figure 6B is a top view of the patterned metal layer 515 alone, showing the smooth surface 550 along all the etched metal. In some embodiments, the metal layer 505 may be a metal-containing layer. The patterned mask layer 507 has patterned mask features forming lines. ALE etches the features into the metal layer 505, producing metal lines with a line width roughness of less than 2 nm.

[0081] Regarding the reduction of loading effects, ruthenium and molybdenum ALEs can also provide aspect ratio-independent etching profiles for features below 10 nm and isotropic / wide trenches. Particularly for sizes below 10 nm, one of the most challenging problems for active ion etching processes is ensuring that etching is an aspect ratio-dependent load. In active ion etching, the delivery of active etch species (neutral particles and ions) to the etching front and the removal of etching byproducts from the feature can cause non-uniform etching in features with different aspect ratios. During active ion etching, as ion flux and energy are delivered to the etching front of dense trenches, the ion flux and energy interact with the sidewalls, and even trench size variations as small as 1 nm can lead to significant differences in the reduced etching depth of dense trenches. In contrast, an ALE process is self-limiting, which can tolerate variations in trench width and depth by etching the same amount in each feature regardless of aspect ratio. Because ALE can be adjusted to make the modification process self-limiting, etching is non-aspect ratio dependent, thus expanding the process window for structures below 10 nm.

[0082] Figure 7 shows a cross-sectional view of a portion of a stack 700, wherein a metal layer 704 is on a patterned mask 708, which is on a patterned dielectric layer 712. Figure 8 shows a cross-sectional view of a portion of a stack 800 etched according to prior art. The stack 800 includes a patterned mask 808 on a patterned dielectric layer 812. The patterned mask 808 and the patterned dielectric layer 812 form a wider feature 816 and a narrower feature 820. Using prior art etching methods, the metal layer in the wider feature 816 is etched faster than the portion containing the metal layer in the narrower feature 820. As a result, the portion containing the metal layer 824 in the wider feature 816 is etched more than the portion containing the metal layer 828 in the narrower feature 820. As a result, the etchback of the lines between the metal-containing layers 824 in the wider feature portion exhibits non-uniformity compared to the metal-containing portion 828 in the narrower feature portion 820. In some embodiments, the non-uniformity of the lines is greater than 5 nm.

[0083] FIG9 shows a cross-sectional view of a portion of a stack 900 etched according to an embodiment of atomic layer etching using a metal-containing layer. The stack 900 includes a patterned mask 908 on a patterned dielectric layer 912. The patterned mask 908 and the patterned dielectric layer 912 form a wider feature 916 and a narrower feature 920. A metal-containing layer is formed on the patterned mask 908 such that the metal-containing layer fills the wider feature 916 and the narrower feature 920 of the patterned mask 908. In an embodiment providing atomic layer etching, the portions of the metal-containing layer in the wider feature 916 and the portion of the metal-containing layer in the narrower feature 920 are etched at the same rate. As a result, the portions of the metal-containing layer 924 in the wider feature 916 and the portions of the metal-containing layer 928 in the narrower feature 920 are etched approximately equally. In various embodiments, the line non-uniformity caused by any difference in the etch rate between the metal-containing layer 924 in the wider feature 916 and the metal-containing layer 928 in the narrower feature 920 is less than 5 nm.

[0084] The terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "semi-finished integrated circuit" are used interchangeably. "Semi-finished integrated circuit" can refer to silicon or other semiconductor wafers at any stage of the many phases of integrated circuit manufacturing. A substrate used in the semiconductor device industry typically has a diameter of 200 mm or 300 mm, although the industry as a whole is moving towards the adoption of substrates with a diameter of 450 mm. The flow rates and conditions provided herein are suitable for processing 300 mm substrates. Those skilled in the art will understand that these flow rates may be adjusted for other substrate sizes as required. Power levels and flow rates are typically scaled linearly with the number of stations and the substrate area. Flow rates and power may be presented on a per-zone basis. Besides reaction chambers used for depositing films on semiconductor substrates, other types of deposition reactors may utilize the embodiments disclosed herein. Other types of reactors that may benefit from the embodiments disclosed herein include those used to produce a variety of different objects, such as printed circuit boards, displays, and the like.

[0085] [Instrumentation] Figure 10 schematically shows a cross-sectional view of an inductively coupled plasma etching apparatus 1000 according to a specific embodiment herein. A Kiyo™ reactor manufactured by Lam Research Corp. of Fremont, CA is an example of a suitable reactor that may be used to implement the techniques described herein. The inductively coupled plasma etching apparatus 1000 includes a main etching chamber 1001 structurally defined by chamber walls and a window 1011. The chamber walls may be made of stainless steel or aluminum. The window 1011 may be made of quartz or other dielectric material. An optional internal plasma grid 1050 divides the main etching chamber into an upper sub-chamber 1002 and a lower sub-chamber 1003. The plasma grid 1050 may comprise a single grid or a plurality of independent grids. In many embodiments, the plasma grid 1050 may be removed, thereby utilizing the single chamber space formed by the upper sub-chamber 1002 and the lower sub-chamber 1003.

[0086] A chuck 1017 is located in the lower sub-chamber 1003 near the bottom inner surface. The chuck 1017 is configured to receive and support a semiconductor wafer 1019 on which an etching process is performed. The chuck 1017 may be an electrostatic chuck used to support the semiconductor wafer 1019 when it appears. In some embodiments, an edge ring (not shown) surrounds the chuck 1017, and when a semiconductor wafer 1019 appears on the chuck 1017, the edge ring has an upper surface that is almost planar with a top surface of the semiconductor wafer 1019. The chuck 1017 also includes electrostatic electrodes for clamping and releasing the semiconductor wafer. A filter and a DC clamp power supply (not shown) may be provided for this purpose. Other control systems may also be provided for lifting the semiconductor wafer 1019 off the chuck 1017. The chuck 1017 may be charged using an RF power supply 1023. RF power supply 1023 is connected to matching circuit 1021 via connection 1027. Matching circuit 1021 is connected to chuck 1017 via connection 1025. In this way, RF power supply 1023 is connected to chuck 1017. The chuck can be biased with any suitable bias power, such as between approximately 10 V and approximately 150 V, for example, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 11, 120, 130, 140, or 150 V. In some cases, the bias may be pulsed at approximately 10% of the duty cycle between 0 V and a peak bias power between approximately 600 V and approximately 1200 V.

[0087] A coil 1033 is positioned above window 1011. The coil 1033 is made of a conductive material and includes at least one complete turn. The illustrative coil 1033 shown in Figure 10 includes 3 turns. A cross-section of the coil 1033 is shown with symbols; the coil with an "X" extends rotatably into the page, while the coil with a "●" extends rotatably out of the page. An RF power supply 1041 is configured to provide RF power to the coil 1033. Generally, the RF power supply 1041 is connected to a matching circuit 1039 via a connection 1045. The matching circuit 1039 is connected to the coil 1033 via a connection 1043. In this way, the RF power supply 1041 is connected to the coil 1033. An optional Faraday shield 1049 is positioned between the coil 1033 and window 1011. The Faraday shield 1049 is spatially separated from the coil 1033. Faraday shield 1049 is disposed adjacent to window 1011. Coil 1033, Faraday shield 1049, and window 1011 are each disposed substantially parallel to each other. Faraday shield may prevent metal or other species from depositing on the dielectric window of plasma chamber.

[0088] Processing gases (e.g., oxygen (O2), chlorine (Cl2), boron trichloride (BCl3), hydrogen (H2), carbon tetrafluoride (CF4), and combinations thereof) may be supplied via a main inlet 1060 located in the upper chamber and / or via a side inlet 1070 (sometimes referred to as an STG). A vacuum pump, such as a one- or two-stage mechanical dry pump and / or a turbomolecular pump 1040, may be used during operational plasma processing by employing a closed-loop controlled fluid limiting device (e.g., a throttle valve (not shown) or a pendulum valve (not shown)) to draw the processing gases out of the processing chamber and maintain pressure within the processing apparatus 1000.

[0089] During operation of the instrument, one or more reaction gases may be supplied via inlets 1060 and / or 1070. In certain embodiments, the gas may be supplied only via the main inlet 1060 or only via the side inlet 1070. In some instances, the inlets may be replaced by spray heads. The Faraday shield 1049 and / or optional plasma grid 1050 may include internal channels and orifices that allow the process gas to be delivered into the chamber. One or both of the Faraday shield 1049 and optional plasma grid 1050 may be used as a spray head for delivering the process gas.

[0090] Radio frequency (RF) power is supplied from the RF power supply 1041 to the coil 1033, causing an RF current to flow through the coil 1033. The RF current flowing through the coil 1033 generates an electromagnetic field around the coil 1033. This electromagnetic field induces a current in the upper substation 1002. Various generated ions and free radicals interact physically and chemically with the semiconductor wafer 1019, selectively etching the feature portions of the wafer.

[0091] If the plasma grid 1050 is used, resulting in both an upper sub-chamber 1002 and a lower sub-chamber 1003, an induced current acts on the gas present in the upper sub-chamber 1002 to generate an electron-ion plasma in the upper sub-chamber 1002. If an optional internal plasma grid 1050 is present, it may serve to limit the number of thermoelectrodes in the lower sub-chamber 1003. In several embodiments, the instrument is designed and operated such that the plasma present in the lower sub-chamber 1003 is an ion-ion plasma. In other embodiments, the instrument may be designed and operated such that the plasma present in the lower sub-chamber 1003 is an electron-ion plasma.

[0092] Volatile etching byproducts may be removed from the lower chamber 1003 via port 1022. The chuck 1017 disclosed herein may operate at a high temperature ranging from approximately 30°C to approximately 250°C. In several examples, the chuck 1017 may also operate at a lower temperature, such as when the chuck 1017 is actively cooled. In such examples, the chuck 1017 may, as desired, operate at a substantially lower temperature. The temperature will depend on the etching process and the specific formulation. In several embodiments, chamber 1001 may operate within a pressure range of approximately 1 mTorr to approximately 100 mTorr, or from approximately 50 mTorr to approximately 100 mTorr, for example, approximately 50 mTorr, approximately 60 mTorr, approximately 70 mTorr, approximately 80 mTorr, approximately 90 mTorr, or approximately 100 mTorr. In certain embodiments, the pressure may be higher.

[0093] When chamber 1001 is installed in a cleanroom or a manufacturing facility, chamber 1001 may be coupled to multiple facilities (not shown). These facilities include piping that provides process gases, vacuum, temperature control, and environmental particle control. When these facilities are installed in the target manufacturing facility, they are coupled to chamber 1001. In addition, chamber 1001 may be coupled to a transfer chamber that allows robots to transfer semiconductor wafers into or out of chamber 1001 using conventional automated systems.

[0094] In several embodiments, a system controller 1030 (which may include one or more physical or logic controllers) controls some or all of the operations of an etching chamber. The system controller 1030 may include one or more memory devices and one or more processors. The processor may include: a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor controller board, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions may be stored on memory devices associated with the system controller 1030 or they may be provided via a network. In a particular embodiment, the system controller 1030 executes system control software.

[0095] In several examples, the system controller 1030 controls the gas concentration, wafer movement, and / or the power supplied to the coil 1033 and / or the electrostatic chuck 1017. The system controller 1030 controls the gas concentration by, for example, opening or closing relevant valves to generate one or more input gas flows that provide the necessary reactants at appropriate concentrations. Control of wafer movement may be achieved by, for example, instructing a wafer positioning system to move as desired. The power supplied to the coil 1033 and / or the chuck 1017 may be controlled to provide a specific RF power level. Similarly, if an internal plasma grid 1050 is used, any RF power applied to the grid may be adjusted by the system controller 1030.

[0096] The system controller 1030 may control these and other objects based on: sensor output (e.g., when power, potential, pressure, etc., reach a specific threshold), operating time (e.g., opening a valve at a specific time in the process), or based on instructions received from the user. An illustrative controller is further discussed below.

[0097] Figure 11 shows a semiconductor process cluster architecture with various modules that interface with a vacuum transfer module 1138 (VTM). The configuration of the transfer modules used to "transfer" wafers between multiple storage facilities and processing modules may refer to a "cluster tooling architecture" system. An airlock 1130 (also referred to as a load gate or transfer module) is shown in the VTM 1138, accompanied by four processing modules 1120a-1120d, which may each be optimized to perform various different manufacturing processes. For example, processing modules 1120a-1120d may be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and / or other semiconductor processes. One or more substrate etching processing modules (any of 1120a-1120d) may be implemented as disclosed herein. The airlock 1130 and processing module 1120 may refer to a "station". Each station has a facet 1136 that interfaces with the VTM 1138. Within each facet, sensors 1-18 are used to detect the passage of the wafer 1126 as it moves between the corresponding stations.

[0098] Robot 1122 transfers wafers 1126 between stations. In one embodiment, robot 1122 has one arm, while in another embodiment, robot 1122 has two arms, each arm having an end effector 1124 to pick up wafers (such as wafer 1126) for transfer. A front-end robot 1132, within the Atmospheric Transfer Module (ATM) 1140, is used to transfer wafers 1126 to the airlock 1130 via a gate or front-open wafer transfer cassette (FOUP) 1134 within the Load Port Module (LPM) 1142. A module center 1128 within the processing module 1120 is a location for placing wafers 1126. An aligner 1144 within the ATM 1140 is used to align the wafers.

[0099] In one exemplary processing method, a wafer is placed in one of the FOUPs 1134 within an LPM 1142. A front-end robot 1132 transfers the wafer from the FOUP 1134 to an alignment device 1144, which allows the wafer 1126 to be properly centered before etching or processing. After alignment, the wafer 1126 is moved by the front-end robot 1132 into an airlock 1130. Because the airlock module is capable of accommodating environments between an ATM and a VTM, the wafer 1126 can move between these two pressure environments without damage. The robot 1122 moves the wafer 1126 from the airlock 1130 via the VTM 1138 and into one of the processing modules 1120a-1120d. To achieve this wafer movement, the robot 1122 uses end effectors 1124 on each of its arms. Once wafer 1126 has been processed, it is moved by robot 1122 from processing modules 1120a-1120d to an airlock 1130. From there, wafer 1126 may be moved by front-end robot 1132 to one of FOUP 1134 or to the alignment device 1144.

[0100] It should be noted that the computer controlling the movement of the wafer can be located locally in the cluster architecture, or in a manufacturing floor outside the cluster architecture, or in a remote location and connected to the cluster architecture via a network.

[0101] In several embodiments, a controller is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing equipment, including one or more processing tools, chambers, processing platforms, and / or specific processing elements (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronic devices to control their operation before, during, and after the processing of a semiconductor wafer or substrate. The electronic device may be referred to as a "controller," which may control various different elements or sub-parts of one or more systems. Depending on the processing requirements and / or system type, the controller may be programmed to control any processes disclosed herein, including: delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer into and out of a tool and other transfer tools, and / or load gates connected to or interfacing with a specific system.

[0102] Figure 12 is a high-level block diagram showing a computer system 1200 suitable for implementing one of the controllers used in the embodiments. The computer system may have many physical forms, ranging from an integrated circuit, a printed circuit board, and a small handheld device to a massive supercomputer. The computer system 1200 includes one or more processors 1202 and may further include an electronic display device 1204 (for displaying charts, text, and other data), a main memory 1206 (e.g., random access memory (RAM)), a storage device 1208 (e.g., a hard disk drive), a removable storage device 1210 (e.g., an optical disc drive), a user interface device 1212 (e.g., a keyboard, touchscreen, keypad, mouse, or other pointing device, etc.), and a communication interface 1214 (e.g., a wireless network interface). The communication interface 1214 allows software and data to be transferred between the computer system 1200 and external devices via a link. The system may also include a communication infrastructure 1216 (e.g., a communication bus, a switching network, or a network) connected to the aforementioned devices / modules.

[0103] The information transmitted via the communication interface 1214 may be in the form of a signal transmitted through a communication link, such as an electronic, electromagnetic, optical, or other signal that can be received by the communication interface 1214. This communication link carries the signal and may be implemented using wiring or cables, optical fibers, a telephone line, a mobile phone link, a radio frequency link, and / or other communication channels. With such a communication interface, it is understood that one or more processors 1202 may receive information from a network or output information to a network during the execution of the above method steps. Furthermore, the method embodiments may be executed only on the processor, or may be executed via a network (such as the Internet) in conjunction with a remote processor that shares some of the processing.

[0104] The term "non-transitory computer-readable media" is used generally to refer to primary memory, secondary memory, removable storage, and storage devices (such as hard drives, flash memory, disk-driven memory, optical discs, and other forms of persistent memory), and should not be construed as encompassing transient targets such as carrier waves or signals. Examples of computer code include machine code (such as that generated by a compiler) and files containing higher-order code (which are executed by a computer using a decoder). Computer-readable media may also be computer code transmitted by computer information signals that are contained in a carrier wave and represent a series of instructions that can be executed by a processor.

[0105] Not limited thereto, the illustrated system may include a plasma etching chamber or module, a deposition chamber or module, a spin cleaning chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, an orbital chamber or module, and any other semiconductor processing system that may be associated with or used in the manufacture and / or production of semiconductor substrates. The chambers used in various embodiments may include: inductively coupled, capacitively coupled, a combination of both, or other power systems may be used.

[0106] As described above, depending on the tool performing one or more processing steps, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools distributed throughout a plant, a host computer, another controller, or a tool used for material transport, which carries a container of substrates to and from the tool location and / or a loading port in a semiconductor manufacturing plant.

[0107] In several embodiments, no inert gas for forming an inert plasma is provided during the exposure of the modifying gas (step 404), which modifies at least one region of a surface containing a metal layer to form a modified metal region. Such embodiments provide the modifying gas during the exposure of the modifying gas (step 404), but may not provide the modifying gas during the exposure of the modified layer to an inert bombardment plasma generated from an inert gas to selectively remove the modified metal region (step 408). In various embodiments, the metal-containing layer comprises at least one metal-containing layer comprising at least one of ruthenium, tungsten, titanium, or molybdenum. In various embodiments, the modified metal region may comprise at least one of ruthenium oxide, tungsten chloride, molybdenum chloride, or molybdenum oxide.

[0108] In other embodiments, an inert gas for forming the inert plasma is continuously supplied during the exposure of the modifying gas (when at least a region of a surface containing a metal layer is modified to form a modified metal region) (step 404) and during the exposure of the modified layer to an inert bombardment plasma generated from an inert gas to selectively remove the modified metal region (step 408). Several embodiments provide the modifying gas only during the exposure of the modifying gas (step 404). In such embodiments, a bias voltage sufficient to provide the inert bombardment plasma is provided only during the exposure of the modified layer to the inert plasma (step 408), and no bias voltage sufficient to provide an inert bombardment plasma is provided during the exposure of the modifying gas (step 404).

[0109] In other embodiments, the modified gas and the inert gas for forming the inert plasma are continuously supplied during the exposure of the modified gas (modifying at least a region of a surface containing a metal layer to form a modified metal region) (step 404) and during the exposure of the modified layer to inert bombardment plasma (step 408). In such embodiments, a bias voltage sufficient to provide the inert bombardment plasma is provided only during the exposure of the modified layer to the inert plasma (step 408), and wherein the exposure of the modified gas (step 404) does not have a bias voltage sufficient to provide an inert bombardment plasma. In addition, sufficient plasma excitation power sufficient to form a plasma from the modified gas is provided only during the exposure of the modified gas (step 404), and wherein the exposure of the modified layer to the inert plasma (step 408) does not have sufficient plasma excitation power to form a plasma from the modified gas. In such an embodiment, even if the gas flow of the modified gas and the inert gas remains constant, the pulses of bias power and plasma energy provide different steps for each ALE cycle.

[0110] [Experiment][Experiment 1] A substrate system is provided having a ruthenium blanket coating and a patterned mask having a critical dimension of 16 nm ± 1 nm on the ruthenium. The substrate is exposed to a cycle of pulsed atomic layer etching—that is, a cycle of exposure to oxygen plasma and a cycle of exposure to pulsed biased argon plasma—to etch ruthenium. A bias pulse is applied at approximately 900 V using 10% duty cycle. The resulting substrate after ruthenium is etched using pulsed ALE subtractive etching is depicted in: a cross-sectional view of FIG13A, a top-angle bird's-eye view of FIG13B, and a top view of FIG13C. The results show smooth sidewalls and clearly defined patterned ruthenium remaining on the substrate.

[0111] [Experiment 2] The ALE synergistic effect for various bias voltages used to implement ALE of molybdenum was calculated, and the etch rate of molybdenum was also measured. Figure 13D shows a graph of molybdenum etch rate as a function of argon bias voltage for argon-only and chlorine-only exposures, as well as the ALE synergistic effect curves and the calculated synergistic effect values.

[0112] [Experiment 3] Ruthenium was etched using O2 / Ar ALE with a continuous Ar bias, and an "ALE window" was obtained for various bias voltages used during removal. Figure 14A shows a graph depicting the etching per cycle of argon sputtering only (labeled Ar sputtering), the etching per cycle of oxygen sputtering only (labeled O2 only), and the etching per cycle of ALE using alternating exposure to oxygen and inert argon plasma (labeled ALE). The optimal window achieved was between 60 V and 100 V.

[0113] Ruthenium was etched using pulsed ALE (with pulsed Ar bias), and an "ALE window" was obtained for various bias voltages used during removal. Figure 14B shows a graph depicting the etching per cycle of argon sputtering only (labeled Ar sputtering), etching per cycle of oxygen sputtering only (labeled O2 only), and etching per cycle of ALE with alternating exposure using oxygen and pulsed inert argon plasma using a 10% working cycle (labeled ALE). The optimal window achieved was between 600 V and 1200 V.

[0114] Ruthenium was exposed to argon sputtering only to demonstrate the essential effect of ruthenium removal by sputtering alone for both continuous exposure (100% duty cycle) and pulsed exposure (10% duty cycle) without modification. The results are shown in Figure 14C, which shows that when using pulsed ALE, a wider range of argon bias voltages can be used without such a high etch rate compared to continuous ALE.

[0115] [Experiment 4] Molybdenum etching was performed using an ALE with continuous Ar bias at various bias voltages applied during removal, and the etching rate was measured. Figure 15A shows a graph depicting the etching per cycle for argon sputtering only (labeled as argon sputtering), etching per cycle for chlorine exposure only (labeled as Cl2 only), and etching per cycle for ALE with alternating exposure to chlorine and inert argon plasma (labeled as Cl2 / Ar ALE). The optimal bias voltage depicted is approximately 60 V.

[0116] Observe the roughness before and after ALE; the results are shown in Figure 15B, which shows a set of photos labeled "before" to indicate a roughness of 2.1 nm before ALE; and a set of photos labeled "ALE-50V" to indicate a roughness of approximately 1.4 nm after ALE was performed with a bias power of approximately 50 V during removal. These results mean that performing ALE not only etches the material, but also smooths it.

[0117] Molybdenum was etched using pulsed ALE, and an "ALE window" was obtained for various bias voltages used during removal. Figure 15C shows a graph depicting: etching per cycle of argon sputtering only (labeled Ar sputtering), etching per cycle of chlorine exposure only (labeled Cl2 only), and etching per cycle of ALE (labeled ALE) with alternating exposure using chlorine and (using 10% duty cycle) pulsed inert argon plasma. The optimized window achieved was between 600 V and 1200 V. The ALE synergy increased to 75% (compared to approximately 60% synergy of continuous ALE). Pulsed ALE also resulted in a faster etching rate, with an etching rate of approximately 5-6 Å per cycle, compared to 2-3 Å per cycle of continuous ALE.

[0118] Exposing molybdenum to chlorine only demonstrates the essential effect of molybdenum removal by exposure to chlorine only without sputtering in the case of continuous exposure. The results are shown in Figure 15D, which shows that some molybdenum may be removed by chlorine only and may be rapidly etched at some temperatures; therefore, in some cases, lower temperatures may be used to control the self-limiting layer of ALE.

[0119] [Conclusion] Although this disclosure has described aspects of several preferred embodiments, changes, modifications, and various alternatives exist, all of which are within the scope of this disclosure. It is worth noting that there are many alternatives to the methods and apparatus disclosed herein. Therefore, the appended claims are intended to be understood as encompassing all such changes, modifications, substitutions, and various alternatives, all of which are within the true spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0008] Figures 1, 2A, and 2B are schematic diagrams of exemplary substrates undergoing an etching process.

[0009] Figure 3 is a schematic diagram showing the grains and grain boundaries before and after active ion etching and atomic layer etching.

[0010] Figure 4A shows an example schematic diagram of a substrate undergoing atomic layer etching.

[0011] Figure 4B is a process flow diagram depicting an operation of a method according to a disclosed embodiment.

[0012] Figures 5, 6A, and 6B are schematic diagrams of exemplary substrates subjected to an etching process according to specific disclosed embodiments.

[0013] Figure 7 is a schematic diagram of an example substrate on which metal is deposited.

[0014] Figure 8 is a schematic diagram of an example substrate after being etched by active ion etching using a prior art process.

[0015] Figure 9 is a schematic diagram of an example substrate after being etched by atomic layer etching.

[0016] Figure 10 is a schematic diagram of an exemplary processing chamber for implementing a specific disclosed embodiment.

[0017] Figure 11 is a schematic diagram of an exemplary processing apparatus for implementing a specific disclosed embodiment.

[0018] Figure 12 is a schematic diagram of a computer system that may be used to implement one embodiment.

[0019] Figure 13A is a cross-sectional view of a ruthenium image obtained by subtractive etching using atomic layer etching.

[0020] Figure 13B is an aerial view of ruthenium etched using atomic layer etching with subtractive etching.

[0021] Figure 13C is a top view of a ruthenium image obtained by subtractive etching using atomic layer etching.

[0022] Figure 13D shows the molybdenum etching rate as a function of argon bias voltage and the synergistic effect of molybdenum ALE.

[0023] Figure 14A is a graph showing the ruthenium etching rate as a function of argon bias voltage during continuous atomic layer etching.

[0024] Figure 14B is a graph showing the ruthenium etching rate as a function of argon bias voltage during pulsed atomic layer etching.

[0025] Figure 14C shows a graph of ruthenium etching rate as a function of argon bias when exposed only to argon sputtering in continuous and pulsed sputtering.

[0026] Figure 15A shows a graph of molybdenum etching rate as a function of argon bias voltage for chlorine exposure, argon sputtering only, and continuous atomic layer etching.

[0027] Figure 15B shows images of a molybdenum surface before and after atomic layer etching.

[0028] Figure 15C shows a graph of molybdenum etching rate as a function of argon bias voltage for chlorine exposure, argon sputtering only, and pulsed atomic layer etching.

[0029] Figure 15D shows a graph of molybdenum etching rate as a function of temperature using only chlorine.

Claims

1. A method for atomic layer etching of a molybdenum (Mo) layer, comprising: (a) modifying at least a region of a surface of the Mo layer to form a modified Mo region by exposing a surface of the Mo layer to a modifying gas, wherein an unmodified Mo region remains adjacent to the modified Mo region; (b) selectively removing the modified Mo region relative to the unmodified Mo region by exposing the surface of the Mo layer to an inert bombardment plasma generated by an inert gas; and forming a patterned mask defining a plurality of features, wherein the Mo layer is selectively etched relative to the patterned mask to form the plurality of features in the Mo layer.

2. The method of claim 1, wherein the features have a width of less than 10 nm.

3. The method of claim 1, wherein the features in the Mo-containing layer are a plurality of interlayer windows, wherein the interlayer windows have a linewidth roughness of less than about 2 nm.

4. The method of claim 1, wherein the modified gas comprises at least one of oxygen, chlorine, boron trichloride, hydrogen, and carbon tetrafluoride.

5. The method of claim 1, wherein the modified Mo-containing region comprises at least one of molybdenum chloride or molybdenum oxide.

6. The method of claim 1, wherein the step of exposing the surface containing the Mo layer to an inert plasma does not remove the region containing the unmodified Mo.

7. The method of claim 1, wherein the step of exposing the surface of the Mo-containing layer to the modified gas does not etch the Mo-containing layer.

8. The method of claim 1, wherein during the step of exposing the surface containing the Mo layer to the inert bombardment plasma, the inert gas system is continuously supplied and a continuous bias system is applied, wherein the continuous bias has a bias power between about 60 V and about 100 V such that a plasma formed from the inert gas provides ion bombardment to the surface containing the Mo layer.

9. The method of request item 1, wherein steps (a) and (b) are repeated cyclically a plurality of times.

10. The method of claim 9, wherein the inert gas is provided during steps (a) and (b), wherein step (b) has a bias voltage sufficient to provide the inert bombardment plasma, and wherein step (a) does not have a bias voltage sufficient to provide the inert bombardment plasma.

11. The method of claim 9 further includes a purging step between step (a) and step (b), wherein the purging step purges the modified gas.

12. The method of claim 1, wherein the step of modifying at least a region of the surface containing the Mo layer comprises: flowing a modifying gas; and forming the modifying gas into a plasma.

13. A method for atomic layer etching of a molybdenum (Mo) layer, comprising: (a) modifying at least a region of the surface of the Mo layer to form a modified Mo region by exposing a surface of the Mo layer to a modified gas, wherein an unmodified Mo region remains adjacent to the modified Mo region; and (b) selectively removing the modified Mo region relative to the unmodified Mo region by exposing the surface of the Mo layer to an inert bombardment plasma generated by an inert gas, wherein during the step of exposing the surface of the Mo layer to the inert bombardment plasma, the inert gas system is continuously supplied and a pulsed bias system is applied, the pulsed bias having a peak bias power between approximately 600 V and approximately 1200 V such that a plasma formed from the inert gas provides ion bombardment to the surface of the Mo layer.

14. A method for atomic layer etching of a molybdenum (Mo) layer, comprising: (a) modifying at least a region of a surface of the Mo layer to form a modified Mo region by exposing a surface of the Mo layer to a modifying gas, wherein an unmodified Mo region remains adjacent to the modified Mo region; (b) selectively removing the modified Mo region relative to the unmodified Mo region by exposing the surface of the Mo layer to an inert bombardment plasma generated by an inert gas; and forming a patterned mask on the Mo layer, wherein the patterned mask defines a plurality of patterned mask features.

15. The method of claim 14, wherein the patterned mask defines a plurality of lines, wherein atomic layer etching forms the plurality of Mo-containing lines of the Mo-containing layer, wherein the Mo-containing lines have a linewidth roughness of less than 2 nm.

16. A method for atomic layer etching of a molybdenum (Mo) layer, comprising: (a) modifying at least a region of a surface of the Mo layer to form a modified Mo region by exposing a surface of the Mo layer to a modifying gas, wherein an unmodified Mo region remains adjacent to the modified Mo region; and (b) selectively removing the modified Mo region relative to the unmodified Mo region by exposing the surface of the Mo layer to an inert bombardment plasma generated by an inert gas, wherein the Mo layer is on a patterned mask, wherein the patterned mask forms a plurality of features, and wherein the Mo layer fills the plurality of features, and wherein a first plurality of the plurality of features is narrower than a second plurality of the plurality of features, and wherein the step of etching the Mo layer etches back the portion of the Mo layer filling the plurality of features.

17. The method of claim 16, wherein the Mo-containing layer of the first plurality of the plurality of features is etched back at the same rate as the Mo-containing layer of the second plurality of the plurality of features, and wherein the non-uniformity of the lines of the plurality of features is less than 5 nm.

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