Semiconductor device and method of forming thereof

Abstract

This disclosure provides a semiconductor structure and a method for forming the same. An exemplary method includes receiving a workpiece comprising a fin structure and a dummy gate stack disposed above the fin structure. The fin structure includes a fin substrate, a bottom semiconductor stack, an intermediate dielectric layer disposed above the bottom semiconductor stack, and a top semiconductor stack. Both the top and bottom semiconductor stacks include channel layers interleaved by sacrificial layers. The method further includes: recessing a portion of the dummy gate stack to form a trench, thereby exposing the fin structure; removing the sacrificial layers from the top and bottom semiconductor stacks from the trench; removing the channel layers from the top and bottom semiconductor stacks from the trench; and depositing dielectric features in the trench. The dielectric features surround the intermediate dielectric layer.

Description

Technical Field

[0001] none. Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Advances in IC materials and design technologies have spurred generation after generation of ICs, each generation smaller and more complex than the last. Throughout IC development, functional density (the number of interconnects per wafer area) has generally increased, while geometry (the smallest device (or line) that can be manufactured using a process) has decreased. This shrinking process typically improves production efficiency and reduces associated costs.

[0003] This shrinkage also increases the complexity of integrated circuit (IC) fabrication and manufacturing. For example, as IC technology advances to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effect (SCE). Multi-gate devices generally refer to devices where the gate structure or a portion thereof is located on multiple sides of the channel region. FinFETs and gate-on-a-ring (GAA) transistors are examples of multi-gate devices, and they have become popular and promising candidates for high-efficiency and low-leakage applications. A FinFET has an elevated channel that is surrounded by a gate on multiple sides (e.g., the gate surrounds the top and sidewalls of a semiconductor material "fin" extending from the substrate). A GAA transistor has a gate structure that can extend partially or completely around the channel region, allowing access to the channel region from two or more sides. The channel region of a GAA transistor can be formed from nanowires, nanosheets, or other suitable nanostructures. Due to the shape of the channel region, GAA transistors can also be called nanosheet transistors or nanowire transistors.

[0004] As the semiconductor industry continues to pursue higher device density, performance, and cost efficiency, manufacturing and design challenges have led to the adoption of stacked device structures. Complementary field-effect transistors (C-FETs) are one such structure, in which n-type multigate transistors and p-type multigate transistors are vertically stacked, one on top of the other. While existing C-FET isolation structures and their manufacturing techniques are generally sufficient for their intended applications, not all aspects are entirely satisfactory. Summary of the Invention

[0005] none. Simple Explanation of the Diagram

[0006] The various features disclosed herein can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figure 1 shows a perspective view of a semiconductor device including a vertical complementary field-effect transistor according to one or more aspects of this disclosure. Figure 2 shows a flowchart of a method for forming a semiconductor device including a vertical complementary field-effect transistor according to one or more aspects of this disclosure. Figures 3A, 3B, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B, 25A, 25B, 26A, 26B, 27A, 27B, 28A, and 28B show partial cross-sectional views of the workpiece during various manufacturing stages in the method of Figure 2 according to various aspects of this disclosure. Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact.

[0008] For ease of description, this document uses spatially relative terms such as "below," "down," "above," and "up" to describe the relationship between one device or feature and another as shown in the figure. These spatially relative terms are intended to cover different orientations of the device during use or operation, other than those shown in the figure. The device may be in other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0009] Furthermore, when terms such as "about" or "approximately" are used to describe a numerical value or range, the term is intended to encompass values ​​within a reasonable range as understood by those skilled in the art, taking into account inherent variations in the manufacturing process. For example, this numerical value or range encompasses a reasonable range including, for instance, values ​​within ±10% of the value, based on known manufacturing tolerances associated with manufacturing features having characteristics related to that value. For example, a material layer with a thickness of "about 5 nm" may cover a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with depositing such a material layer are known to those skilled in the art to be ±15%.

[0010] A stacked multi-gate device (CFET) refers to a semiconductor device comprising a bottom CFET and a top CFET stacked on top of the bottom CFET. When the bottom and top CFETs are transistors of different conductivity types, the stacked CFET can be a complementary field-effect transistor (C-FET). The CFET can be a FinFET or a GAA transistor. An intermediate dielectric layer inserted between the stacked transistors in a C-FET electrically isolates the n-type and p-type transistors, preventing current leakage and minimizing crosstalk. To maintain continuous scaling and higher density in advanced technology nodes, a defined edge cut (CPODE) process using polysilicon oxide can be used to form isolation structures (called CPODE structures or CPODE features) to facilitate further reduction of the contact polysilicon pitch (CPP) (or "gate pitch"). However, the presence of the intermediate dielectric layer presents a challenge in forming CPODE features in a C-FET. For example, CPODE features can be formed by filling CPODE trenches, and the method of filling trenches is to selectively remove part of the dummy gate structure and the stacked active region below the intermediate dielectric layer. Removing dielectric material from the intermediate dielectric layer and semiconductor material from the stacked active region typically requires high-bias etching, which may damage adjacent dielectric features (e.g., gate spacers and inner spacers) and other semiconductor features.

[0011] This disclosure provides a method for forming CPODE features in a C-FET without significantly removing the intermediate dielectric layer. This method enables the formation of CPODE trenches using gentle etching, thereby reducing the risk of damaging adjacent dielectric and semiconductor features. The dielectric material filling the CPODE trenches covers the intermediate dielectric layer, integrating it as part of the formed CPODE feature.

[0012] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, FIG1 shows a perspective view of a semiconductor device incorporating a C-FET according to one or more aspects of this disclosure. FIG2 shows a flowchart of a method 100 for forming a workpiece 200 incorporating a C-FET according to one or more aspects of this disclosure. Method 100 is described below in conjunction with FIGS. 3A to 23B, which are partial cross-sectional views of the workpiece 200 at different manufacturing stages according to an embodiment of method 100. Method 100 is merely an example and is not intended to limit this disclosure to what is explicitly described therein. Additional steps may be provided before, during, and after method 100, and some steps described may be replaced, deleted, or moved for other embodiments of the method. For reasons of brevity, not all steps are described in detail herein. Since the workpiece 200 will be made into a semiconductor device after the manufacturing process is completed, the workpiece 200 may be referred to as a semiconductor device or semiconductor structure as the context requires. Furthermore, in this application and in various embodiments, unless otherwise stated, the same reference numerals denote the same features having similar structures and compositions. To avoid ambiguity, the X, Y, and Z directions in the diagram are perpendicular to each other and remain consistent.

[0013] Figure 1 depicts an exemplary semiconductor device (e.g., C-FET) 10. The semiconductor device 10 includes a lower device 10L (e.g., a p-type transistor) and an upper device 10U (e.g., an n-type transistor) located above the lower device 10L. The lower device 10L includes a channel layer 26'L enclosed by an underlying structure. The bottom gate structure includes a gate dielectric layer 78 and a gate electrode layer 80L. The lower device 10L also includes a source / drain feature (e.g., a p-type epitaxial source / drain feature) 62L coupled to the channel layer 26'L and adjacent to the bottom gate structure.

[0014] The upper device 10U includes a channel layer 26'U, which is enclosed by an upper gate structure. The upper gate structure includes a gate dielectric layer 78 and a gate electrode layer 80U. The upper device 10U also includes a source / drain feature (e.g., an n-type epitaxial source / drain feature) 62U, which is coupled to the channel layer 26'U and adjacent to the upper gate structure. An isolation layer 90 is disposed between the upper device 10U and the lower device 10L to electrically insulate the upper gate structure of the upper device 10U from the bottom gate structure of the lower device 10L. Since the isolation layer 90 is vertically located in the middle of the semiconductor device 10, it is also referred to as the intermediate dielectric layer 90. The configuration of the devices in the semiconductor device 10 described above is for illustrative purposes only and can be modified according to actual applications. It should be understood that some features are omitted in this figure for simplicity.

[0015] Referring now to Figures 2 and 3A-3B, method 100 includes a step 102 for receiving workpiece 200. Figure 3A depicts a cross-sectional view of workpiece 200 in the XZ plane, taken along line AA shown in Figure 3B; Figure 3B depicts a cross-sectional view of workpiece 200 in the YZ plane. Workpiece 200 includes substrate 202. In one embodiment, substrate 202 may be a silicon (Si) substrate. In some other embodiments, substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or group III-V semiconductor materials. Exemplary group III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer, such as a silicon oxide layer, to form a silicon-on-insulator (SOI) structure. Although not explicitly shown in the figures, the substrate 202 may include n-type well regions and p-type well regions for fabricating transistors of different conductivity types. When present, both n-type and p-type wells are formed in the substrate 202 and have doping profiles. The n-type wells may contain a doping profile of n-type dopants (e.g., phosphorus (P) or arsenic (As)). The p-type wells may contain a doping profile of p-type dopants (e.g., boron (B)). The doping in the n-type and p-type wells may be formed by ion implantation or thermal diffusion processes and may be considered as part of the substrate 202. For ease of reference, during method 100, the substrate 202 and the structure formed thereon may be referred to as workpiece 200.

[0016] The workpiece 200 also includes a fin structure 210 formed above the substrate 202. In this embodiment, the fin structure 210 is formed from the top of the superlattice structure 204 and the substrate 202. The superlattice structure 204 can be deposited above the substrate 202 using an epitaxial process. Suitable epitaxial processes include vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The superlattice structure 204 includes a plurality of channel layers 208, which are alternately arranged by a plurality of sacrificial layers 206. The sacrificial layers 206 and the channel layers 208 are deposited alternately to form the superlattice structure 204. The channel layers 208 and the sacrificial layers 206 can have different semiconductor compositions. In some embodiments, the channel layers 208 are formed of silicon (Si), while the sacrificial layers 206 are formed of silicon-germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layer 206 allows for selective removal or etching of the sacrificial layer 206 without causing substantial damage to the channel layer 208.

[0017] For ease of reference, the superlattice structure 204 can be vertically divided into a bottom 204B, an intermediate sacrificial layer 206M on the bottom 204B, and a top 204T on the intermediate sacrificial layer 206M. In this example, the bottom 204B of the superlattice structure 204 includes channel layers 208L1, 208L2, and 208L3, which are alternately arranged by sacrificial layers 206L1, 206L2, and 206L3. The top 204T of the superlattice structure 204 includes channel layers 208U1, 208U2, and 208U3, which are alternately arranged by sacrificial layers 206U1 and 206U2. The channel layers 208L1, 208L2, 208L3, 208U1, 208U2, and 208U3 will provide the nanostructure as the channel region of the C-FET10. In some embodiments, channel layers 208U1 to 208U2 and channel layers 208L2 to 208L3 will provide nanostructures as channel regions for the top GAA transistor and bottom GAA transistor in the C-FET10, respectively. The nanostructure in which the channel regions are located is also referred to as a channel component. As used herein, the term "channel component" refers to any portion of material in a transistor that serves as a channel, having a nanometer-scale size and an elongated shape, regardless of the cross-sectional shape of the portion. The germanium content of the intermediate sacrificial layer 206M may differ from the germanium content of the other sacrificial layers (e.g., sacrificial layers 206U1 to 206U3, sacrificial layers 206L1 to 206L3) of the top 204T and bottom 204B. In some embodiments, the germanium content of the intermediate sacrificial layer 206M may be higher than that of the other sacrificial layers 206U1 to 206U3 and 206L1 to 206L3, such that the entire intermediate sacrificial layer 206M can be selectively removed during the formation of the inner spacer trench. In further description of some embodiments, the germanium molar concentration of sacrificial layers 206U1 to 206U3 and 206L1 to 206L3 can range from about 10% to about 50%, and the germanium molar concentration of the intermediate sacrificial layer 206M can range from about 20% to about 80%.

[0018] It is worth noting that the superlattice structure 204 in Figures 3A and 3B includes six (6) channel layers 208, which are interleaved with six (6) sacrificial layers 206. This is for illustrative purposes only and is not intended to limit the specific content set forth in the claims. It is understood that the superlattice structure 204 may contain any number of channel layers 208 and be distributed between the bottom 204B and the top 204T. The number of layers depends on the number of channel devices required for the top GAA transistor and the bottom GAA transistor. In some embodiments, the number of channel layers 208 in the superlattice structure 204 may be between 4 and 10. The thickness of the channel layers 208 and the sacrificial layers 206 may be selected based on considerations of the device performance of the bottom GAA transistor, the top GAA transistor, and the overall C-FET.

[0019] After forming the superlattice structure 204, the top of the superlattice structure 204 and the substrate 202 are patterned to form fin structures 210. For patterning, a hard masking layer can be deposited over the superlattice structure 204. The hard masking layer can be a single layer or multiple layers. In one example, the hard masking layer includes a silicon oxide layer and a silicon nitride layer located above the silicon oxide layer. As shown in Figures 3A and 3B, each fin structure 210 extends vertically from the substrate 202 along the Z direction and longitudinally along the X direction. Suitable processes (including dual-patterning or multi-patterning processes) can be used to pattern the fin structures 210. Typically, dual-patterning or multi-patterning processes combine photolithography and self-aligned processes, thereby enabling the creation of patterns with smaller pitches, for example, smaller pitches than those obtained using a single direct photolithography process. For example, in one embodiment, a material layer is formed on the substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can be used as an etching mask to etch the top of the superlattice structure 204 and the substrate 202, thereby forming a fin structure 210, including a fin substrate 210B formed from the patterned top of the substrate 202. The horizontal dashed line in Figure 3A and subsequent figures indicates the location of the bottom of the fin structure 210, which also corresponds to the recessed top surface of the substrate 202.

[0020] Referring to Figure 3B, the workpiece 200 also includes an isolation feature 212 formed around the fin structure 210 to separate two adjacent fin structures 210. The isolation feature 212 may also be referred to as a shallow trench isolation (STI) feature 212. In an exemplary process, a dielectric material for the isolation feature 212 is deposited on the workpiece 200, including the fin structure 210, using CVD, subatmospheric pressure CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized and recessed to form the isolation feature 212. The fin structure 210 is higher than the isolation feature 212. In the illustrated embodiment, the top surface of the isolation feature 212 intersects with the opposite sidewall of the fin substrate 210B. Due to the etchant loading effect of the recessed process, the top surface of the isolation feature 212 may exhibit a recessed profile, i.e., the top surface is not flat and curves downwards. The dielectric material used for isolation feature 212 may include silicon oxide, silicon oxynitride, fluorinated silicate glass (FSG), low-k dielectric materials, combinations thereof, and / or other suitable materials. In some embodiments, the dielectric constant of the dielectric material used for isolation feature 212 may be in the range of about 3 to about 5.

[0021] Referring to Figures 2 and 4, method 100 includes step 104, wherein a dummy gate stack (also referred to as a dummy gate structure) 214 is formed over the channel region 210C of the fin structure 210. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 214 serves as a placeholder for the functional gate structure. Other processes and configurations are also possible. To form the dummy gate stack 214, a dummy dielectric layer 216, a dummy gate electrode layer 218, and a gate top hard mask layer 220 need to be deposited over the workpiece 200. The deposition of these layers can be performed using low-pressure chemical vapor deposition (LPCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electron beam evaporation, other suitable deposition techniques, and / or combinations thereof. The dummy dielectric layer 216 may comprise silicon oxide, the dummy gate electrode layer 218 may comprise polysilicon, and the gate-top hard mask layer 220 may be a multilayer structure comprising silicon oxide and silicon nitride. The gate-top hard mask layer 220 is patterned using photolithography and etching processes. Photolithography processes may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. Etching processes may include dry etching, wet etching, and / or other etching methods. Similar to the fin structure 210, the dummy gate stack 214 may also be patterned using dual patterning or multiple patterning techniques. Subsequently, using the patterned gate-top hard mask layer 220 as an etching mask, the dummy dielectric layer 216 and the dummy gate electrode layer 218 are etched to form the dummy gate stack 214. Each dummy gate stack 214 extends longitudinally along the Y direction, covering the fin structure 210 and resting on the isolation feature 212. The fin structure 210 portion beneath each dummy gate stack 214 defines a channel region 210C. Each channel region 210C and its corresponding dummy gate stack 214 also define a source / drain region 210SD that does not vertically overlap with the dummy gate stack 214. The channel region 210C is located along the X direction between two source / drain regions 210SD. A source / drain region can refer to a source region used to form a source or a drain region used to form a drain, and can refer to them individually or collectively depending on the context.

[0022] Referring again to Figures 2 and 4, method 100 includes step 106, wherein the source / drain region 210SD of the fin structure 210 is recessed to form a source / drain trench (also referred to as a source / drain recess) 224. The operation in step 106 may include forming a gate spacer 222 above the sidewalls of the dummy gate stack 214 prior to the recessing of the source / drain region 210SD. In some embodiments, the formation of the gate spacer 222 includes depositing one or more dielectric layers over the workpiece 200. In exemplary processes, one or more dielectric layers are conformally deposited using CVD, SACVD, or ALD. One or more dielectric layers may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonoxy, silicon carbonitride, and / or combinations thereof. After depositing gate spacer 222, the workpiece 200 undergoes an anisotropic etching process to form source / drain trench 224. The etching process in step 106 can be a dry etching process or other suitable etching processes. Exemplary dry etching processes may employ oxygen-containing gases, hydrogen-containing gases, fluorine-containing gases (e.g., CF4, SF6, NF3, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. As shown in FIG5, the sidewalls of the sacrificial layer 206 and the channel layer 208 in the channel region 210C are exposed in the source / drain trench 224.

[0023] Referring to Figures 2 and 5, method 100 includes step 108, wherein an inner spacer recess 225 is formed. An etching process can be performed to selectively partially recess the sacrificial layer 206 exposed in the source / drain trench 224, thereby forming the inner spacer recess 225. In some embodiments, the etching process can be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree to which the sacrificial layer 206 is recessed is controlled by the duration of the etching process. A selective dry etching process can include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. A selective wet etching process can include the use of hydrogen fluoride (HF) or ammonium hydroxide (NH4OH). In the illustrated embodiment, the germanium content of the intermediate sacrificial layer 206M is higher than that of the sacrificial layers 206U1 to 206U3 and 206L1 to 206L3, and the etchant etching process etches the intermediate sacrificial layer 206M at a higher rate than the process that etches the other sacrificial layers. Therefore, the inner spacer groove 225 is formed by partially laterally recessing sacrificial layers 206U1 to 206U3 and 206L1 to 206L3. During the formation of the inner spacer groove, the entire intermediate sacrificial layer 206M is removed, leaving a gap 225M that runs through the entire fin structure 210 and separates the top 204T and the bottom 204B. Similarly, in the illustrated embodiment, due to limited etching contrast, the ends of the channel layer 208 may suffer etching loss, especially in the vertical direction. Therefore, the thickness at the ends of the channel layer 208 may be less than the thickness of the middle portion, and the vertical height of the inner spacer groove 225 may exceed the thickness of the sacrificial layer 206. Furthermore, the two channel layers 208L1 and 208U3 sandwiching the gap 225M may have vertical recesses on their top and bottom surfaces, respectively, opposite the gap 225M. Therefore, the gap 225M may expand in the vertical direction, becoming thicker than the original thickness of the intermediate sacrificial layer 206M. Therefore, the thickness of channel layers 208L1 and 208U3 can be reduced compared to other channel layers 208L2 to 208L3 and 208U1 to 208U2.

[0024] Referring to Figures 2 and 6, method 100 includes step 110 of forming an inner spacer 226. After forming the inner spacer recess 225, an inner spacer material layer is deposited over the workpiece 200 to fill the inner spacer recess 225. Additionally, the inner spacer material layer is also deposited in the gap 225M, which is the space left after selectively removing the intermediate sacrificial layer 206M. The inner spacer material layer may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excess portions of the inner spacer material layer above the dummy gate stack 214, gate spacer layer 222, and channel layer 208 sidewalls, thereby forming the inner spacer 226 and the intermediate dielectric layer 226M. In this embodiment, the inner spacers 226 include inner spacers 226a and 226b disposed above the intermediate dielectric layer 226M, and inner spacers 226c, 226d, and 226e disposed below the intermediate dielectric layer 226M. The inner spacers 226a to 226e and the intermediate dielectric layer 226M are respectively located between two vertically adjacent channel layers 208. For example, inner spacer 226b is located between channel layers 208U2 and 208U3, and inner spacer 226c is located between channel layers 208L1 and 208L2. In some embodiments, the etch-back process at step 110 can be a dry etching process, which includes using oxygen-containing gas, hydrogen, nitrogen, fluorine-containing gas (e.g., NF3, CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas (e.g., CF3I), other suitable gases and / or plasma, and / or combinations thereof. In the illustrated embodiment, the inner spacer 226 and the intermediate dielectric layer 226M contain the same dielectric material composition. Alternatively, the inner spacer 226 and the intermediate dielectric layer 226M may contain different dielectric material compositions, for example, by filling the gap 225M in a separate deposition process different from that used to fill the inner spacer recess 225.

[0025] Referring to Figures 2 and 7, method 100 includes step 112, wherein a leakage barrier layer 228 is formed in a source / drain trench 224, and a bottom source / drain feature 230 is formed over the leakage barrier layer 228 in the source / drain trench 224. The leakage barrier layer 228 is used to reduce leakage into the substrate 202. The leakage barrier layer 228 may include an undoped semiconductor material or a dielectric material. In some embodiments, the leakage barrier layer 228 includes an undoped semiconductor material, such as undoped silicon (Si), undoped silicon germanium (SiGe), or undoped germanium (Ge). Alternatively, the leakage barrier layer 228 may be a dielectric layer, such as an oxide layer or a nitride layer. In these embodiments, the leakage barrier layer 228 may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable epitaxial deposition processes.

[0026] Referring again to Figure 7, after forming the leakage barrier layer 228, the bottom source / drain feature 230 can be formed using epitaxial processes (e.g., VPE, UHV-CVD, MBE, and / or other suitable processes). The epitaxial growth process can use gaseous and / or liquid precursors that interact with the exposed sidewalls of the bottom channel layers 208L2 and 208L3. The leakage barrier layer 228 prevents the bottom source / drain feature 230 from epitaxially growing from the top surface of the substrate 202. In some alternative embodiments, if the formation of the leakage barrier layer 228 is optionally skipped, the epitaxial growth of the bottom source / drain feature 230 can proceed from the top surface of the substrate 202 and the exposed sidewalls of the channel layer 208. As shown in Figure 7, the bottom source / drain feature 230 is in physical contact (or adjacent) to the channel layers 208L2 and 208L3. Depending on the design, the bottom source / drain feature 230 can be n-type or p-type. In the illustrated embodiment, the bottom source / drain feature 230 is a p-type source / drain feature and may contain germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials. In-situ doping can be performed by introducing a p-type dopant (e.g., boron or gallium) during the epitaxial process, or ex-situ doping can be performed using a junction implantation process.

[0027] Referring to Figures 2 and 8, method 100 includes step 114, wherein a bottom contact etch stop layer (CESL) 232 and a bottom interlayer dielectric layer (ILD) 234 are deposited over the bottom source / drain feature 230. The bottom CESL 232 may comprise silicon nitride, silicon oxynitride, and / or other materials, and may be formed via CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. In one embodiment, the bottom CESL 232 comprises silicon nitride, and the ratio of nitrogen concentration to silicon concentration (i.e., N / Si) of the bottom CESL 232 is in the range of about 1.1 to about 1.3. In some embodiments, the bottom CESL 232 is first conformally deposited on the workpiece 200, and then the bottom ILD layer 234 is deposited on the bottom CESL 232 via spin coating, flow chemical vapor deposition (FCVD), chemical vapor deposition (CVD), or other suitable deposition techniques. The bottom ILD layer 234 may include, for example, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicate oxide (e.g., borosilicate silicate glass (BPSG), fused silica glass (FSG), phosphosilate glass (PSG), boron-doped silicate glass (BSG)) and / or other suitable dielectric materials. The dielectric constant of the bottom CESL 232 is greater than that of the bottom ILD layer 234.

[0028] Referring to Figures 2 and 9, method 100 includes step 116, wherein the bottom CESL 232 and the bottom ILD layer 234 are etched back. In the illustrated embodiment, the bottom CESL 232 and the bottom ILD layer 234 are etched back until the sidewalls of the channel layers 208U1 and 208U2 are exposed. After etching back, the bottom CESL 232 is in direct contact with the inner spacers 226b to 226c, the channel layers 208U3 and 208L1, and the intermediate dielectric layer 226M.

[0029] Referring to Figures 2 and 10, method 100 includes step 118, in which a top source / drain feature 248 is formed over the bottom CESL 232 and the bottom ILD layer 234. The top source / drain feature 248 can be formed using epitaxial processes such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can use gaseous and / or liquid precursors that interact with the composition of the channel layers (e.g., channel layers 208U1 and 208U2) at the top 204T of the superlattice structure 204. Epitaxial growth of the top source / drain feature 248 can be performed from the exposed sidewalls of the top channel layers 208U1 and 208U2. The deposited top source / drain feature 248 is in physical contact (or adjacent) to the channel layers at the top 204T of the superlattice structure 204. Depending on the design, the top source / drain feature 248 can be n-type or p-type. In the illustrated embodiment, the top source / drain feature 248 is an n-type source / drain feature, which may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials. It can be in-situ doped by introducing an n-type dopant (e.g., phosphorus, arsenic, or antimony) during the epitaxial process, or it can be in-situ doped using a junction implantation process.

[0030] Referring to Figures 2 and 11, method 100 includes step 120, wherein a top CESL 250 and a top ILD layer 252 are deposited over a top source / drain feature 248. The top CESL 250 may comprise silicon nitride, silicon oxynitride, and / or other materials known in the art, and may be formed via CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) processes and / or other suitable deposition or oxidation processes. In some embodiments, the top CESL 250 is first conformally deposited on the workpiece 200, and then the top ILD layer 252 is deposited over the top CESL 250 via spin coating, FCVD, CVD, or other suitable deposition techniques. The material of the top interlayer dielectric layer 252 may include: tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silica, such as tetraethyl borophosphosilicate (TEOS) oxide, undoped silicate glass, or doped silica, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica, or other doped materials. The dielectric constant of the bottom contact etch stop layer (CESL) 250 is greater than that of the bottom interlayer dielectric layer 252. After forming the top interlayer dielectric layer 252, the workpiece 200 can be planarized through a planarization process to remove excess material, thereby exposing the dummy gate stack 214. For example, the planarization process may include a chemical mechanical planarization (CMP) process. In the illustrated embodiment, the gate top hard mask layer 220 is also removed through a CMP process.

[0031] Referring to Figures 2 and 12, method 100 includes step 122, wherein a capping layer 253 is formed on a top ILD layer 252. The capping layer 253 is formed of a different dielectric material than the top ILD layer 252 and serves as a protective layer to prevent damage to the top ILD layer 252 during subsequent etching processes. In some embodiments, the top ILD layer 252 is selectively recessed to form a top recess, and the capping layer 253 is deposited thereon. The capping layer 253 may include silicon nitride, silicon carbonitride, silicon carbide, or silicon carbonitride oxide. In one embodiment, the capping layer 253 is composed of silicon nitride. A planarization process is then performed to remove excess dielectric material from the capping layer 253 and expose the dummy gate stack 214. For example, the planarization process may include another CMP process. After planarization, the top surfaces of the capping layer 253, the top CESL 250, the gate spacer layer 222, and the dummy gate stack 214 are coplanar.

[0032] Referring to Figures 2 and 13A-13B, method 100 includes step 124, wherein a hard mask layer 260 is formed over a workpiece 200, and an etching mask 262 is formed over the hard mask layer 260. Figure 13A depicts a cross-sectional view of the workpiece 200 in the XZ plane, and Figure 13B depicts a cross-sectional view of the workpiece 200 in the YZ plane, the cross-section being taken along line BB shown in Figure 13A. The hard mask layer 260 may be a single-layer hard mask formed from materials such as silicon nitride, silicon oxynitride, etc., using a suitable formation method (e.g., CVD). In some embodiments, the hard mask layer 260 is a multilayer structure. For example, the hard mask layer 260 may include a silicon layer sandwiched between two silicon nitride layers. The etching mask 262 may be a single-layer structure (may include a photoresist layer) or a double-layer structure (including a bottom anti-reflective coating (BARC) and a photoresist layer). In the illustrated embodiment, the etch mask 262 has a three-layer structure, including a bottom layer 264 (e.g., a BARC layer), an intermediate layer 266 (e.g., a silicon nitride layer or a silicon oxynitride layer), and a top layer 268 (e.g., a photoresist layer). In the illustrated embodiment, the top layer 268 includes an opening 270 located above the fin structure 210. The opening 270 can be formed by a photolithography process.

[0033] Referring to Figures 2 and 14A-14B, method 100 includes step 126, in which an opening 270 is transferred onto a hard mask layer 260 to form an opening 272 in the hard mask layer 260. Figure 14A depicts a cross-sectional view of workpiece 200 in the XZ plane, and Figure 14B depicts a cross-sectional view of workpiece 200 in the YZ plane, the cross-section being taken along line BB shown in Figure 14A. The operation in step 126 may include: extending the opening 270 in the top layer 268 through the intermediate layer 266 and the bottom layer 264, and then transferring the opening 270 onto the hard mask layer 260 using a suitable method (e.g., one or more anisotropic etching processes) to form the opening 272. Next, the etch mask 262 is removed by a suitable process (e.g., etching, ashing, or a combination thereof).

[0034] Opening 272 exposes a section of dummy gate stack 214 for removal and replacement with an isolation structure in subsequent processes. Removal of the exposed dummy gate stack 214 is also known as the CPODE process, the resulting trench is called a CPODE trench, and the isolation structure filling the trench is called a CPODE feature, the details of which will be discussed below. It is noteworthy that, as shown in Figure 14A, the dielectric material composition selected for the gate spacer layer 222, the top CESL 250, and the capping layer 253 expands the process window, making the precise location of the edge of opening 272 insensitive. Therefore, subsequent selective etching processes are confined to the exposed portion of the dummy gate stack 214, and adjacent dielectric features are essentially not etched, even though one or more top surfaces of the gate spacer 222, the top CESL 250, and the capping layer 253 are exposed by opening 272.

[0035] Referring to Figures 2 and 15A-15B, method 100 includes step 128, wherein an etching process 274 is performed to extend an opening 272 through an exposed portion of a dummy gate stack 214. Figure 15A depicts a cross-sectional view of workpiece 200 in the XZ plane, and Figure 15B depicts a cross-sectional view of workpiece 200 in the YZ plane, taken along the cut line BB shown in Figure 15A. The extended opening 272 is also referred to as a CPODE trench 272. The CPODE trench 272 exposes a dummy dielectric layer 216. The dummy dielectric layer 216 may be used as an etch stop layer during the etching process 274. In the illustrated embodiment, the etching process 274 is an anisotropic etching process, which may include a dry etching process or a suitable etching process. For example, dry etching processes can employ oxygen-containing gases, hydrogen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), their respective gases, and combinations of other gases. As shown in Figure 15A, the gate spacer 222 remains substantially intact during the etching process 274, confining the etching process 274 between the opposing sidewalls of the gate spacer 222 in the XZ plane.

[0036] Referring to Figures 2 and 16A-16B, method 100 includes step 130, wherein an etching process 276 is performed to remove the dummy dielectric layer 216 from the CPODE trench 272. Figure 16A depicts a cross-sectional view of the workpiece 200 in the XZ plane, and Figure 16B depicts a cross-sectional view of the workpiece 200 in the YZ plane, the cross-section being taken along the cutting line BB shown in Figure 16A. In the illustrated embodiment, the etching process 276 is an isotropic etching process (e.g., dry chemical etching or wet etching). Alternatively, the etching process 276 may also be an anisotropic etching process (e.g., dry plasma etching). After the dummy dielectric layer 216 is removed, the fin structure 210 is exposed within the CPODE trench 272. Specifically, the sidewalls of the channel layer 208, the sacrificial layer 206, and the intermediate dielectric layer 226M, as well as the top surface of the isolation feature 212 and the top channel layer 208U1, are exposed in the CPODE trench 272.

[0037] The exposure of the fin structure 210 in the CPODE trench 272 allows for its removal. Notably, the presence of the intermediate dielectric layer 226M presents a challenge to the etching process. Specifically, due to low etching selectivity, a single etching step that simultaneously removes the channel layer 208, the sacrificial layer 206, and the intermediate dielectric layer 226M can compromise the integrity of adjacent dielectric features, such as the gate spacer 222 and the inner spacer 226. Conversely, if the etching process removes the channel layer 208 first, then the sacrificial layer 206, or both simultaneously, sufficient time is required to etch at least half the width of the channel layer 208 in the YZ plane (along the Y direction). This lengthy etching process may inadvertently etch through the relatively thinner ends of the channel layer 208 in the XZ plane (the portion vertically stacked between the inner spacers 226), resulting in unintended exposure of the source / drain features 230 and 248. As discussed in detail below, some embodiments of this disclosure employ a selective etching process to remove the sacrificial layer 206 before removing the channel layer 208, while substantially preserving the intermediate dielectric layer 226M. This approach maintains the integrity of adjacent dielectric features and prevents the ends of the channel layer 208 in the XZ plane from being etched through.

[0038] Referring to Figures 2 and 17A-17B, method 100 includes step 132, in which an etching process 278 is performed to remove the sacrificial layer 206 from the CPODE trench 272. Figure 17A depicts a cross-sectional view of the workpiece 200 in the XZ plane, and Figure 17B depicts a cross-sectional view of the workpiece 200 in the YZ plane, taken along line BB shown in Figure 17A. In the illustrated embodiment, the etching process 278 is an isotropic etching process (e.g., dry chemical etching or wet etching) because if an anisotropic etching process is used, the presence of the intermediate dielectric layer 226M would obscure the removal of the underlying sacrificial layer 206. In some embodiments, the etching process 278 includes dry chemical etching, which uses a vapor-phase etchant (e.g., xenon difluoride (XeF2)) to react with the SiGe in the sacrificial layer 206 and form volatile byproducts. Dry chemical etching typically has high selectivity for SiGe, thereby minimizing the impact on adjacent silicon and dielectric materials. In other embodiments, etching process 278 includes remote plasma etching, which generates reactive radicals to facilitate selective removal of SiGe while minimizing damage to surrounding materials. For example, nitrogen trifluoride (NF3) and ammonia (NH3) can be used in a remote plasma apparatus to generate reactive materials that are isotropically etchable to SiGe. Furthermore, in other embodiments, a wet etching process can be employed to selectively remove the sacrificial layer 206. For example, a wet etching solution containing a mixture of nitric acid (HNO3), acetic acid (CH3COOH), and hydrofluoric acid (HF) can be used to achieve high selectivity between SiGe and adjacent silicon and dielectric materials. Alternatively, tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH) solutions, along with oxidants (e.g., hydrogen peroxide (H2O2)), can be used to enhance etching selectivity.

[0039] Referring to Figures 2 and 18A-18B, method 100 includes step 134, in which an etching process 280 is performed to remove the channel layer 208 from the CPODE trench 272. Figure 18A depicts a cross-sectional view of the workpiece 200 in the XZ plane, and Figure 18B depicts a cross-sectional view of the workpiece 200 in the YZ plane, taken along the cutting line BB shown in Figure 18A. In the illustrated embodiment, the etching process 280 is an isotropic etching process (e.g., dry chemical etching or wet etching) because if an anisotropic etching process is used, the presence of the intermediate dielectric layer 226M would obscure the removal of the underlying channel layer 208. In some embodiments, the etching process 280 includes dry chemical etching, which uses a vapor-phase etchant (e.g., HF vapor) to react with the Si in the channel layer 208 and form volatile byproducts. In other embodiments, etching process 280 includes remote plasma etching, which generates reactive free radicals that facilitate selective removal of Si while minimizing damage to surrounding materials. For example, a mixture of CHF3, CF4, and Ar can be used in a remote plasma apparatus to generate an active material that isotropically etches Si. Furthermore, in other embodiments, a wet etching process can be employed to selectively and isotropically remove channel layer 208. For example, a wet etching solution containing potassium hydroxide (KOH) can be used to remove Si. Alternatively, hydrofluoric acid, nitric acid, or acetic acid (HNA) can be used to enhance etching selectivity.

[0040] The removal of sacrificial layer 206 exposes the top and bottom surfaces of channel layers 208U1, 208U2, 208L2, and 208L3, as well as the top surface of channel layer 208U3 and the bottom surface of channel layer 208L1. These exposed surfaces allow etching process 280 to etch channel layer 208 in the thickness direction, requiring significantly less time than etching in the width direction. Therefore, in the XZ plane (FIG. 18A), the end portions of channel layer 208 (labeled 208E) remain intact, effectively blocking the gap between adjacent inner spacer layers 226 and gate spacer 222. These retained end portions protect source / drain features 230 and 248 from exposure. The length of the remaining end portion 208E (along the X direction) varies with the duration of etching process 280. In the embodiment shown in FIG. 18A, the remaining end portion 208E protrudes from the sidewall of inner spacer 226 and extends into CPODE trench 272. Alternatively, the sidewall of end 208E may be flush with the sidewall of the inner spacer 226, or it may be recessed relative to the inner spacer 226 and extend toward the source / drain features 230 and 248.

[0041] As shown in Figure 18B, due to etching process 280, the fin substrate 210B may also experience a reduction in width (along the Y direction) and a partial height depression. For comparison, the dashed line in Figure 18B represents the original outline of the fin substrate 210B before etching process 280. After etching, the width of the top of the fin substrate 210B above the isolation feature 212 (labeled as width W1) is smaller than the width of the bottom below the isolation feature 212 (labeled as width W0) (i.e., width W1 < width W0). Furthermore, compared to other fin substrates 210B, the exposed top height within the CPODE trench 272 is reduced. Similarly, as shown in Figure 18B, and as shown in Figure 18A, the top surface of the fin substrate 210B exposed in the CPODE trench 272 may exhibit a recessed profile, making it lower than the covered portion of the fin substrate 210B.

[0042] Furthermore, as shown in Figure 18B, the intermediate dielectric layer 226M may suffer some etching loss due to non-ideal etching selectivity. Compared to the unexposed intermediate dielectric layer 226M, the exposed intermediate dielectric layer 226M may have rounded corners instead of right angles. The width and thickness of the exposed intermediate dielectric layer 226M may be reduced. For comparison, the dashed lines in Figure 18B represent the original outline of the intermediate dielectric layer 226M before etching process 280. After etching, the reduced width of the intermediate dielectric layer 226M (labeled as width W3) is smaller than its original width (labeled as width W2) (i.e., width W3 < width W2). In addition, the original width W2 can be approximately equal to the width W0 at the bottom of the fin substrate 210B. The reduced width W3 becomes narrower than the width W0, but still wider than the reduced width W1 at the top of the fin substrate 210B (i.e., width W1 < width W3 < width W2 ≈ width W0).

[0043] Figures 19A, 19B, 20A, and 20B illustrate an alternative embodiment for releasing the intermediate dielectric layer 226M in the CPODE trench 272, wherein a first etching process 278' removes the channel layer 208, followed by a second etching process 280' to remove the sacrificial layer 206. Figure 19A shows a cross-sectional view of the workpiece 200 in the XZ plane, and Figure 19B shows a cross-sectional view of the workpiece 200 in the YZ plane, the cross-sections being taken along line BB shown in Figure 19A. In the illustrated embodiment, etching process 278' is an isotropic etching process (e.g., dry chemical etching or wet etching) because if an anisotropic etching process were used, the presence of the intermediate dielectric layer 226M would obscure the removal of the underlying channel layer 208. Due to etching process 278', the fin substrate 210B may also experience a reduction in width (along the Y direction) and partial height recess. Due to less than ideal etching selectivity, the intermediate dielectric layer 226M may experience some etch loss. Compared to an unexposed intermediate dielectric layer 226M, the exposed intermediate dielectric layer 226M may have rounded corners instead of right angles. As shown in Figure 19B, the width and thickness of the exposed intermediate dielectric layer 226M can be reduced. Figure 20A depicts a cross-sectional view of workpiece 200 in the XZ plane, and Figure 20B depicts a cross-sectional view of workpiece 200 in the XZ plane. Figure 20B depicts a cross-sectional view of workpiece 200 in the YZ plane, taken along line BB shown in Figure 20A. In the illustrated embodiment, the etching process 280' is an isotropic etching process (e.g., dry chemical etching or wet etching) because if an anisotropic etching process were used, the presence of the intermediate dielectric layer 226M would obscure the removal of the underlying sacrificial layer 206. Due to non-ideal etch selectivity, the intermediate dielectric layer 226M may suffer further etch losses. As shown in Figure 20B, the width and thickness of the exposed intermediate dielectric layer 226M can be further reduced.

[0044] Figures 21A and 21B illustrate another alternative embodiment for releasing the intermediate dielectric layer 226M in the CPODE trench 272, wherein an etching process 278” removes the channel layer 208 and the sacrificial layer 206 together. In the illustrated embodiment, the etching process 278” is an isotropic etching process (e.g., dry chemical etching or wet etching) because if an anisotropic etching process were used, the presence of the intermediate dielectric layer 226M would obscure the removal of the underlying channel layer 208 and sacrificial layer 206. The etchant selection for the etching process 278” should allow it to simultaneously etch the channel layer 208 and the sacrificial layer 206 at a relatively small etch rate contrast.

[0045] Referring to Figures 2 and 22A-22B, method 100 includes step 136, wherein an isolation structure 282 is formed in the CPODE trench 272. Figure 22A depicts a cross-sectional view of the workpiece 200 in the XZ plane, and Figure 22B depicts a cross-sectional view of the workpiece 200 in the YZ plane, the cross-section being taken along line BB shown in Figure 22A. The isolation structure 282 (also referred to as CPODE feature 282) can be configured as a single-layer or multi-layer structure. In the case of a single-layer structure, the CPODE feature 282 can consist of an oxygen-free dielectric layer. In some embodiments, this oxygen-free dielectric layer can include a nitride material (e.g., silicon nitride or silicon carbonitride) and can be deposited using ALD, CVD, PVD, or other suitable processes. For a multi-layer structure, a dielectric liner (not shown) can be conformally deposited on the sidewalls and bottom surface of the CPODE trench 272 first, and then encapsulated over an intermediate dielectric layer 226M, for example, through an ALD process. In some embodiments, the dielectric pad comprises a nitride material (e.g., silicon nitride or silicon carbonitride) and can be deposited using ALD, CVD, PVD, or other suitable processes. Subsequently, a dielectric layer is deposited in the CPODE trench 272 to fill the trench using ALD, CVD, PVD, or other suitable processes. In some embodiments, this dielectric layer may be an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride or silicon carbonitride) different from the composition of the dielectric pad. The dielectric pad and the dielectric layer together define the CPODE feature 282. After step 136 is completed, a planarization process (e.g., CMP) can be performed to remove excess dielectric material and hard mask layer 260, thereby exposing other dummy gate stacks 214.

[0046] In the embodiment shown in FIG22A, CPODE feature 282 is in direct contact with the sidewalls of the gate spacer 222, the inner isolation layer 226, and the end portion 208E of the removed channel layer 208. Due to the protrusion of the end portion 208E, the sidewalls of CPODE feature 282 have protruding portions that are vertically stacked between adjacent ends 208E. As previously mentioned, in some embodiments, the end portion 208E may be recessed relative to the inner isolation layer 226. In this case, the sidewalls of CPODE feature 282 instead have protruding portions that are vertically stacked between adjacent inner isolation layers 226. Referring also to FIG22B, CPODE feature 282 surrounds the intermediate dielectric layer 226M. In some embodiments, the intermediate dielectric layer 226M and CPODE feature 282 are made of different dielectric materials. In an alternative embodiment, the intermediate dielectric layer 226M and the CPODE feature 282 may share the same dielectric material composition, but the interface between the intermediate dielectric layer 226M and the CPODE feature 282 remains clearly visible.

[0047] In Figure 22B, the top of the fin substrate 210B is higher than the top surface of the isolation feature 212 and extends into the bottom of the CPODE feature 282. Figures 23A and 23B show an alternative embodiment in which the bottom of the CPODE feature 282 extends below the top of the isolation feature 212. Figure 23A depicts a cross-sectional view of the workpiece 200 in the XZ plane, and Figure 23B depicts a cross-sectional view of the workpiece 200 in the YZ plane, which is taken along line BB shown in Figure 23A. In a previous etching process that releases the intermediate dielectric layer 226M from the CPODE trench 272, the fin substrate 210B may have been recessed below the top surface of the isolation feature 212, causing the bottom of the CPODE feature 282 to extend further downward below the top surface of the isolation feature 212. The extended bottom of the CPODE feature 282 may even be below the leakage barrier layer 228, as shown in Figure 23A.

[0048] Referring to Figures 2 and 24A-24B, method 100 includes step 138, wherein a dummy gate stack 214 is replaced with a gate structure 254. Figure 24A depicts a cross-sectional view of workpiece 200 in the XZ plane, and Figure 24B depicts a cross-sectional view of workpiece 200 in the YZ plane, the cross-section being cut along the cutting line BB shown in Figure 24A. The operation at step 138 may include: removing the dummy gate stack 214; releasing the channel layer 208 as channel members (including top channel members 2080U1 and 2080U2 and bottom channel members 2080L1 and 2080L2) and nanostructures (including nanostructures 2080N1 and 2080N2); and forming the gate structure 254 to encapsulate the channel members 2080. The removal of the dummy gate stack 214 may include one or more etching processes selective for the material in the dummy gate stack 214. For example, selective wet etching, selective dry etching, or a combination thereof can be used to remove the dummy gate stack 214. After removing the dummy gate stack 214, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 210C are exposed. The sacrificial layer 206 in the channel region 210C is then selectively removed to release the channel layer 208 as channel members (including top channel members 2080U1 and 2080U2, and bottom channel members 2080L1 and 2080L2) and the nanostructures (including nanostructures 2080N1 and 2080N2). The selective removal of the sacrificial layer 206 can be achieved through selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In other embodiments, selective removal includes SiGe oxidation followed by removal of silicon germanium oxide. For example, oxidation can be performed by ozone cleaning, followed by removal of silicon germanium oxide with an etchant such as NH4OH.

[0049] In the illustrated embodiment, the top channel components 2080U1 and 2080U2 are in direct contact with the top source / drain feature 248; the bottom channel components 2080L1 and 2080L2 are in direct contact with the bottom source / drain feature 230; and the nanostructures 2080N1, 2080N2 and the intermediate dielectric layer 226M are in direct contact with the bottom CESL232.

[0050] After selectively removing the sacrificial layer 206, a gate structure 254 is deposited to encapsulate the top channel members 2080U1 and 2080U2 and the bottom channel members 2080L1 and 2080L2, thereby forming a bottom multi-gate transistor (e.g., 10L in FIG. 1) and a top multi-gate transistor (e.g., 10U in FIG. 1) located above the bottom multi-gate transistor. In the illustrated embodiment, both the bottom and top multi-gate transistors are GAA transistors. In some embodiments, the gate structure 254 may be a shared gate structure to join the bottom and top channel members. In other embodiments shown in the figures, the gate structure 254 includes a bottom gate portion 254B for connecting the bottom channel members 2080L1 and 2080L2, and a top gate portion 254T for connecting the top channel members 2080U1 and 2080U2. The bottom gate portion 254B and the top gate portion 254T have different work function layers. For example, the bottom gate portion 254B may include an n-type work function layer, while the top gate portion 254T may include a p-type work function layer. Although not explicitly shown in the figures, the gate structure 254 includes an interface layer for connecting the channel members. The gate structure 254 also includes a gate dielectric layer 254d located above the interface layer, and work function layers 254e / 254f (e.g., p-type or n-type work function layers). The gate dielectric layer 254d is deposited over the workpiece 200 using ALD, CVD, and / or other suitable methods. The gate dielectric layer 254d is formed of a high-k dielectric material. As described herein, high-k dielectric materials include dielectric materials with a high dielectric constant, for example, a dielectric constant greater than that of thermally heated silicon oxide (~3.9). The dielectric constant of the gate dielectric layer 254d is greater than that of the gate spacer 222. The gate dielectric layer 254d may include hafnium oxide. Alternatively, the gate dielectric layer 254d may include other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), stoichioate (STO), barium titanate (BTO), BaZrO, europium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), europium titanium oxide (HfTiO), (Ba,Sr)TiO (BST), silicon nitride (SiN), silicon nitride oxide (SiON), combinations thereof, or other suitable materials.

[0051] After depositing the gate dielectric layer 254d, an n-type work function layer 254e and a p-type work function layer 254f can be formed above the channel region 210C. The p-type work function layer 254f and the n-type work function layer 254e can be a single-layer structure or a multi-layer structure, for example, various combinations of metal layers with specific work functions (work function metal layers) to enhance device performance. For example, the p-type work function layer 254f may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicon (ZrSi2), molybdenum silicon (MoSi2), tantalum silicon (TaSi2), nickel silicon (NiSi2), other p-type work function materials, or combinations thereof. The n-type work function layer 254e may include titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), other n-type work function materials, or combinations thereof. The gate structure 254 may also include a metal filler to reduce contact resistance. In some cases, the metal filler includes tungsten (W). The gate structure 254 may also include a pad layer, a wetting layer, an adhesive layer, a metal alloy, or a metal silicate. In the illustrated embodiment, the top gate portion 254T also includes a dielectric capping layer 254c formed above the n-type work function layer 254e.

[0052] Referring to Figures 2 and 25A-25B, method 100 includes step 140, in which a further process is performed to form a front-side multilayer interconnect (MLI) structure 288 on the front side of workpiece 200. Figure 25A depicts a cross-sectional view of workpiece 200 in the XZ plane, and Figure 25B depicts a cross-sectional view of workpiece 200 in the YZ plane, taken along line BB shown in Figure 25A. The front-side MLI 288 may include various interconnect structures, such as vias 258v and conductors 258m, which are disposed on dielectric layers 258d (e.g., etch stop layers and ILD layers). In some embodiments, the vias are vertical interconnect structures used to interconnect device-level contacts, such as source / drain contacts 286 formed above the top source / drain structure 248. The source / drain contacts 286 extend through the top ILD layer 252 to electrically couple to the top source / drain structure 248. The conductivity of the source / drain contact 286 is greater than that of the top source / drain structure 248. Before forming the source / drain contact, a metal silicide layer 284 can be formed above the top source / drain structure 248. The metal silicide layer 284 can have a curved profile.

[0053] Referring to Figures 2 and 26A-26B, method 100 includes step 142, in which workpiece 200 is thinned from the back side of workpiece 200 and the fin substrate 210B is replaced with a back-side dielectric layer 290. Figure 26A depicts a cross-sectional view of workpiece 200 in the XZ plane, and Figure 26B depicts a cross-sectional view of workpiece 200 in the YZ plane, which is taken along line BB shown in Figure 26A. In some embodiments, the operation in step 142 thins workpiece 200 from the back side of workpiece 200 until the fin substrate 210B and the isolation feature 212 are exposed from the back side of workpiece 200. The thinning process may include a mechanical polishing process and / or a chemical thinning process. First, in the mechanical polishing process, a large amount of substrate material can be removed from the substrate 202. Then, the chemical thinning process may apply etching chemicals to the back side of substrate 202 to further thin the substrate 202. In the illustrated embodiment, the isolation feature 212 can be used as a thinning stop layer, such that the thinning process stops at the bottom surface of the isolation feature 212.

[0054] Subsequently, in step 142, the fin substrate 210B is selectively etched to form a back trench, and a back dielectric layer 290 is deposited in the back trench. The etching process is adapted to be selective for the semiconductor material (e.g., Si) in the fin substrate 210B and to etch away (or minimally) the back dielectric features. In the embodiment shown in FIG. 22A, the leakage barrier layer 228 is also removed. The back trench exposes the bottom surface of the CPODE feature 282, the gate dielectric layer 254d, the bottom source / drain feature 230, and the bottommost inner spacer 226e. Then, in the operation of step 142, a back dielectric layer 290 with one or more dielectric materials is deposited in the back trench. In some embodiments, the back dielectric layer 290 may include SiOCN, SiOC, SiCN, SiO2, SiC, ZrSi, other suitable materials, or combinations thereof. In some embodiments, the back dielectric layer 290 may comprise a metal oxide or metal nitride, such as La2O3, Al2O3, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, other suitable combinations of materials, or thereof. The back dielectric layer 290 may be formed by PE-CVD, F-CVD, or other suitable methods. The back dielectric layer 290 is in direct contact with the bottom surface of the CPODE feature 282, the gate dielectric layer 254d, the bottom source / drain feature 230, and the bottom inner isolation layer 226e. After depositing the back dielectric layer 290, the back surface of the workpiece 200 is planarized by a planarization process (e.g., CMP) to expose the bottom surface of the isolation feature 212.

[0055] In the illustrated embodiment, the back dielectric layer 290 and the isolation feature 212 comprise different dielectric materials. In some embodiments, the back dielectric layer 290 and the CPODE feature 282 comprise different dielectric materials. In some embodiments, the back dielectric layer 290, the intermediate dielectric layer 226M, and the CPODE feature 282 comprise dielectric material compositions that differ from each other. In some embodiments, the back dielectric layer 290 and the intermediate dielectric layer 226M comprise the same dielectric material, but different from the CPODE feature 282. In some embodiments, the back dielectric layer 290, the intermediate dielectric layer 226M, and the CPODE feature 282 comprise the same dielectric material composition, but the interfaces between the three dielectric features remain distinguishable.

[0056] Referring to Figures 2 and 27A-27B, method 100 includes step 144, in which a further process is performed to form a back-side multilayer interconnect (MLI) structure 294 on the back side of workpiece 200. Figure 27A depicts a cross-sectional view of workpiece 200 in the XZ plane, and Figure 27B depicts a cross-sectional view of workpiece 200 in the YZ plane, the cross-section being cut along the cutting line BB shown in Figure 27A. The back-side MLI 294 may include various interconnect features, such as a back-side via 294v and a back-side conductive line 294m disposed in the back-side dielectric layer 294d. In some embodiments, the back-side via is a vertical interconnect structure for interconnecting the back-side conductive line 294m and the bottom source / drain structure 230. Prior to forming the back-side via 294v, a back-side metallide layer 292 may be formed below the bottom surface of the bottom source / drain structure 230. The back-side metallide layer 292 may have a curved profile. Other processes may also be performed.

[0057] As described above with reference to Figures 23A and 23B, the bottom of CPODE feature 282 may extend downward below the top surface of isolation feature 212. Figures 28A and 28B illustrate such an alternative embodiment at the end of step 144. Figure 28A depicts a cross-sectional view of workpiece 200 in the XZ plane, and Figure 28B depicts a cross-sectional view of workpiece 200 in the YZ plane, taken along line BB shown in Figure 28A. The interface between the bottom surface of CPODE feature 282 and the back dielectric layer 290 may be located below the top surface of isolation feature 212.

[0058] While not intended to limit this disclosure, one or more embodiments of this disclosure provide several advantages for semiconductor devices and their fabrication. For example, this disclosure provides an isolation structure disposed between two complementary field-effect transistors (C-FETs) to achieve electrical isolation. Each C-FET includes top and bottom source / drain features, and dielectric features vertically stacked between them. These dielectric features may include a contact etch-stop layer (CESL) and a bottom interlayer dielectric layer (ILD). An intermediate dielectric layer connects the dielectric features of the two C-FETs, and the isolation structure encloses this intermediate dielectric layer. Forming the isolation structure and enclosing it within the intermediate dielectric layer helps maintain the integrity of adjacent dielectric and semiconductor features during fabrication, thereby improving the overall reliability of the semiconductor device.

[0059] In one exemplary aspect, this disclosure relates to a method. The method includes receiving a workpiece. The workpiece includes a substrate, a fin structure extending longitudinally over the substrate along a first direction, the fin structure including a fin substrate, a bottom semiconductor stack above the fin substrate, an intermediate dielectric layer above the bottom semiconductor stack, and a top semiconductor stack above the intermediate dielectric layer. Both the top and bottom semiconductor stacks include channel layers interleaved by sacrificial layers. The workpiece also includes an isolation feature disposed over the substrate, the top surface of which is non-planar when viewed along the first direction, and the dielectric constant of the isolation feature being between about 3 and about 5; and a dummy gate stack disposed over the fin structure and the isolation feature, the dummy gate stack extending longitudinally along a second direction different from the first direction. The method further includes: recessing a portion of the dummy gate stack to form a trench exposing the fin structure; removing sacrificial layers from the top and bottom semiconductor stacks from the trench; removing channel layers from the top and bottom semiconductor stacks from the trench; and depositing a dielectric feature in the trench surrounding the intermediate dielectric layer. In some embodiments, removing the sacrificial layer includes applying a first isotropic etching process. In some embodiments, removing the channel layer includes applying a second isotropic etching process different from the first isotropic etching process. In some embodiments, recessing a portion of the dummy gate stack includes applying an anisotropic etching process. In some embodiments, the dielectric feature includes a dielectric pad and a dielectric layer located above the dielectric pad. The dielectric pad intersects with and surrounds the intermediate dielectric layer. In some embodiments, the dielectric feature and the intermediate dielectric layer contain different material compositions. In some embodiments, the method further includes etching a finned substrate to form a back trench and depositing a back dielectric layer in the back trench. In some embodiments, the top of the back dielectric layer is embedded in the dielectric feature. In some embodiments, the method further includes replacing the dummy gate stack with a gate structure after depositing the dielectric feature, the gate structure including a gate dielectric layer deposited on the sidewalls of the dielectric feature. In some embodiments, the gate structure includes a bottom gate electrode layer and a top gate electrode layer located above the bottom gate electrode layer, the top gate electrode layer and the bottom gate electrode layer containing different material compositions, and the interface between the top gate electrode layer and the bottom gate electrode layer is located vertically between the top and bottom layers of the intermediate dielectric layer.

[0060] In another exemplary aspect, this disclosure relates to a method. The method includes: forming a fin-like structure protruding from a substrate and extending longitudinally along a first direction, the fin-like structure including a plurality of channel layers alternately arranged by a plurality of sacrificial layers; forming a dummy gate stack over a first region of the fin-like structure, the dummy gate stack extending longitudinally along a second direction different from the first direction; depositing gate spacer layers on the sidewalls of the dummy gate stack; recessing a second region of the fin-like structure to form a first source / drain trench, and recessing a third region of the fin-like structure to form a second source / drain trench; replacing one of the sacrificial layers with an intermediate dielectric layer; depositing a first bottom source / drain feature in the first source / drain trench, depositing a first dielectric layer over the first bottom source / drain feature, and depositing a first top source / drain feature over the first dielectric layer; and depositing a second bottom feature in the second source / drain trench. A source / drain feature is formed, a first dielectric layer is formed above a second bottom source / drain feature, and a second top source / drain feature is formed above the second dielectric layer, wherein an intermediate dielectric layer connects the first and second dielectric layers; a dummy gate stack is removed to form a trench between opposing sidewalls of a gate spacer; a sacrificial layer is removed from the trench to release a channel layer; the channel layer is removed from the trench to release the intermediate dielectric layer; a dielectric feature is deposited in the trench, wherein the dielectric feature surrounds the intermediate dielectric layer; a top dielectric layer is deposited above the second top source / drain feature; a metal silicate layer with a curved profile is formed above the second top source / drain feature; and a source / drain contact extending through the top dielectric layer is formed to electrically couple to the second top source / drain feature through the metal silicate layer. The conductivity of the source / drain contact is greater than the conductivity of the second top source / drain feature. In some embodiments, the intermediate dielectric layer protrudes from the sidewalls of the dielectric feature along a first direction. In some embodiments, removing the sacrificial layer includes a first isotropic etching process, and removing the channel layer includes a second isotropic etching process different from the first isotropic etching process. In some embodiments, removing the dummy gate stack includes an anisotropic etching process. In some embodiments, removing the channel layer reduces the width and height of the fin structure base. In some embodiments, the method further includes replacing the base of the fin structure with a back dielectric layer. In some embodiments, the material composition of one of the sacrificial layers replaced by the intermediate dielectric layer is different from the material composition of the other sacrificial layers.

[0061] In another exemplary aspect, this disclosure relates to a semiconductor device. This semiconductor device includes: a lower source / drain feature; a first plurality of nanostructures coupled to the lower source / drain feature; a first gate structure surrounding each of the first plurality of nanostructures; a lower contact etch stop layer (CESL); and a lower interlayer dielectric (ILD) layer located above the lower source / drain feature. The dielectric constant of the lower CESL is greater than the dielectric constant of the lower ILD layer. This semiconductor device also includes: an upper source / drain feature located above the lower CESL and the lower ILD layer; and an upper CESL and an upper ILD layer located above the upper source / drain feature. The dielectric constant of the upper CESL is greater than the dielectric constant of the upper ILD layer. This semiconductor device also includes: a second plurality of nanostructures coupled to the upper source / drain feature; and a second gate structure surrounding each of the second plurality of nanostructures. The second gate structure includes a gate dielectric layer and a gate electrode layer located above the gate dielectric layer. This semiconductor device also includes a gate spacer extending along the sidewall of the second gate structure. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer. This semiconductor device also includes a dielectric nanostructure extending horizontally from the lower CESL sidewall, and an isolation structure surrounding the dielectric nanostructure. The isolation structure is connected to the sidewalls of the first and second gate structures. In some embodiments, the dielectric nanostructure and the isolation structure comprise different material compositions. In some embodiments, this semiconductor device also includes fin-shaped dielectric features partially embedded in the bottom of the isolation structure.

[0062] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily design or modify other processes and structures based on this disclosure to achieve the same purposes and / or the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations to this disclosure without departing from its spirit and scope.

[0063] 10: Semiconductor Devices (C-FET) 10L: Lower device 10U: Upper device 26'L: Channel layer 26'U: Channel layer 62L: Source / Drain Characteristics 62U: Source / Drain Characteristics 78: Gate dielectric layer 80L: Gate electrode layer 80U: Gate electrode layer 90: Isolation layer 100: Method 102: Steps 104: Steps 106: Steps 108: Steps 110: Steps 112: Steps 114: Steps 116: Steps 118: Steps 120: Steps 122: Steps 124: Steps 126: Steps 128: Steps 130: Steps 132: Steps 134: Steps 136: Steps 138: Steps 140: Steps 142: Steps 144: Steps 200: Workpiece 202:Substrate 204: Superlattice structure 204B: Bottom 204T: Top 206: Sacrifice Layer 206M: Intermediate Sacrificial Layer 206L1: Sacrifice Layer 206L2: Sacrifice Layer 206L3: Sacrifice Layer 206U1: Sacrificial Layer 206U2: Sacrificial Layer 206U3: Sacrificial Layer 208: Channel Layer 2080: Channel component 2080L1: Channel component 2080L2: Channel component 2080N1: Nanostructure 2080N2: Nanostructure 2080U1: Channel component 2080U2: Channel Component 208L1: Channel Layer 208L2: Channel Layer 208L3: Channel Layer 208U1: Channel Layer 208U2: Channel Layer 208U3: Channel Layer 208E: End 210: Fin-like structure 210B: Fin-like base 210C: Passage Area 210SD: Source / Drain Region 212: Separation Feature (STI) 214: Dummy gate stack (dummy gate structure) 216: Dummy Dielectric Layer 218: Virtual gate electrode layer 220: Gate top hard shielding layer 222: Gate spacer 224: Source / Drain Trench (Source / Drain Recess) 225: Inner spacer groove 225M: Gap 226: Internal spacer 226a: Internal spacer 226b: Internal spacer 226c: Internal spacer 226d: Internal spacer 226e: Internal spacer 226M: Intermediate Dielectric Layer 228: Leakage barrier layer 230: Source / Drain Characteristics 232: Contact Etching Stop Layer (CESL) 234: Interlayer dielectric layer (ILD layer) 248: Source / Drain Characteristics (Source / Drain Structure) 250: Contact Etching Stop Layer (CESL) 252: Interlayer dielectric layer (ILD layer) 253: Overlay 254: Gate structure 254B: Bottom Gate Section 254c: Overlay 254d: Dielectric layer 254e: Work Function Layer 254f: Work Function Layer 254T: Top gate section 258d: Dielectric layer 258V: Through-hole 260: Hard mask layer 262: Etching Mask 264: Bottom layer 266: Intermediate layer 268: Intermediate Layer 270: Opening 272: Opening 274: Etching Process 276: Etching Process 278: Etching Process 278': Etching process 278”: Etching process 280: Etching process 280': Etching process 282: Isolation Structure (CPODE Feature) 284: Metal silicide layer 286: Source / Drain Contact 288: Multilayer Interconnect (MLI) 290: Backside dielectric layer 292: Backside metallic silicon layer 294: Backside Multilayer Interconnect (MLI) Structure 294d: Dielectric layer 294v: Through-hole on the back 294m: Backside conductive wire W0: Width W1: Width W2: Width W3: Width AA: Line BB: Line

[0064] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, comprising: receiving a workpiece including: a substrate; a fin structure extending over the substrate along a first direction, the fin structure including a fin substrate, a bottom semiconductor stack above the fin substrate, an intermediate dielectric layer above the bottom semiconductor stack, and a top semiconductor stack above the intermediate dielectric layer, the top semiconductor stack and the bottom semiconductor stack each including a plurality of channel layers staggered by a plurality of sacrificial layers; an isolation feature disposed over the substrate, a top surface of the isolation feature being non-planar when viewed along the first direction, and a dielectric constant of the isolation feature being between about 3 and about 5; and a dummy gate stack disposed over the fin structure and the isolation feature, extending along a second direction different from the first direction; recessing a portion of the dummy gate stack to form a trench exposing the fin structure; and removing the sacrificial layers from the top semiconductor stack and the bottom semiconductor stack from the trench; Remove the channel layers from the top semiconductor stack and the bottom semiconductor stack from the trench; and deposit a dielectric feature in the trench surrounding the intermediate dielectric layer.

2. The method as described in claim 1, wherein, Removing these sacrificial layers involves applying a first isotropic etching process.

3. The method as described in claim 2, wherein, Removing these channel layers includes applying a second isotropic etching process, different from the first isotropic etching process.

4. The method as described in claim 3, wherein, The recessed portion of the dummy gate stack is created by applying an anisotropic etching process.

5. The method as described in claim 1, wherein, The dielectric feature includes a dielectric pad and a dielectric layer above the dielectric pad, wherein the dielectric pad intersects with and encloses the intermediate dielectric layer.

6. A method of forming a semiconductor device, comprising: forming a fin-like structure protruding from a substrate and extending along a first direction, the fin-like structure including a plurality of channel layers arranged alternately by a plurality of sacrificial layers; forming a dummy gate stack over a first region of the fin-like structure, the dummy gate stack extending along a second direction different from the first direction; depositing a plurality of gate spacers on a plurality of sidewalls of the dummy gate stack; recessing a second region of the fin-like structure to form a first source / drain trench, and recessing a third region of the fin-like structure to form a second source / drain trench; replacing one of the sacrificial layers with an intermediate dielectric layer; depositing a first bottom source / drain feature in the first source / drain trench, depositing a first dielectric layer over the first bottom source / drain feature, and depositing a first top source / drain feature over the first dielectric layer; A second bottom source / drain feature is deposited in the second source / drain trench; a second dielectric layer is deposited above the second bottom source / drain feature; and a second top source / drain feature is deposited above the second dielectric layer, wherein the intermediate dielectric layer connects the first dielectric layer and the second dielectric layer; the dummy gate stack is removed to form a trench between the opposing plurality of sidewalls of the gate spacers; the sacrificial layers are removed from the trench to release the channel layers; the channel layers are removed from the trench to release the intermediate dielectric layer; a dielectric feature is deposited in the trench, wherein the dielectric feature covers the intermediate dielectric layer; and a top dielectric layer is deposited above the second top source / drain feature. A metal silicate layer is formed above the second top source / drain feature, wherein the metal silicate layer has a curved profile; and a source / drain contact is formed through the top dielectric layer to electrically couple with the second top source / drain feature through the metal silicate layer, wherein the conductivity of the source / drain contact is greater than the conductivity of the second top source / drain feature.

7. The method as described in claim 6, wherein, Along the first direction, the intermediate dielectric layer protrudes from the plurality of sidewalls of the dielectric feature.

8. The method as described in claim 6, wherein, Removing the sacrificial layers includes a first isotropic etching process, and removing the channel layers includes a second isotropic etching process different from the first isotropic etching process.

9. A semiconductor device comprising: a lower source / drain feature; a plurality of first nanostructures coupled to the lower source / drain feature; a first gate structure surrounding each of the first nanostructures; a lower contact etch stop layer and a lower interlayer dielectric layer located above the lower source / drain feature, wherein a dielectric constant of the lower contact etch stop layer is greater than a dielectric constant of the lower interlayer dielectric layer; an upper source / drain feature located above the lower contact etch stop layer and the lower interlayer dielectric layer; an upper contact etch stop layer and an upper interlayer dielectric layer located above the upper source / drain feature, wherein a dielectric constant of the upper contact etch stop layer is greater than a dielectric constant of the upper interlayer dielectric layer; and a plurality of second nanostructures coupled to the upper source / drain feature. A second gate structure surrounding each of the second plurality of nanostructures, wherein the second gate structure includes a gate dielectric layer and a gate layer located above the gate dielectric layer; a gate spacer extending along a sidewall of the second gate structure, wherein a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the gate spacer; a dielectric nanostructure extending horizontally along a sidewall of the lower contact etch stop layer; and an isolation structure surrounding the dielectric nanostructure, wherein the isolation structure intersects with a plurality of sidewalls of the first gate structure and the second gate structure.

10. The semiconductor device as claimed in claim 9 further includes: a fin-shaped dielectric feature partially embedded in a bottom of the isolation structure.

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