Partial flush method for cache data and electronic device

Abstract

This invention provides a method and electronic device for partially writing back cached data. The method includes: performing a read operation on a cache buffer according to access information to read first cached data from the cache buffer; automatically clearing the first cached data from the cache buffer in response to the read operation; performing a write operation on memory according to access information after performing the read operation; and storing the first cached data in memory while bypassing the cache buffer during the write operation.

Description

[Technical Field]

[0001] This invention relates to a cache management technology, and more particularly to a method and electronic device for partially writing back cached data. [Previous Technology]

[0002] With the advancement of technology, people have increasingly higher performance requirements for electronic devices with computing capabilities. Therefore, to improve data access performance, a common configuration involves additionally configuring a cache buffer between various computing cores such as the Central Processing Unit (CPU) or Graphics Processing Unit (GPU) and main memory (e.g., Random Access Memory, RAM). Compared to main memory, the cache buffer has the advantage of faster access speed. However, the capacity of the cache buffer is often smaller than that of main memory. When fast data access and computation are required, the computing core can improve data access and computation performance by accessing the cache buffer. Furthermore, when storing large amounts of data, the computing core can flush the data cached in the cache buffer (also known as cached data) back to main memory. This achieves a balance between data access efficiency and storage capacity.

[0003] However, in practice, a common problem encountered in using a cache cache combined with main memory access architecture is that when writing cached data back to main memory, most computing cores only support synchronous write-back of all data in the cache cache, and cannot write back only specific data in the cache cache. [Summary of the Invention]

[0004] The present invention provides a method and electronic device for partially writing back cached data, which can perform partial write-back of specific data in the cache buffer.

[0005] Embodiments of the present invention provide a partial write-back method for cached data, which is used in a computing core. The computing core is connected to a cache cache and memory. The partial write-back method for cached data includes: performing a read operation on the cache cache according to access information to read first cached data from the cache cache; automatically clearing the first cached data from the cache cache in response to the read operation; performing a write operation on the memory according to the access information after performing the read operation; and in the write operation, skipping the cache cache and storing the first cached data in the memory.

[0006] An embodiment of the present invention further provides an electronic device, which includes a cache, memory, and a computing core. The computing core is connected to the cache and the memory. The computing core is used to perform a partial write-back method for the cached data.

[0007] Based on the above, after performing a read operation on the cache cache according to the access information to read the first cached data from the cache cache, the first cached data can be automatically cleared from the cache cache in response to the read operation. Then, after performing the read operation, a write operation can be performed on the memory according to the access information. In particular, in the write operation, the first cached data can be stored in the memory without bypassing the cache cache. Thus, the technical effect of partially writing back specific data in the cache cache can be achieved.

Implementation Method

[0009] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0010] As mentioned above, in the prior art, a problem that is easily encountered in the access architecture of using a cache buffer in conjunction with main memory is that when writing back (flush) the cached data in the cache buffer to main memory, most computing cores only support synchronous writing back of all data in the cache buffer, and cannot write back only specific data in the cache buffer.

[0011] The method and electronic device for partial write-back of cached data proposed in this invention can achieve the technical effect of partial flushing of specific data in the cached cache by performing a read operation on the cached cache and then performing a write operation on the memory.

[0012] FIG1 is a schematic diagram of an electronic device according to an embodiment of the present invention. Referring to FIG1, the electronic device 100 may include a smartphone, tablet computer, notebook computer, desktop computer, industrial computer, server, or computer device disposed in any carrier (e.g., vehicle, aircraft, or ship), and the present invention is not limited thereto.

[0013] In one embodiment, the electronic device 100 includes a computing core 11, a cache 12, and memory 13. The computing core 11 can be used to perform tasks such as data processing, information processing, and logical operations. For example, the computing core 11 may include a central processing unit (CPU), a graphics processing unit (GPU), a vision processing unit (VPU), a neural network processing unit (NPU), a tensor processing unit (TPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof. The number of computing cores 11 may be one or more, and the present invention is not limited thereto.

[0014] Both the cache 12 and the memory 13 are connected to the computing core 11 and used to cache data. For example, the cache 12 may include static random access memory (SRAM) or a memory module with similar functions. The memory 13 may include dynamic random access memory (DRAM) or a memory module with similar functions. The number of cache 12 and memory 13 may be one or more, and the present invention is not limited thereto.

[0015] In one embodiment, the computing core 11 and the cache 12 may be disposed on the same chip, while the memory 13 may be disposed outside the chip. In one embodiment, the computing core 11, the cache 12, and the memory 13 may all be disposed on the same chip. In one embodiment, the cache 12 and the memory 13 may be disposed outside the chip where the computing core 11 is located.

[0016] It should be noted that the data access speed of the cache 12 is faster than that of the memory 13. For example, the speed at which the computing core 11 performs data read and write operations on the cache 12 can be higher than the speed at which the computing core 11 performs data read and write operations on the memory 13. However, the capacity of the cache 12 can be smaller than the capacity of the memory 13.

[0017] In one embodiment, the electronic device 100 may further include power management circuitry, communication interface circuitry (e.g., network interface card), mouse, keyboard, screen, speaker and / or microphone, and other various input / output devices or peripheral devices. Furthermore, the types of input / output interfaces and peripheral devices are not limited thereto.

[0018] In one embodiment, the computing core 11 may perform a read operation on the cache buffer 12 according to access information to read specific data (also referred to as first cache data) from the cache buffer 12. For example, before performing the read operation on the cache buffer 12 according to the access information, the computing core 11 may cache the first cache data in the cache buffer 12 in advance and record the access information. Subsequently, the computing core 11 may access the first cache data according to the access information.

[0019] In one embodiment, in response to the read operation, the computing core 11 can automatically clear the first cached data from the cache cache 12. For example, suppose the first cached data originally cached in the cache cache 12 is valid data. In response to the read operation, the computing core 11 can automatically mark the first cached data cached in the cache cache 12 as invalid data. That is, in response to the read operation, the computing core 11 can automatically convert the first cached data cached in the cache cache 12 from valid data to invalid data.

[0020] In one embodiment, if a piece of data is mapped to a logical unit, then this data can be considered valid data. For example, a logical unit may include a Logical Block Address (LBA) or other logical management units. However, if a piece of data is not mapped to any logical unit, then this data can be considered invalid data. In one embodiment, valid data and invalid data can also be classified according to other management rules, and the present invention is not limited thereto.

[0021] In one embodiment, the operation of automatically clearing the first cached data from the cache cache 12 in response to the read operation does not involve clearing other data in the cache cache 12. For example, in one embodiment, it is assumed that the cache cache 12 stores both the first cached data and other data (also referred to as the second cached data). In response to the read operation, only the first cached data is cleared from the cache cache 12 (e.g., marked as invalid data), while the second cached data is not cleared (i.e., the second cached data remains valid data in the cache cache 12).

[0022] In one embodiment, after performing the read operation, the computing core 11 can perform a write operation on the memory 13 according to the access information. Specifically, in the write operation, the computing core 11 can bypass the cache 12 and store (i.e., write back) the first cached data into the memory 13. Alternatively, from another perspective, bypassing the cache 12 and storing the first cached data into the memory 13 means storing (i.e., writing back) the first cached data into the memory 13 (directly) without going through the cache 12 (its cache). Through the combination of the above operations, the technical effect of partially writing back the data (e.g., the first cached data) in the cache 12 to the memory 13 can be achieved.

[0023] In one embodiment, the access information may point to a specific storage area (also referred to as a first storage area) in memory 13. In one embodiment, during the write operation, computing core 11 may bypass cache cache 12 and store (i.e. write back) the first cache data to the first storage area in memory 13.

[0024] In one embodiment, the access information includes address information and data volume information. The address information may reflect the starting address of the first storage area. The data volume information may reflect the capacity of the first storage area. For example, the capacity of the first storage area may be the same as (or greater than) the data volume of the first cached data.

[0025] In one embodiment, before performing the read operation on the cache cache 12 according to the access information, the computing core 11 may pre-cache the first cache data in a specific storage area (also referred to as the second storage area) in the cache cache 12. For example, the capacity of the second storage area may be less than the total capacity of the cache cache 12. In addition, the capacity of the first storage area may be the same as the capacity of the second storage area.

[0026] In one embodiment, the first storage region and the second storage region are associated (e.g., mapped). In one embodiment, the computing core 11 can access (e.g., read or update) the first cached data from the second storage region in the cache cache 12 according to the access information. Alternatively, in one embodiment, after writing the first cached data portion in the cache cache 12 back to the memory 13, the computing core 11 can access (e.g., read or update) the first cached data from the first storage space in the memory 13 according to the access information.

[0027] Figure 2 is a schematic diagram illustrating the caching of first cached data in a cache buffer according to an embodiment of the present invention. Referring to Figure 2, in one embodiment, the computing core 11 can store data D(1) in storage area 22 (i.e., second storage area) in cache buffer 12. It should be noted that after data D(1) is cached in storage area 22, data D(1) cached in storage area 22 can become cached data (i.e., first cached data). At this time, data D(1) is valid data.

[0028] On the other hand, in response to storing data D(1) in storage area 22, computing core 11 may record access information 201. For example, access information 201 may carry information related to the cache location of data D(1). In one embodiment, access information 201 may point to storage area 21 (i.e., the first storage area) in memory 13. There is an association (e.g., a mapping relationship) between storage areas 21 and 22.

[0029] Figures 3 and 4 are schematic diagrams illustrating a partial write-back of the first cache data according to an embodiment of the present invention. Referring to Figure 3, in one embodiment, the computing core 11 may perform a read operation on the cache buffer 12 according to access information 201 (marked as action "1" in Figure 3) to read data D(1) (i.e., the first cache data) from the storage area 22. After reading data D(1) from the storage area 22, the computing core 11 may automatically clear data D(1) from the cache buffer 12 (marked as action "2" in Figure 3). For example, after reading data D(1) from the storage area 22, the computing core 11 may automatically mark the data D(1) still cached in the storage area 22 as invalid data.

[0030] In one embodiment, the read operation in FIG3 for reading data D(1) from cache buffer 12 is also referred to as a last-read operation. For example, this last-read operation may include or trigger actions "1" and "2" in FIG3.

[0031] Referring to FIG4, continuing with the embodiment of FIG3, after performing the read operation on data D(1), the computing core 11 can perform a write operation on memory 13 according to access information 201 (marked as action "3" in FIG4). In particular, in the write operation, the computing core 11 can bypass the cache cache 12 and (directly) store (i.e. write back) data D(1) to storage area 21 in memory 13.

[0032] In one embodiment, the write operation in FIG4 that skips cache buffer 12 and (directly) stores data D(1) into memory 13 is also called a By-Pass-L2 write operation. Here, L2 refers to L2 cache (i.e., cache buffer 12). For example, this By-Pass-L2 write operation may include or trigger action "3" in FIG4.

[0033] In one embodiment, the exemplary operations (e.g., actions "1", "2" and "3") illustrated in Figures 3 and 4 can achieve the technical effect of writing a portion of the data D(1) in the cache 12 back to the memory 13 (while the remaining data in the cache 12 remains in the cache 12 and is not written back to the memory 13). In some cases (e.g., when the remaining data in the cache 12 is still useful and does not want to be written back to the memory 13), the aforementioned operation of writing a portion of the data D(1) in the cache 12 back to the memory 13 can effectively improve the operational flexibility, data access performance and / or computational performance of the computing core 11 (or electronic device 100).

[0034] FIG5 is a schematic diagram illustrating access information according to an embodiment of the present invention. Referring to FIG5, in one embodiment, access information 201 may include address information 501 and data volume information 502. Address information 501 may reflect (e.g., point to) the starting address (i.e., addr) of storage area 21. Data volume information 502 may reflect the capacity (i.e., ΔS) of storage area 21. Thus, access information 201 can define storage area 21 in memory 13. In addition, access information 201 may also carry other useful data or information, which is not limited by the present invention.

[0035] FIG6 is a schematic diagram of virtual code according to an embodiment of the present invention. Referring to FIG6, in one embodiment, the computing core 11 can run virtual code 61 to sequentially execute the read operation marked as action "1", the clear operation marked as action "2", and the store operation marked as action "3" in FIG3 and FIG4. That is, by running virtual code 61, the computing core 11 can write back the first cached data (e.g., data D(1)) in the cache buffer 12 to the memory 13. It should be noted that virtual code 61 is only an example and can be adjusted according to practical needs, and the present invention is not limited thereto.

[0036] FIG7 is a flowchart illustrating a partial write-back method for cached data according to an embodiment of the present invention. Referring to FIG7, in step S701, a read operation is performed on the cache buffer according to access information to read first cached data from the cache buffer. In step S702, in response to the read operation, the first cached data is automatically cleared from the cache buffer. After performing the read operation, in step S703, a write operation is performed on the memory according to the access information. In particular, in step S704, in the write operation, the cache buffer is bypassed and the first cached data is stored in the memory.

[0037] In one embodiment, the access information points to a first storage area in the memory, and in the write operation, the step of skipping the cache and storing the first cached data in the memory includes: skipping the cache and storing the first cached data in the first storage area in the memory.

[0038] In one embodiment, the step of reading the first cached data from the cache cache includes: reading the first cached data from a second storage area in the cache cache, wherein the capacity of the second storage area is less than the total capacity of the cache cache.

[0039] In one embodiment, the step of automatically clearing the first cache data from the cache in response to the read operation does not involve clearing other data in the cache.

[0040] In one embodiment, the step of automatically clearing the first cached data in the cache cache includes: marking the first cached data cached in the cache cache as invalid data.

[0041] In one embodiment, the method for partially writing back cached data further includes: before performing the read operation on the cache buffer according to the access information, caching the first cached data in the cache buffer and recording the access information.

[0042] However, the steps in Figure 7 have been described in detail above, and will not be repeated here. It is worth noting that each step in Figure 7 can be implemented as multiple pieces of code or circuits, and the present invention is not limited thereto. In addition, the method in Figure 7 can be used in conjunction with the above exemplary embodiments, or it can be used alone, and the present invention is not limited thereto.

[0043] In summary, the partial write-back method and electronic device proposed in this invention can achieve the technical effect of partially writing back specific data in the cache by utilizing and combining existing operations of the computing core.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention. [Simplified Explanation of the Diagram]

[0008] FIG1 is a schematic diagram of an electronic device according to an embodiment of the present invention. FIG2 is a schematic diagram of caching first cached data to a cache buffer according to an embodiment of the present invention. FIG3 and FIG4 are schematic diagrams of performing a partial write-back of the first cached data according to an embodiment of the present invention. FIG5 is a schematic diagram of access information according to an embodiment of the present invention. FIG6 is a schematic diagram of virtual code according to an embodiment of the present invention. FIG7 is a flowchart of a partial write-back method of cached data according to an embodiment of the present invention.

Claims

1. A method for partially writing back cached data, used in a computing core, wherein the computing core is connected to a cache cache and memory, and the method for partially writing back cached data includes: A read operation is performed on the cache cache according to access information to read first cached data from a second storage area in the cache cache, wherein the access information points to a first storage area in the memory, and the capacity of the second storage area is less than the total capacity of the cache cache; in response to the read operation, the first cached data is automatically cleared from the cache cache; after performing the read operation, a write operation is performed on the memory according to the access information; and in the write operation, the cache cache is bypassed and the first cached data is stored in the first storage area in the memory.

2. The partial write-back method for cached data as described in claim 1, wherein the access information includes address information and data volume information, the address information reflecting the starting address of the first storage area, and the data volume information reflecting the capacity of the first storage area.

3. The partial write-back method for cached data as described in claim 1, wherein the capacity of the first storage area is the same as the capacity of the second storage area.

4. The partial write-back method for cached data as described in claim 1, wherein the step of automatically clearing the first cached data from the cache in response to the read operation does not involve clearing other data in the cache.

5. The method for partially writing back cached data as described in claim 1, wherein the step of automatically clearing the first cached data in the cache cache includes: The first cached data stored in the cache is marked as invalid data.

6. The method for partially writing back cached data as described in claim 1 further includes: Before performing the read operation on the cache cache based on the access information, the first cache data is cached in the cache cache, and the access information is recorded.

7. An electronic device comprising: Cache cache; Memory; And a computing core connected to the cache and the memory, wherein the computing core is used to execute the partial write-back method of cached data as described in any of requests 1 to 6.

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