Memory device and testing method thereof

Abstract

A memory device and its testing method are disclosed. The memory device includes a memory array, a data terminal, a data selection terminal, a clock terminal, an output circuit, an input circuit, and a comparator circuit. During the write phase of the test operation, the output circuit transmits test data from a first output register to the data terminal based on an output clock signal, and the input circuit writes the test data from the data terminal to the memory array based on a data queue control signal and an input clock signal, thus creating the data under test. During the read phase of the test operation, the memory array temporarily stores the data under test in a second output register, and the comparator circuit compares the test data provided by the first output register with the data under test to generate a comparison signal. The comparison signal is used to determine whether the data access function of the memory device is correct.

Claims

1. A memory device, comprising: Memory array, data terminal, data gate terminal, and clock terminal; Multiple output registers, including a first output register and a second output register, wherein the first output register temporarily stores test data; The output circuit is coupled to the output terminal of the output register and the data terminal. The input circuit is coupled to the data terminal and the input terminal of the output register; A comparison circuit, wherein the first input terminal of the comparison circuit is coupled to the output terminal of the first output register, the second input terminal of the comparison circuit is coupled to the output terminal of the second output register, and the output terminal of the comparison circuit provides a comparison signal; A data gating circuit provides a data queue control signal based on the data gating terminal; The system includes a clock control circuit that provides an output clock signal and an input clock signal based on the clock terminal. During the write-through phase of the test operation, the output circuit transmits the test data from the first output register to the data terminal based on the output clock signal, and the input circuit writes the test data from the data terminal to the memory array based on the data queue control signal and the input clock signal, thus creating test data. During the read-through phase of the test operation, the memory array temporarily stores the test data in the second output register, and the comparison circuit compares the test data provided by the first output register with the test data to generate the comparison signal.

2. The memory device as claimed in claim 1, further comprising: A controller is coupled to the output registers, wherein the controller selects at least one or more of the output registers as the first output register and selects at least another or more of the output registers as the second output register. During the read phase, the memory array is prohibited from temporarily storing the data under test in the first output register.

3. The memory device as claimed in claim 2, wherein, if the number of the first output registers is greater than or equal to 2, the memory device further comprises: A switching circuit is provided, wherein multiple input terminals of the switching circuit are respectively coupled to the output terminals of the first output register, and the output terminal of the switching circuit is coupled to the first input terminal of the comparison circuit. Each of the first output registers includes different test data. The controller provides a selection signal to the switching circuit, and the switching circuit selects one of the test data from the first output registers according to the selection signal, and provides the selected test data to the first input terminal of the comparison circuit.

4. The memory device as claimed in claim 1, wherein the output circuitry includes: Parallel-to-serial circuit converts the test data provided by the first output register from parallel to serial form; And a first output driver, which transmits the test data in serial form to the data terminal.

5. The memory device as claimed in claim 1, wherein the input circuitry includes: The first input buffer buffers the test data from the data terminal. And a serial-to-parallel conversion circuit to convert the test data in serial form into parallel form and transmit the test data in parallel form to the memory array.

6. The memory device as claimed in claim 1, wherein the data gating circuitry includes: The second input buffer is coupled to the data gating terminal to receive the data gating signal; And a data input control circuit, coupled to the second input buffer, receives the data strobe signal through the second input buffer, and generates the data queue control signal based on the data strobe signal.

7. The memory device as claimed in claim 1, wherein the clock control circuitry comprises: A third input buffer is coupled to the clock terminal to receive the clock signal; A clock output control circuit receives the clock signal through the third input buffer and generates the output clock signal based on the clock signal; and a clock input control circuit receives the clock signal through the third input buffer and generates the input clock signal based on the clock signal.

8. The memory device as claimed in claim 1, further comprising: Input / output pads receive the comparison signal, wherein the comparison signal is used to determine whether the data access function of the memory device is correct.

9. A method for testing a memory device, wherein the memory device includes a memory array, a plurality of output registers and a data terminal, the output registers including a first output register and a second output register, the first output register temporarily storing test data, wherein the testing method includes: During the write-through phase of the test operation, the test data is transferred from the first output register to the data terminal based on the output clock signal; During the write-through phase, the test data is written from the data terminal to the memory array based on the data queue control signal and the input clock signal, becoming the data under test; during the read-through phase of the test operation, the memory array temporarily stores the data under test to the second output register; and during the read-through phase, the test data provided by the first output register and the data under test are compared to generate a comparison signal, wherein the comparison signal is used to determine whether the data access function of the memory device is correct.

10. The method for testing a memory device as described in claim 9, wherein when the number of the first output registers is greater than or equal to 2, the method further comprises: During the write-through phase, one of the test data from the first output register is selected based on a selection signal, and the selected test data is provided to the data terminal; and during the read-through phase, one of the test data from the first output register is selected based on the selection signal, and the selected test data is provided to the first input terminal of the comparator circuit, wherein the plurality of input terminals of the switching circuit are respectively coupled to the output terminal of the first output register, and the output terminal of the switching circuit is coupled to the first input terminal of the comparator circuit.

11. The method for testing a memory device as described in claim 9, further comprising: At least one or more of the output registers are selected as the first output register, and at least another or more of the output registers are selected as the second output register; and during the reading phase, the memory array is prohibited from temporarily storing the data under test in the first output register.

Images