Dram structure and method of manufacturing the same

Abstract

A DRAM structure includes a substrate, multiple bit lines, multiple memory node contact windows, multiple dummy contact windows, and at least one pickup contact window. The substrate includes a cell region and a pickup region outside the cell region. The multiple bit lines are disposed on the substrate, wherein each bit line spans the cell region and extends to the pickup region. The multiple memory node contact windows are located on the cell region between the multiple bit lines. The multiple dummy contact windows are located on the pickup region between the multiple bit lines. At least one pickup contact window spans two dummy contact windows and contacts the bit line between them.

Claims

1. A method for manufacturing a DRAM structure, comprising: A substrate is provided, the substrate including a cell region and a pickup region outside the cell region; Multiple bit lines are formed on the substrate, each bit line spanning the cell region and extending to the pickup region; a patterned mask layer covering the multiple bit lines is formed on the substrate, the patterned mask layer having multiple first openings located between the multiple bit lines; multiple storage node contact windows and multiple dummy contact windows are formed in the multiple first openings, wherein the storage node contact windows are located on the cell region and the dummy contact windows are located on the pickup region; a portion of the patterned mask layer between the multiple dummy contact windows on the pickup region is removed to form at least one second opening and expose the top surface of the bit line; and a pickup contact window is formed within the at least one second opening.

2. A method for manufacturing a DRAM structure as described in claim 1, wherein the method for forming the plurality of storage node contact windows and the plurality of dummy contact windows includes: The patterned mask layer is used as an etching mask for etching until the cell region is exposed. Multiple conductor structures are formed in the plurality of first openings; And the multiple conductor structures were etched back.

3. A method for manufacturing a DRAM structure as claimed in claim 1, wherein the method for removing a portion of the patterned mask layer between the plurality of dummy contact windows on the pickup area comprises: A protective layer covering the patterned masking layer is formed on the substrate; An opening corresponding to the at least one second opening is formed in the protective layer, exposing a portion of the patterned mask layer between the plurality of dummy contact windows; the patterned mask layer is etched using the protective layer as an etching mask; and the protective layer is removed.

4. A method for manufacturing a DRAM structure as claimed in claim 1, wherein forming the pickup contact window in the at least one second opening includes forming a connection structure in the plurality of first openings that is connected to the plurality of storage node contact windows.

5. A method of manufacturing a DRAM structure as claimed in claim 4, wherein after forming the pickup contact window within the at least one second opening, the method further comprises: A metal layer is formed, the metal layer including a first connecting portion connected to the pickup contact window and a second connecting portion connected to the connecting structure.

6. A method for manufacturing a DRAM structure, comprising: A substrate is provided, the substrate including a cell region and a pickup region outside the cell region; Multiple bit lines are formed on the substrate, each bit line spanning the cell region and extending to the pickup region; a patterned mask layer covering the multiple bit lines is formed on the substrate, the patterned mask layer having multiple first openings located between the multiple bit lines; multiple conductor structures are formed in the multiple first openings; the patterned mask layer between the multiple conductor structures on the pickup region is removed to form at least one third opening and expose the bit lines; the multiple conductor structures are etched back to form multiple storage node contact windows on the cell region, and multiple dummy contact windows are formed on the pickup region, and at least one fourth opening is formed exposing the multiple dummy contact windows and the top surface of the bit lines; and a pickup contact window is formed in the at least one fourth opening.

7. A method of manufacturing a DRAM structure as claimed in claim 6, wherein the method of removing the patterned mask layer between the plurality of conductor structures on the pickup area comprises: A protective layer covering the patterned masking layer is formed on the substrate; An opening corresponding to the at least one third opening is formed in the protective layer, exposing a portion of the patterned mask layer between the plurality of conductor structures; the patterned mask layer is etched using the protective layer as an etching mask; and the protective layer is removed.

8. A method of manufacturing a DRAM structure as claimed in claim 6, wherein forming the pickup contact window in the at least one fourth opening includes forming a connection structure in the plurality of first openings that is connected to the plurality of storage node contact windows.

9. A method of manufacturing a DRAM structure as claimed in claim 8, wherein after forming the pickup contact window within the at least one fourth opening, the method further comprises: A metal layer is formed, the metal layer including a first connecting portion connected to the pickup contact window and a second connecting portion connected to the connecting structure.

10. A DRAM structure, comprising: The substrate includes the cell region and the pickup region outside the cell region; Multiple bit lines are disposed on the substrate, wherein each bit line spans the cell region and extends to the pickup region; multiple storage node contact windows are located on the cell region between the multiple bit lines; multiple dummy contact windows are located on the pickup region between the multiple bit lines; and at least one pickup contact window spans two of the multiple dummy contact windows and contacts the bit line between the two dummy contact windows.

11. The DRAM structure as claimed in claim 10, wherein, in the top view, the at least one pickup contact window partially overlaps with the two dummy contact windows.

12. The DRAM structure as claimed in claim 10, wherein, in the top view, the at least one pickup contact window completely overlaps with the two dummy contact windows.

13. The DRAM structure as claimed in claim 10, wherein, in the top view, the center line of the at least one pickup contact window is aligned with the center line of the two dummy contact windows.

14. The DRAM structure as described in claim 10, further comprising: The first connecting part is electrically connected to the pickup contact window; And a second connection part, which is electrically connected to the contact window of the storage node.

15. The DRAM structure as claimed in claim 14, wherein the first connection portion and the second connection portion are on the same metal layer.

16. The DRAM structure as described in claim 14, further comprising: A connection structure that connects the storage node contact window to the second connection part.

Images