Complementary field-effect transistor circuit for physically unclonable function technology

Abstract

A CFET transistor circuit for PUF technology includes a PUF device. The PUF device includes a first antifuse element and a second antifuse element. During a registration operation, one of the first and second antifuse elements is in a low-resistance state, and the other is in a high-resistance state. During a read operation, a PUF code is determined based on the storage state of the first antifuse element.

Claims

1. A complementary field-effect transistor circuit for physically non-replicable (PUF) technology, comprising: A first complementary field-effect transistor circuit includes a first element, a second element, and an isolation structure extending in an XY plane; a second complementary field-effect transistor circuit includes a third element, a fourth element, and the isolation structure; a third complementary field-effect transistor circuit includes a fifth element, a sixth element, and the isolation structure; a fourth complementary field-effect transistor circuit includes a seventh element, an eighth element, and the isolation structure, wherein a first physically uncopyable device stores a first physically uncopyable code, including the second element, the fourth element, the sixth element, and the eighth element, and the first physically uncopyable device is located on one side of the isolation structure in the Z direction; and a second physically uncopyable device stores a second physically uncopyable code, including the first element, the third element, the fifth element, and the seventh element formed on a semiconductor substrate, and the second physically uncopyable device is located on the other side of the isolation structure in the Z direction; In the first physically uncopyable device, a first drain / source terminal of the second element is electrically connected to a first word line, and a gate terminal of the second element is electrically connected to a first word line; a first drain / source terminal of the fourth element is electrically coupled to a second drain / source terminal of the second element, and a gate terminal of the fourth element is electrically connected to a first antifuse control line; a first drain / source terminal of the sixth element is electrically connected to a second drain / source terminal of the fourth element, and a gate terminal of the sixth element is electrically connected to a second antifuse control line; and a first drain / source terminal of the eighth element is electrically coupled to a second drain / source terminal of the sixth element, a gate terminal of the eighth element is electrically connected to a second word line, and a second drain / source terminal of the eighth element is electrically connected to a second bit line.

2. The complementary field-effect transistor circuit as claimed in claim 1, wherein in the second physically unreplicable device, a first drain / source terminal of the first element is electrically connected to a third bit line, and a gate terminal of the first element is electrically connected to a third word line; a first drain / source terminal of the third element is electrically coupled to a second drain / source terminal of the first element, and a gate terminal of the third element is electrically connected to a third antifuse control line; a first drain / source terminal of the fifth element is electrically connected to a second drain / source terminal of the third element, and a gate terminal of the fifth element is electrically connected to a fourth antifuse control line; and a first drain / source terminal of the seventh element is electrically coupled to a second drain / source terminal of the fifth element, a gate terminal of the seventh element is electrically connected to a fourth word line, and a second drain / source terminal of the seventh element is electrically connected to a fourth bit line.

3. The complementary field-effect transistor circuit as described in claim 1, wherein the first physically unreplicable device comprises: The second element is a first selection element, including a first drain / source structure, a second drain / source structure, a first nanoline, and a first gate structure; the first gate structure includes a first gate dielectric layer and a first gate layer; the first gate dielectric layer surrounds a middle region of the first nanoline, and the first gate layer surrounds the first gate dielectric layer; the first drain / source structure is electrically contacted to a first side region of the first nanoline, and the second drain / source structure is electrically contacted to a second side region of the first nanoline; and the first drain / source structure is electrically connected to the first word line, and the first gate layer is electrically connected to the first word line; The fourth element is a first antifuse element, including the second drain / source structure, a third drain / source structure, a second nanowire, and a second gate structure; the second gate structure includes a second gate dielectric layer and a second gate layer; the second gate dielectric layer surrounds a middle region of the second nanowire, and the second gate layer surrounds the second gate dielectric layer; the second drain / source structure is electrically contacted to a first side region of the second nanowire, and the third drain / source structure is electrically contacted to a second side region of the second nanowire; and the second gate layer is electrically connected to the first antifuse control line; The sixth element is a second antifuse element, including the third drain / source structure, a fourth drain / source structure, a third nanowire, and a third gate structure; the third gate structure includes a third gate dielectric layer and a third gate layer; the third gate dielectric layer surrounds a middle region of the third nanowire, and the third gate layer surrounds the third gate dielectric layer; the third drain / source structure is electrically contacted to a first side region of the third nanowire, and the fourth drain / source structure is electrically contacted to a second side region of the third nanowire; and the third gate layer is electrically connected to the second antifuse control line; and the eighth element is a The second selectable element includes the fourth drain / source structure, a fifth drain / source structure, a fourth nanoline, and a fourth gate structure; the fourth gate structure includes a fourth gate dielectric layer and a fourth gate layer; the fourth gate dielectric layer surrounds an intermediate region of the fourth nanoline, and the fourth gate layer surrounds the fourth gate dielectric layer; the fourth drain / source structure is electrically contacted to a first side region of the fourth nanoline, and the fifth drain / source structure is electrically contacted to a second side region of the fourth nanoline; and the fifth drain / source structure is electrically connected to the second bit line, and the fourth gate layer is electrically connected to the second word line.

4. The complementary field-effect transistor circuit as described in claim 3, wherein during a registration operation, the first bit line and the second bit line receive a ground voltage, the first word line and the second word line receive an enable voltage, the first antifuse control line and the second antifuse control line receive a registration voltage; the first select element and the second select element are enabled, and the voltage stress on the second gate dielectric layer and the third gate dielectric layer is the registration voltage; and one of the second gate dielectric layer and the third gate dielectric layer breaks to determine the first physically uncopyable code of a bit.

5. A complementary field-effect transistor circuit for physically non-replicable (PUF) technology, comprising: A first complementary field-effect transistor circuit includes a first element, a second element, and an isolation structure; a second complementary field-effect transistor circuit includes a third element, a fourth element, and the isolation structure; wherein a physically uncopyable device stores a physically uncopyable code, including: the first element, the second element, the third element, and the fourth element; wherein the isolation structure extends in an XY plane, the first element and the third element are located on one side of the isolation structure in the Z direction, the second element and the fourth element are located on the other side of the isolation structure in the Z direction, and the first element and the third element are formed above a semiconductor substrate; In this physically uncopyable device, a first drain / source terminal of the first element is electrically connected to a first word line, and a gate terminal of the first element is electrically connected to a first word line; a first drain / source terminal of the third element is electrically coupled to a second drain / source terminal of the first element, and a gate terminal of the third element is electrically connected to a first antifuse control line; a first drain / source terminal of the fourth element is electrically connected to a second drain / source terminal of the third element, and a gate terminal of the fourth element is electrically connected to a second antifuse control line; and a first drain / source terminal of the second element is electrically coupled to a second drain / source terminal of the fourth element, a gate terminal of the second element is electrically connected to a second word line, and a second drain / source terminal of the second element is electrically connected to a second bit line.

6. The complementary field-effect transistor circuit as described in claim 5, wherein the physically unreplicable device comprises: The first element is a first selection element, including a first drain / source structure, a second drain / source structure, a first nanoline, and a first gate structure; the first gate structure includes a first gate dielectric layer and a first gate layer; the first gate dielectric layer surrounds a middle region of the first nanoline, and the first gate layer surrounds the first gate dielectric layer; the first drain / source structure is electrically contacted to a first side region of the first nanoline, and the second drain / source structure is electrically contacted to a second side region of the first nanoline; and the first drain / source structure is electrically connected to the first word line, and the first gate layer is electrically connected to the first word line; The third element is a first antifuse element, including the second drain / source structure, a third drain / source structure, a second nanowire, and a second gate structure; the second gate structure includes a second gate dielectric layer and a second gate layer; the second gate dielectric layer surrounds a middle region of the second nanowire, and the second gate layer surrounds the second gate dielectric layer; the second drain / source structure is electrically contacted to a first side region of the second nanowire, and the third drain / source structure is electrically contacted to a second side region of the second nanowire; and the second gate layer is electrically connected to the first antifuse control line; The fourth element is a second antifuse element, including a fourth drain / source structure, a fifth drain / source structure, a third nanowire, and a third gate structure; the third gate structure includes a third gate dielectric layer and a third gate layer; the third gate dielectric layer surrounds a middle region of the third nanowire, and the third gate layer surrounds the third gate dielectric layer; the fourth drain / source structure is electrically contacted to a first side region of the third nanowire, and the fifth drain / source structure is electrically contacted to a second side region of the third nanowire; and the third gate layer is electrically connected to the second antifuse control line, and the fourth drain / source structure is electrically connected to the third drain / source... The structure; and the second element is a second selection element, including the fifth drain / source structure, a sixth drain / source structure, a fourth nanoline, and a fourth gate structure; the fourth gate structure includes a fourth gate dielectric layer and a fourth gate layer; the fourth gate dielectric layer surrounds an intermediate region of the fourth nanoline, and the fourth gate layer surrounds the fourth gate dielectric layer; the fifth drain / source structure is electrically contacted to a first side region of the fourth nanoline, and the sixth drain / source structure is electrically contacted to a second side region of the fourth nanoline; and the sixth drain / source structure is electrically connected to the second bit line, and the fourth gate layer is electrically connected to the second word line.

7. The complementary field-effect transistor circuit as described in claim 6, wherein the physically unreplicable device further includes a wire electrically connecting the fourth water / source structure and the third water / source structure; or, the fourth water / source structure and the third water / source structure in the physically unreplicable device are a shared water / source structure.

8. The complementary field-effect transistor circuit as described in claim 6, wherein during a registration operation, the first bit line and the second bit line receive a ground voltage, the first word line and the second word line receive an enable voltage, the first antifuse control line and the second antifuse control line receive a registration voltage; the first select element and the second select element are enabled, and the voltage stress on the second gate dielectric layer and the third gate dielectric layer is the registration voltage; and one of the second gate dielectric layer and the third gate dielectric layer breaks to determine the physically uncopyable code of a bit.

9. The complementary field-effect transistor circuit as described in claim 6, further comprising: A third complementary field-effect transistor circuit includes a fifth element, a sixth element, and the isolation structure; wherein, in the physically uncopyable device, a first drain / source terminal of the fifth element is electrically connected to the second drain / source terminal of the third element, a gate terminal of the fifth element is electrically connected to a read word line, and a second drain / source terminal of the fifth element is electrically connected to a read bit line.

10. The complementary field-effect transistor circuit as claimed in claim 9, wherein during a registration operation, the first bit line, the second bit line, and the read bit line receive a ground voltage, the read word line receives a turn-off voltage, the first word line and the second word line receive an turn-on voltage, and the first antifuse control line and the second antifuse control line receive a registration voltage; the fifth element is off, the first select element and the second select element are on, and the voltage stress on the second gate dielectric layer and the third gate dielectric layer is the registration voltage; and one of the second gate dielectric layer and the third gate dielectric layer breaks to determine the physically uncopyable code of a bit.

11. A complementary field-effect transistor circuit for physically non-replicable (PUF) technology, comprising: A first complementary field-effect transistor circuit includes a first element, a second element, and an isolation structure; a second complementary field-effect transistor circuit includes a third element, a fourth element, and the isolation structure; wherein a physically uncopyable device stores a physically uncopyable code, including: the first element, the second element, the third element, and the fourth element; wherein the isolation structure extends in an XY plane, the first element and the third element are located on one side of the isolation structure in the Z direction, the second element and the fourth element are located on the other side of the isolation structure in the Z direction, and the first element and the third element are formed above a semiconductor substrate; In this physically uncopyable device, a first drain / source terminal of the second element is electrically connected to a bit line, and a gate terminal of the second element is electrically connected to a first word line; a first drain / source terminal of the first element is electrically connected to a second drain / source terminal of the second element, and a gate terminal of the first element is electrically connected to a first antifuse control line; a first drain / source terminal of the third element is electrically connected to a second drain / source terminal of the first element, and a gate terminal of the third element is electrically connected to a second antifuse control line; and a first drain / source terminal of the fourth element is electrically connected to a second drain / source terminal of the third element, a gate terminal of the fourth element is electrically connected to a second word line, and a second drain / source terminal of the fourth element is electrically connected to the bit line.

12. The complementary field-effect transistor circuit as described in claim 11, wherein the physically unreplicable device comprises: The second element is a first selection element, including a first drain / source structure, a second drain / source structure, a first nanoline, and a first gate structure; the first gate structure includes a first gate dielectric layer and a first gate layer; the first gate dielectric layer surrounds a middle region of the first nanoline, and the first gate layer surrounds the first gate dielectric layer; the first drain / source structure is electrically contacted to a first side region of the first nanoline, and the second drain / source structure is electrically contacted to a second side region of the first nanoline; and the first drain / source structure is electrically connected to the bit line, and the first gate layer is electrically connected to the first word line; The first element is a first antifuse element, including a third drain / source structure, a fourth drain / source structure, a second nanowire, and a second gate structure; the second gate structure includes a second gate dielectric layer and a second gate layer; the second gate dielectric layer surrounds a middle region of the second nanowire, and the second gate layer surrounds the second gate dielectric layer; the third drain / source structure is electrically contacted to a first side region of the second nanowire, and the fourth drain / source structure is electrically contacted to a second side region of the second nanowire; and the second gate layer is electrically connected to the first antifuse control line, and the third drain / source structure is electrically connected to the second drain / source structure; The third element is a second antifuse element, including the fourth drain / source structure, a fifth drain / source structure, a third nanowire, and a third gate structure; the third gate structure includes a third gate dielectric layer and a third gate layer; the third gate dielectric layer surrounds a middle region of the third nanowire, and the third gate layer surrounds the third gate dielectric layer; the fourth drain / source structure is electrically contacted to a first side region of the third nanowire, and the fifth drain / source structure is electrically contacted to a second side region of the third nanowire; and the third gate layer is electrically connected to the second antifuse control line; and the fourth element is a first The second selector includes a sixth drain / source structure, the first drain / source structure, a fourth nanoline, and a fourth gate structure; the fourth gate structure includes a fourth gate dielectric layer and a fourth gate layer; the fourth gate dielectric layer surrounds an intermediate region of the fourth nanoline, and the fourth gate layer surrounds the fourth gate dielectric layer; the sixth drain / source structure is electrically contacted to a first side region of the fourth nanoline, and the first drain / source structure is electrically contacted to a second side region of the fourth nanoline; and the fourth gate layer is electrically connected to the second word line, and the sixth drain / source structure is electrically connected to the fifth drain / source structure.

13. The complementary field-effect transistor circuit as claimed in claim 12, wherein the physically unreplicable device further includes a first wire electrically connecting the third source structure and the second source structure, and a second wire electrically connecting the sixth source structure and the fifth source structure; or, the third source structure and the second source structure in the physically unreplicable device are a first shared source structure, and the sixth source structure and the fifth source structure are a second shared source structure.

14. The complementary field-effect transistor circuit as claimed in claim 12, wherein during a registration operation, the bit line receives a ground voltage, the first word line and the second word line receive an enable voltage, the first antifuse control line and the second antifuse control line receive a registration voltage; the first select element and the second select element are enabled, and the voltage stress on the second gate dielectric layer and the third gate dielectric layer is the registration voltage; and one of the second gate dielectric layer and the third gate dielectric layer breaks to determine the physically uncopyable code of a bit.

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