Semiconductor device

Abstract

This disclosure provides a semiconductor device. The semiconductor device includes a substrate portion, a circuit portion, a capacitor structure, and a plurality of capacitor electrode structures. The circuit portion is located on the substrate portion. The capacitor structure includes a metal base plate, a metal top plate, and a plurality of capacitor cells. The metal top plate is located on the metal base plate. The plurality of capacitor cells are located between the metal base plate and the metal top plate. The plurality of capacitor electrode structures are located on the metal base plate and the metal top plate, and are coupled to the metal base plate or the metal top plate of the capacitor structure. The plurality of capacitor electrode structures have coplanar contact surfaces.

Description

Technical Field

[0001] This disclosure relates to an interposer structure and its manufacturing method, particularly the disclosed interposer structure having a plurality of three-dimensional (3D) capacitors located in a middle-end-of-line (MOL / MEOL) structure. Prior Technology

[0002] 2.5D assembly is a packaging technology used to include multiple integrated circuit (IC) chips in a single package. This method is typically used in applications with high demands for performance and low power consumption. In the realm of 2.5D assembly, communication between IC chips is achieved via silicon or organic interposers. Currently, driven by the increasing demand for high-performance applications and miniaturization and higher component density, 2.5D packaging technology utilizing silicon interposers is undergoing widespread development. Summary of the Invention

[0003] One embodiment disclosed herein relates to an interposer structure. The interposer structure includes a substrate portion, a circuit portion, an interconnect portion, a through-hole, and a capacitor structure. The circuit portion is disposed on the substrate portion. The interconnect portion is disposed on the circuit portion. The through-hole penetrates both the substrate portion and the circuit portion. The capacitor structure is embedded in the circuit portion. The interconnect portion includes a first metal line electrically coupled to the capacitor structure.

[0004] Another embodiment of this disclosure relates to an interposer structure. The interposer structure includes a plurality of interposer units arranged in an array from a top view. Each of the interposer units includes a first region and a plurality of second regions. The first region has a capacitor structure. Each of the second regions does not have the capacitor structure. The first region surrounds the second regions.

[0005] Another embodiment of this disclosure relates to a method for manufacturing an interposer structure. The method includes the steps of: forming a circuit portion on a front side of a substrate portion; and during the formation of the circuit portion, forming a capacitor structure in the circuit portion. The capacitor structure is formed via a dynamic random access memory process. Simple Explanation of the Diagram

[0006] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. It should be noted that, according to standard industry practice, the various structures are not drawn to scale. In fact, the dimensions of the various structures can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 illustrates a cross-sectional view of an intermediary plate structure according to some embodiments of the present disclosure.

[0008] Figure 2 illustrates a cross-sectional view of a capacitor structure according to some embodiments of this disclosure.

[0009] Figure 3 illustrates a cross-sectional view of a capacitor structure according to some embodiments of this disclosure.

[0010] Figure 4A illustrates a top view of capacitor cells arranged in a rectangular array according to some embodiments of this disclosure. [ ]

[0011] Figure 4B illustrates a top view of capacitor cells arranged in a hexagonal array according to some embodiments of the present disclosure. [ ]

[0012] Figure 5 illustrates a cross-sectional view of a capacitor structure according to some embodiments of this disclosure. [ ]

[0013] Figure 6 illustrates a cross-sectional view of a capacitor structure according to some embodiments of this disclosure. [ ]

[0014] Figure 7 is a top view illustrating the layout of an intermediary plate structure according to some embodiments of the present disclosure. [ ]

[0015] Figure 8A illustrates a cross-sectional view of an encapsulated interposer structure according to some embodiments of this disclosure. [ ]

[0016] Figure 8B illustrates a cross-sectional view of an encapsulated interposer structure according to some embodiments of this disclosure. [ ]

[0017] Figure 9A illustrates a cross-sectional view of an encapsulated interposer structure according to some embodiments of this disclosure. [ ]

[0018] Figure 9B illustrates a cross-sectional view of an encapsulated interposer structure according to some embodiments of this disclosure. [ ]

[0019] Figure 9C illustrates a cross-sectional view of an encapsulated interposer structure according to some embodiments of this disclosure. [ ]

[0020] Figure 9D illustrates a cross-sectional view of an encapsulated interposer structure according to some embodiments of this disclosure. [ ]

[0021] Figures 10A to 10I illustrate cross-sectional views of capacitor structures formed in an interlayer structure according to some embodiments of the present disclosure. [ ]

[0022] Figures 11A to 11H illustrate cross-sectional views of encapsulated intermediate plate structures according to some embodiments of the present disclosure. [ ]

[0023] Figures 12A to 12D illustrate cross-sectional views of encapsulated intermediate plate structures formed according to some embodiments of the present disclosure. [ ] Implementation

[0024] This application claims priority to U.S. Patent Application No. 17 / 085,770, filed October 30, 2020, the entire disclosure of which is incorporated herein by reference. This application also claims priority to U.S. Provisional Patent Application No. 63 / 209,923, filed June 11, 2021, the entire disclosure of which is incorporated herein by reference.

[0025] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the first component is formed above or on the second component, and embodiments may include those where the first and second components are in direct contact, as well as embodiments where an additional component is formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0026] Furthermore, for ease of description, spatial relative terms such as "below," "under," "down," "above," "above," and similar terms may be used in this disclosure to describe the relationship between one element or component and another element(s), as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and these can also be used accordingly to interpret the spatial relative descriptive terms used in this disclosure.

[0027] When terms such as "first," "second," and "third" are used in this disclosure to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, area, layer, or segment from another. Unless clearly indicated by the context, terms such as "first," "second," and "third," when used in this disclosure, do not imply a sequence or order.

[0028] Figure 1 illustrates an interposer structure comprising a plurality of 3D capacitors embedded within a MOL / MOEL structure. As shown, the interposer structure 10 includes a substrate portion 100 having a front side 100A and a back side 100B opposite to the front side 100A. The interposer structure 10 further includes a circuit portion 102 located on the front side 100A of the substrate portion 100.

[0029] In some embodiments, substrate portion 100 is a semiconductor wafer used to house a semiconductor device assembly. In some embodiments, substrate portion 100 is an insulating substrate used to minimize parasitic resistance and inductance. In some embodiments, substrate portion 100 is made of silicon or glass. In some embodiments, substrate portion 100 includes active or passive device assemblies, for example, the device assembly may include a memory structure or a power regulator.

[0030] Existing capacitor structures can be formed on a substrate portion of an interposer structure, wherein a plurality of trenches can be formed on the substrate portion 100. Each trench (or so-called deep trench) can have a depth between about 10 micrometers and about 30 micrometers, or between about 20 micrometers and about 30 micrometers. However, the depth of the trench weakens the mechanical strength of the substrate portion of the interposer structure to some extent. On the other hand, compared to examples where the material is semiconductor, forming deep trenches is less economically efficient when the substrate portion is made of insulating material, and therefore not attractive.

[0031] Therefore, in one aspect of this disclosure, the aim is to change the structure of the layer above the substrate portion 100 of the interposer structure 10 to solve the problems caused by the existing deep trench capacitor structure and to effectively utilize the space in the interposer structure 10. Referring again to FIG1, the line portion 102 is located on the front side 100A of the substrate portion 100. The line portion 102 is a structure formed "before" a first metal layer (M1) is formed in a semiconductor structure; that is, the line portion 102 is referred to as a mid-process (MOL / MEOL) structure, which is formed earlier than the back-end-of-line (BEOL) structure. In some embodiments, the line portion 102 is made of a dielectric material, which may be referred to as a pre-metal dielectric (PMD). In other words, the line portion 102 can be distinguished from the substrate portion 100 below and the BEOL structure above it by different process parameters such as the choice of base material and the choice of metal. For example, the material of the circuit portion 102 may be a low-k dielectric material, that is, a material with a lower dielectric constant than silicon dioxide; similarly, the metal used for electrical connections in the circuit portion 102 is typically tungsten, while the metal typically used in a BEOL structure is copper. These are some exemplary methods for distinguishing the stacked layers in the interposer structure 10, but the embodiments disclosed herein are not limited to these examples.

[0032] In some embodiments, a plurality of capacitor structures 106 are embedded in the line portion 102. In some embodiments, the capacitor structure 106 may be a 3D metal-insulator-metal (MIM) capacitor; this non-planar structure can be used to increase the effective MIM area and the corresponding capacitance density. In some embodiments, the capacitor structure disclosed herein may have a very high density, for example, higher than about 1 microfarad / square millimeter (μF / mm²). In some embodiments, the 3D capacitor may be a cylindrical capacitor.

[0033] As shown in Figure 2, in some embodiments, each capacitor structure includes a metal base plate 108, a metal top plate 110 located on the metal base plate 108, and a plurality of capacitor cells 112 formed between the metal base plate 108 and the metal top plate 110. In some embodiments, a spacing D1 between the metal base plate 108 and the metal top plate 110 is between about 1 micrometer and about 2 micrometers, which is much thinner than the aforementioned examples of active or passive device components formed in deep trenches in the substrate portion 100.

[0034] The capacitor unit 112 can be configured as either a crown-type capacitor structure or a concave-type capacitor structure. As shown in FIG2, in an embodiment where each capacitor unit 112 is crown-shaped, the capacitor unit 112 includes a first conductive film 114 and a second conductive film 116 stacked between a metal base plate 108 and a metal top plate 110. In some embodiments, the first conductive film 114 includes a first portion 114A connected to the metal base plate 108, and a second portion 114B connected to the first portion 114A and extending from the metal base plate 108 to the metal top plate 110. In some embodiments, the second conductive film 116 is disposed adjacent to the first conductive film 114 and connected to the metal top plate 110, and extends from the metal top plate 110 to the metal base plate 108. In some embodiments, the second conductive film 116 is perpendicularly intersected with the second portion 114B of the first conductive film 114. For example, as shown in the cross-sectional view, the second conductive film 116 is disposed adjacent to the inner and outer sides of an accommodating space 104. This accommodating space 104 is surrounded by the first conductive film 114.

[0035] Furthermore, the capacitor unit 112 also includes a first insulating film 128, which is used to isolate the first conductive film 114 and the second conductive film 116. For example, the second conductive film 116 and the second portion 114B of the first conductive film 114 are isolated by the first insulating film 128 along a first direction (vertical direction). In other words, the MIM feature of the capacitor structure 106 is achieved by stacking the first conductive film 114, the first insulating film 128, and the second conductive film 116. As shown in FIG2, in some embodiments, a second insulating film 130 may be selectively used to fill the space between the second conductive film 116 and the metal top plate 110. In some embodiments, the first insulating film 128 and the second insulating film 130 are made of a high-k dielectric material. For example, the high-k dielectric material may include at least one oxide of metals such as lanthanum (La), hafnium (Hf), and zirconium (Zr).

[0036] As shown in Figure 3, in other embodiments, the capacitor cell 112 is formed in a concave shape. This capacitor cell 112 also includes a first conductive film 114 and a second conductive film 116 stacked between a metal base plate 108 and a metal top plate 110. In these embodiments, the second conductive film 116 is formed adjacent to the first conductive film 114 and connected to the metal top plate 110, and extends from the metal top plate 110 to the metal base plate 108. Compared to the crown shape shown in Figure 2, in the embodiment shown in Figure 3, the second conductive film 116 in each concave capacitor cell 112 is laterally surrounded by the second portion 114B of the first conductive film 114, rather than being completely adjacent to the inner and outer sides of the accommodating space 104 surrounded by the first conductive film 114.

[0037] Figures 4A and 4B are top views of a plurality of capacitor cells 112 (concave) according to some embodiments of the present disclosure. As shown in Figure 4A, in some embodiments, the plurality of capacitor cells 112 may be arranged in a rectangular array from a top view between the metal plates of the capacitor (i.e., the metal base plate 108 and metal top plate 110 shown in Figures 2 and 3). Alternatively, in other embodiments, as shown in Figure 4B, the capacitor cells 112 may be arranged in a hexagonal array from a top view between the metal plates of the capacitor. Generally, a hexagonal array arrangement can provide a higher density cluster of capacitor cells 112. The arrangement of the capacitor cells 112 of the present disclosure is not limited to the embodiments of Figures 4A and 4B, as the capacitor cells 112 can be arranged in any symmetrical shape as needed.

[0038] As shown in the embodiments of Figures 1 to 3 above, the capacitor structure 106 embedded in the circuit portion 102 is on the metal base plate 108 and the metal top plate 110, and does not have a direct metal contact with the metal base plate 108 and the metal top plate 110. If the intermediate plate structure 10 is provided to a downstream manufacturer for further processing, for example, forming an interconnect portion on the circuit portion 102 (which will be discussed later), then it is actually quite difficult to perfectly place the metal contact on the surfaces of the metal base plate 108 and the metal top plate 110.

[0039] Specifically, referring to the embodiment shown in Figure 5, the intermediate plate structure 10 may further include a first metal contact 118 and a second metal contact 120. The first metal contact 118 rests directly on the top surface of the metal top plate 110, and the second metal contact 120 rests directly on an uncovered area 122 of the metal bottom plate 108 that is not covered by the metal top plate 110. In this embodiment, the first metal contact 118 and the second metal contact 120 have different vertical lengths. For example, along the vertical direction, the first metal contact 118 has a first length that is substantially equal to the distance D3, and the second metal contact 120 has a second length that is substantially equal to the distance D2, the second length being greater than the first length.

[0040] The difference in spacing between the metal base plate 108 and the metal top plate 110 and the top surface of the wiring section 102 (i.e., the difference between spacings D2 and D3) can lead to relatively complex landings of the first and second metal contacts 118 and 120. In particular, as mentioned earlier, downstream manufacturers must accurately locate the uncovered area 122 of the metal base plate 108 that is not covered by the metal top plate 110. However, the area of ​​this uncovered area 122 is much smaller than the area of ​​the top surface of the top metal plate 110. Therefore, the positioning operation may fail, and unwanted misalignment of the metal contacts may occur.

[0041] Therefore, in other embodiments, the intermediate plate structure 10 provided in this disclosure may further include a plurality of capacitor electrode structures 124 located on the metal base plate 108 and the metal top plate 110. As shown in FIG6, the intermediate plate structure 10 may include a first capacitor electrode structure 124A contacting the uncovered area 122 of the metal base plate 108, and a second capacitor electrode structure 124B contacting the top surface of the metal top plate 110. In these embodiments, the first capacitor electrode structure 124A and the second capacitor electrode structure 124B may provide a coplanar contact surface 126 on the capacitor structure 106 for allowing the metal contacts to contact and settle. That is, in these embodiments, the vertical lengths of the first metal contact 118 and the second metal contact 120 are substantially the same. In some embodiments, each first capacitor electrode structure 124A or each second capacitor electrode structure 124B includes a combination consisting of a capacitor contact and a capacitor pad. In some embodiments, the height of the first capacitor electrode structure 124A is greater than the height of the second capacitor electrode structure 124B.

[0042] On the other hand, the first capacitor electrode structure 124A may have a top area larger than the area of ​​the uncovered region 122 of the metal base plate 108. Therefore, compared to being located in the uncovered region 122, the first metal contact 118 can be more easily located in the first capacitor electrode structure 124A, and the product yield can be improved.

[0043] In some implementations, in addition to the capacitor structure 106, the interposer structure 10 may further include a memory structure within the circuit portion 102. Since both the capacitor structure 106 and the memory structure can be formed using a compatible Dynamic Random Access Memory (DRAM) process, this means that the capacitor structure 106 and the memory structure can be formed using semiconductor processes compatible with common DRAM manufacturing processes, thereby achieving high density, thinner thickness, and lower cost. In common DRAM semiconductor process technologies, capacitors can be formed without utilizing structures formed under the silicon substrate surface (such as deep trench capacitors), and this is also very suitable for reducing the vertical dimensions of capacitor devices. Furthermore, by adopting common DRAM semiconductor process technologies, process development costs can also be reduced. The memory structure formed in the circuit portion 102 can be used as a cache for the die disposed above the interposer structure 10.

[0044] Figure 7 is a top view of the layout of an interposer structure 10 according to some embodiments of the present disclosure. In the embodiment shown in Figure 7, the interposer structure 10 includes a plurality of interposer units 20 arranged in an array in a top view. Each interposer unit 20 includes a first region 202 and a plurality of second regions 204. In some embodiments, the first region 202 may have a mesh feature in a top view because the second regions 204 are substantially the same shape. The second regions 204 are arranged in an array or distributed in a periodic manner among the interposer units 20. In some embodiments, the first region 202 surrounds each second region 204. In some embodiments, the interposer structure 10 exists in the form of a semiconductor wafer carrying a plurality of interposer units 20 as shown in Figure 7.

[0045] The first region 202 of the interposer unit 20 is used to accommodate the capacitor structure 106, while each second region 204 is reserved for forming a through-via, such as a through silicon via (TSV). That is, each second region 204 is used to accommodate a through-via that penetrates the interposer structure. Since only a portion of the region (i.e., the second region 204) is reserved for forming a TSV, the remainder of the interposer unit 20 can be filled with 3D capacitors to effectively utilize the space of the circuit portion 102 (i.e., the MOL / MOEL structure) of the interposer unit 20. In some embodiments, the capacitor structure 106 may cover more than half of the interposer structure 10 at an upward viewing angle. In some embodiments, the area ratio of the first region 202 to one of the interposer units 20 is greater than 50%. In some embodiments, the area ratio of the first region 202 to one of the interposer units 20 is between about 50% and about 80%.

[0046] In some embodiments, the pitch P between adjacent second regions 204 is less than about 100 micrometers. In some embodiments, the length L of one side of one of the interposer units 20 is between about 0.5 mm and 1 mm. Furthermore, as shown in FIG7, adjacent interposer units 20 are separated by cleaving grooves 206. Cleaving grooves 206 allow any number of interposer units 20 to be divided into different groups by cutting along suitable cleaving grooves 206. For example, 2x2 interposer units 20 can be used for bonding with a first type of semiconductor die or die stack by cutting, and 4x4 interposer units 20 can be used for bonding with a second type of semiconductor die or die stack by cutting. The array arrangement of interposer units 20 can provide modular product geometries to suit various types of interposer applications. The width of the cleaving grooves 206 is sufficient to allow the interposer structure to be cut into multiple block units, each block unit containing one or more interposer units 20. Multiple interposer cells 20 within a single block cell can be arranged in a row or an array. The size of the block cell depends on the size and number of IC dies to be bonded to the single block cell. In other words, because the size of the interposer structure is highly relevant to the purpose of 2.5D packaging technology, IC packaging manufacturers can flexibly use the disclosed interposer structure 10 to cut it to an ideal size that meets their IC packaging requirements.

[0047] Referring to Figure 8A, in the case where the interposer structure has been applied to a semiconductor structure after packaging technology, the interposer structure 30 may include an interconnect portion 300 on the circuit portion 102. Herein, the capacitor structure 106 is located between the substrate portion 100 and the interconnect portion 300 of the interposer structure 30 in cross-sectional view. Typically, the interconnect portion 300 is used to bond to one or more semiconductor dies 80 on the interposer structure 30, while the substrate portion 100 is used to bond to a packaging substrate 90 under the interposer structure 30. The semiconductor dies 80 on the interposer structure 30 have a critical size smaller than a critical size of the interposer structure 30. In some embodiments, the interconnect portion 300 is referred to as a BEOL structure on a MOL / MEOL structure, therefore the interconnect portion 300 includes a first metal layer 302 that is in direct contact with the top surface of the circuit portion 102. In addition to the first metal layer (M1) 302, the interconnect portion 300 may also include more metal layers, such as M2, M3, etc. These metal layers or metal tiers can be electrically coupled via metal vias, and the uppermost metal layer can provide bonding points for connection to the wafer / die to be packaged. In one embodiment, a plurality of metal lines are formed within the interconnect portion 300, wherein each metal line may be composed of metal vias and one or more metal layers (i.e., M1, M2, M3, etc.), and the arrangement of the metal lines can be used to determine the connection between the semiconductor die 80 and the package substrate 90.

[0048] Additionally, as shown in Figure 8A, the interposer structure 30 may include one or more through-holes 304, or referred to as through-silicon vias (TSVs), which penetrate the substrate portion 100 and the circuit portion 102 to electrically couple the semiconductor die 80 and the package substrate 90. The TSVs 304 and capacitor structures 106 are interleaved within the circuit portion 102. As previously shown and explained in Figure 7, each second region 204 is reserved to form a TSV therein; therefore, the capacitor structures 106 embedded in the circuit portion 102 do not interfere with the circuit arrangement in the interposer structure 30.

[0049] Referring again to FIG8A, the first metal layer 302 is electrically coupled not only to TSV 304, but also to capacitor structure 106. In some embodiments, capacitor structure 106 may be electrically coupled to the first metal layer 302 via first metal contact 118 and second metal contact 120 (as shown in FIG5) on metal top plate 110 and metal bottom plate 108, respectively. In the embodiment shown in FIG8A, the vertical lengths of first metal contact 118 and second metal contact 120 are different because no capacitor electrode structure is pre-formed in the line portion 102 to provide a flat contact surface for first metal contact 118 and second metal contact 120.

[0050] In contrast, referring to other embodiments shown in FIG8B, the capacitor electrode structure 124 is formed in the circuit portion 102 to reduce the difficulty of the first metal contact 118 and the second metal contact 120 falling on the capacitor structure 106. Details of the capacitor electrode structure 124 can be found in the description above in FIG6, which is omitted here for the sake of brevity and will not be repeated.

[0051] As shown in Figures 8A and 8B, the interconnect portion 300 can be electrically connected to the semiconductor die 80 on the interposer structure 30 via a first conductive terminal 306. The first conductive terminal 306 may include a plurality of conductive pillars (e.g., copper pillars) or other suitable bump connection forms, wherein the first conductive terminal 306 may be surrounded by a suitable protective or passivating material (not shown). In other embodiments, a hybrid bonding structure may be implemented to electrically connect the interconnect portion 300 and the semiconductor die 80. On the opposing surfaces of the interposer structure 30, a second conductive terminal 308 may be implemented between the package substrate 90 and the substrate portion 100 of the interposer structure 30. In some embodiments, the second conductive terminal 308 may include C4 bumps, solder balls, or similar structures. In some embodiments, the semiconductor die 80 may include a system-on-a-chip (SOC), high bandwidth memory (HBM), logic die, memory die, graphics processing unit (GPU), central processing unit (CPU), or similar components. In some embodiments, the semiconductor die 80 may be replaced by a chiplet. In some embodiments, an interconnect portion (not shown) of the semiconductor die 80 has a line size smaller than a line size of the interconnect portion 300 of the interposer structure 30.

[0052] As shown in FIG9A, in some embodiments, the interconnect portion 300 includes a first metal line 316. The first metal line 316 includes a portion of the first metal layer 302, and the first metal line 316 is electrically coupled to the capacitor structure 106. In some embodiments, the first metal line 316 is disposed on the TSV 304, and the first metal line 316 is electrically coupled to the TSV 304 and the capacitor structure 106.

[0053] In some embodiments, a first semiconductor die 81 and a second semiconductor die 82 may be bonded to the interposer structure 30. In some embodiments, the first semiconductor structure 81 is the same as the second semiconductor die 82. In other embodiments, the first semiconductor structure 81 is different from the second semiconductor die 82. The first semiconductor die 81 may be electrically coupled to the second semiconductor die 82 via an interconnect portion 300. As shown in FIG9A, in some embodiments, the interconnect portion 300 includes a second metal line 318 located in the interconnect portion 300, and the second metal line 318 is electrically connected to the first semiconductor die 81 and the second semiconductor die 82. In some embodiments, a portion of the second metal line 318 may include a portion of the first metal layer 302, such as the second metal line 318b shown in the figure. In other examples, some second metal lines 318a may be entirely located on the first metal line 302. In some embodiments, the second metal line 318 is disconnected from the first metal line 316 or TSV 304. In other words, the second metal line 318 is used to transmit electrical signals between the first semiconductor die 81 and the second semiconductor die 82, without needing to detour to the TSV 304 or the capacitor structure 106. As shown in FIG9A, the portion of the line portion 102 located directly below the second metal line 318 does not have the capacitor structure 106. The staggered arrangement of the second metal line 318 and the capacitor structure 106 can reduce the interference caused by the capacitor structure 106 in the lower layer to the signals in the second metal line 318. However, this is not a limitation of the embodiment. When the requirement for interference of the capacitor structure 106 in the lower layer to the signals in the second metal line 318 is relatively relaxed, the capacitor structure 106 in the line portion 102 can also be formed directly below the second metal line 318.

[0054] As shown in Figure 9B, in some embodiments, the TSV 304 can penetrate the substrate portion 100, the circuit portion 102, and the interconnect portion 300, and the TSV 304 is disconnected from the first metal circuit 316 and the second metal circuit 318. In these embodiments, the TSV 304 is formed after the interconnect portion 300 is formed on the circuit portion 102. The top surfaces of the first metal circuit 316, the second metal circuit 318, and the TSV 304 are all aligned with the top surface of the interconnect portion 300. In addition, in these embodiments, the first metal layer 302 is not located on the TSV 304, therefore the TSV 304 is disconnected from the first metal layer 302.

[0055] Figures 9A and 9B illustrate the features of various metal circuits designed specifically for signal transmission, and extended vias that allow for high-speed signal transmission while disconnecting from other circuits. In some embodiments, as shown in Figures 9C and 9D, a capacitor structure 106 with capacitor electrode structure 124 can be applied to the architecture shown in Figures 9A and 9B. A detailed description of the capacitor structure 106 with capacitor electrode structure 124 can be found in Figures 6 and 8B, and is omitted here for brevity.

[0056] When manufacturing the interposer structure 10 shown in FIG1, particularly regarding the operation of forming the capacitor structure 106 in the circuit portion 102, reference can be made to FIG10A to 10I. As shown in FIG10A, a semiconductor substrate or a glass substrate may be received as a substrate portion 100, and the front side 100A of the substrate portion 100 is covered by a first PMD layer 400, and a metal base plate 108 is formed on the first PMD layer 400. The first PMD layer 400 may contain a low-k dielectric material.

[0057] As shown in Figure 10B, a plurality of metal substrates can be formed on the top surface of the metal substrate 108 via deposition and patterning operations. These metal substrates are equivalent to the first portion 114A of the first conductive film 114 previously shown in Figure 6. The first portion 114A can elevate the second portion 114B of the subsequently formed first conductive film 114 to space the second portion 114B from the metal substrate 108, and thus the bottom of the second portion 114B of the first conductive film 114 can be laterally aligned with the bottom of the subsequently formed second conductive film 116.

[0058] Referring to Figure 10C, a first nitride film 402, a second PMD layer 404, and a second nitride film 406 are sequentially formed on the metal substrate 108. The formation of the second nitride film 406 is to prevent the crown capacitor structure from collapsing during subsequent operations. Next, referring to Figure 10D, the stack of the first nitride film 402, the second PMD layer 404, and the second nitride film 406 is patterned to form an opening 408, thereby exposing the top surface of the first portion 114A. Then, referring to Figure 10E, a conductive layer 410 is formed on the second nitride film 406, covering the outline of the opening 408. The conductive layer 410 is used to form the second portion 114B of the first conductive film 114.

[0059] Referring to FIG10F, conductive layer 410 is patterned to remove a portion of the top of conductive layer 410. The patterning in this operation determines the type of capacitor structure. For example, the embodiment shown in FIG10F can be used to form a crown-shaped capacitor structure 106 because there is an etched opening 414 between the vertical portions of conductive layer 410; however, in other embodiments, since a small portion of the second PMD layer 404 between the vertical portions of conductive layer 410 is not removed, a concave capacitor structure 106 can be formed without the opening 414. This disclosure uses an embodiment of forming a crown-shaped capacitor structure 106 as an example. In fact, the operation of forming other concave capacitor structures 106 is substantially the same as that of forming a crown-shaped capacitor structure 106, and is omitted here for simplicity and will not be described further.

[0060] Subsequently, as shown in Figure 10G, an insulating film 416 is formed on the conductive layer 410. The insulating film 416 may contain a high-k dielectric material, such as oxides of metals like lanthanum, hafnium, and zirconium. Referring to Figure 10H, another conductive layer 412 is formed on the insulating film 416. The conductive layer 412 is substantially the same as the second conductive film 416, adjacent to the first conductive film 114 and connected to the metal top plate 110, and extends from the metal top plate 110 to the metal bottom plate 108. Therefore, by successively stacking the conductive layer 410, the insulating film 416, and the conductive layer 412, and performing a planarization operation, a MIM capacitor structure, as illustrated in Figure 10I, can be achieved.

[0061] In some embodiments, prior to the operation of covering the capacitor structure 106 with PMD material to embed the capacitor structure 106 in the circuit portion 102, a plurality of capacitor electrode structures 124 may be formed on the capacitor structure 106 so that metal contacts formed in subsequent operations can rest thereon. In other embodiments without capacitor electrode structures, PMD material may be formed on the capacitor structure 106 to embed the capacitor structure 106 in the circuit portion 102.

[0062] When manufacturing the interposer structure 30, as shown in Figures 8A, 8B, 9A, and 9C, which encapsulates semiconductor dies 80 (or first and second semiconductor dies 81, 82) and a packaging substrate 90, the operation can be referred to the embodiments disclosed in Figures 11A to 11H. As shown in Figures 11A to 11C, the interposer structure 30 is received after the circuit portion 102 is formed on the front side 100A of the substrate portion 100, and the capacitor structure 106 is formed in the circuit portion 102 during the formation of the circuit portion 102. A photoresist layer 50 may be disposed on the circuit portion 102. A trench 502 may be formed by performing a TSV etching operation. As shown, the trench 502 penetrates the circuit portion 102 and extends toward the substrate portion 100. The trench 502 is positioned to bypass the capacitor structure 106, so that the subsequently formed vias do not overlap with the capacitor structure 106. The trench 502 may then be filled by a via-fill operation. In some embodiments, an oxide pad 504 may be formed in the trench 502 before a conductive material such as copper is formed and filled into the trench 502. One end of the TSV 304 will be exposed after the substrate portion 100 is thinned by polishing or grinding operations from its back side 100B.

[0063] After the via filling operation, a chemical mechanical polishing (CMP) operation can be performed on the top surface of the circuit portion 102 to form a flat surface before the interconnect portion 300 is formed on the circuit portion 102. Furthermore, since the capacitor structure 106 embedded in the circuit portion 102 must also be electrically connected, a first metal contact 118 and a second metal contact 120 can be formed on the capacitor structure 106 by performing at least one via etching operation and one via filling operation. The aforementioned CMP operation can be performed after the TSV 304, the first metal contact 118, and the second metal contact 120 have been formed.

[0064] Referring to Figure 11D, interconnect portions 300 are sequentially formed on line portions 102. The formation of interconnect portions 300 may include a plurality of interlayer dielectric (ILD) layers, metal layers, and metal vias formed via a BEOL process. The first metal layer 302 in interconnect portion 300 may be electrically coupled to TSV 304 and capacitor structure 106 via a BEOL process.

[0065] Next, referring to FIG11E, a bumping operation can be performed on the top surface of the interconnect portion 300 to form a first conductive terminal 306. In some embodiments, the first conductive terminal 306 may include a plurality of conductive pillars (e.g., copper pillars), or other suitable bump connection structure forms. In some embodiments, the first conductive terminal 306 further includes an under bump metallization (UBM) 310 located under the bump connection structure. By utilizing the first conductive terminal 306, the TSV 304 and the capacitor structure 106 are incorporated into the conductive path extending to the front side 30A of the interposer structure 30. The TSV 304 and the capacitor structure 106 can be electrically connected to the semiconductor die 80 in subsequent packaging operations.

[0066] As shown in Figure 11F, before bonding the semiconductor die 80 to the interposer structure 30, a TSV exposure operation can be performed, thereby thinning the substrate portion 100 from its back side 100B to one end 304a of the TSV 304. Subsequently, as shown in Figure 11G, a reflow operation can be performed on the back side 100B of the substrate portion 100 to form a second conductive terminal such as a C4 bump 312. In this embodiment, the C4 bump 312 is in contact with another UBM 314 disposed on the back side 100B of the substrate portion 100.

[0067] Subsequently, as shown in FIG11H, a 2.5D assembly operation can be performed to bond the semiconductor die 80 to the front side 30A of the interposer structure 30 and to bond the package substrate 90 to a back side 30B of the interposer structure 30 (equivalent to the back side 100B of the substrate portion 100). The package substrate 90 may further include a plurality of solder balls 901 located on its back side 90B.

[0068] In other embodiments, the intermediate plate structure 10 shown in FIG. 6 above includes a first capacitor electrode structure 124A that contacts the uncovered area 122 of the metal base plate 108 and a second capacitor electrode structure 124B that contacts the top surface of the metal top plate 110. The manufacturing method for packaging the intermediate plate structure 10 with the semiconductor die 80 and the packaging substrate 90 is substantially equivalent to the steps shown in FIG. 11A to FIG. 11H above.

[0069] In embodiments where the TSV 304 penetrates the substrate portion 100, the circuit portion 102, and the interconnect portion 300 (i.e., the embodiments previously disclosed in FIG9B and FIG9D), the via etching and via filling operations used to form the TSV 304 can be performed after the interconnect portion 300 is formed.

[0070] As shown in Figures 12A to 12D, when the capacitor structure 106 has a first capacitor electrode structure 124A and a second capacitor electrode structure 124B located thereon, via etching and via filling operations can still be performed to form a first metal contact 118 and a second metal contact 120 on the capacitor structure 106. These operations are relatively easy because the first capacitor electrode structure 124A and the second capacitor electrode structure 124B can provide coplanar contact surfaces 126 on the capacitor structure 106, allowing the metal contacts to reach them. Furthermore, the first capacitor electrode structure 124A can provide a larger top area, making it easier for the first metal contact 118 to be positioned, thereby improving product yield. In the method of manufacturing the interposer structure, other steps regarding the encapsulation of the interposer structure with the semiconductor die 80 and the packaging substrate 90 are the same as in the embodiments shown in Figures 11A to 11H, and are omitted here for simplicity.

[0071] In short, this disclosure provides an interposer structure with 3D capacitors in a MOL / MOEL structure. By effectively utilizing the space of the interposer structure, a large number of capacitors can be added to the 2.5D package structure. Furthermore, compared to adding capacitors to other spaces in the 2.5D package structure, the MOL / MOEL structure in the interposer structure is very close to the packaged semiconductor die, such as a SOC, so these capacitors can more effectively minimize parasitic resistance and inductance.

[0072] In one exemplary embodiment, this disclosure provides an interposer structure. The interposer structure includes a substrate portion, a circuit portion, an interconnect portion, a via, and a capacitor structure. The circuit portion is disposed on the substrate portion. The interconnect portion is disposed on the circuit portion. The via penetrates both the substrate portion and the circuit portion. The capacitor structure is embedded in the circuit portion. The interconnect portion includes a first metal line electrically coupled to the capacitor structure.

[0073] In another exemplary embodiment, this disclosure provides an interposer structure. The interposer structure comprises a plurality of interposer units arranged in an array from a top viewpoint. Each of the interposer units includes a first region and a plurality of second regions. The first region has a capacitor structure. Each of the second regions does not have the capacitor structure. The first region surrounds the second regions.

[0074] In another exemplary embodiment, this disclosure provides a method for manufacturing an interposer structure. The method includes the steps of: forming a circuit portion on a front side of a substrate portion; and during the formation of the circuit portion, forming a capacitor structure in the circuit portion. The capacitor structure is formed via a dynamic random access memory process.

[0075] The foregoing outlines the structure of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or benefits as the embodiments described in this disclosure. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from its spirit and scope.

[0076] 10: Intermediate board structure 20: Intermediate board unit 30: Intermediate board structure 30A: Front side 30B: Dorsal side 50: Photoresist layer 80: Semiconductor die 81: Second semiconductor die 82: First semiconductor die 90: Packaging substrate 90B: Dorsal side 100: Substrate portion 100A: Front side 100B: Backside 102: Line Section 104: Storage space 106: Capacitor Structure 108: Metal base plate 110: Metal roof 112: Capacitor Unit 114: First conductive film 114A: Part One 114B: Part Two 116: Second conductive film 118: First Metal Contact 120: Second metal contact 122: Non-coverage area 124: Capacitor Electrode Structure 124A: First capacitor electrode structure 124B: Second capacitor electrode structure 126: Coplanar contact surfaces 128: First insulating film 130: Second insulating film 202: Area 1 204: Second Zone 206: Cutting Track 300: Interconnection section 302: First metal layer 304: Through-hole / TSV 306: First conductive terminal 308: Second conductive terminal 310:UBM 312:C4 bump 314:UBM 316: First Metal Circuit 318: Second metal circuit 318a: Second metal circuit 318b: Second metal circuit 400: First PMD layer 402: First nitride film 404: Second PMD layer 406: Second nitride film 408: Opening 410: Conductive layer 412: Conductive layer 414: Opening 416: Insulating film 502: Trench 504: Oxide Pad 901: Solder ball D1: Spacing D2: Spacing D3: Spacing L: Length P: Pitch

Claims

1. A semiconductor device comprising: a substrate portion; a circuit portion located on the substrate portion; and a capacitor structure formed in the circuit portion, the capacitor structure comprising: a metal base plate; a metal top plate located on the metal base plate; and a plurality of capacitor cells equally located between the metal base plate and the metal top plate; and a plurality of capacitor electrode structures equally located on the metal base plate and the metal top plate, and equally coupled to the metal base plate or the metal top plate of the capacitor structure, wherein... The plurality of capacitor electrode structures have a coplanar contact surface.

2. The semiconductor device of claim 1, wherein the plurality of capacitor electrode structures comprises: a first capacitor electrode structure coupled to the metal substrate; and a second capacitor electrode structure coupled to the metal top plate, wherein, Each of the first capacitor electrode structures and each of the second capacitor electrode structures includes a combination consisting of a capacitor contact and a capacitor pad.

3. The semiconductor device as claimed in claim 2, wherein the length of the first capacitor electrode structure in a vertical direction is greater than the length of the second capacitor electrode structure in the vertical direction.

4. The semiconductor device of claim 2, wherein the first capacitor electrode structure is in contact with a region of the metal base plate, the region of which is not covered by the metal top plate.

5. The semiconductor device as claimed in claim 4, wherein the first capacitor electrode structure has a top area larger than the area of ​​the region of the metal substrate.

6. The semiconductor device as claimed in claim 2, wherein the capacitor pad of the first capacitor electrode structure covers a portion of the metal top plate.

7. The semiconductor device of claim 2, further comprising: an interconnect portion located on the line portion, the interconnect portion including a first metal line, the capacitor structure being electrically coupled to the first metal line.

8. The semiconductor device of claim 7, further comprising: at least one first metal contact located in the circuit portion, the at least one first metal contact contacting the capacitor pad of the second capacitor electrode structure; and at least one second metal contact located in the circuit portion, the at least one second metal contact contacting the capacitor pad of the first capacitor electrode structure, wherein, The at least one first metal contact and the at least one second metal contact further contact different positions of the first metal layer of the first metal line of the interconnect portion, and the second metal contact and the first metal contact have the same length in a vertical direction.

9. The semiconductor device of claim 1, wherein, at a cross-sectional angle, the plurality of capacitor electrode structures are located at least on opposite sides of the plurality of capacitor cells.

10. The semiconductor device of claim 1, wherein the plurality of capacitor units have a crown capacitor structure or a concave capacitor structure.

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