Ruthenium liner and cap for back-end-of-line applications

Abstract

This describes an electronic device using a ruthenium or ruthenium-doped pad and cap layer, and a method for forming the electronic device. A pad with ruthenium and cobalt layers is formed on a barrier layer. A conductive filler forms a second conductive line that contacts a first conductive line.

Description

Technical Field

[0001] The embodiments of the present invention are generally related to methods for forming interconnects in electronic devices. More specifically, the embodiments of the present invention relate to methods and electronic devices using a ruthenium-containing double layer for pads and caps. Prior Technology

[0002] Miniaturization of semiconductor circuit components has reached the point where feature sizes of 20 nm and smaller can be manufactured on a commercial scale. As the critical size continues to decrease, new challenges arise for processing steps such as filling the gaps between circuit components. As the width between components continues to shrink, the gaps between components typically become higher and narrower, making the gaps more difficult to fill and the contacts more difficult to secure.

[0003] From the 20 nm node to the 3 nm node, cobalt (Co) pads and Co caps have been the primary materials for improving copper (Cu) interstitial filling and reliability. For the 3 nm plus node and more advanced nodes, interstitial filling on cobalt pads has shown several limitations.

[0004] Copper reflow over ruthenium (Ru) pads has shown potential for expansion into smaller structures. However, reliability issues exist with the use of ruthenium. For example, copper corrosion of interconnects has been observed, resulting in reduced device life.

[0005] Therefore, there is a need for improved methods of interconnect formation in electronic devices. Summary of the Invention

[0006] One or more embodiments of the present invention relate to an electronic device. A first conductive line extends along a first direction. A dielectric material is formed on a substrate surface on the first conductive line. The dielectric material has a top surface with a surface structure formed in the surface of the dielectric material. The surface structure has sidewalls and a via bottom. The via bottom includes the top surface of the first conductive line. A barrier layer is formed on the top surface and sidewalls of the dielectric material. A pad is formed on the barrier layer. The pad has a pad bottom spaced apart from the top surface of the first conductive line by a distance. A conductive filler is within the surface structure. The conductive filler forms a second conductive line extending along a second direction and contacting the first conductive line.

[0007] Additional embodiments of the present invention relate to a method of forming an electronic device. A passivation layer is formed in a via portion of a surface structure, the surface structure being formed in a dielectric material. The passivation layer is formed on the surface of a first conductive material and spaced from the dielectric material by a barrier layer formed on the sidewalls, the bottom of a trench portion of the surface structure, and the top of the dielectric material. The first conductive material extends along a first direction. A pad is formed on the barrier layer. The pad has a bottom surface that contacts the passivation layer in the via portion. The passivation layer is removed to leave a bottom surface of the pad spaced apart from the top surface of the first conductive line. The surface structure is filled with a conductive filler to form a second conductive line in the via portion and the trench portion. The second conductive line extends along a second direction. The via contacts the first conductive line in the via portion. A cap layer is formed on the conductive filler. Simple Explanation of the Diagram

[0008] By referring to the embodiments, some of which are illustrated in the accompanying drawings, a more specific description of the invention briefly summarized above can be obtained, and the manner in which the above-described features of the invention are used can be understood in detail. However, it will be noted that the accompanying drawings illustrate only typical embodiments of the invention and are therefore not intended to limit the scope of the invention; other equivalent embodiments are permissible. The embodiments described herein are illustrated as examples and are not limited to the illustrations in the accompanying drawings, in which similar symbols indicate similar elements.

[0009] Figure 1 shows a partial cross-sectional view of an electronic device formed according to one or more embodiments of the present invention;

[0010] Figure 2 shows a partial cross-sectional view of an electronic device formed according to one or more embodiments of the present invention;

[0011] Figure 3A shows a partial cross-sectional view of an electronic device formed according to one or more embodiments of the present invention;

[0012] Figure 3B shows an enlarged view of region 3 in Figure 3A;

[0013] Figure 4A shows a partial cross-sectional view of an electronic device formed according to one or more embodiments of the present invention;

[0014] Figure 4B shows an enlarged view of region 3 in Figure 4A;

[0015] Figure 5A shows a partial cross-sectional view of an electronic device formed according to one or more embodiments of the present invention;

[0016] Figure 5B shows an enlarged view of region 3 in Figure 5A;

[0017] Figure 6A shows a partial cross-sectional view of an electronic device formed according to one or more embodiments of the present invention; and

[0018] Figure 6B shows an enlarged view of region 6 in Figure 6A. Implementation

[0019] Before describing several exemplary embodiments of the present invention, it will be understood that the invention is not limited to the details of the architecture or processing steps described below. The invention can be implemented or performed in various ways and in other embodiments.

[0020] When used in this specification and the accompanying claims, the term "substrate" refers to a surface or a portion thereof on which the processing is performed. Those skilled in the art will also understand that "substrate" may also refer to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, "deposition on a substrate" may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0021] As used herein, "substrate" refers to any substrate or material surface formed on a substrate, over which a film treatment is performed during the manufacturing process. For example, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates are not limited to semiconductor wafers. Substrates may be exposed to pretreatments such as polishing, etching, reduction, oxidation, alkylation, annealing, UV curing, electron beam curing, and / or baking. In addition to film treatments performed directly on the substrate surface itself, any film treatment steps disclosed in this invention may also be performed over an underlying layer formed on the substrate, as will be described in more detail later, and the term "substrate surface" is intended to include such an underlying layer as indicated by the context. Therefore, for example, when a film / layer or part of a film / layer has been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0022] Ruthenium (Ru) as a pad is no longer suitable for use at the N3 (3 nm node) due to reliability, line resistance (Rs), copper corrosion, chemical mechanical planarization (CMP), and other integration issues. Some embodiments use Ruthenium at the N2 node, employing optional Ru (doped Ru, bottomless Ru) pads and / or Ru (doped Ru) caps to mitigate processing integration problems. Some embodiments use bottomless Ruthenium pads to avoid copper corrosion and reduce via resistance. In some embodiments, the bottomless pad is deposited by selectively depositing Ruthenium on a dielectric surface above the copper surface.

[0023] One or more embodiments of the present invention allow ruthenium to replace cobalt as a gasket and capping layer in advanced node applications. Certain embodiments address reliability issues limiting the application of ruthenium in larger node devices. Certain embodiments of the present invention provide an overall integrated solution that enables ruthenium to serve as a gasket for gap-filling expansion, as a capping layer for reliability, to reduce via contact resistance (Rc), and / or to prevent or mitigate copper corrosion.

[0024] In some embodiments, ruthenium pads or doped ruthenium pads extend physical vapor deposition (PVD) copper reflow as an interstitial filling solution for advanced nodes. Some embodiments provide ruthenium or doped ruthenium caps to improve device reliability. Some embodiments incorporate surfactant-assisted ruthenium treatment to complete the device without ruthenium on the bottom of the structure, preventing corrosion and improving via resistance.

[0025] Figures 1 through 6B illustrate the electronic device 100 during different stages of a method according to one or more embodiments of the present invention. Various fill patterns used in the figures are for easy identification of multiple components and should not be construed as referring to any particular material.

[0026] Referring to Figure 1, a first conductive line 120 is formed on the substrate 110 and extends along a first direction. This first direction may also be referred to as the X-axis direction. For example, in some embodiments, the first conductive line 120 has a length along the X-axis direction, a width along the Y-axis direction, and a thickness measured along the Z-axis direction. The figure shows an XZ plane with the Y-axis extending perpendicular to the illustrated page. The use of the X, Y, and Z axes should not be construed as indicating any particular orientation with respect to gravity.

[0027] In the illustrated embodiments, various spacer layers 112, 114, 116, and 118 are shown. These various spacer layers are optional, and in some embodiments, any or all of them may be omitted. The use of the term "spacer layer" is not intended to refer to any particular function or purpose of the illustrated layer. Spacer layers 112, 114, 116, and 118 may be any suitable material having any suitable purpose. For example, spacer layers may include dielectrics, diffusion barriers, adhesion promoters, or any other layers known to those skilled in the art. In some embodiments, spacer layer 114 comprises a dielectric material, and spacer layers 112 and 116 comprise barrier or padding materials to prevent direct contact between the first conductive line 120 and the substrate 110.

[0028] In some embodiments, forming the first conductive line 120 includes filling trenches with a layer of conductive material. In one or more embodiments, a base layer (not shown) is first deposited over the inner sidewalls and the bottom of the trench, followed by a conductive layer (e.g., spacer layer 112) deposited over the base layer. In one or more embodiments, the base layer includes a conductive seed layer (not shown) deposited over a conductive barrier layer (not shown). The seed layer may include copper (Cu), and the conductive barrier layer may include aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), and similar metals. The conductive barrier layer serves to prevent the diffusion of conductive metals (e.g., copper or cobalt) from the seed layer into the first insulating layer 104. Furthermore, the conductive barrier layer serves to provide adhesion for the seed layer (e.g., copper).

[0029] The first conductive line 120 may be formed by any suitable process known to those skilled in the art. For example, in some embodiments, the first conductive line 120 may be formed by one or more of the following deposition techniques known to those skilled in the art in the field of microelectronic device manufacturing: electroplating, selective deposition, electrolysis, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), spin coating, or other deposition techniques known to those skilled in the art in the field of microelectronic device manufacturing.

[0030] The first conductive line 120 may be any suitable conductive material known to those skilled in the art. In one or more embodiments, the first conductive line 120 comprises a metal, such as copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), molybdenum (Mo), rhodium (Rh), iridium (Ir), niobium (Nb), nickel silicide (NiSi), a ternary compound (e.g., LaRu₂As₂), or any combination thereof.

[0031] The first conductive line 120 may have any suitable thickness (as measured along the Z-axis of Figure 1). In some embodiments, the first conductive line 120 has a thickness ranging from 15 nm to 1000 nm, or from 20 nm to 200 nm. In a non-limiting example, the width of the first conductive line 120 (as measured along the y-axis of Figure 1, which extends perpendicular to the plane of the page) ranges from 5 nm to 500 nm. In a non-limiting example, the spacing (pitch) between adjacent first conductive lines 120 ranges from 2 nm to 500 nm, or from 50 nm to 50 nm.

[0032] Dielectric material 130 is formed on the substrate surface (top surface 122 of the first conductive line) on the first conductive line 120. When used in this manner, the substrate surface is the exposed surface of the material on which the dielectric material 130 is formed. For example, in some embodiments, the first conductive line 120 is formed on the surface of the substrate 110, and a new substrate surface is formed on the new substrate surface, on which the dielectric material 130 is formed.

[0033] In some embodiments, the dielectric material 130 has a top surface 132 with a surface structure 140. The surface structure 140 is formed in the top surface 132 of the dielectric material 130. In some embodiments, the surface structure 140 includes sidewalls 141, via portions 142, and trench portions 146. In some embodiments, the via portion 142 includes a via bottom 143 and a via sidewall 144 opposite to the sidewall 141. In some embodiments, the via bottom 143 includes the top surface 122 of the first conductive line 120.

[0034] In some embodiments, the groove portion 146 includes a groove bottom 147 that connects the through-hole sidewall 144 to the sidewall 141 to form a stepped structure, as shown. In some embodiments, the surface structure 140 includes a uniformly shaped through-hole or groove without a stepped structure.

[0035] The dielectric material 130 can be any material suitable for insulating adjacent devices and preventing leakage current. In one or more embodiments, the dielectric material 130 is an oxide layer, such as silicon dioxide, or any other electrical insulating layer determined by the design of the electronic device. In one or more embodiments, the dielectric material 130 comprises an interlayer dielectric (ILD). In one or more embodiments, the dielectric material 130 is a low-k dielectric, including but not limited to materials such as, for example, silicon dioxide, silicon oxide, carbon-doped oxide (CDO), such as carbon-doped silicon dioxide, porous silicon dioxide (SiO2), silicon nitride (SiN), or any combination of the foregoing. Although the term "silicon oxide" can be used to describe the dielectric material 130, those skilled in the art will recognize that the invention is not limited to a specific stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" can be used to describe materials having any suitable stoichiometric ratio of silicon and oxygen atoms. The same applies to other materials listed in this invention, such as silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and the like.

[0036] In one or more embodiments, dielectric material 130 comprises dielectric material having an ĸ value less than 5. In one or more embodiments, dielectric material 130 comprises dielectric material having an ĸ value from about 2 to about 4. In at least some embodiments, dielectric material 130 comprises oxides, carbon-doped oxides, Black Diamond®, porous silica, carbides, carbon oxides, nitrides, nitrides, carbon oxides, polymers, phosphosilicate glasses, fluorosilicate (SiOF) glasses, organosilicon glasses (SiOCH), fluorosilicate glasses (FSG), porous low-ĸ materials, or any combination of the foregoing, other electrical insulating layers determined by the electronic device design, or any combination of the foregoing. In at least some embodiments, dielectric material 130 may comprise polyimide, epoxy resin, photodefinable materials such as benzocyclobutene (BCB), and WPR series materials, or spin-coated glass.

[0037] In one or more embodiments, dielectric material 130 is a low-k interlayer dielectric to isolate a metal line from other metal lines on substrate 110. In one or more embodiments, the thickness of dielectric material 130 is in a general range from about 10 nanometers (nm) to about 2 micrometers (µm).

[0038] In one or more embodiments, the dielectric material 130 is deposited or formed using one of the following deposition techniques: plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating, or other insulating deposition techniques known to those skilled in the art in the field of microelectronic device manufacturing.

[0039] In some embodiments, the surface structure 140 is formed using any suitable technique known to those skilled in the art. In some embodiments, the dielectric material 130 is patterned and etched using a hard mask to form the surface structure 140 using one or more patterning and etching techniques known to those skilled in the art in the field of microelectronic device manufacturing.

[0040] A barrier layer 150 is formed on the top surface 132 of the dielectric layer 130 and on the sidewalls 141 of the surface structure 140. In some embodiments, in addition to the sidewalls 141 and the top surface 132 of the dielectric material 130, the barrier layer 150 is formed on the via sidewalls 144 and the bottom of the trench 147, as shown in Figure 1. In some embodiments, the barrier layer 150 is conformally formed on the sidewalls 141, the top surface 132, the via sidewalls 144, and the bottom of the trench 147.

[0041] The barrier layer 150 may comprise any suitable material known to those skilled in the art, formed using any suitable technique known to them. In one or more embodiments, the barrier layer 150 comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), or the like. In some embodiments, the barrier layer is deposited by atomic layer deposition.

[0042] In some embodiments, the barrier layer 150 is selectively deposited on the dielectric material 130 above the first conductive line 120. For example, as shown, the barrier layer 150 is formed in contact with the dielectric material 130 but does not nucleate, or undergoes a relatively long nucleation delay on the first conductive line 120.

[0043] Referring to Figure 2, a passivation layer 160 is formed through surface structure 140 on the exposed top surface 122 of the first conductive line 120. The passivation layer 160 can be any suitable material known to those skilled in the art and can be deposited by any suitable technique. In some embodiments, the passivation layer 160 is selectively deposited on the first conductive line 120 above the barrier layer 150. The passivation layer 160 can be any material that protects the first conductive line 120 from the formation of the subsequent pad 170. In some embodiments, the passivation layer 160 has a thickness ranging from 5 Å to 1000 Å, or from 1 nm to 50 nm.

[0044] In other words, in some embodiments, a passivation layer 160 is formed in the via portion 142 of the surface structure 140, which is formed in the dielectric material 130. The passivation layer 160 is formed on the surface of the first conductive material 120 and is separated from the dielectric material 130 by a barrier layer 150 formed on the sidewall 141, the via sidewall 144, the bottom of the trench portion 146 of the surface structure 140, and the top surface 132 of the dielectric material 130.

[0045] Referring to the enlarged region 3 shown in Figures 3A and 3B, a gasket 170 is formed on the barrier layer 150. In some embodiments, the gasket 170 is co-formed on the barrier layer 150. In some embodiments, the gasket 170 is selectively formed on the barrier layer 150 above the passivation layer 160. The figures show the gasket 170 contacting the passivation layer 160; however, those skilled in the art will recognize that the gasket 170 does not nucleate on the passivation layer 160, and that the contact between the gasket 170 and the passivation layer 160 is a physical contact, not a chemical contact.

[0046] When the passivation layer 160 is on the first conductive line 120, the pad 170 forms a pad bottom surface 172 spaced apart from the top surface 122 of the first conductive line 120. The distance between the top surface 122 of the first conductive line 120 and the pad bottom surface 172 of the pad 170 is defined by the thickness of the passivation layer 160.

[0047] Referring to the enlarged view of region 3 shown in Figure 3B, in some embodiments, the pad 170 includes a first pad layer and a second pad layer. The first pad layer has a first pad bottom surface 172a and the second pad layer has a second pad bottom surface 172b, each pad bottom surface being spaced apart from the top surface 122 of the first conductive line 120 by a distance.

[0048] In some embodiments, the pad 170 includes a ruthenium layer 174 in contact with the barrier layer 150 and a cobalt layer 177 on the opposite side of the ruthenium layer 174 from the barrier layer 150. In other words, in some embodiments, the pad 170 includes a ruthenium layer 174 in direct contact with the barrier layer 150 and a cobalt layer 177 in contact with the ruthenium layer 174 and separated from the barrier layer 150 by the ruthenium layer 174.

[0049] In some embodiments, the liner 170 has a total thickness (i.e., the sum of the thicknesses of all layers) ranging from 5 Å to 50 Å. The thickness of the liner 170 is measured along the sidewall 141, the through-hole sidewall 144, and the bottom 147 of the trench in the surface structure 140. In some embodiments, the ruthenium layer 174 has a thickness ranging from 2.5 Å to 25 Å, or from 5 Å to 20 Å, or from 10 Å to 15 Å. In some embodiments, the cobalt layer 177 has a thickness ranging from 2.5 Å to 25 Å, or from 5 Å to 20 Å, or from 10 Å to 15 Å. In some embodiments, the ruthenium layer 174 and the cobalt layer 177 have approximately the same thickness. In some embodiments, the ruthenium layer 174 and the cobalt layer 177 have a thickness ratio ranging from 0.95:1 to 1:0.95. In some embodiments, the ruthenium:cobalt thickness ratio is approximately 1:1. In some embodiments, the ruthenium and cobalt layers are each approximately 10 Å thick.

[0050] In some embodiments, the liner 170 comprises a ruthenium and cobalt bilayer, wherein the ruthenium contact barrier layer 150. The ruthenium may be metallic ruthenium or doped ruthenium. Suitable dopants include, but are not limited to, oxygen, nitrogen, boron, carbon, copper, tungsten, molybdenum, aluminum, or manganese.

[0051] The pad 170 can be deposited using any suitable technique known to those skilled in the art. In some embodiments, the pad 170 or individual layers of the pad are deposited by atomic layer deposition.

[0052] In some embodiments, after the pad 170 is formed, the passivation layer 160 is removed, as shown in Figures 4A and 4B. Removing the passivation layer 160 leaves a gap 180 such that the bottom surface 172 of the pad is spaced apart from the top surface 122 of the first conductive line 120 by a distance. The distance or thickness of the gap 180 is substantially the same as (i.e., within ±10%) the thickness of the passivation layer 160. The passivation layer 160 can be removed by any suitable technique depending on the materials used. In some embodiments, the passivation layer 160 is removed by a selective etching process that does not significantly affect other surface materials.

[0053] As shown in Figure 4B, in some embodiments, the passivation layer 160 is removed to expose the bottom surfaces 172a and 172b of the first pad in the gap 180. In other words, in some embodiments, the pad 170 does not contact the first conductive line 120, such that there is a gap 180 between the top surface 122 of the first conductive line 120 and the bottom edge of the pad 170.

[0054] Referring to Figures 5A and 5B, after the passivation layer 160 is removed, a conductive filler 185 is deposited within the surface structure 140. The conductive filler 185 forms a second conductive line 181 extending along a second direction. The conductive filler 185 (second conductive line 181) directly contacts the first conductive line 120 at the bottom 143 of the via portion 142 of the surface structure 140.

[0055] The conductive filler 185 can be any suitable material and can be deposited by any suitable technique known to those skilled in the art. In some embodiments, the conductive filler 185 forming the second conductive line 181 comprises copper or is substantially composed of copper. When used in this manner, the term "substantially composed of" means that the film contains greater than or equal to 95%, 98%, 99%, or 99.5% of the aforementioned material.

[0056] The conductive filler 185 can be formed using any suitable technique known to those skilled in the art. In some embodiments, the conductive filler 185 is deposited by physical vapor deposition. In one or more embodiments, the second conductive material 220 comprises or contains a metal film. Suitable metal films for the conductive filler 185 include, but are not limited to, films containing one or more of cobalt (Co), molybdenum (Mo), tungsten (W), tantalum (Ta), titanium (Ti), ruthenium (Ru), rhodium (Rh), copper (Cu), iron (Fe), manganese (Mn), vanadium (V), niobium (Nb), hafnium (Hf), zirconium (Zr), yttrium (Y), aluminum (Al), tin (Sn), chromium (Cr), lanthanum (La), or any combination thereof. In some embodiments, the conductive filler 185 forming the second conductive line comprises copper (Cu).

[0057] In one or more embodiments, the conductive filler 185 is deposited using a deposition technique, such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other pad deposition techniques known to those skilled in the art in the field of microelectronic device manufacturing.

[0058] Referring to Figures 6A and 6B, in some embodiments, a capping layer 190 is formed on a conductive filler 185 that forms the second conductive line 181. Figure 6B shows an enlarged view of region 6 of Figure 6A. In some embodiments, the capping layer 190 formed on the top surface 182 of the second conductive line 181 includes a first capping layer and a second capping layer. In some embodiments, the capping layer 190 includes a ruthenium layer 192 and a cobalt layer 194, the ruthenium layer 192 being in contact with the conductive filler 185 forming the second conductive line 181, and the cobalt layer 194 being on the opposite side of the ruthenium layer 192 from the conductive filler 185, which forms the second conductive line 181.

[0059] In other words, in some embodiments, the cap layer 190 includes a ruthenium layer 192 and a cobalt layer 194, the ruthenium layer 192 contacting the second conductive line 181, and the cobalt layer 194 contacting the ruthenium layer 192 and being separated from the second conductive line 181 by the ruthenium layer 192.

[0060] In some embodiments, the cap layer 190 has a total thickness (i.e., the sum of the thicknesses of all layers) ranging from 5 Å to 50 Å. In some embodiments, the ruthenium layer 192 has a thickness ranging from 2.5 Å to 25 Å, or from 5 Å to 20 Å, or from 10 Å to 15 Å. In some embodiments, the cobalt layer 194 has a thickness ranging from 2.5 Å to 25 Å, or from 5 Å to 20 Å, or from 10 Å to 15 Å. In some embodiments, the ruthenium layer 192 and the cobalt layer 194 have approximately the same thickness. In some embodiments, the thickness ratio of the ruthenium layer 192 to the cobalt layer 194 ranges from 0.95:1 to 1:0.95. In some embodiments, the ruthenium:cobalt thickness ratio is approximately 1:1. In some embodiments, each of the ruthenium and cobalt layers is approximately 10 Å thick.

[0061] The capping layer 190 can be deposited using any suitable technique known to those skilled in the art. In some embodiments, the capping layer 190, or individual layers, is deposited by atomic layer deposition. In some embodiments, the capping layer 190 is selectively formed on the top surface 182 of the second conductive line 181.

[0062] In some embodiments, the use of a selective double capping layer and a ruthenium liner increases the electromigration failure time (at the 50% level) by more than 2.5 times. This results in a failure rate increase of more than 2 times compared to a failure rate increase of more than 50% when Ru is first placed in the capping layer followed by Co, compared to a failure rate increase of more than Co followed by Ru. In addition to the double capping layer, the use of a double liner further increases the failure time.

[0063] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" indicate that a particular feature, structure, material, or characteristic described in the embodiment is included in at least one embodiment of the invention. Therefore, phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment of the invention. Furthermore, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0064] Although the present invention has been described herein with reference to specific embodiments, those skilled in the art will understand that the embodiments are merely illustrative of the principles and applications of the invention. Various modifications and variations can be made to the methods and apparatus of the present invention without departing from the spirit and scope of the invention, as will be apparent to those skilled in the art. Therefore, the present invention may include modifications and variations falling within the scope of the appended claims and their equivalents.

[0065] 3,6: Area 100: Electronic devices 110:Substrate 112, 114, 116, 118: Spacer layers 120: First conductive line 122: Top surface 130: Dielectric materials 132: Top surface 140: Surface Structure 141: Sidewall 142: Through-hole section 143: Bottom of through hole 144: Through-hole sidewall 146: Groove section 147: Bottom of the trench 150: Barrier Layer 160: Passivation layer 170: Padding 172: Bottom surface of the pad 172a: Bottom surface of the first liner 172b: Bottom surface of the second liner 174: Ruthenium layer 177: Cobalt layer 180: Gap 181: Second conductive line 182: Top surface 185: Conductive filler 190: Cap layer 192: Ruthenium layer 194: Cobalt layer

[0066] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An electronic device comprising: a first conductive line extending along a first direction; a dielectric material formed on a substrate surface of the first conductive line, the dielectric material having a top surface, the top surface having a surface structure formed in a surface of the dielectric material, the surface structure having a plurality of sidewalls and a bottom of a via, the bottom of the via including the top surface of the first conductive line; a barrier layer formed on the top surface of the dielectric material and the sidewalls; a pad formed on the barrier layer, the pad having a bottom surface spaced apart from the top surface of the first conductive line by a distance, wherein the pad includes a ruthenium layer and a cobalt layer, the ruthenium layer contacting the barrier layer, and the cobalt layer being on an opposite side of the ruthenium layer from the barrier layer; A conductive filler, within the surface structure, comprising copper, forming a second conductive line extending along a second direction, the conductive filler contacting the first conductive line; and a capping layer on the conductive filler, the capping layer comprising a ruthenium layer and a cobalt layer, the ruthenium layer contacting the conductive filler, and the cobalt layer being on an opposite side of the ruthenium layer from the conductive filler.

2. The electronic device as claimed in claim 1, wherein the pad has a total thickness ranging from 5 Å to 50 Å.

3. The electronic device as claimed in claim 1, wherein the ruthenium layer has a thickness ranging from 2.5 Å to 25 Å, and the cobalt layer has a thickness ranging from 2.5 Å to 25 Å.

4. The electronic device as claimed in claim 1, wherein the ruthenium layer and the cobalt layer have a thickness ratio ranging from 0.95:1 to 1:0.

95.

5. The electronic device as claimed in claim 1, wherein the surface structure in the dielectric material includes a trench portion and a through-hole portion, the trench portion having a trench bottom and the through-hole portion having the through-hole bottom.

6. The electronic device as claimed in claim 5, wherein the barrier layer is formed on the bottom of the trench.

7. The electronic device as claimed in claim 6, wherein the barrier layer is a conformal layer.

8. The electronic device as claimed in claim 7, wherein the second conductive line is in direct contact with the first conductive line at the bottom of the through-hole portion of the surface structure.

9. The electronic device as claimed in claim 1, wherein the pad does not contact the first conductive line, such that there is a gap between the top surface of the first conductive line and a bottom edge of the pad.

10. The electronic device as claimed in claim 1, wherein an electromigration failure time (at a 50% level) is greater than 2.5 times that of a comparable electronic device without the pad containing a ruthenium layer and a cobalt layer.

11. A method of forming an electronic device, the method comprising: forming a passivation layer in a via portion of a surface structure formed in a dielectric material, the passivation layer being formed on a surface of a first conductive material and separated from the dielectric material by a barrier layer, the barrier layer being formed on a plurality of sidewalls of the surface structure, a bottom of a trench portion, and a top of the dielectric material, the first conductive material extending along a first direction; forming a pad on the barrier layer, the pad having a pad bottom surface contacting the passivation layer in the via portion, wherein the pad includes a ruthenium layer and a cobalt layer, the ruthenium layer contacting the barrier layer, and the cobalt layer being on an opposite side of the ruthenium layer from the barrier layer; removing the passivation layer to leave the bottom surface of the pad, the bottom surface being spaced apart from a top surface of the first conductive line by a distance; The surface structure is filled with a conductive filler containing copper to form a through hole in the through hole portion and a second conductive line in the trench portion, the second conductive line extending along a second direction, the through hole contacting the first conductive line in the through hole portion; and a capping layer is formed on the conductive filler, wherein the capping layer includes a ruthenium layer and a cobalt layer, the ruthenium layer contacting the conductive filler, and the cobalt layer being on an opposite side of the ruthenium layer from the conductive filler.

12. The method as claimed in claim 11, wherein the ruthenium layer has a thickness ranging from 2.5 Å to 25 Å, and the cobalt layer has a thickness ranging from 2.5 Å to 25 Å.

13. The method as described in claim 11, wherein the ruthenium layer and the cobalt layer have a thickness ratio ranging from 0.95:1 to 1:0.

95.

14. The method as claimed in claim 11, wherein the ruthenium layer of the cap layer has a thickness ranging from 2.5 Å to 25 Å, and the cobalt layer of the cap layer has a thickness ranging from 2.5 Å to 25 Å.

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