Method of pattern alignment for field stitching

Abstract

This document provides a method for pattern alignment. The method includes identifying a reference pattern positioned below the working surface of a wafer. The wafer is exposed to a first pattern of photochemical radiation. The first pattern is a first component of a composite pattern. The first pattern of photochemical radiation is aligned using the reference pattern. The wafer is then exposed to a second pattern of photochemical radiation. The second pattern is a second component of a composite pattern and is exposed adjacent to the first pattern. The second pattern of photochemical radiation is aligned with the first pattern of photochemical radiation using the reference pattern.

Description

Technical Field

[0001] This disclosure relates generally to methods for manufacturing semiconductor devices, and more specifically to coverage errors and pattern alignment. [Cross-reference to related applications]

[0002] This disclosure claims the rights of U.S. Provisional Patent Application No. 63 / 066,779, filed August 17, 2020, the entire contents of which are incorporated herein by reference. Prior Technology

[0003] Semiconductor manufacturing involves several different steps and processes. A typical manufacturing process is called photolithography (also known as micro-etching). Photolithography uses radiation such as ultraviolet or visible light to create intricate patterns in semiconductor device designs. Many types of semiconductor devices, such as diodes, transistors, and integrated circuits, can be constructed using semiconductor manufacturing techniques that include photolithography, etching, film deposition, surface cleaning, and metallization.

[0004] Microfabrication involves forming and processing multiple films and stacks on a wafer. This may include dozens or more films stacked on the wafer. Patterns applied to the wafer for the films and stacks need to be aligned with previously formed patterns. Conventionally, such alignment is achieved by forming alignment marks and scribing using portions of the wafer. However, the inventors have discovered that many film deposition, etching, and processing techniques sometimes cover or even completely remove alignment marks. When alignment marks are sometimes covered or disappear, subsequent patterning on the wafer may be inaccurate. The terms "coverage" or "coverage error" refer to the difference between the placement of a given pattern and a previously set pattern. When alignment marks are frequently damaged, coverage error may accumulate with additional layers, which may lead to poor performance and device malfunctions.

[0005] Extreme ultraviolet (EUV) lithography (also known as EUVL) is a state-of-the-art microfabrication technique that uses a range of EUV wavelengths, such as 13.5 nm. Due to the short wavelength of EUV light, EUV lithography allows for the exposure of fine patterns at half-pitch (HP) of less than 20 nm. EUV tools may include a radiation system for supplying the EUV beam, a mask stage for holding the EUV photomask, a wafer stage for holding the wafer, and projection optics for imaging the irradiated portion of the EUV photomask onto a target portion of the wafer. Summary of the Invention

[0006] This disclosure pertains to methods for pattern alignment.

[0007] The method (1) includes a pattern alignment method. This method includes identifying a reference pattern positioned below the working surface of a wafer. The wafer is exposed to a first pattern of photochemical radiation. The first pattern is a first component of a composite pattern. The first pattern of photochemical radiation is aligned using the reference pattern. The wafer is exposed to a second pattern of photochemical radiation. The second pattern is a second component of a composite pattern and is exposed adjacent to the first pattern. The second pattern of photochemical radiation is aligned with the first pattern of photochemical radiation using the reference pattern.

[0008] The pattern (2) includes the method of the pattern (1), and further includes measuring a first coverage value between the first pattern and the reference pattern to align the first pattern. A second coverage value is measured between the second pattern and the reference pattern. A third coverage value between the first pattern and the second pattern is calculated based on the first and second coverage values. The second pattern is aligned with the first pattern using the third coverage value.

[0009] The method of the sample (3) includes the method of the sample (2), and further includes capturing an image of a reference pattern, an image of a first pattern, and an image of a second pattern. A first coverage value is measured by analyzing the image of the reference pattern and the image of the first pattern. A second coverage value is measured by analyzing the image of the reference pattern and the image of the second pattern.

[0010] The state pattern (4) includes the method of state pattern (1), and further includes identifying the first coordinate position of the first pattern relative to the reference pattern. Identifying the second coordinate position of the second pattern relative to the reference pattern. Calculating the coverage value using the first coordinate position and the second coordinate position. Aligning the second pattern with the first pattern using the coverage value.

[0011] The method of the state sample (5) includes the state sample (1), and further includes forming a photoresist layer on the working surface of the wafer. The photoresist layer contains photoreactive species configured to form a composite pattern.

[0012] The method of the state pattern (6) including the state pattern (5) further includes forming an in-field alignment mark outside the device area or under the photoresist layer in the device area. The first pattern is aligned with the in-field alignment mark using a reference pattern. The second pattern is aligned with the in-field alignment mark using a reference pattern.

[0013] The state (7) includes a method of the state (5), and further includes developing the photoresist layer such that a first feature of the first pattern is connected to a second feature of the second pattern.

[0014] The state sample (8) includes a method of the state sample (1), and further includes exposing the wafer to one or more additional patterns of photochemical radiation. The one or more additional patterns are additional components of a composite pattern. The one or more additional patterns of photochemical radiation are aligned using a reference pattern.

[0015] The method of state (9) includes state (1), further comprising, in a first operation, exposing the plurality of wafers to a first pattern of photochemical radiation when the plurality of wafers are placed on the wafer stage of the lithography tool; transferring the wafers from the wafer stage to the wafer storage of the lithography tool; switching a mask for the mask stage of the lithography tool; transferring the wafers from the wafer storage to the wafer stage; and in a second operation, exposing the wafers to a second pattern of photochemical radiation.

[0016] The method of the state pattern (10) including the state pattern (1) further includes exposing the plurality of wafers to a first pattern of photochemical radiation in a first operation when the plurality of wafers are placed on the wafer stage of the lithography tool. When the wafers are on the wafer stage, a mask is switched for the mask stage of the lithography tool. When the wafers are on the wafer stage, the wafers are exposed to a second pattern of photochemical radiation in a second operation.

[0017] The method of the state (11) comprising the state (1) further comprising exposing the wafer to a first pattern of photochemical radiation through a first mask having a first pattern, thereby printing a first latent image on the wafer, such that the first latent image is scaled down compared to the first pattern on the first mask. The method of exposing the wafer to a second pattern of photochemical radiation through a second mask having a second pattern, thereby printing a second latent image on the wafer, such that the second latent image is scaled down compared to the second pattern on the second mask.

[0018] The method of comprising state (1) includes state (1), wherein the first pattern of photochemical radiation includes an extreme ultraviolet (EUV) wavelength or a deep ultraviolet (DUV) wavelength. The second pattern of photochemical radiation includes an EUV wavelength or a DUV wavelength.

[0019] The method of the state pattern (13) includes the state pattern (1), wherein the reference pattern is incorporated in a reference plate positioned on or attached to the back side of the wafer.

[0020] The method of the state pattern (14) includes the state pattern (1), wherein the reference pattern is incorporated in a reference plate, which is incorporated in a substrate holder of a lithography scanner or stepper.

[0021] The method of the state pattern (15) includes the state pattern (1), wherein the reference pattern is formed on the back side of the wafer or embedded in the wafer.

[0022] The state pattern (16) includes the method of the state pattern (1), wherein the reference pattern contains radioactive or fluorescent material.

[0023] The method of the state pattern (17) includes the state pattern (1), wherein the reference pattern includes at least one of points, lines, angles, frames, triangles, numbers or marks.

[0024] The state pattern (18) includes the method of the state pattern (1), and further includes identifying a reference pattern located below the working surface of the wafer via quantum tunneling imaging or infrared (IR) transmission imaging.

[0025] The state pattern (19) includes a method of the state pattern (1), wherein a reference pattern is projected onto the surface of a wafer.

[0026] The sample (20) includes a method for pattern alignment. This method includes imaging a reference plate positioned beneath a wafer via quantum tunneling imaging or infrared (IR) transmission imaging. The reference plate contains a reference pattern. A first pattern of photochemical radiation is aligned using the reference pattern. The first pattern is a first component of a composite pattern. A first field of the wafer is exposed to the first pattern of photochemical radiation. A second pattern of photochemical radiation is aligned using the reference pattern. The second pattern is a second component of a composite pattern. A second field of the wafer is exposed to the second pattern of photochemical radiation. The second field is adjacent to the first field.

[0027] Note that this summary does not specify every embodiment and / or incremental novelty of the invention or the claimed invention. Rather, this summary provides only a preliminary discussion of different embodiments and corresponding novel aspects. For additional details and / or possible perspectives regarding the invention and its embodiments, please refer to the implementation section and corresponding drawings of this summary, as discussed further below. Simple Explanation of the Diagram

[0028] The best understanding of this disclosure can be obtained by reading it in conjunction with the accompanying drawings, and from the following detailed description. Note that, in accordance with standard industry practice, many features are not drawn to scale. In fact, the dimensions of many features may be increased or decreased for clarity of discussion.

[0029] Figure 1A shows an example diagram of an extreme ultraviolet (EUV) tool.

[0030] Figure 1B illustrates an example of de-magnification in a projection printing system.

[0031] Figure 1C shows a simplified schematic diagram of splicing in a projection printing system.

[0032] Figure 2A shows the industry issues covered.

[0033] Figure 2B illustrates an illustrative embodiment of the present disclosure using a reference pattern for overlay alleviation.

[0034] Figure 3A shows a schematic diagram of aligning a wafer using a reference pattern, according to an exemplary embodiment of the present disclosure.

[0035] Figure 3B shows a reference panel according to an exemplary embodiment of the present disclosure.

[0036] Figures 4A and 4B show image analyses with and without reference patterns, respectively, according to exemplary embodiments of the present disclosure.

[0037] Figure 4C shows a detailed view of the rectangle 400C in Figure 4B according to an exemplary embodiment of the present disclosure.

[0038] Figure 4D shows an illustrative embodiment of the present disclosure, illustrating the coverage calculation using the reference pattern shown in Figure 4C.

[0039] Figures 5A, 5B, and 5C are top views of a wafer stage at an intermediate step in the splicing process, according to embodiments of the present disclosure.

[0040] Figure 5D shows an enlarged view of the dashed rectangle 500D in Figure 5C according to an embodiment of the present disclosure.

[0041] Figure 6 shows an exemplary process flow diagram for processing a wafer according to an exemplary embodiment of the present disclosure. Implementation

[0042] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, the following description of forming a first feature on or above a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in numerous instances in this disclosure. This repetition is for the purpose of brevity and clarity and does not in itself specify a relationship between the numerous embodiments and / or configurations discussed. Moreover, for ease of description, spatial relative terms such as "top," "bottom," "below," "under," "below," "down," "above," "up," etc., may be used herein to describe the relationship of an element or feature shown in the figures to another element or feature. In addition to the orientations illustrated in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used in this article can be interpreted accordingly.

[0043] The order in which the different steps described herein are presented has been for clarity. Generally, these steps can be performed in any suitable order. Furthermore, although the various features, techniques, configurations, etc., described herein may be discussed in different places within this disclosure, it is intended that these concepts be performed independently of each other or in combination with each other. Therefore, the present invention can be practiced and examined in many different ways.

[0044] As described in the prior art, extreme ultraviolet (EUV) lithography is an important technology for microfabrication. U.S. patents held by Advanced Semiconductor Materials Lithography (ASML) in the Netherlands (e.g., US6459472B1 and US6232615B1, each incorporated herein by reference in its entirety) include examples of EUV tools. As used herein, "EUV tool" generally refers to any lithography tool that incorporates an EUV light source. EUV tools can include EUV tools with a numerical aperture (NA) less than 0.5 (e.g., NA=0.33), high NA EUV tools (NA>0.5, e.g., NA=0.55), etc.

[0045] Figure 1A shows an exemplary diagram of an EUV tool 100. As shown, the EUV tool 100 includes a radiation system 110 for supplying the EUV beam, indicated by the arrow. The radiation system 110 includes an EUV light source 111 that generates the EUV beam, such as a laser-driven tin (Sn) plasma light source. Although not shown, the radiation system 110 may also include optical components such as a condenser lens, a selective reflector, an intensity integrator, etc. These optical components are configured such that the EUV beam exiting the radiation system 110 is substantially collimated, uniform, and monochromatic.

[0046] EUV tool 100 also includes a mask stage 120 for holding the EUV mask 121. Unlike conventional light masks that use a single chromium layer on a quartz substrate to block light, the EUV mask 121 can reflect EUV beams by using multiple (e.g., forty) alternating layers of molybdenum (Mo) and silicon (Si). The multiple alternating layers act to reflect the EUV beams by Bragg diffraction. Therefore, the EUV mask 121 is a reflective mask. Patterns can be defined in tantalum-based absorbing layers on the multiple alternating layers. Because almost all of it absorbs EUV radiation, EUV lithography is performed in a vacuum environment. Furthermore, many optical components, including the EUV mask 121, may require the use of defect-free Mo / Si multilayer films to reflect EUV light by interlayer interference.

[0047] EUV tool 100 also includes an optical element 130 having a projection optics element 131, and a wafer stage 140 for holding the wafer 141. The projection optics element 131 is configured to image the irradiated portion of the EUV mask 121 onto a target portion (e.g., a field or die) of the wafer 141. The projection optics element 131 may include lenses, mirror groups, reflection and refraction systems, particle focusing systems, and / or the like.

[0048] Referring again to Figure 1, the EUV mask 121 is positioned away from the wafer 141, and the pattern of the EUV mask 121 is focused onto the wafer 141 by a projection optics element 131. The projection optics element 131 can be configured such that the image printed on the wafer 141 is magnified compared to the original pattern of the EUV mask 121, thereby improving resolution. Unlike conventional contact printing or proximity printing systems where the photomask (also called a mask) typically covers the entire wafer, the projection photomask (also called a magnification mask) typically displays only a single die (also called a field) or a die array due to magnification.

[0049] In next-generation EUV tools, higher magnification is sought, especially when using high numerical aperture (NA) lens systems. However, higher magnification may necessitate larger mask sizes or result in smaller printed field sizes. On the one hand, manufacturing complexity makes it undesirable to manufacture larger masks to compensate, but on the other hand, smaller fields may lead to the need for "stitching" or accept significantly reduced yields, exacerbating existing problems in EUV lithography. Specifically, reducing the field size may involve dividing a full-size wafer pattern (e.g., 26mm × 33mm) between two or more conventional 6-inch EUV photomasks. Therefore, large wafers, such as those used for graphics processing units (GPUs), may need to be stitched together from two or more component patterns to form a complete composite pattern. Two or more component patterns typically require two or more photomasks, and changing photomasks during lithography can undesirably reduce EUVL yields. Furthermore, features located near or across field boundaries may have alignment errors.

[0050] Figure 1B illustrates a scaling example in a projection printing system (e.g., in an EUV tool). As shown, a projection mask 160 (e.g., an EUV mask) can be isomorphically or deformably scaled to different degrees by the projection optics 170. In a non-limiting example, the projection mask 160 has lateral dimensions of 104 mm and 132 mm in the x and y directions, respectively. In one embodiment, the projection mask 160 has a 4X isomorphic scaling. Therefore, the first image 161 printed on the wafer has lateral dimensions of 26 mm and 33 mm in the x and y directions, respectively. Note that 26 mm × 33 mm can be the lateral dimension of a wafer pattern. In another embodiment, the projection mask 160 has an 8X isomorphic scaling. Therefore, the second image 163 printed on the wafer has lateral dimensions of 13 mm and 16.5 mm in the x and y directions, respectively. In another embodiment, the projection mask 160 has a deformable scaling, having a 4X scaling in the x direction and an 8X scaling in the y direction. Therefore, the third image 165 printed on the wafer has lateral dimensions of 26 mm and 16.5 mm in the x and y directions, respectively.

[0051] In fact, in current 0.33 NA EUV tools (such as the TWINSCAN NXE:3400B from Advanced Semiconductor Materials Lithography (ASML) in the Netherlands), isomorphic lenses can support 4X scaling, with a maximum scan exposure field size of 26 mm x 33 mm. However, in high NA EUV tools (such as NA = 0.55, EXE:5000, ASML, Netherlands), anamorphic lenses can support 8X scaling in the scan direction and 4X scaling in the vertical direction. As shown in Figure 1B, such size reduction or scaling provides a significant scaling advantage for improved resolution, but also limits the exposure size by reducing the image field size. That is, if a complete image of the entire wafer is formed in one exposure or printing, a larger mask than usual will be required. However, due to manufacturing complexity, it is not desirable to manufacture such a large mask to compensate. As a result, it is usually necessary to repeatedly project and / or project multiple masks onto different areas of the wafer to produce a complete pattern. For example, this could involve a process of exposing one part of a composite pattern with one mask and then exposing another part of the composite pattern with another mask. The patterns from the two masks are then developed and stitched together.

[0052] Figure 1C shows a simplified schematic diagram of splicing in projection printing (e.g., in EUV tools). Herein, projection printing system 180 prints a photomask (not shown) on a first region 191 of wafer 190. The first region 191 may, for example, contain a first die or field. Wafer 190 also contains a second region 192 adjacent to the first region 191 (e.g., a second die or field). Note that although in the example of Figure 1C, wafer 190 has only two regions (i.e., 191 and 192), in other embodiments, wafer 190 may have any number of regions, as determined by the size of wafer 190, the size of the photomask, the degree of scaling, etc. In one embodiment, projection printing system 180 uses the same photomask to print the same image on the second region 192 as on the first region 191. In another embodiment, projection printing system 180 uses different photomasks to print different images on the second region 192, such that the images on the first region 191 and the second region 192 form a composite pattern. This process is an example of splicing or field splicing.

[0053] Field stitching is crucial for overcoming the size limitations of photomasks in high-NA EUV lithography. Without field stitching, die size can be limited. In fact, high-NA EUV lithography typically requires the stitching of multiple fields to produce die sizes commensurate with high-volume manufacturing (HVM) wafer designs. During field stitching, proper alignment of the photomask may be necessary to minimize overlay errors. Large overlay errors can lead to incorrect electrical connections between component patterns or adjacent layers, resulting in device malfunctions or even wafer failure.

[0054] The technique described in this paper involves a method for "stitching" patterns together. In lithography patterning, there are sometimes situations where the desired pattern size of a wafer is larger than the exposure capability of a given system. To pattern the desired wafer size, composite patterns are required. In other words, two or more exposures (using two or more masks) may be needed to combine the constituent patterns together. Due to overlay issues, aligning the constituent images for proper joining can be challenging.

[0055] The techniques described herein encompass complementary stitching methods between different lithography techniques or tools. The first and second patterns of photochemical radiation may contain the same light or two different light sources. For example, the first and second patterns of photochemical radiation may independently contain extreme ultraviolet (EUV) wavelengths (e.g., 13.5 nm) or deep ultraviolet (DUV) wavelengths (e.g., 193 nm).

[0056] The technique described herein uses through-wafer technology and independent reference patterns or boards to properly stitch together (align and expose) two or more constituent patterns. A reference board positioned beneath the wafer provides constant and accurate reference points. A quantum tunneling imaging system, combined with a surface imaging system, is used to capture an image of a reference pattern that is equivalent to the first constituent pattern. The second set of patterned equivalents can then be set up with knowledge of many points on the first pattern to ensure that features are properly aligned and joined.

[0057] The techniques described herein use reference patterns for pattern alignment, as disclosed in the applicant's patent applications entitled "Method for Producing Overlay Results with Absolute Reference for Semiconductor Manufacturing" (Attorney's File Nos. 537182US and 537267US), all of which are incorporated herein by reference in their entirety. The techniques described herein also use coaxial see-through alignment imaging systems, as disclosed in the applicant's patent applications entitled "Coaxial See-Through Alignment Imaging System and Method" (Attorney's File Nos. 537264US and 537276US), all of which are incorporated herein by reference in their entirety.

[0058] This disclosure discloses embodiments in which an apparatus or tool sees through a semiconductor wafer to image a pattern within or under the wafer. This see-through technique can be used to compare a pattern or reference object under or within the wafer with a pattern on the working surface of the wafer (e.g., the top surface or front side).

[0059] The technology described herein includes an imaging system capable of coaxially aligning two beams of different wavelengths, focusing the coaxially aligned beams onto a first pattern located on the top surface of a substrate and a second pattern located below the first pattern, and capturing images of the first and second patterns. For example, the imaging system may include a first light source, a second light source, an alignment module, a coaxial module, a first image capturing device, and a second image capturing device.

[0060] The technology includes a coaxial imaging system. In some embodiments, a first wavelength of light, such as ultraviolet (UV) light, and a second wavelength of light, such as infrared (IR) light, are coaxially directed to a target on a wafer. An image sensor captures images generated from both the UV and IR light. Using the images captured and superimposed on the same axis, comparisons can be made for exposure, inspection, alignment, or other processing. Although the UV and IR images are captured coaxially, the transmission to the image detector may or may not be coaxial. For example, the coaxially captured images may be optically separated and transmitted to separate image detectors, as described below.

[0061] This disclosure discloses methods for wafer alignment and through-wafer alignment inspection. The techniques described herein utilize a light source with wavelengths and power sufficient to tunnel through the wafer material to image alignment marks within or beneath the wafer. This through-wafer imaging provides an accurate and precise alignment mechanism independent of conventional alignment marks formed on the working surface of the wafer (e.g., the top surface or front side). Instead, reliable references can be repeatedly accessed by referring to patterns or grids within / below the wafer for accurate and precise alignment and subsequent patterning.

[0062] This invention utilizes through-wafer technology for wafer inspection and testing. The systems and methods described herein can identify overlay errors and defects in wafers, including inspection relative to a reference pattern and inspection of intermediate layers. In some embodiments, intermediate layers can be inspected using a light source with wavelengths and power sufficient to tunnel through the wafer material and focus on a patterned layer formed in the wafer but covered by subsequent wafer processing.

[0063] Using the technique described in this paper, it is no longer necessary to generate and regenerate alignment marks. Conventionally, there is no independent grid or board reference. Therefore, all overlay corrections must take into account different tools and correction features. Furthermore, the initial pattern set on the new wafer lacks an independent reference point. Instead, the initial pattern is set on the new wafer and assumed to be perfect, as if it were formed using excellent tools. However, in reality, such a blind trust is flawed. Many factors can affect the initial pattern, particularly, for example, drive motor accuracy and calibration curve errors. In this regard, a distortion map is used from the outset. Then, moving from mark A to mark B or moving between layers introduces and compoundes overlay errors.

[0064] Figure 2A illustrates an industrial problem related to coverage. Each arrow in this text has a starting point (e.g., 211a) corresponding to the position of a previous pattern and an ending point or arrowhead (e.g., 211a') corresponding to the position of a subsequent pattern. Therefore, when a subsequent pattern is formed above or alongside a corresponding previous pattern, each arrow represents a coverage value or coverage error. For example, in process 210A, there is no grid or board reference when the initial pattern is placed. Therefore, the starting point 211a of the first arrow may be misaligned, meaning the initial pattern may have placement errors, for example, relative to the wafer edge. Subsequent patterns then attempt to align based on their corresponding last pattern. As shown in Figure 2A, the starting point of a subsequent arrow (e.g., 211b) overlaps with the arrowhead (e.g., 211a') of the corresponding last or previous arrow. In some instances, degradation of alignment marks can lead to alignment errors in subsequent patterns placed using such degraded alignment marks. Note that downtime can occur even in theoretically perfect systems. For example, if the system patterning tolerance is + / - 4 nm, and each layer references the previous layer. Taking the reference layer as 0 error, the first layer could be offset by +4 nm. For the second layer alignment of the first layer, a offset of +4 nm would mean the second layer is now offset by +8 nm from the reference layer. There are also process factors that cause or mitigate stress throughout the manufacturing process, which can increase cumulative errors even when the original alignment marks are visible. These factors can cause downtime / alignment misalignment.

[0065] Furthermore, the alignment mark may be disrupted in step S220 of the process and repositioned without a reference mark. Similar to the starting point 211a, the starting point 221a of the new arrow may be misaligned. In the example of Figure 2A, the starting point 221a deviates from the arrow 211n'. The process continues by aligning subsequent patterns based on the corresponding last pattern until the alignment mark is disrupted again in step S230. Similarly, placement occurs without a reference mark, and the starting point 231a deviates from the arrow 221n'. As can be seen in Figure 2A, as the stack increases, coverage errors may accumulate, leading to poor manufacturing yield, device errors, etc. Note that process 210A is a non-limiting example. Other processes (e.g., 210B and 210C) may have different coverage values ​​(different arrows) and / or different steps.

[0066] Figure 2B illustrates overlay mitigation using a reference pattern according to an exemplary embodiment of this disclosure. Although not shown, using the techniques described herein, all patterns placed on the wafer are based on the same reference pattern. In some embodiments, a reference grid may be used and considered absolute, or more precisely, independent of any pattern on the wafer. In one embodiment, a (separate) reference grid is compared to the wafer when a new pattern is placed. For an initial pattern, this means that the pattern can be fitted to the reference grid. For subsequent patterns, this means that one or more patterns can be compared to the reference grid to calculate overlay correction to return the same alignment.

[0067] For example, in process 240, a reference pattern (not shown) is used to align with an initial pattern on the wafer. In one embodiment, the reference pattern can be positioned at a fixed location relative to the wafer surface, for example, by attaching a reference to the back side of the wafer or embedding the pattern within the wafer. Therefore, the starting point 241a of the first arrow is aligned with the fixed reference pattern, its position shown as line 250. Subsequent patterns are also aligned using the reference pattern. New photoresist layers can be formed for each subsequent pattern, but due to the reference pattern, it is not necessary to form and / or destroy alignment marks on the wafer. As a result, the arrow is centered around line 250, meaning that subsequent patterns are aligned with the reference pattern. Therefore, as more and more layers are formed, coverage errors are less likely to accumulate. Note that in some embodiments, the reference pattern is located below the working surface of the wafer (e.g., the top surface or front side), on which subsequent patterns are formed. Therefore, the reference pattern is independent of the working surface of the wafer. In other words, the reference pattern is not affected by lithography processes performed on the working surface of the wafer, such as etching, deposition, chemical mechanical polishing, etc., to form the pattern.

[0068] Figure 3A shows a schematic diagram 300A of a wafer aligned using a reference pattern according to an exemplary embodiment of the present disclosure. As shown, the wafer 310 has a front side 311 (also referred to as the working surface) and a back side 319. In the example of Figure 3A, an imaging system 380 is used to image a photoresist layer 320 formed on the front side 311 and a reference pattern 351 located on the back side 319.

[0069] As shown in Figure 3A, the imaging system 380 includes a first beam 330 for imaging a top-side pattern (e.g., 321a) on the front side 311 of the wafer 310. The imaging system 380 also includes a second beam 340 configured to tunnel through the wafer 310 to image a reference pattern 351. The first beam 330 and the second beam 340 are configured to be coaxially aligned such that the image of the top-side pattern captured by the first beam 330 and the image of the reference pattern 351 captured by the second beam 340 can be analyzed to determine the location of the top-side pattern relative to the reference pattern 351.

[0070] In some embodiments, the images of the pattern and the reference pattern 351 are analyzed so that the coordinate position of the pattern relative to the reference pattern 351 can be determined. For example, vector analysis can be performed to determine the total offset by overlaying the images in the same physical space or by effectively overlaying them by comparing coordinate position data collected from the reference pattern 351 and the pattern. As a result, the pattern can be aligned using the reference pattern 351. For example, alignment can occur by moving a mask of the pattern image or moving the wafer relative to a fixed mask. In some embodiments, the photoresist layer 320 is exposed and a latent pattern 321a is formed in the photoresist layer 320. In one embodiment, the latent pattern 321a is then developed, thereby forming a solid pattern in the photoresist layer 320. In another embodiment, in a "step and repeat" or "step and scan" system, two beams and a photomask can be moved to another area of ​​the wafer 310, as indicated by the hollow arrow in FIG3A, and this process is repeated to form one or more latent patterns (e.g., 321n) in the photoresist layer 320. In such a case, the latent pattern is exposed separately but will be developed together.

[0071] Although not shown in Figure 3A, the imaging system 380 may include alignment optics in addition to a sensor or camera for capturing images generated by the first beam 330 and the second beam 340. The alignment optics are configured such that the first beam 330 and the second beam 340 are coaxially aligned to image different planes. In other words, the imaging system 380 can coaxially align two beams of different wavelengths (e.g., 330 and 340), focus the coaxially aligned two beams onto a top-side pattern (e.g., 321a) located on the front side 311 of the wafer 310 and a reference pattern (e.g., 351) located below the top-side pattern (e.g., 321a), and capture images of the top-side pattern (e.g., 321a) and the reference pattern (e.g., 351).

[0072] Referring again to FIG. 3A, reference pattern 351 is located on the back side 319 of wafer 310. In one embodiment, reference pattern 351 is formed on the back side 319 of wafer 310 and is thus fixed to the wafer throughout the wafer's processing. In another embodiment, reference pattern 351 is incorporated into a reference plate, such as reference plate 300B shown in FIG. 3B. In the example of FIG. 3B, reference plate 300B is a grid plate having nearly perfectly aligned 20-micron by 20-micron squares (e.g., 353). In this embodiment, the accuracy of the grid plate will determine the alignment capability of the patterning or inspection system. Therefore, the grid plate should be obtained from a manufacturer capable of forming grid plates within a predetermined manufacturing tolerance. Alternatively, reference plate 300B may contain at least one of dots, lines, corners, frames, numbers, markings, or any other pattern suitable for alignment purposes. Reference plate 300B may be attached to the back side 319 of wafer 310 or incorporated into a substrate support of a lithography tool, such as a scanner or stepper.

[0073] Although in the example of FIG. 3A, the reference pattern 351 is located on the back side 319 of the wafer 310, in another example, the reference pattern 351 may be disposed within the wafer 310. That is, the reference pattern 351 is disposed below the front side 311 of the wafer 310, whether below or within the wafer 310, such that the reference pattern 351 is independent of the front side 311 of the wafer 310 and the photoresist layer 320. Furthermore, the reference pattern 351 is independent of any pattern (e.g., 321a) formed on or to be formed on the front side 311 of the wafer 310.

[0074] In a non-limiting example, a photomask containing a pattern (not shown) is positioned on the front side 311 of wafer 310. The photomask may be configured to directly contact wafer 310 in a contact printing system. In a proximity printing system or a projection printing system, the photomask may be positioned away from wafer 310. Before printing the pattern onto wafer 310, image analysis performed by reference pattern 351 and imaging system 380 is used to align the photomask, or more precisely, the pattern.

[0075] In one embodiment, the pattern is an initial pattern and can therefore be aligned with a reference pattern. For example, the reference pattern may contain a grid of lines such that the pattern is aligned with the grid of lines. In another embodiment, the pattern is a subsequent pattern positioned above or alongside a previous pattern. In some embodiments, to align the subsequent pattern, the imaging system 380 images the previous pattern relative to the reference pattern, and also images the subsequent pattern relative to the reference pattern using the imaging system 380. The coverage value of the second pattern relative to the first pattern can then be determined. Further details regarding image analysis and coverage calculation will be illustrated in Figures 4A-4D.

[0076] Figures 4A and 4B illustrate image analysis with and without a reference pattern, respectively, according to exemplary embodiments of the present disclosure. In Figure 4A, the images of the two patterns are superimposed to produce image 400A. In this example, image 400A includes a plurality of lines and dots from a first pattern (e.g., 410) represented in black, and lines and dots from a second pattern (e.g., 420) represented in gray. This figure shows that without a reference pattern, it is difficult to accurately align the lines and dots of one pattern with the lines and dots of another pattern.

[0077] The embodiment of image 400B in Figure 4B is similar to the embodiment of image 400A in Figure 4A, except that image 400B further includes an overlaid image of a reference pattern. In a non-limiting example, the reference pattern comprises an array of boxes (e.g., 430). This figure shows that the array of boxes can be used to guide the alignment of two patterns. In other embodiments, the reference pattern may comprise at least one of dots, lines, corners, boxes, numbers, markers, or any other pattern suitable for alignment purposes.

[0078] As described above, reference patterns can be fixed to the wafer (e.g., by bonding to the back side or embedding within the wafer) or separated from the wafer (e.g., by using a grating or by bonding the reference to a substrate support). The advantage of a fixed reference is that each individual pattern can be aligned on the wafer using only the fixed reference pattern, regardless of the relative arrangement of other patterns previously formed on the wafer. However, special handling of the wafer used to provide the fixed reference may be undesirable; in such cases, a separate reference, such as a grating, can be used. When using a separate grating, the overlap between the two patterns can be calculated to account for the change in the wafer's position relative to the grating as the wafer moves between tools or processes.

[0079] According to an exemplary embodiment of this disclosure, FIG4C shows a detailed view of rectangle 400C in FIG4B, and FIG4D further shows the overlay calculation using the reference pattern in FIG4C. FIG4C and 4D show how the overlay values ​​of two patterns can be calculated using independent reference patterns. This is accomplished by knowing each common reference in the coordinate system and using that reference to determine the "position" of each pattern in that coordinate system. Once the distance between each layer is known, for example, the vector calculation required to extract the overlay values ​​can be performed using simple vector algebra. We can think of this as a mix-match overlay (MMO) using a golden tool that is always present for the one below the pedestal itself.

[0080] In a non-limiting example, reference point M of the reference pattern is used to calculate the overlap value between point N of the first pattern and point P of the second pattern. In this document, boxes (e.g., 430) or lines (e.g., AA', BB', CC', DD', EE', and FF') are the grid lines of the reference pattern. Point M is the corner of box 430 and the intersection of lines AA' and DD'. Point N is the intersection of lines BB' and EE'. Point P is the intersection of lines CC' and FF'. This reference pattern can be imaged and precisely superimposed on the image of one or more patterns (e.g., the first and second patterns). Therefore, by analyzing the superimposed image, the coordinate positions of the patterns can be identified, and then superposition calculations can be performed.

[0081] In a non-limiting example, box 430 provides a reference point M that is absolute or independent of the wafer. By superimposing a first pattern on the reference pattern, the coordinate difference or vector from the reference point M to a point N in the first pattern is determined. Similarly, by superimposing a second pattern onto a reference pattern, the coordinate difference or vector distance from the reference point M to point P in the second pattern is determined. Then, the coverage value between point N and point P can be calculated. : This coverage value helps determine the setting of the second pattern relative to the reference grid, while also taking into account process deviations that affect the setting of the first pattern.

[0082] Furthermore, given that the coordinate positions of points from the first pattern (e.g., N) and the coordinate positions of points from the second pattern (e.g., P) are known, the coverage value or offset from the first pattern to the second pattern can be determined. This coverage value can then be used to set a second or subsequent pattern to correct the coverage relative to an independent reference grid. In some embodiments, a reference image that is uniform for each image comparison enables the correction of adjacent patterns based on an initial line or absolute reference while maintaining coverage correction. Note that in some embodiments, image overlay is not necessary. Coordinate position data can be collected from a reference board and the working surface of the wafer, and vector analysis can then be used to determine the total offset or coverage value.

[0083] Figures 5A, 5B, and 5C show top views of the wafer stage 510 at an intermediate step in the stitching process, according to an embodiment of this disclosure. Figure 5D shows an enlarged view of the dashed rectangle 500D in Figure 5C, according to an embodiment of this disclosure. Although not shown, the wafer stage 510 can be exemplified as part of the lithography tool of the EUV tool 100 shown in Figure 1A. The lithography tool may also include a mask stage for holding a mask.

[0084] In Figure 5A, at least one wafer 520 is mounted on a wafer stage 510. The at least one wafer 520 has a back side facing the wafer stage 510 and a working surface to be patterned. In some embodiments, a photoresist layer is deposited on the working surface of the wafer 520. The photoresist layer contains photoreactive species configured to form a composite pattern.

[0085] Although not shown in Figure 5A, the reference pattern is positioned below the working surface of wafer 520. This reference pattern corresponds to the reference patterns in Figures 3A-3B and 4A-4D. The descriptions have been provided above and will be omitted here for simplicity. Note that the shape and size of the wafer stage 510, the shape and size of the wafer 520, and the relative positions of the wafers 520 are flexible and can be customized to meet specific manufacturing requirements.

[0086] Figure 5B shows a wafer stage 510 after exposing wafer 520 to a first pattern of photochemical radiation. In some embodiments, the first pattern of photochemical radiation is aligned with a first region (also referred to as a first die or first field) 521 of wafer 520 using a reference pattern. The first region 521 is then exposed to the first pattern of photochemical radiation by a first mask (not shown) held on a mask stage. Thus, a first latent image is printed in a photoresist layer in the first region 521.

[0087] In some embodiments, a plurality of wafers 520 (e.g., twenty-five wafers) are mounted in a plurality of slots (e.g., twenty-five slots) on a wafer stage 510. A first region 521 of the plurality of wafers 520 may be exposed to a first pattern of photochemical radiation during a first operation. In a non-limiting example, in a "step-repeat" or "step-scan" system, a first mask is configured to print a first latent image in a photoresist layer on a wafer at a time. A reference pattern may be disposed below the working surface of each wafer 520 and used to align the first mask prior to exposure.

[0088] In the examples of Figures 5A-5D, the first pattern of the first mask is a first component of the composite pattern. The second mask may contain a second pattern, which is a second component of the composite pattern. The first and second patterns are adjacent to each other. In a non-limiting example, the first and second patterns are combined to complete the composite pattern. Therefore, the wafer 520 has a second region (also referred to as a second die or second field) 522 adjacent to the first region 521. The photoresist layer is configured to form the second pattern in the second region 522.

[0089] In some embodiments, a plurality of wafers 520 may be removed from the wafer stage 510 and transferred to a wafer storage library (not shown) of a lithography tool. While the plurality of wafers 520 are temporarily held in the wafer storage library, a mask stage may be switched from a first mask to a second mask. The plurality of wafers 520 are then transferred back to the wafer stage 510. In some embodiments, the wafer storage library may not be necessary. The plurality of wafers 520 may be located on the wafer stage 510 when the mask stage switches from the first mask to the second mask. Further, in some embodiments, the wafer stage 510 may be moved to a different optical system for the second mask. In a non-limiting example, EUV light is exposed through the first mask, and DUV light is exposed through the second mask.

[0090] Figure 5C shows a wafer stage 510 after wafer 520 is exposed to a second pattern of photochemical radiation through a second mask. In some embodiments, a reference pattern is used to align the second pattern of photochemical radiation with a second region 522 of wafer 520. The second region 522 is then exposed to the second pattern of photochemical radiation through a second mask held on the mask stage. Thus, a second latent image is printed in a photoresist layer in the second region 522. Similar to the first operation, in some embodiments, the second regions 522 of a plurality of wafers 520 may be exposed to the second pattern of photochemical radiation in a second operation.

[0091] In some embodiments, a first coverage value is measured between a first pattern and a reference pattern to align the first pattern and update the first coverage value. Then, a second coverage value is measured between a second pattern and the reference pattern. Subsequently, a third coverage value is calculated between the first and second patterns based on the first and second coverage values. The second pattern is then aligned with the first pattern using the third coverage value.

[0092] In some embodiments, images of a reference pattern, a first pattern, and a second pattern are captured. The images of the reference pattern and the first pattern are superimposed to form a first superimposed image to measure a first coverage value. The images of the reference pattern and the second pattern are superimposed to form a second superimposed image to measure a second coverage value. Alternatively, the image of the second pattern can be superimposed on the first superimposed image to measure the second coverage value. Note that in some embodiments, superimposed images may not be necessary. Coordinate position data can be collected from a reference board and the working surface of the wafer, and vector analysis can then be used to determine the corresponding total offset or coverage value.

[0093] In some embodiments, a first coordinate position of the first pattern relative to a reference pattern is identified. A second coordinate position of the second pattern relative to the reference pattern is also identified. An overlay value is then calculated using the first and second coordinate positions. The overlay value is used to align the second pattern with the first pattern.

[0094] Furthermore, the first and second patterns of photochemical radiation can independently include EUV wavelengths (e.g., 13.5 nm) or DUV wavelengths (e.g., 193 nm). In one example, both the first and second patterns of photochemical radiation include EUV wavelengths. In another example, the first pattern of photochemical radiation includes EUV wavelengths, while the second pattern includes DUV wavelengths. Therefore, the wafer stage 510 can be moved to different optical systems used for the second shield.

[0095] Figure 5D shows an enlarged view of the dashed rectangle 500D in Figure 5C. In one embodiment, Figures 5C and 5D show latent images of the first and second patterns. In another embodiment, Figures 5C and 5D show the first and second patterns after the photoresist layer has been developed.

[0096] In a non-limiting example, the first pattern in the first region 521 includes first lines 541 (e.g., 541a and 541b). The second pattern in the second region 522 includes second lines 551 (e.g., 551a and 551b). A boundary line 530 is located between the first region 521 and the second region 522. The boundary line 530 is also referred to as the field boundary.

[0097] During stitching, it may be necessary to connect the first feature of the first pattern with the second feature of the second pattern at boundary line 530 to form a composite feature. In other words, when a composite pattern is divided into two fields (or two patterns), the original feature crossing the field boundary may be divided into two features. When the two fields are stitched together, these two features may need to be connected to each other to form the original feature. However, alignment errors or overlay errors may cause continuity problems. For example, in Figure 5D, the first line 541a and the second line 551a are not connected; the first line 541b and the second line 551b are not connected.

[0098] Furthermore, in some embodiments, the in-field alignment mark may optionally be formed outside the device region or under the photoresist layer within the device region. In a non-limiting example, the in-field mark includes a plus sign 531 crossing the boundary line 530. Both the first pattern and the second pattern can be aligned with the in-field alignment mark using a reference pattern. Note that in some embodiments, the in-field alignment mark is not required, whether outside the device region or under the photoresist layer within the device region.

[0099] Although only two fields are involved in the splicing process in the examples of Figures 5A-5D, in other examples, wafer 520 may contain more than two fields. Therefore, more masks may be required. Latent images can be printed separately, but developed together to form the corresponding composite pattern.

[0100] Figure 6 shows a flowchart of a process 600 for processing a wafer according to an exemplary embodiment of the present disclosure. Process 600 begins at step S610, in which a reference pattern located below the working surface (e.g., the front or top surface) of the wafer is identified, for example, via quantum tunneling imaging, IR transmission imaging, etc.

[0101] Because the reference pattern is positioned below the working surface of the wafer, it can be independent of the wafer's working surface. In this context, "reference pattern independent of the wafer's working surface" means that the reference pattern is not affected by any manufacturing processes performed on the wafer's working surface. Such manufacturing processes typically include lithography processes such as etching, deposition, and chemical mechanical polishing. As a result, the reference pattern is also independent of one or more patterns formed on the wafer's working surface.

[0102] The reference pattern includes at least one of dots, lines, corners, frames, triangles, numbers, marks, or any other pattern suitable for alignment purposes. One embodiment includes using a grid plate under the wafer, but this is not limiting. The grid plate may have grid lines and frames formed by the grid lines. The intersections of the grid lines or frame corners can be used as reference points for coverage calculations, as shown in Figure 4D. For example, a 20-micron by 20-micron square grid plate with near-perfect alignment, manufactured by precision machining, can be used.

[0103] In some embodiments, a reference pattern is incorporated into a reference plate located on the back side of the wafer. In one example, the reference plate is adhered to the back side of the wafer. Thus, the reference plate and the wafer can function as a module. In another example, the reference plate is incorporated into a substrate holder of a photolithography scanner or stepper. When a wafer without a pattern is placed above the reference plate, the wafer will be substantially aligned with the reference plate. When a wafer with an existing pattern is placed on the reference plate, the existing pattern and the reference plate can be coaxially aligned. In conventional lithography processes, measurement errors caused by wafer back-side scratches, back-side dust, and / or substrate deformation due to heat can affect overlay, but conventional overlay systems typically ignore these problems. The techniques described herein include a separate reference plate and high spatial resolution to overcome these problems.

[0104] In some embodiments, a reference pattern is formed on the back side of the wafer. Other techniques may involve embedding the reference pattern (e.g., grid lines) into the wafer, for example, using a radioactive or fluorescent material. In one example, the reference pattern is formed on the surface of the wafer, and then a silicon and / or silicon oxide layer is deposited thereon. For example, the silicon and / or silicon oxide layer may have a thickness of 1-5 micrometers, such that the reference pattern is effectively "embedded" in the wafer, and the pattern may be formed on the silicon and / or silicon oxide layer. In another example, the reference pattern is formed on the back side of the wafer before a protective layer, such as silicon or silicon oxide, is formed on the back side of the wafer. Thus, the reference pattern is embedded in the wafer. In another example, the reference pattern may be formed on the front side of a carrier wafer before the front side of the carrier wafer is bonded to the back side of the target wafer. As a result, the reference pattern is sandwiched between the carrier wafer and the target wafer, which together operate as a single wafer.

[0105] Process 600 then proceeds to step S620 by exposing the wafer to a first pattern of photochemical radiation. The first pattern is a first component of a composite pattern, and the first pattern of photochemical radiation is aligned using a reference pattern. In step S630, the wafer is exposed to a second pattern of photochemical radiation. The second pattern is a second component of a composite pattern and is exposed adjacent to the first pattern. The second pattern of photochemical radiation is aligned with the first pattern of photochemical radiation using a reference pattern.

[0106] In some embodiments, a first coverage value is measured between a first pattern and a reference pattern to align the first pattern and update the first coverage value. A second coverage value is measured between a second pattern and a reference pattern. A third coverage value is calculated between the first and second coverage values. The second pattern is then aligned with the first pattern using the third coverage value.

[0107] In some embodiments, images of a reference pattern and a first pattern are captured. Image analysis is performed to measure a first coverage value to determine the setup of the first pattern. For example, image analysis may be performed by superimposing images of the reference pattern and the first pattern and identifying the coordinate position of the first pattern relative to the reference pattern. In some embodiments, image superposition may not be necessary. Coordinate position data may be collected from a reference plate and the working surface of the wafer, and vector analysis can then be used to determine the total offset or coverage value. In some embodiments, image analysis is performed in real time, allowing the setup of the first pattern to be adjusted in real time. Furthermore, a second coverage value can be measured similarly.

[0108] In some embodiments, a first coordinate position of the first pattern relative to a reference pattern is identified. A second coordinate position of the second pattern relative to the reference pattern is also identified. An overlay value is then used using the first and second coordinate positions. Therefore, the second pattern is aligned with the first pattern using the overlay value.

[0109] In some embodiments, a photoresist layer is formed on the working surface of a wafer. The photoresist layer contains photoreactive species configured to form a composite pattern. The photoresist layer may be inactive for quantum tunneling imaging or IR transmission imaging. In some embodiments, the photoresist layer is developed such that features of a first pattern are connected to features of a second pattern.

[0110] In some embodiments, the field alignment marks may optionally be formed outside the device region or under the photoresist layer within the device region. The first pattern is aligned with the field alignment marks using a reference pattern, and the second pattern is also aligned with the field alignment marks using a reference pattern.

[0111] In some embodiments, the wafer is exposed to one or more additional photochemical radiation patterns. These additional patterns are additional components of a composite pattern. One or more additional photochemical radiation patterns are aligned using a reference pattern.

[0112] In some embodiments, the first pattern of photochemical radiation includes an EUV wavelength (e.g., 13.5 nm) or a DUV wavelength (e.g., 193 nm). The second pattern of photochemical radiation includes an EUV wavelength (e.g., 13.5 nm) or a DUV wavelength (e.g., 193 nm). Therefore, the first and second patterns of photochemical radiation may contain the same light or two different lights.

[0113] In some embodiments, when a plurality of wafers are positioned on a stage of a lithography tool, the plurality of wafers are exposed to a first pattern of photochemical radiation in a first run. The wafers are then transferred from the stage to a wafer storage container of the lithography tool. A mask is switched for a mask stage of the lithography tool. The wafers are then transferred from the wafer storage container back to the stage. Then, in a second run, the wafers are exposed to a second pattern of photochemical radiation. In some embodiments, a wafer storage container may not be necessary. The plurality of wafers may be positioned on the stage when the mask stage switches from the first mask to the second mask. Further, in some embodiments, the stage may be movable to a different optical system for the second mask. In a non-limiting example, the first pattern of photochemical radiation comprises EUV light, and the second pattern of photochemical radiation comprises DUV light.

[0114] In some embodiments, the wafer is exposed to a first pattern of photochemical radiation through a first mask having a first pattern to print a first latent image on the wafer. For example, in Figures 1B-1C, the first latent image is scaled down compared to the first pattern on the first mask. Similarly, the wafer is exposed to a second pattern of photochemical radiation through a second mask having a second pattern to print a second latent image on the wafer. The second latent image is scaled down compared to the second pattern on the second mask.

[0115] In a non-limiting example, a reference plate positioned beneath the wafer is imaged via quantum tunneling imaging, IR transmission imaging, or the like. The reference plate includes a reference pattern. A first pattern of photochemical radiation is aligned using the reference pattern. The first pattern is a first component of a composite pattern. A first field region of the wafer is exposed to the first pattern of photochemical radiation. A second pattern of photochemical radiation is aligned using the reference pattern. The second pattern is a second component of a composite pattern. A second field region of the wafer is exposed to the second pattern of photochemical radiation, wherein the second field region is adjacent to the first field region.

[0116] In some embodiments, light projection may also be used. For example, the reference object may be a projected grid, which is not a physical entity existing in the wafer, on the substrate support, or as a grid plate beneath the substrate support. In some embodiments, the reference pattern may be a combination of physical markings and light projection. For example, physical reference markings may be provided on the peripheral area of ​​the substrate support not covered by the wafer disposed on the substrate support, and light projection may complete the reference pattern in the area of ​​the wafer, making tunneling potentially unnecessary.

[0117] For reference plates located under the wafer, embedded marks within the wafer, or embedded marks on the back surface of the wafer, quantum tunneling imaging, IR transmission imaging, etc., are used to image the reference pattern, and then compare it with the pattern formed on the working surface of the wafer.

[0118] Therefore, a separate reference pattern can be used for patterning. The reference pattern can be considered absolute in one approach and relative in another. For example, the reference pattern can maintain or retain fixed grid lines (or points, corners, frames, or any other suitable shape) and remain unchanged despite numerous deposition and etching steps on the wafer. In one embodiment, this can be a grid plate integrated with a pedestal or wafer support. In this way, the grid plate is absolute because the same solid grid plate is used throughout the wafer processing, but relative because the solid grid plate is not fixed to the wafer itself and can move relative to the wafer throughout the wafer processing. Although each time a given wafer is set on the pedestal, it may be in a different position or orientation than previously set; this is irrelevant. For a given new pattern to be set or exposed, the wafer is imaged using the reference grid. The reference grid can then provide relative reference points for identifying vectors leading to two or more points, thereby allowing vector analysis to be used to calculate overlay correction adjustments in the next exposure. That is, the process shown in Figures 4C-4D can be used to mathematically correct for changes in the relative positions of the wafer and the grating, so that the grating can operate in the same way as, for example, a fixed reference embedded in the wafer.

[0119] The IR and UV sensors and sources are conventionally available and applicable to the embodiments described herein. In a non-limiting example, the FLIR X8500 MWIR (Teledyne FLIR LLC, Oregon, USA) is a high-speed, high-resolution MWIR camera that can be used herein. For the sensor, a DataRay (DataRay Inc., California, USA) camera sensor can be used. Solid-state lasers from Optowaves (Optowares Inc., Massachusetts, USA), such as pumped nanosecond lasers for surface imaging, can be used. For the IR source, an IR-tunable quantum cascade laser from Pranalytica, Inc. (California, USA) can be used. These are illustrative components. Other available systems may be substituted.

[0120] The technique may include periodic calibration of the relative positions of IR and UV, also known as red and blue relative position calibration. It is beneficial to keep the relative positions of IR and UV within the sensor's dynamic range, which is in the tens and quite forgiving for this purpose. However, normalization can be accomplished using stage artifacts of known relative transmittance imaged as needed. For example, once a day, making any relative intensity normalization easy to perform. Offset calibration caused by relative position or TIS tools is common in metrology stations. As measurements are made, the relative positions are recalibrated instantaneously relative to the grid. A significant advantage of this system is that it always has an instantaneous absolute reference. Digital image capture and regression can be used.

[0121] When using deep ultraviolet (DUV) light, photoresist damage is negligible. For example, the 250 μm field of view here corresponds to approximately 60 nm per pixel in a 4K resolution scenario, which is sufficient for a resolution with a 0.1 nm alignment error measurement. Sufficient light source intensity mitigates any shading of the metal layer.

[0122] To address potential concerns regarding the CD variation effect of the photoresist layer, the technique presented in this paper extracts the pattern coordinates without the CD variation effect of the photoresist layer and the underlying pattern (the metallic photoresist pattern covers most of the via pattern). Note that the CD variation effect of the photoresist layer is always an alignment issue and is consistently ignored by coverage measurement teams because it is disregarded in relevant cases. The technique presented in this paper is significantly improved because the pattern itself provides a much better pattern setup indicator than alignment marks suffering from CD astigmatism and Zernike-induced pattern offset.

[0123] The techniques described herein include detection systems and methods. The techniques described herein can be used to visualize wafers according to their design. Wafer scanning and imaging systems are used, which involve imaging through the wafer to a pattern beneath or within the wafer. This involves using light of wavelengths and intensities sufficient for quantum tunneling or transmission through the wafer. The techniques described herein can utilize quantum cascade lasers and visible light detection to provide alignment less than nanometers. The detection techniques described herein can image and analyze overlays and defects without using conventional overlays and alignment marks. As scaling continues, alignment marks on the wafer become too large and have an inherent optical distortion sensitivity different from the main pattern, making them unstable.

[0124] The technique described in this paper eliminates the need for conventional overlay markings. The top frame is now patterned, and the bottom frame is directly beneath the wafer. This technique offers a completely different overlay paradigm that eliminates the need for cleanup, loss of real estate, complex scribing designs to improve silicon area utilization, and complex integration for alignment marks. Best of all, unlike alignment marks, the reference mark is unaffected and unremoved by adverse processes in the manufacturing apparatus, as alignment marks are typically subject to such processes. Overlay setup accuracy can now also be measured from the first layer, as the first reference layer is now not only nearly perfect every time but is always hidden beneath the pedestal.

[0125] As a non-limiting embodiment, a highly accurate and precise grid plate can be used. One example could be a grid plate with nearly perfectly aligned 20 μm by 20 μm squares. The technique then uses wavelengths of several μm to resolve the 20 μm grid reference points using a QCL optical system. Infrared resolution capability is sufficient for this, as resolution is a function of wavelength. 2-3 μm, accompanied by a resolution factor of 1.0 "k", is considered very easy and therefore allows for imaging of grid marks on the order of 2-3 μm. In the case where the grid marks are ten times larger than 20 μm, they are resolved accurately.

[0126] The technique described in this paper provides high positioning accuracy for reference boards. For example, a grid board with a 20-micron by 20-micron square can be set with sub-nanometer positioning accuracy or uncertainty. What makes the grid special is not the size of the markers, but the crucial knowledge of the accuracy or uncertainty of the reference markers being set to the sub-nanometer level. That is, although the square of the reference pattern is on the order of 20 microns, and the feature size of the pattern to be formed on the wafer can be on the order of several nanometers, a reference point of the square (e.g., point M in Figure 4C) rather than the entire square (e.g., box 430 in Figure 4C) can be used for coverage calculations. Since the coverage value between points N and P is calculated using point M as the reference point, the positional uncertainty of point M is incorporated into the calculated coverage value. When the calculated coverage value is on the order of several nanometers or more, the sub-nanometer positional uncertainty of point M is negligible. Therefore, ensuring the positional accuracy of the reference pattern is important and advantageous. Depending on the specific pattern to be formed in many applications, sub-nanometer positioning accuracy is highly desirable, but may not be necessary.

[0127] The techniques described herein provide real-time imaging, overlay calculation, and pattern alignment. The wafer's position can be actively determined using a reference pattern. The position of any previously formed pattern on the wafer's working surface can also be actively determined using a reference pattern. Calculations can then be used to adjust the position to be exposed. In related examples, when moving from one area of ​​the wafer to another (e.g., stepping), alignment marks need to be searched, and movement stopped while searching for alignment marks. Typically, images are acquired to adjust focus, and a stage can be positioned. This series of operations can be time-consuming, especially for "step-repeat" or "step-scan" systems in projection printing. However, in this disclosure, images are captured and analyzed in real-time to continuously determine relative position. In fact, each captured image is a snapshot of the overlay. We only need to track positional data from the reference pattern and digitally regenerate the high spatial term of the overlay map from the image analysis. Therefore, unlike related examples, there are no "stepping," "searching," "acquiring," "stopping," "positioning," or "focusing" functions. The techniques described herein enable high-speed measurement.

[0128] In some embodiments, a color filter may be used to detect only the fluorescence of the photoresist resin to enhance the pattern from the photoresist.

[0129] Specific details, such as the particular geometry of the processing system and the description of the numerous components and processes used therein, have been set forth in the preceding description. However, it should be understood that the techniques described herein may be implemented in other embodiments departing from these specific details, and that these details are for illustrative purposes and not for limiting purposes. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been presented for illustrative purposes to provide a thorough understanding. However, embodiments may be implemented without these specific details. Components having substantially the same functional structure are indicated by similar reference numerals, and therefore any redundant description may be omitted.

[0130] To aid in understanding the various embodiments, numerous techniques have been described as multiple discrete operations. The order of description should not be construed as implying that these operations necessarily depend on a specific order. In fact, these operations do not need to be performed in the order presented. The described operations may be performed in an order different from that of the embodiments described. In additional embodiments, numerous additional operations may be performed and / or these operations may be omitted.

[0131] As used herein, "substrate" or "wafer" generally refers to the object being processed according to the present invention. A substrate may contain any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a semiconductor wafer, a substrate structure of a photomask, or a layer, such as a thin film, on or covering a substrate. Therefore, a substrate is not limited to any particular substrate structure, lower or upper layer, patterned or unpatterned, but is contemplated to include any such layer or substrate structure, and any combination of layers and / or substrate structures. The description may refer to a particular type of substrate, but this is for illustrative purposes only.

[0132] Those skilled in the art will also understand that many variations can be made to the operation of the techniques described above while still achieving the same objective of the invention. Such variations are intended to be covered by the scope of this disclosure. In this regard, the description of the preceding embodiments of the invention is not intended to be limiting. Rather, any limitation on the embodiments of the invention is presented in the following claims.

[0133] 100: EUV tools 110: Radiation System 111: EUV light source 120: Shielding Platform 121: EUV mask 130: Optical Components 131: Projection optical elements 140: Wafer Stage 141: Wafer 160: Projection light mask 161: First Image 163: Second Image 165: Third Image 170: Projection optical elements 180: Projection Printing System 190: Wafer 191: Area 1 192: Second Region 210A: Manufacturing Process 210B: Process 210C: Process 211a: Starting point 211a': Arrow 211b: Starting point 211n': Arrow 221a: Starting point 221n': Arrow 231a: Starting point 240: Process 250: Line 300A: Schematic Diagram 300B: Reference Board 310: Wafer 311: Front 319: Dorsal side 320: Photoresist layer 321a: Pattern 321n: Pattern 330: First Beam 340: Second Beam 351: Reference Pattern 380: Imaging System 400A: Image 400B: Image 400C: Rectangle 410: First Pattern 420: Second Pattern 430: Box 500D: Dashed Rectangle 510: Wafer Stage 520: Wafer 521: Area 1 522: Second Zone 530: Boundary Line 531: Plus sign 541: First Line 541a: First Line 541b: First Line 551: Second Line 551a: Second line 551b: Second Line 600: Process S220: Steps S230: Steps S610: Steps S620: Steps S630: Steps

Claims

1. A pattern alignment method comprising: identifying a reference pattern positioned below a working surface of a wafer; exposing the wafer to a first pattern of photochemical radiation, the first pattern being a first component of a composite pattern, wherein the first pattern of photochemical radiation is aligned using the reference pattern; exposing the wafer to a second pattern of photochemical radiation, the second pattern being a second component of the composite pattern and exposed adjacent to the first pattern, wherein the second pattern of photochemical radiation is aligned using the reference pattern to the first pattern of photochemical radiation; forming a photoresist layer on the working surface of the wafer, wherein the photoresist layer includes a photoreactive species configured to form the composite pattern; and developing the photoresist layer such that a first feature of the first pattern is connected to a second feature of the second pattern.

2. The pattern alignment method of claim 1 further includes: measuring a first coverage value between the first pattern and the reference pattern to align the first pattern; measuring a second coverage value between the second pattern and the reference pattern; calculating a third coverage value between the first pattern and the second pattern based on the first coverage value and the second coverage value; and aligning the second pattern with the first pattern using the third coverage value.

3. The pattern alignment method of claim 2 further includes: capturing an image of the reference pattern, an image of the first pattern, and an image of the second pattern; measuring the first coverage value by analyzing the image of the reference pattern and the image of the first pattern; and measuring the second coverage value by analyzing the image of the reference pattern and the image of the second pattern.

4. The pattern alignment method of claim 1 further includes: identifying a first coordinate position of the first pattern relative to the reference pattern; identifying a second coordinate position of the second pattern relative to the reference pattern; calculating an overlay value using the first coordinate position and the second coordinate position; and aligning the second pattern with the first pattern using the overlay value.

5. The pattern alignment method of claim 1 further comprises: forming an in-field alignment mark outside a device region or under the photoresist layer in the device region; aligning the first pattern with the in-field alignment mark using the reference pattern; and aligning the second pattern with the in-field alignment mark using the reference pattern.

6. The pattern alignment method of claim 1 further includes: exposing the wafer to one or more additional patterns of photochemical radiation, the one or more additional patterns being additional components of the composite pattern, wherein the one or more additional patterns of photochemical radiation are aligned using the reference pattern.

7. The pattern alignment method of claim 1 further comprises: when a plurality of wafers are placed on a wafer stage of a lithography tool, exposing the plurality of wafers to the first pattern of photochemical radiation in a first operation; transferring the wafers from the wafer stage to a wafer storage of the lithography tool; switching a mask for a mask stage of the lithography tool; transferring the wafers from the wafer storage to the wafer stage; and exposing the wafers to the second pattern of photochemical radiation in a second operation.

8. The pattern alignment method of claim 1 further comprises: when a plurality of wafers are placed on a wafer stage of a lithography tool, exposing the plurality of wafers to the first pattern of photochemical radiation in a first operation; when the wafers are on the wafer stage, switching a mask for a mask stage of the lithography tool; and when the wafers are on the wafer stage, exposing the wafers to the second pattern of photochemical radiation in a second operation.

9. The pattern alignment method of claim 1 further comprises: exposing the wafer to the first pattern of photochemical radiation through a first mask having the first pattern, so as to print a first latent image on the wafer, such that the first latent image is scaled down compared to the first pattern on the first mask; and exposing the wafer to the second pattern of photochemical radiation through a second mask having the second pattern, so as to print a second latent image on the wafer, such that the second latent image is scaled down compared to the second pattern on the second mask.

10. The pattern alignment method as described in request item 1, wherein: The first pattern of photochemical radiation includes an extreme ultraviolet (EUV) wavelength or a deep ultraviolet (DUV) wavelength, and the second pattern of photochemical radiation includes an EUV wavelength or a DUV wavelength.

11. The pattern alignment method of claim 1, wherein the reference pattern is incorporated in or attached to a reference plate located on or attached to the back side of the wafer.

12. The pattern alignment method of claim 1, wherein the reference pattern is incorporated in a reference plate, which is incorporated in a substrate holder of a lithography scanner or stepper.

13. The pattern alignment method of claim 1, wherein the reference pattern is formed on the back side of the wafer or embedded in the wafer.

14. The pattern alignment method of claim 1, wherein the reference pattern comprises radioactive or fluorescent material.

15. The pattern alignment method of claim 1, wherein the reference pattern comprises at least one of a dot, line, angle, frame, triangle, number or mark.

16. The pattern alignment method of claim 1 further includes identifying the reference pattern located below the working surface of the wafer via quantum tunneling imaging or infrared (IR) transmission imaging.

17. The pattern alignment method of claim 1, wherein the reference pattern is projected onto the surface of the wafer.

18. A pattern alignment method comprising: imaging a reference plate positioned beneath a wafer via quantum tunneling imaging or infrared (IR) transmission imaging, the reference plate including a reference pattern; aligning a first pattern of photochemical radiation using the reference pattern, the first pattern being a first component of a composite pattern; exposing a first field of the wafer to the first pattern of photochemical radiation; aligning a second pattern of photochemical radiation using the reference pattern, the second pattern being a second component of the composite pattern; and exposing a second field of the wafer to the second pattern of photochemical radiation, wherein the second field is adjacent to the first field.

19. A pattern alignment method comprising: identifying a reference pattern positioned below a working surface of a wafer; exposing the wafer to a first pattern of photochemical radiation, the first pattern being a first component of a composite pattern, wherein the first pattern of photochemical radiation is aligned using the reference pattern; and exposing the wafer to a second pattern of photochemical radiation, the second pattern being a second component of the composite pattern and exposed adjacent to the first pattern, wherein the second pattern of photochemical radiation is aligned using the reference pattern to the first pattern of photochemical radiation, wherein the reference pattern is incorporated in or attached to a reference plate located on or attached to the back side of the wafer.

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