Synchronization of RF generators

Abstract

Systems and methods for synchronizing radio frequency (RF) generators are described. One method includes receiving a first recipe set via a first RF generator, the first recipe set including information about a first complex pulse block for operating the first RF generator. The method further includes receiving a second recipe set via a second RF generator, the second recipe set including information about a second complex pulse block for operating the second RF generator. Upon receiving a digital pulse signal, the method includes executing the first recipe set and executing the second recipe set. The method further includes outputting a first pulse block from the first complex pulse block in synchronization with a synchronization signal based on the first recipe set. The method also includes outputting a first pulse block from the second complex pulse block in synchronization with a synchronization signal based on the second recipe set.

Description

[Technical Field]

[0001] This embodiment relates to a system and method for synchronizing a radio frequency (RF) generator. [Previous Technology]

[0002] The prior art description provided herein is intended to generally present the context of the disclosed content. The achievements of the inventors listed in this case within the scope described in this prior art section, as well as embodiments of the specification that may not have been qualified as prior art at the time of application, are not intended or implied to be recognized as prior art against the content of this disclosure.

[0003] The plasma tool includes multiple radio frequency (RF) generators. The RF generators are coupled to a plasma chamber. A substrate is placed in the plasma chamber. The RF generators generate RF signals supplied to the plasma chamber to generate plasma, which is used to process the substrate.

[0004] Many substrates are processed using RF generators and plasma chambers. The goal is to process the substrates in an ideal manner to achieve the desired results.

[0005] It is under these circumstances that the embodiments described in the disclosure of this case came into being. [Summary of the Invention]

[0006] The embodiments disclosed provide systems, apparatus, methods, and computer programs for synchronizing radio frequency (RF) generators. It should be understood that these embodiments can be implemented in numerous ways, such as as processes, apparatuses, systems, devices, or methods on a computer-readable medium. Several embodiments are described below.

[0007] The pulse scheme includes a pattern in which the pulse has two or more different power states, such as power levels, and repeats the pattern in increments of several seconds to hundreds of seconds. This pattern involves pulse blocks consisting of two or more power states with different durations and RF frequencies, with frequency tuning capability in each state. A pulse block comprises multiple pulse blocks linked together and then repeated. The duration of each pulse block is in the range of 10 to 1000 milliseconds (ms), and each pulse block can be different in terms of power and duration for each RF generator. Typically, a single synchronous pulse transistor-transistor logic (TTL) signal is used to synchronize all RF generators on a single rising edge. However, relying on a TTL signal to continuously set all pulse blocks for the RF generators may not account for time slip. Time slip may be a result of a failure of the internal clock of one of the RF generators.

[0008] The systems and methods described herein utilize analog signals to trigger high and low signals each time a pulse block, such as pulse block 1 or pulse block N, should begin, thereby providing timing for all RF generators to start and end pulse blocks together, and providing a way to continuously synchronize the RF generators in case one of the RF generators slips in the start time, where N is a positive integer.

[0009] Control of ionic and neutral fluxes is an important aspect of plasma processing, such as plasma etching, for ideally processing multiple substrates. Better control of ionic and neutral fluxes is achieved by pulsed RF generators in a controlled manner with a precise number of pulses or pulse blocks. A method is described for synchronizing RF generators via an Ethernet-controlled automation system (EtherCAT) (ECAT) or analog signals to start and stop each pulse block, ensuring that all RF generators are aligned at the start and stop times of the pulse blocks.

[0010] By using an analog signal derived from one of the RF generators or a single generator, a synchronization signal, such as a central clock, is generated and sent to all RF generators to notify each of the RF generators when to begin and end their respective pulse blocks. Information about the synchronization signal is embedded in an ECAT column. Furthermore, an analog signal is an example of a synchronization signal. The ECAT column can be used end-to-end to control the synchronization of the RF generators in generating their respective pulse blocks. By periodically sending pulses of the synchronization signal at the beginning of each pulse block, any time delay of any RF generator can be corrected for each clock cycle.

[0011] By providing a synchronization signal to indicate when the RF generator begins a pulse block, any timing errors caused by computer software, timers, or the internal clock of each RF generator are corrected. The systems and methods described herein provide a way to align the pulse blocks of the RF generator.

[0012] In one embodiment, a method for synchronizing an RF generator is described. The method includes receiving a first recipe set via a first RF generator, the first recipe set including information about a first complex pulse block for operating the first RF generator. The method further includes receiving a second recipe set via a second RF generator, the second recipe set including information about a second complex pulse block for operating the second RF generator. The method also includes receiving a digital pulse signal via the first and second RF generators. Once the digital pulse signal is received, the method includes executing the first recipe set via the first RF generator and executing the second recipe set via the second RF generator. The method further includes outputting a first pulse block from the first complex pulse block via the first RF generator in synchronization with a synchronization signal based on the first recipe set. The method includes outputting a first pulse block from the second complex pulse block via the second RF generator in synchronization with a synchronization signal based on the second recipe set.

[0013] In one embodiment, a system for synchronizing RF generators is described. The system includes a first RF generator configured to receive a first set of recipes, the first set of recipes including information about a first complex pulse block for operating the first RF generator. The system further includes a second RF generator configured to receive a second set of recipes, the second set of recipes including information about a second complex pulse block for operating the second RF generator. The first and second RF generators are configured to receive digital pulse signals. Once the digital pulse signals are received, the first RF generator is configured to execute the first set of recipes and the second RF generator is configured to execute the second set of recipes. During the execution of the first set of recipes, the first RF generator is configured to generate a synchronization signal and provide the synchronization signal to the second RF generator. The first RF generator is configured to output a first pulse block in the first complex pulse block in synchronization with the synchronization signal based on the first set of recipes. Once the synchronization signal is received, the second RF generator is configured to output a first pulse block in the second complex pulse block in synchronization with the synchronization signal based on the second set of recipes.

[0014] In one embodiment, a system for synchronizing RF generators is described. The system includes a first RF generator configured to receive a first set of recipes, the first set of recipes including information about a first complex pulse block for operating the first RF generator. The system includes a second RF generator configured to receive a second set of recipes, the second set of recipes including information about a second complex pulse block for operating the second RF generator. The system includes a host coupled to the first and second RF generators. The host is configured to generate a digital pulse signal and a synchronization signal. The first and second RF generators are configured to receive the digital pulse signal and the synchronization signal from the host. Once the digital pulse signal is received, the first RF generator is configured to execute the first set of recipes and the second RF generator is configured to execute the second set of recipes. Furthermore, once the synchronization signal is received, the first RF generator is configured to output a first pulse block in the first complex pulse block in synchronization with the synchronization signal based on the first set of recipes. Once the synchronization signal is received, the second RF generator is configured to output a first pulse block in the second complex pulse block in synchronization with the synchronization signal based on the second set of recipes.

[0015] Some advantages of the systems and methods described herein include reduced latency caused by the internal clock of the RF generator. A synchronization signal is generated. As an example, a synchronization signal is sent to the RF generator after a recipe signal is sent to it. Furthermore, a trigger signal for executing the recipe information within the recipe signal is sent to the RF generator. Upon receiving the trigger signal, the RF generator executes the recipe information. The current pulse block within the recipe information is generated at the moment the RF generator receives the pulse of the synchronization signal. The RF generator does not generate any remaining portion of the previous pulse block. When no remaining portion is generated and the current pulse block is generated, synchronization is achieved between the synchronization signal and the current pulse block. Synchronization is beneficial for achieving desired results in multi-wafer processing.

[0016] Other embodiments will become clear from the following detailed description in conjunction with the accompanying drawings.

Implementation Method

[0043] The following embodiments describe systems and methods for synchronizing radio frequency (RF) generators. It will be apparent that the embodiments of this case can be implemented without some or all of these specific details. In other respects, well-known process operations have not been described in detail in order not to cause unnecessary confusion regarding the embodiments of this case.

[0044] Figure 1A is a diagram illustrating an embodiment of a system 100 using a synchronization signal 102 to synchronize the operation of complex radio frequency (RF) generators (RFGs) 1, 2, and z, where z is a positive integer. Examples of the synchronization signal 102 include digital signals and analog signals. System 100 includes RF generators 1 to z, and a host 104. Examples of the host 104 include desktop computers, laptops, tablets, and smartphones. For example, examples of RF generators used herein include RF generators with an operating frequency of 100 kHz, RF generators with an operating frequency of 400 kHz, RF generators with an operating frequency of 2 MHz, RF generators with an operating frequency of 13.56 MHz, RF generators with an operating frequency of 27 MHz, and RF generators with an operating frequency of 60 MHz.

[0045] The host 104 includes a processor 106 and a memory device 108. For example, the processor used herein may be an application-specific integrated circuit (ASIC), a programmable logic element (PLD), a central processing unit (CPU), a microprocessor, or a microcontroller. Examples of memory devices include random access memory (RAM) and read-only memory (ROM). For illustrative purposes, the memory device may be flash memory, a hard disk, or a storage device, etc. The memory device may be an example of a computer-readable medium. The processor 106 is coupled to the memory device 108.

[0046] Processor 106 is coupled to RF generators 1 through 2. For example, processor 106 is coupled to RF generator 1 via transmission cable 110, to RF generator 2 via transmission cable 112, and to RF generator 2 via transmission cable 114. Examples of transmission cables include coaxial cables and Universal Serial Bus (USB) cables. For illustrative purposes, the transmission cables are used for data transmission in serial, parallel, or via the USB communication protocol.

[0047] Furthermore, RF generator 1 is coupled to RF generators 2 through z. For example, RF generator 1 is coupled to RF generator 2 via communication cable 116 and to RF generator z via communication cable 118. For illustration, RF generator 1 is used as the master generator and RF generators 2 through z are used as slave generators. In this way, RF generator 1 is coupled to each of RF generators 2 through z in a master-slave configuration. For example, examples of communication cables used herein include Ethernet cables. For example, examples of Ethernet cables used herein include twisted-pair cables. For illustration, the Ethernet cable is a 100BASE-TX™ or 100BASE-T4™ cable capable of transmitting data at speeds of 100 megabits per second (Mbps) or higher.

[0048] RF generator 1 has an output O1 coupled to RF cable RFC1, RF generator 2 has an output O3 coupled to RF cable RFC2, and RF generator z has an output Oz coupled to RF cable RFCz.

[0049] Two or more RF generators 1 to z are coupled to the same impedance matching network or to different impedance matching networks. For example, RF generators 1 and 2 are coupled to a first impedance matching network via their respective RF cables RFC1 and RFC2, while RF generator z is coupled to a second impedance matching network. As another example, RF generators 1 to z are coupled to the same impedance matching network via their respective RF cables RFC1 to RFCz. As yet another example, RF generators 2 and z are coupled to a first impedance matching network via their respective RF cables RFC2 and RFCz, while RF generator 1 is coupled to a second impedance matching network via RF cable RFC1.

[0050] For example, the impedance matching network used herein is an example of an impedance matching circuit comprising a network of circuit components such as inductors, resistors, and capacitors. For illustrative purposes, an impedance matching network has one or more series circuits and one or more shunt circuits. Each series circuit includes one or more inductors and one or more capacitors coupled in series with each other. Similarly, each shunt circuit includes one or more inductors and one or more capacitors coupled in series with each other, and one of the one or more inductors and one or more capacitors of the shunt circuit is coupled to ground potential. Each of the one or more shunt circuits is coupled to a corresponding one of the one or more series circuits. The terms impedance matching network, impedance matching circuit, impedance matching shield, matching shield, and matching are used interchangeably herein.

[0051] The processor 106 accesses recipe information for each of the RF generators 1 to z from the memory device 108 and sends the recipe information to the RF generator. For example, the processor 106 obtains recipe information for the RF generator 1 from the memory device 108, embeds the recipe information into recipe signal 120, and sends recipe signal 120 to the RF generator 1 via transmission cable 110. As another example, the processor 106 obtains recipe information for the RF generator 2 from the memory device 108, embeds the recipe information into recipe signal 122, and sends recipe signal 122 to the RF generator 2 via transmission cable 112. As yet another example, the processor 106 obtains recipe information for the RF generator z from the memory device 108, embeds the recipe information into recipe signal 124, and sends recipe signal 124 to the RF generator z via transmission cable 114.

[0052] As an example, the recipe information for an RF generator used herein includes several pulse blocks of an RF signal to be generated by the RF generator. An example of a pulse block is provided below. The recipe information for the RF generator further includes the time interval of each pulse cycle within the pulse block and several pulse cycles within each pulse block. Furthermore, the recipe information for the RF generator includes several states of the RF signal during each pulse cycle, the duty cycle of each of these states, and the variable level of each of these states. The duty cycle of a state is the time interval between the occurrence of that state. As an example, the variable level is a frequency level or a power level. For illustrative purposes, the variable level includes one or more power values ​​or one or more frequency values.

[0053] It should be noted that the pulse period is a time interval or time period. It should be further noted that, as an example, each pulse period of a pulse block of an RF signal has the same time interval. For illustrative purposes, the time interval of the first pulse period of a pulse block of an RF signal is equivalent to the time interval of the second pulse period of the pulse block.

[0054] Furthermore, as an example, the first variable level used for the first state is different from the second variable level used for the second state. For illustration, the first variable level is higher or lower than the second variable level. To further illustrate, the value of the first variable level excludes the value of the second variable level. When the first variable level is higher than the second variable level, the minimum value of all values ​​of the first variable level is higher than the maximum value of all values ​​of the second variable level. Each variable level includes one or more values ​​of a variable.

[0055] The processor systems of each RF generator 1 to z store the recipe information received from processor 106 in one or more memory devices of the RF generator. For example, the processor system of RF generator 1 receives recipe signal 120, retrieves recipe information from recipe signal 120, and stores the recipe information in one or more memory devices of RF generator 1. Similarly, the processor system of RF generator 2 receives recipe signal 122, retrieves recipe information from recipe signal 122, and stores the recipe information in one or more memory devices of RF generator 2. Furthermore, the processor system of RF generator z receives recipe signal 124, retrieves recipe information from recipe signal 124, and stores the recipe information in one or more memory devices of RF generator z.

[0056] Processor 106 transmits digital pulse signals via transmission cables to the processor systems of each of RF generators 1 to z. These digital pulse signals are, for example, trigger signals or transistor-to-transistor logic (TTL) signals. For example, processor 106 transmits TTL signal 128 to the processor system of RF generator 1 via transmission cable 110, TTL signal 128 to the processor system of RF generator 2 via transmission cable 112, and TTL signal 128 to the processor system of RF generator z via transmission cable 114. As an example, TTL signal 128 is non-periodic. For example, TTL signal 128 does not repeat after a predetermined time period. For illustrative purposes, TTL signal 128 is a single pulse that triggers the execution of the recipe sets 120, 122, and 124 by the respective RF generators 1, 2, and z.

[0057] In response to receiving the TTL signal 128, the processor systems of each RF generator 1 to 2 execute the recipe information received by the RF generator. For example, once the TTL signal 128 is received, the processor system of RF processor 1 executes the recipe information received in recipe signal 120 to generate RF signal 130 at output O1. Furthermore, once the TTL signal 128 is received, the processor system of RF processor 2 executes the recipe information received in recipe signal 122 to generate RF signal 132 at output O2. Once the TTL signal 128 is received, the processor system of RF processor 2 executes the recipe information received in recipe signal 124 to generate RF signal 134 at output O2.

[0058] Each RF generator 1 to 2 includes, for example, an internal clock, a clock source, a clock oscillator, a clock circuit, or a clock generator. The internal clock becomes inaccurate over time. For example, it may become inaccurate due to a malfunction or due to prolonged use. This inaccuracy results in the RF generator not generating pulse blocks of RF signals based on the recipe information received by the RF generator. Instead, the pulse blocks are delayed by one or more pulse cycles.

[0059] The processor system of RF generator 1 generates a synchronization signal 102 and transmits the synchronization signal to each of RF generators 2 to z via communication cables. For example, the processor system of RF generator 1 transmits the synchronization signal 102 to the processor system of RF generator 2 via communication cable 116, and transmits the synchronization signal 102 to the processor system of RF generator z via communication cable 118. In this way, the processor system of RF generator 1 controls the RF power supply of RF generator 1 to generate an RF signal 130 synchronized with the synchronization signal 102.

[0060] The processor systems of each RF generator 2 to z receive a synchronization signal 102 from RF generator 1 and control the generation of a pulse block of a corresponding RF signal 132 or 134 based on the pulses of the synchronization signal 102. As an example, the synchronization signal 102 includes timing information, which in this document sometimes refers to information about the synchronization signal 102. For illustration, the timing information includes the time for the pulse block to be generated by RF generator 2 and the time for the pulse block to be generated by RF generator z. As another illustration, the timing information also includes the time interval between two consecutive pulses of the synchronization signal 102. The time interval between two consecutive pulses provides the frequency at which the pulses of the synchronization signal 102 are generated. To further illustrate, the timing information includes one or more times when the logic level of the synchronization information 102 is 1 and one or more time intervals when the logic level of the synchronization information 102 is not 1, such as 0. As an example, the processor system of RF generator z receives timing information embedded in synchronization signal 102, such as the time when pulse blocks are to be generated by RF generator z.

[0061] Each RF generator 1 to z adjusts the generation or start time of its pulse block based on the synchronization signal 102. For example, after receiving the synchronization signal 102, RF generators 2 to z adjust the corresponding start time of their pulse blocks. For illustration purposes, RF generator 2 generates a pulse block at the same time as RF generator 2 receives the pulse of the synchronization signal 102. In this description, RF generator z generates a pulse block at the same time as RF generator 2 receives the pulse of the synchronization signal 102. In this way, the pulse blocks are generated synchronously by RF generators 1 to z.

[0062] In one embodiment, after receiving the TTL signal 128, the processor system of each of the RF generators 2 to z receives the synchronization signal 102 from the RF generator 1. In one embodiment, simultaneously with the reception of the TTL signal 128, the processor system of each of the RF generators 2 to z receives the synchronization signal 102 from the RF generator 1.

[0063] In one embodiment, the recipe signal is sometimes referred to herein as a recipe set.

[0064] Figure 1B is a diagram illustrating an embodiment of a system 140 used for transmitting synchronization signal 102 via an EtherCAT (ECAT) cable. System 140 includes RF generators 1 through 2 and a host 104. RF generator 1 includes communication port PRT1. Similarly, RF generator 2 includes communication port PRT2a and another port PRT2b. Furthermore, RF generator 2 includes communication port PRT2z. Port PRT1 is coupled to port PRT2a via communication cable 142 and port PRT2b is coupled to port PRT2z via another communication cable 144. Communication cables used for transmitting ECAT frames comprising one or more ECAT frames are sometimes referred to herein as ECAT cables.

[0065] The digital signal processor (DSP) of RF generator 1 receives timing information for generating pulse blocks of each of RF processors 1 to 2 via transmission cable 110 from processor 106, and transmits timing information for generating pulse blocks of each of RF processors 2 to 2 to the communication controller of RF generator 1. The communication controller of RF generator 1 embeds the timing information for each of RF processors 2 to 2 into one or more EtherCAT frames, and transmits the one or more EtherCAT frames to RF generator 2 via port PRT1. For example, the communication controller of RF generator 1 specifies the timing information for RF generator 2 in one or more EtherCAT frames, and specifies the timing information for RF generator 2 in one or more EtherCAT frames. For illustration, the communication controller of RF generator 1 provides a first identifier to the timing information for RF generator 1 and a second identifier to the timing information for RF generator 2. To further illustrate, the specification or identification of the timing information for RF generator 2 is different from or distinguishable from the specification or identification of the timing information for RF generator 2. Port PRT1 transmits one or more EtherCAT frames to port PRT2a of RF generator 2 via communication cable 142.

[0066] As used herein, examples of controllers include processors and memory devices. The processor is coupled to the memory device. Other examples of controllers include ASICs and PLDs. Yet another example of a controller includes multiple processors and multiple memory devices. These processors are coupled to these memory devices.

[0067] The communication controller of RF generator 2 receives one or more EtherCAT frames via port PRT2a and identifies time information specified for RF generator 2 from the one or more EtherCAT frames. The communication controller of RF generator 2, for example, acquires the time information specified for RF generator 2 from the one or more EtherCAT frames in an acquiring manner and sends the time information to the processor system of RF generator 2 for execution. When the communication controller of RF generator 2 acquires and sends the time information to the processor system of RF generator 2, the communication controller sends the one or more EtherCAT frames from port PRT2a to port PRT2b of RF generator 2. Port PRT2b of RF generator 2 receives the one or more EtherCAT frames from port PRT2a and sends the one or more EtherCAT frames to port PRT2z of RF generator 2 via communication cable 144.

[0068] The communication controller of RF generator z receives one or more EtherCAT frames at port PRTz and identifies time information specified for RF generator z from the one or more EtherCAT frames. The communication controller of RF generator z extracts the time information specified for RF generator z from the one or more EtherCAT frames in an acquiring manner, and sends the time information to the processor system of RF generator z for execution. When the communication controller of RF generator z extracts and sends the time information to the processor system of RF generator z, the communication controller sends the one or more EtherCAT frames from port PRTz to port PRT2b of RF generator 2 via communication cable 144. The communication controller of RF generator 2 receives one or more EtherCAT frames from port PRT2b and sends them to port PRT2a, and further sends the one or more EtherCAT frames from port PRT2a back to port PRT1 of RF generator 1 via communication cable 142.

[0069] The processor system of RF generator 1 executes timing information for RF generator 1 to generate pulse blocks of RF signal 130. Furthermore, the processor system of RF generator 2 executes timing information for RF generator 2 to generate pulse blocks of RF signal 132 synchronized with the generation of pulse blocks of RF signal 130. The processor system of RF generator z executes timing information for RF generator z to generate pulse blocks of RF signal 134 synchronized with the generation of pulse blocks of RF signal 130. In this way, the pulse blocks of RF signals 130, 132, and 134 are generated synchronously with each other to reduce any influence from the internal clocks of RF generators 1 to z.

[0070] In one embodiment, the timing information used for RF generators 1 through z is the same. For example, the timing information used for RF generator 1 is the same as the timing information used for RF generator 2 and the timing information used for RF generator z. For illustration purposes, the time at which RF generator 1 will generate a pulse block is the same as the time at which RF generator 2 will generate a pulse block and the time at which RF generator z will generate a pulse block.

[0071] FIG1C is a diagram of an embodiment of a system 160 having a processor 106 that generates and transmits synchronization signals 102 to RF generators 1 to z. System 160 includes a host 104 and RF generators 1 to z. The processor 106 transmits the synchronization signal 102 to RF generator 1 via transmission cable 110. Similarly, the processor 106 transmits the synchronization signal 102 to RF generator 2 via transmission cable 112 and to RF generator z via transmission cable 114. As an example, the synchronization signal 102 is transmitted to RF generators 1 to z simultaneously with or after the transmission of the TTL signal 128.

[0072] Once the synchronization signal 102 is received, RF generator 1 generates each pulse block of RF signal 130 synchronized with the synchronization signal 102. Similarly, RF generator 2 generates each pulse block of RF signal 132 synchronized with the synchronization signal 102 in response to receiving the synchronization signal 102, and RF generator 3 generates each pulse block of RF signal 134 synchronized with the synchronization signal 102 in response to receiving the synchronization signal 102. For example, pulse blocks 2 of each of RF signals 130, 132, and 134 are generated at the same time, pulse blocks 3 of each of RF signals 130, 132, and 134 are generated at the same time, and so on until pulse blocks Mm of each of RF signals 130, 132, and 134 are generated at the same time, where Mm is a positive integer. The integer Mm depends on the time t0 at which the pulse blocks of RF signals 130, 132, and 134 are generated.

[0073] Figure 2A is a diagram illustrating the use of RF generators 1, 2, and z with capacitively coupled plasma chamber 202. System 200 includes RF generators 1 to z, matching 204, and plasma chamber 202.

[0074] The plasma chamber 202 includes a substrate support 206 and an upper electrode 208. Examples of the substrate support 206 include, for example, an electrostatic chuck (ESC). For illustration, the chuck includes a metal base and a dielectric layer on top of the metal base. For example, a semiconductor wafer substrate S is placed on the top surface of the substrate support 206 for processing in the plasma chamber 202. The substrate support 206 includes a lower electrode made of a metal such as aluminum or an aluminum alloy. The lower electrode is embedded within the dielectric layer of the chuck.

[0075] The plasma chamber 202 further includes an upper electrode 208 facing the top surface of the substrate support 206. A gap is formed between the upper electrode 208 and the substrate support 206.

[0076] The output O1 of RF generator 1 is coupled to input 210 of match 204 via RF cable RFC1. Furthermore, the output O2 of RF generator 2 is coupled to another input 212 of match 204 via RF cable RFC2, and the output Oz of RF generator z is coupled to yet another input 214 of match 204 via RF cable RFCz.

[0077] Input 210 of match 204 is coupled to output 216 of match 204 via the first branch of match 204. Similarly, input 212 of match 204 is coupled to output 216 via the second branch of match 204 and input 214 of match 204 is coupled to output 216 via the third branch of match 204.

[0078] Output 216 is coupled to the lower electrode of substrate support 206 via RF transmission line 218. As an example, RF transmission line 218 includes an RF rod, an insulating material, and an RF sheath. The insulating material is located between the RF rod and the RF sheath. The insulating material surrounds the RF rod and the RF sheath surrounds the insulating material. RF transmission line 218 further includes one or more RF strips and an RF cylinder. The RF rod is coupled to output 216 of mating 204. The one or more RF strips couple the RF rod to the RF cylinder, which is coupled to the lower electrode of substrate support 206.

[0079] RF generator 1 generates RF signal 130 and transmits RF signal 130 to the first branch of match 204 via output O1, RF cable RFC1, and input 210. Similarly, RF generator 2 generates RF signal 132 and transmits RF signal 132 to the second branch of match 204 via output O2, RF cable RFC2, and input 212. Furthermore, RF generator 2 generates RF signal 134 and transmits RF signal 134 to the third branch of match 204 via output Oz, RF cable RFCz, and input 214.

[0080] The first branch modifies the impedance of RF signal 130 to output a first modified RF signal, the second branch modifies the impedance of RF signal 132 to output a second modified RF signal, and the third branch modifies the impedance of RF signal 134 to output a third modified RF signal. The first, second, and third modified RF signals are combined at output 216 by matching 204 in an additive manner to provide a combined RF signal 220. The combined RF signal 220 is transferred to the lower electrode of the substrate support 206 via RF transmission line 218.

[0081] Furthermore, one or more processing gas systems, such as oxygen-containing gas and fluorine-containing gas, are supplied to the gap between the substrate support 206 and the upper electrode 208. When one or more processing gases and a combined RF signal 220 are supplied to the gap in the plasma chamber 202, the plasma is impacted or maintained within the plasma chamber 202, and the plasma is used to process the substrate S. Examples of processing the substrate S include depositing one or more materials on the substrate S, or etching the substrate S, or cleaning the substrate S, or polishing the substrate S, or sputtering the substrate S, or combinations thereof.

[0082] Figure 2B is a diagram illustrating an embodiment of a system 250 for a transformer-coupled plasma (TCP) chamber 252. System 250 includes RF generators 1 to 2, a matching element 254, and another matching element 256. The plasma chamber 252 includes a dielectric window 262 disposed on the top of a sidewall 265. The plasma chamber 252 further includes a TCP coil 264 located above the dielectric window 262. A substrate support 206 is located within the plasma chamber 252.

[0083] The output O1 of RF generator 1 is coupled to input 258 of match 254 via RF cable RFC1. The output 260 of match 254 is coupled to the first end of TCP coil 264 via RF transmission line 266. As an example, RF transmission line 266 includes an RF rod, an insulating material, and an RF sheath. The insulating material is located between the RF rod and the RF sheath. The insulating material surrounds the RF rod and the RF sheath surrounds the insulating material. The opposite second end of TCP coil 264 is coupled to ground potential.

[0084] The output O2 of RF generator 2 is coupled to input 268 of match 256 via RF cable RFC2, and the output Oz of RF generator z is coupled to another input 270 of match 256 via RF cable RFCz. Input 268 is coupled to output 272 via a first branch of match 256, and input 270 is coupled to output 272 via a second branch of match 256. Output 272 is coupled to the lower electrode of substrate support 206 via RF transmission line 218.

[0085] RF generator 1 supplies RF signal 130 at output O1. RF signal 130 is transmitted to match 254 via RF cable RFC1 and input 258. Match 254 matches the impedance of the load coupled to output 260 with the impedance of the source coupled to input 258 to output modified RF signal 274 at output 260. Examples of sources coupled to input 258 include RF cable RFC1 and RF generator 1. Examples of loads coupled to output 260 include RF transmission line 266 and plasma chamber 252. Modified RF signal 274 is transmitted to TCP coil 264 via RF transmission line 266.

[0086] Furthermore, RF generator 2 supplies RF signal 132 at output O2. RF signal 132 is supplied to a first branch of matching 256 via RF cable RFC2 and input 268. The first branch matches the impedance of the load coupled to output 272 with the impedance of the source coupled to input 268 to output a first modified RF signal. Examples of sources coupled to input 268 include RF generator 2 and RF cable RFC2. Examples of loads coupled to output 272 include RF transmission line 218 and plasma chamber 252. Similarly, a second branch matches the impedance of the load coupled to output 272 with the impedance of the source coupled to input 270 to output a second modified RF signal. Examples of sources coupled to input 270 include RF generator 2 and RF cable RFC2. The first and second modified RF signals are combined at the output 272 of the matching 256 in an additive manner, for example, to output a combined RF signal 276 at the output 272. The combined RF signal 276 is transmitted to the lower electrode of the substrate support 206 via the RF transmission line 218.

[0087] When one or more processing gases are supplied to the gap between the substrate support 206 in the dielectric window 262 and the plasma chamber 252, and the modified RF signal 274 and the combined RF signal 276 are supplied to the plasma chamber 252, the one or more processing gases are ignited to impinge the plasma in the gap. The plasma is used to process the substrate S placed on the top surface of the substrate support 206.

[0088] Figure 3A depicts a graph 300 used to illustrate the TTL signal 128. Graph 300 plots the relative relationship between the logic level and time t of the TTL signal 128. The logic level is plotted on the y-axis and the time t is plotted on the x-axis. Time t includes times t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20, t21, t22, t23, t24, t25, and t26.

[0089] The time interval between any two consecutive times from t1 to t26 is the same. For example, the time interval between times t0 and t1 is equivalent to the time interval between times t1 and t2.

[0090] The TTL signal 128 has a logic level of 1 during the time interval between time t0 and time t0.5, and has a pulse at time t0.5 that occurs midway between time t0 and t1, from logic level 1 to logic level 0. For example, the time interval between time t0 and t1 is divided into two equal time intervals at time t0.5. The TTL signal 128 remains at logic level 0 from time t0.5.

[0091] In one embodiment, the TTL signal 128 transitions from logic level 1 to logic level 0 at a time other than t0.5. For example, the TTL signal 128 transitions from logic level 1 to logic level 0 at time t1 or time t2.

[0092] Figure 3B depicts a graph 302 illustrating the multi-pulse blocks 1, 2, and 3 of the RF signal 130 (Figure 1A) generated by the RF generator 1. Graph 302 plots the relative relationship between variables such as frequency or power of the RF signal 130 and time t. The variables of the RF signal 130 are plotted on the y-axis, while time t is plotted on the x-axis.

[0093] Each pulse block of the RF signal 130 has N parts, where N is a positive integer as used herein. The N parts of each pulse block of the RF signal 130 occur consecutively. For example, the second part of pulse block 1 of the RF signal 130 occurs immediately after the first part of pulse block 1 of the RF signal 130. There are no other parts between the first and second parts of pulse block 1 of the RF signal 130.

[0094] Pulse block 1 begins at time t0 and ends at time t10. The first part of pulse block 1 occurs during pulse period PP1, which is the time interval between times t0 and t2. Similarly, the second part of pulse block 1 occurs during pulse period PP2, which is the time interval between times t2 and t4. The Nth part of pulse block 1 occurs during pulse period PPN, which is the time interval between times t8 and t10.

[0095] Pulse block 2 begins at time t10 and ends at time t20. The first part of pulse block 2 occurs during pulse period PP1, which is the time interval between times t10 and t12. Similarly, the second part of pulse block 2 occurs during pulse period PP2, which is the time interval between times t12 and t14. The Nth part of pulse block 2 occurs during pulse period PPN, which is the time interval between times t18 and t20. Similarly, pulse block 3 has parts 1 to N occurring during pulse periods PP1 to PPN, and pulse period PP1 begins at time t20.

[0096] It should be noted that pulse block 2 of the RF signal follows pulse block 1 of the RF signal, and pulse block 3 of the RF signal follows pulse block 2 of the RF signal. There are no pulse blocks between pulse blocks 1 and 2, and between pulse blocks 2 and 3.

[0097] It should be further noted that, as depicted in Figure 3B, the internal clock of RF generator 1 has no errors in generating clock signals or has a minimum error, such that the minimum error is less than a predetermined amount when generating clock signals. It should be noted that the internal clock described herein has errors caused by internal clock malfunctions or prolonged use of the internal clock.

[0098] It should be noted again that each portion of each pulse block of the RF signal 130 has one or more variable levels between zero and V1a. For example, the first portion of pulse block 1 has an encapsulation between a variable level of zero and a variable level of V1a, and the Nth portion of pulse block 1 has an encapsulation between a variable level of zero and a variable level of V1a. As an example, the encapsulation used herein refers to the peak-to-peak amplitude or zero-to-peak amplitude of the RF signal. As an example, the variable level includes one or more variable values.

[0099] In one embodiment, the pulse blocks in Figure 302 depict the RF signal 130 generated after the RF generator 1 receives the synchronization signal 102 from the processor 106 (FIG. 1A). The pulse blocks of the RF signal 130 depicted in Figure 302 are synchronized with the synchronization signal 102.

[0100] In one embodiment, the pulse blocks in Figure 302 depict the RF signal 130 generated after the RF generator 1 generates the synchronization signal 102. The pulse blocks of the RF signal 130 depicted in Figure 302 are synchronized with the synchronization signal 102.

[0101] Figure 3C depicts a graph 304 illustrating the multi-pulse blocks (PBs) 1, 2, and 3 of the RF signal 132 (Figure 1A) generated by RF generator 2 when RF generator 2 does not receive the synchronization signal 102. Graph 304 plots the relative relationship between the variables of RF signal 132 and time t. The variables of RF signal 132 are plotted on the y-axis, while time t is plotted on the x-axis.

[0102] Each pulse block of RF signal 132 has N parts. The N parts of each pulse block of RF signal 132 occur consecutively. For example, the second part of pulse block 1 of RF signal 132 occurs immediately after the first part of pulse block 1 of RF signal 132. There are no other parts between the first and second parts of pulse block 1 of RF signal 132.

[0103] Due to an error in the internal clock of RF generator 2, the pulse block 1 of RF signal 132 does not begin at time t0. Instead, it begins at time t2 and ends at time t12 instead of time t10. For example, the first part of pulse block 1 of RF signal 132 occurs during the pulse period PP1, which is the time interval between times t2 and t4, instead of the time interval between times t0 and t2. Similarly, the second part of pulse block 1 of RF signal 132 occurs during the pulse period PP2, which is the time interval between times t4 and t6, instead of the time interval between times t2 and t4. The (N-1)th part of pulse block 1 of RF signal 132 occurs during the pulse period PP(N-1), which is the time interval between times t8 and t10, instead of the time interval between times t6 and t8. The Nth part of pulse block 1 of RF signal 132 occurs during the pulse period PPN, which is the time interval between times t10 and t12. Due to an error in the internal clock of RF generator 2, the pulse period PPN occurs during the time interval between times t10 and t12 instead of the time interval between times t8 and t10. As a result, pulse block 1 of RF signal 132 is delayed by one pulse period, and this delay is depicted as a slash between times t0 and t2.

[0104] Furthermore, the pulse block 2 of the RF signal 132 generated by the RF generator 2 is delayed by one pulse period. The pulse block 2 of the RF signal 132 begins at time t12 instead of time t10, and ends at time t22 instead of time t20. For example, the first part of the pulse block 2 of the RF signal 132 does not occur between times t10 and t12, but rather between times t12 and t14. Similarly, the Nth part of the pulse block 2 of the RF signal 132 does not occur between times t18 and t20, but rather between times t20 and t22.

[0105] It should be noted that each portion of each pulse block of RF signal 132 is within the range of a variable level from zero to a variable level of V1b. For example, the first portion of pulse block 1 has an encapsulation within the range of a variable level from zero to V1b, and the Nth portion of pulse block 1 has an encapsulation within the range of a variable level from zero to V1b.

[0106] In one embodiment, the pulse block 1 of the RF signal 132 is delayed from time t0 by any other number of pulse cycles, for example, by two or three pulse cycles.

[0107] In one embodiment, the pulse block 1 of the RF signal 132 is delayed by a fraction of the pulse period PP1. For example, the pulse block 1 of the RF signal 132 is delayed by three-quarters of the pulse period PP1.

[0108] Figure 3D depicts the multi-pulse blocks 1, 2, and 3 of the RF signal 134 (Figure 1A) generated by RF generator z when RF generator z does not receive synchronization signal 102. Figure 306 plots the relative relationship between the variables of RF signal 134 and time t. The variables of RF signal 134 are plotted on the y-axis, and time t is plotted on the x-axis.

[0109] Each pulse block of the RF signal 134 has N parts. The N parts of each pulse block of the RF signal 134 occur consecutively. For example, the second part of pulse block 1 of the RF signal 134 occurs immediately after the first part of pulse block 1 of the RF signal 134. There are no other parts between the first and second parts of pulse block 1 of the RF signal 134.

[0110] Due to an error in the internal clock of the RF generator z, pulse block 1 of the RF signal 134 begins at time t4 instead of time t0, and ends at time t14 instead of time t12. For example, the first part of pulse block 1 of the RF signal 134 occurs during the pulse period PP1, which is the time interval between times t4 and t6, instead of the time interval between times t0 and t2. Similarly, the second part of pulse block 1 of the RF signal 134 occurs during the pulse period PP2, which is the time interval between times t6 and t8, instead of the time interval between times t2 and t4. The (N-2)th part of pulse block 1 of the RF signal 134 occurs during the pulse period PP(N-2), which is the time interval between times t8 and t10, instead of the time interval between times t4 and t6. The (N-1)th portion of pulse block 1 of RF signal 134 occurs during the pulse period PP(N-1), which is the time interval between times t10 and t12, instead of the time interval between times t6 and t8. The Nth portion of pulse block 1 of RF signal 134 occurs during the pulse period PPN, which is the time interval between times t12 and t14. Due to an error in the internal clock of RF generator z, the pulse period PPN occurs during the time interval between times t12 and t14 instead of the time interval between times t8 and t10. Thus, pulse block 1 of RF signal 134 is delayed by two pulse periods, and this delay is depicted by a slash between times t0 and t4.

[0111] Furthermore, pulse block 2 of RF signal 134 is delayed by two pulse cycles. Pulse block 2 of RF signal 134 begins at time t14 instead of time t10, and ends at time t24 instead of time t20. For example, the first part of pulse block 2 of RF signal 134 does not occur between times t10 and t12, but rather between times t14 and t16. Similarly, the Nth part of pulse block 2 of RF signal 134 does not occur between times t18 and t20, but rather between times t22 and t24.

[0112] It should be noted that each portion of each pulse block of the RF signal 134 is within the range of a variable level from zero to a variable level of V1c. For example, the first portion of pulse block 1 has an encapsulation within the range of a variable level from zero to V1c, and the Nth portion of pulse block 1 has an encapsulation within the range of a variable level from zero to V1c.

[0113] In one embodiment, the pulse block 1 of the RF signal 134 is delayed from time t0 by any other number of pulse cycles, for example, by one, three or four pulse cycles.

[0114] In one embodiment, the pulse block 1 of the RF signal 134 is delayed by a fraction of the pulse period PP1. For example, the pulse block 1 of the RF signal 134 is delayed by half or three-quarters of the pulse period PP1.

[0115] Figure 3E depicts a graph 308 illustrating the forward (FWD) power of the RF signal 130 supplied by RF generator 1 of system 250 (Figure 2B). Graph 308 depicts the relative relationship between forward power and time t. There are no errors in the forward power caused by the internal clock of RF generator 1. The supply of forward power via RF generator 1 is not delayed from time t0, and the TTL signal 128 is received from processor 106 by RF generators 1, 2, and 3 at time t0. Pulse block 1 of the forward power supplied by RF generator 1 begins at time t0. After the end of pulse block 1 of the forward power, another pulse block 2 of the forward power begins.

[0116] Figure 3F depicts a graph 310 illustrating the reverse (REV) power received by RF generator 1 of system 250 (Figure 2B), such as reflected power. For example, the reflected power is reflected from plasma chamber 252 and transmitted via RF transmission line 266, output 260 of match 254, match 254, input 258 of match 254, and RF cable RFC1 to output O1 of RF generator 1. Graph 310 depicts the relative relationship between reverse power and time t. There is no error in the reverse power caused by the internal clock of RF generator 1. There is no delay in the reverse power received by RF generator 1. The delay in the reverse power is measured from time t0, and the TTL signal 128 is received by RF generators 1, 2, and 3 from processor 106 at time t0. Pulse block 1 of the reverse power received by RF generator 1 begins at time t0. After pulse block 1 of the reverse power ends, another pulse block 2 of the reverse power begins.

[0117] Figure 3G depicts a graph 312 illustrating the positive power of the RF signal 132 supplied by the RF generator 2 of system 250 (Figure 2B). Graph 312 depicts the relative relationship between positive power and time t. There is an error in the positive power caused by the internal clock of RF generator 2. The supply of positive power via RF generator 2 is delayed. As an example, the delay in the supply of positive power is two pulse cycles (PP x 2). The pulse block 2 of the positive power supplied by RF generator 2 begins at a time two pulse cycles later than the end of the pulse block 1 of the positive power supplied by RF generator 1 of system 250.

[0118] Figure 3H depicts a graph 314 illustrating the reverse power received by the RF generator 2 of system 250 (Figure 2B), such as reflected power. The reflected power is reflected from plasma chamber 252 and passes through RF transmission line 218, output 272 of matching 256, matching 256, input 268 of matching 256, and RF cable RFC2 to output O2 of RF generator 2. Graph 314 depicts the relative relationship between reverse power and time t. Due to an error in the internal clock of RF generator 2, the supply of reverse power received by RF generator 2 is delayed. As an example, the delay in receiving reverse power via RF generator 2 is two pulse periods (PP x 2). The pulse block 2 of reverse power received by RF generator 2 begins at the time when the pulse block 1 of reverse power received by RF generator 1 of system 250 ends, delayed by two pulse periods.

[0119] Figure 4A depicts a diagram 400 illustrating a synchronization signal 102, which is a periodic signal. Diagram 400 illustrates the relative relationship between the logic level and time t of the synchronization signal 102. The synchronization signal 102 has multiple pulses at periodic time intervals. For example, the synchronization signal 102 has pulse 102A, another pulse 102B, and yet another pulse 102C.

[0120] The logic level of synchronization signal 102 is plotted on the y-axis, and the time t is plotted on the x-axis. At time t0, synchronization signal 102 is at logic level 1. Synchronization signal 102 pulses back from logic level 1 to logic level 0 and reaches logic level 0 at time t0.25 to generate pulse 102A. Time t0.25 occurs at one-quarter of the time interval between time t0 and t1. Synchronization signal 120 remains at logic level 0 from time t0.25 to time t9.75. Time t9.75 occurs at three-quarters of the time interval between time t9 and t10.

[0121] Synchronization signal 102 transitions from logic level 0 to logic level 1 at time t9.75. Synchronization signal 102 is at logic level 1 at time t10 and begins transitioning from logic level 1 to logic level 0 at time t10. Synchronization signal 102 arrives at logic level 0 at time t10.25 to generate pulse 102B, time t10.25 being one-quarter of the time interval between times t10 and t11. Synchronization signal 120 remains at logic level 0 from time t10.25 to time t19.75. Time t19.75 occurs three-quarters of the time interval between times t19 and t20.

[0122] Synchronization signal 102 transitions from logic level 0 to logic level 1 at time t19.75. Synchronization signal 102 arrives at logic level 1 at time t20 and begins transitioning from logic level 1 to logic level 0 at time t20. Synchronization signal 102 arrives at logic level 0 at time t20.25 to generate pulse 102C. Time t20.25 occurs one-quarter of the time interval between times t20 and t21.

[0123] In one embodiment, the synchronization signal 102 is a rectangular pulse rather than a triangular pulse. For example, the synchronization signal 102 pulses from logic level 0 to logic level 1 at time t10, remains at logic level 1 from time t10 and time t11, and pulses from logic level 1 to logic level 0 at time t11.

[0124] Figure 4B depicts a graph 402 illustrating the correction of the delay in the pulse block of the RF signal 132 generated by the RF generator 2 (Figure 1A) by the synchronization signal 102, such correction being, for example, reduction, deletion, minimization, or correction. The synchronization signal 102 is received by the RF generator 2. Graph 402 depicts the relative relationship between the pulse block of the RF signal 132 and time t. Pulse block 1 of the RF signal 132 is delayed by one pulse period. However, when the synchronization signal 102 pulses from logic level 0 to logic level 1 at time t10, the (N-1)th portion of pulse block 1 of the RF signal 132 ends at time t10, and pulse block 1 ends at the (N-1)th portion at time t10.

[0125] When the synchronization signal 102 pulses from logic level 0 to logic level 1 at time t10, the RF generator 2 does not generate the Nth part of pulse block 1. For example, the RF generator 2 avoids generating the Nth part of pulse block 1 of the RF signal 132 at time t10. Instead, the RF generator 2 generates pulse block 2 at time t10. For example, the RF generator 2 generates the first part of pulse block 2 at time t10, instead of generating the Nth part of pulse block 1 at time t10. By generating the first part of pulse block 2 at time t10, pulse block 2 is synchronized with the pulse of the synchronization signal 102 generated at time t10 and received by the RF generator 2 at time t10 via the RF generator 2.

[0126] It should be noted that it is not necessary to synchronize the pulse block 2 generated by RF generator 1. The pulse block of RF signal 130 does not contain any errors caused by the internal clock of RF generator 1, or any minimal errors caused by the internal clock of RF generator 1. In the absence of errors or with minimal errors, the pulse block 2 of RF signal 130 generated by RF generator 1 is synchronized with the pulse of synchronization signal 102 generated at time t10.

[0127] Since the first part of the pulse block 2 of the RF signal 132 is generated at time t10, the Nth part of the pulse block 2 is generated at time t18 and the Nth part of the pulse block 2 is very likely to end at time t20. In this way, the Nth part of the pulse block 2 of the RF signal 132 will not be delayed by one pulse period.

[0128] The pulse 102C of the synchronization signal 102 reaches logic level 1 at time t20. If pulse block 2 of the RF signal 132 is delayed due to the internal clock of the RF generator 2, this delay is corrected by the pulse 102C of the synchronization signal 102 at time t20, such correction being, for example, minimization, reduction, cancellation, or deletion. At time t20, when the pulse 102C of the synchronization signal 102 is generated, pulse block 2 of the RF signal 132 ends and pulse block 3 of the RF signal 132 begins. Pulse block 3 is not delayed by one pulse cycle. Instead, pulse block 3 of the RF signal 132 begins at time t20.

[0129] Figure 4C depicts a graph 404 illustrating the correction of the delay in the pulse block of the RF signal 134 generated by the RF generator z (Figure 1A) by the synchronization signal 102, such correction being, for example, reduction, deletion, or minimization. The synchronization signal 102 is received by the RF generator z. Graph 404 depicts the relative relationship between the pulse block of the RF signal 134 and time t. Pulse block 1 of the RF signal 134 is delayed by two pulse cycles. However, when the synchronization signal 102 pulses from logic level 0 to logic level 1 at time t10, the (N-2)th portion of pulse block 1 of the RF signal 134 ends at time t10, and pulse block 1 ends at the (N-2)th portion at time t10.

[0130] When the synchronization signal 102 pulses from logic level 0 to logic level 1 at time t10, the RF generator z does not generate the remaining portion, which is, for example, the (N-1)th and Nth portions of pulse block 1. For example, the RF generator z avoids generating the (N-1)th portion of pulse block 1 of RF signal 134 at time t10 and avoids generating the Nth portion of pulse block 1 of RF signal 134 at time t12. Instead, the RF generator z generates pulse block 2 of RF signal 134 at time t10. For example, the RF generator z generates the first portion of pulse block 2 at time t10, instead of generating the (N-1)th portion of pulse block 1 at time t10. By generating the first portion of pulse block 2 at time t10, pulse block 2 is synchronized with the pulse of the synchronization signal 102 generated at time t10 and received by the RF generator z at time t10.

[0131] Since the first part of pulse block 2 is generated at time t10, the Nth part of pulse block 2 of RF signal 134 is generated at time t18 and the Nth part of pulse block 2 of RF signal 134 is very likely to end at time t20. In this way, the Nth part of pulse block 2 of RF signal 134 will not be delayed by two pulse cycles.

[0132] Another pulse of the synchronization signal 102 arrives at logic level 1 at time t20 to generate the pulse. If pulse block 2 of RF signal 134 is delayed due to the internal clock of RF generator 2, this internal error is corrected by the pulse of synchronization signal 102 at time t20, such correction being, for example, minimization, reduction, cancellation, or deletion. The minimum error is illustrated by the slash between time t18 and time t18.25, where time t18.25 is one-quarter of the time interval between time t18 and t19. At time t20, when the pulse of synchronization signal 102 is generated, pulse block 2 of RF signal 134 ends and pulse block 3 of RF signal 134 begins. Pulse block 3 is not delayed by two pulse cycles. Instead, pulse block 3 of RF signal 134 begins at time t20.

[0133] Synchronization signal 102 synchronizes pulse blocks 2 and 3 of each of RF signals 130, 132, and 134. If any pulse block of RF signals 130, 132, and 134 is delayed, the error is corrected by synchronization signal 102. Thus, pulse blocks 1 to 3 of RF signals 130, 132, and 134 are synchronized. For example, pulse block 1 of each of RF signals 130, 132, and 134 begins at the same time. Similarly, pulse block N of each of RF signals 130, 132, and 134 begins at the same time.

[0134] Figure 5A depicts a diagram 502 illustrating each pulse block of the RF signal 130. Diagram 502 illustrates the relative relationship between the variable level and time t of each pulse block of the RF signal 130. The first part of pulse block 1 of the RF signal 130 includes four states S1, S2, S3, and S4. Each part of pulse block 1 of the RF signal 130 includes the four states S1, S2, S3, and S4.

[0135] Each state of the variable in pulse block 1 of RF signal 130 corresponds to a variable level of that variable. For example, state S4 of the variable of RF signal 130 has a variable level V1a, state S3 of the variable of RF signal 130 has a variable level V0.8a, state S2 of the variable of RF signal 130 has a variable level V0.6a, and state S1 of the variable of RF signal 130 has a variable level V0.2a. The variable level V0.2a is greater than zero. Furthermore, the variable level V0.6a is greater than the variable level V0.2a. The variable level V0.8a is greater than the variable level V0.6a, and the variable level V1a is greater than the variable level V0.8a.

[0136] It should be noted that the first variable level of the variable is different from the second variable level of the variable; for example, the first variable level excludes the second variable level. For example, the value of variable level V0.8a does not include the value of variable level V0.6a. For illustrative purposes, variable level V0.8a has one or more values, and the minimum of these values ​​is greater than the maximum of one or more values ​​of variable level V0.6a.

[0137] During the pulse period PP1, at time t0, the first portion of pulse block 1 of RF signal 130 transitions from variable level V0.2a to variable level V1a. From time t0 to time t0.5, the first portion of pulse block 1 of RF signal 130 is located at variable level V1a. Time t0.5 is half the time interval between time t0 and t1. Furthermore, during the pulse period PP1, at time t0.5, the first portion of pulse block 1 of RF signal 130 transitions from variable level V1a to variable level V0.8a. From time t0.5 to time t1, the first portion of pulse block 1 of RF signal 130 is located at variable level V0.8a.

[0138] Furthermore, during the pulse period PP1, at time t1, the first portion of pulse block 1 of RF signal 130 transitions from variable level V0.8a to variable level V0.6a. From time t1 to time t1.5, the first portion of pulse block 1 of RF signal 130 is located at variable level V0.6a. Time t1.5 is half the time interval between time t1 and t2. During the pulse period PP1, at time t1.5, the first portion of pulse block 1 of RF signal 130 transitions from variable level V0.6a to variable level V0.2a. From time t1.5 to time t2, the first portion of pulse block 1 of RF signal 130 is located at variable level V0.2a. The first portion of pulse block 1 of RF signal 130 transitions to variable level V1a at time t2.

[0139] The states S1 to S4 of the variables of RF signal 130 are repeated as each part of pulse block 1 of RF signal 130 until the Nth part of pulse block 1 of RF signal 130 occurs. The Nth part of pulse block 1 of RF signal 130 occurs during the pulse period PPN of pulse block 1, and the Nth part includes the four states S1 to S4. For example, states S1 to S4 are repeated during the pulse period PP2 of pulse block 1 of RF signal 130, and are repeated again during the pulse period PP3 of pulse block 1, and so on until the pulse period PPN of pulse block 1. Pulse block 1 of RF signal 130 ends at time t10.

[0140] Pulse block 2 of RF signal 130 continues from pulse block 1 of RF signal 130. Pulse block 2 of RF signal 130 includes N parts. The first part of pulse block 2 of RF signal 130 includes three states S1, S2, and S3. Each part of pulse block 2 of RF signal 130 includes the three states S1, S2, and S3.

[0141] Each state of the variable in pulse block 2 of RF signal 130 corresponds to a variable level of that variable. For example, state S3 of the variable in pulse block 2 of RF signal 130 has a variable level V1a, state S2 of the variable in pulse block 2 of RF signal 130 has a variable level V0.6a, and state S1 of the variable in pulse block 2 of RF signal 130 has a variable level V0.4a.

[0142] During the pulse period PP1, at time t10, the first portion of pulse block 2 of RF signal 130 transitions from variable level V0.2a to variable level V1a. From time t10 to time t10.5, the first portion of pulse block 2 of RF signal 130 is located at variable level V1a. Time t10.5 is half the time interval between times t10 and t11. Furthermore, during the pulse period PP1, at time t10.5, the first portion of pulse block 2 of RF signal 130 transitions from variable level V1a to variable level V0.6a. From time t10.5 to time t11, the first portion of pulse block 2 of RF signal 130 is located at variable level V0.6a.

[0143] Furthermore, during the pulse period PP1, at time t11, the first portion of pulse block 2 of RF signal 130 transitions from the variable level V0.6a to the variable level V0.4a. From time t11 to time t12, the first portion of pulse block 2 of RF signal 130 is located at the variable level V0.4a. At time t12, the first portion of pulse block 2 of RF signal 130 transitions from the variable level V0.4a to the variable level V1a.

[0144] The states S1 to S3 of the variable of RF signal 130 are repeated as each pulse period of pulse block 2 until the pulse period PPN of pulse block 2. For example, states S1 to S3 are repeated during the pulse period PP2 of pulse block 2, and then repeated again during the pulse period PP3 of pulse block 2, and so on until the pulse period PPN of pulse block 2.

[0145] In one embodiment, the pulse block 1 of the RF signal 130 includes any other number of states. For example, the pulse block 1 includes two states, five states, or ten states.

[0146] In one embodiment, the pulse block 2 of the RF signal 130 includes any other number of states. For example, the pulse block 2 includes two states, five states, ten states, or twenty states.

[0147] In one embodiment, the number of pulse cycles in the first pulse block of an RF signal is different from the number of pulse cycles in the second pulse block of the RF signal. For example, pulse block 1 of RF signal 130 has N parts while pulse block 2 has (N-1) parts. For illustration purposes, pulse block 1 of RF signal 130 has 4 parts and pulse block 2 of RF signal 130 has 6 parts.

[0148] Figure 5B depicts a diagram 504 illustrating each pulse block of the RF signal 132. Diagram 504 illustrates the relative relationship between the variable level and time t of each pulse block of the RF signal 132. The first part of pulse block 1 of the RF signal 132 includes three states S1, S2, and S3.

[0149] Each state of the variable in pulse block 1 of RF signal 132 corresponds to a variable level of that variable. For example, state S2 of the variable of RF signal 132 has a variable level V0.5b, state S3 of the variable of RF signal 132 has a variable level V1b, and state S1 of the variable of RF signal 132 has a variable level V0.25b. Variable level V0.25b is greater than variable level zero. Variable level V0.5b is greater than variable level V0.25b, and variable level V1b is greater than variable level V0.5b.

[0150] It should be noted that the first variable level of the variable is different from the second variable level of the variable; for example, the first variable level excludes the second variable level. For example, the value of variable level V1b does not include the value of variable level V0.5b. For illustrative purposes, variable level V1b has one or more values, and the minimum of these values ​​is greater than the maximum of one or more values ​​of variable level V0.5b.

[0151] Due to an error caused by the internal clock of RF generator 2, the generation of the variable of RF signal 132 is delayed by one pulse period. For example, the state S2 of the variable of RF signal 132 does not start at time t0, but instead starts at time t2.

[0152] During the pulse period PP1, at time t2, the first portion of pulse block 1 of RF signal 132 transitions from the variable level V0.25b to the variable level V0.5b. From time t2 to time t3, the first portion of pulse block 1 of RF signal 132 is located at the variable level V0.5b. Furthermore, during the pulse period PP1, at time t3, the first portion of pulse block 1 of RF signal 132 transitions from the variable level V0.5b to the variable level V1b. From time t3 to time t3.5, the first portion of pulse block 1 of RF signal 132 is located at the variable level V1b. Time t3.5 occurs at half the time interval between times t3 and t4.

[0153] Furthermore, during the pulse period PP1, at time t3.5, the first portion of pulse block 1 of RF signal 132 transitions from the variable level V1b to the variable level V0.25b. From time t3.5 to time t4, the first portion of pulse block 1 of RF signal 132 is located at the variable level V0.25b. At time t4, the first portion of pulse block 1 of RF signal 132 transitions from the variable level V0.25b to the variable level V0.5b.

[0154] The states S1 to S3 of the variables of RF signal 132 are repeated as each part of pulse block 1 of RF signal 132 until the Nth part of pulse block 1 of RF signal 132 occurs. Each part of pulse block 1 of RF signal 132 has states S1 to S3. The Nth part of pulse block 1 of RF signal 132 occurs during the pulse period PPN of pulse block 1, and the Nth part includes the three states S1 to S3. For example, states S1 to S3 are repeated during the pulse period PP2 of pulse block 1 of RF signal 132, and are repeated again during the pulse period PP3 of pulse block 1, and so on until the pulse period PPN of pulse block 1. Due to an error caused by the internal clock of RF generator 2, pulse block 1 of RF signal 132 ends at time t12 instead of time t10.

[0155] Pulse block 2 of RF signal 132 continues from pulse block 1 of RF signal 132. Pulse block 2 of RF signal 132 includes N parts. The first part of pulse block 2 of RF signal 132 includes two states S1 and S2. Each part of pulse block 2 of RF signal 132 has these states S1 and S2.

[0156] Each state of the variable in pulse block 2 of RF signal 132 corresponds to a variable level of that variable. For example, state S1 of the variable of RF signal 132 has a variable level V0.5b and state S2 of the variable of RF signal 132 has a variable level V1b.

[0157] During pulse period PP1, at time t12, the first portion of pulse block 2 of RF signal 132 transitions from variable level V0.25b to variable level V0.5b. From time t12 to time t13, the first portion of pulse block 2 of RF signal 132 is located at variable level V0.5b. Furthermore, during pulse period PP1, at time t13, the first portion of pulse block 2 of RF signal 132 transitions from variable level V0.5b to variable level V1b. From time t13 to time t14, the first portion of pulse block 2 of RF signal 132 is located at variable level V1b. At time t14, the first portion of pulse block 2 of RF signal 132 transitions from variable level V1b to variable level V0.5b.

[0158] The states S1 and S2 of the variable of RF signal 132 are repeated until the pulse period PPN of pulse block 2. For example, states S1 and S2 are repeated during the pulse period PP2 of pulse block 2, and then repeated again during the pulse period PP3 of pulse block 2, and so on until the pulse period PPN of pulse block 2.

[0159] In one embodiment, the pulse block 1 of the RF signal 132 includes any other number of states. For example, the pulse block 1 includes four states or ten states.

[0160] In one embodiment, the pulse block 2 of the RF signal 132 includes any other number of states. For example, the pulse block 2 includes four states, five states, ten states, or twenty states.

[0161] Figure 5C depicts a diagram 506 illustrating each pulse block of the RF signal 134. Diagram 506 depicts the relative relationship between the variable level and time t of each pulse block of the RF signal 134. The first part of pulse block 1 of the RF signal 134 includes two states, S1 and S2. Each part of pulse block 1 of the RF signal 134 has these states S1 and S2.

[0162] Each state of the variable in pulse block 1 of RF signal 134 corresponds to a variable level of that variable. For example, state S2 of the variable of RF signal 134 has a variable level V1c and state S1 of the variable of RF signal 134 has a variable level V0.33c. Variable level V0.33c is greater than variable level zero. Variable level V1c is greater than variable level V0.33c.

[0163] It should be noted that the first variable level of the variable is different from the second variable level of the variable; for example, the first variable level excludes the second variable level. For example, the value of variable level V1c does not include the value of variable level V0.33c. For illustrative purposes, variable level V1c has one or more values, and the minimum of these values ​​is greater than the maximum of one or more values ​​of variable level V0.33c.

[0164] Due to an error caused by the internal clock of the RF generator z, the generation of the variable of the RF signal 134 is delayed by two pulse cycles. For example, the state S2 of the variable in pulse block 1 of the RF signal 134 does not start at time t0, but instead starts at time t4.

[0165] During the pulse period PP1, at time t4, the first portion of pulse block 1 of RF signal 134 transitions from the variable level V0.33c to the variable level V1c. From time t4 to time t5, the first portion of pulse block 1 of RF signal 134 remains at the variable level V1c. Furthermore, during the pulse period PP1, at time t5, the first portion of pulse block 1 of RF signal 134 transitions from the variable level V1c to the variable level V0.33c. From time t5 to time t6, the first portion of pulse block 1 of RF signal 134 remains at the variable level V0.33c. At time t6, the first portion of pulse block 1 of RF signal 134 transitions from the variable level V0.33c to the variable level V1c.

[0166] The states S1 and S2 of the variables of RF signal 134 are repeated to form each part of pulse block 1 of RF signal 134 until the Nth part of pulse block 1 of RF signal 134 is formed. The Nth part of pulse block 1 of RF signal 134 occurs during the pulse period PPN of pulse block 1, and the Nth part includes the two states S1 and S2. For example, states S1 and S2 are repeated during the pulse period PP2 of pulse block 1, and then repeated again during the pulse period PP3 of pulse block 1, and so on until the pulse period PPN of pulse block 1. Due to an error caused by the internal clock of RF generator z, pulse block 1 of RF signal 134 ends at time t14 instead of time t10.

[0167] Pulse block 2 of RF signal 134 continues from pulse block 1 of RF signal 134. Pulse block 2 includes N parts. The first part of pulse block 2 of RF signal 134 includes three states S1, S2, and S3. Each part of pulse block 2 of RF signal 134 has the states S1, S2, and S3.

[0168] Each state of the variable in pulse block 2 of RF signal 134 corresponds to a variable level of that variable. For example, state S2 of the variable of RF signal 134 has a variable level V1c, state S3 of the variable of RF signal 134 has a variable level V1.66c, and state S1 of the variable of RF signal 134 has a variable level V0.66c. Variable level V0.66c is greater than variable level V0.33c and variable level V1.66c is greater than variable level V0.66c.

[0169] During pulse period PP1, at time t14, the first portion of pulse block 2 of RF signal 134 transitions from variable level V0.33c to variable level V1c. From time t14 to time t14.5, the first portion of pulse block 2 of RF signal 134 is located at variable level V1c, and time t14.5 occurs at half the time interval between time t14 and t15. Furthermore, during pulse period PP1, at time t14.5, the first portion of pulse block 2 of RF signal 134 transitions from variable level V1c to variable level V1.66c. From time t14.5 to time t15, the first portion of pulse block 2 of RF signal 134 is located at variable level V1.66c. At time t15, the first portion of pulse block 2 of RF signal 134 transitions from variable level V1.66c to variable level V0.66c. From time t15 to time t16, the first part of pulse block 2 of RF signal 134 is located at the variable level V0.66c. The first part of pulse block 2 of RF signal 134 transitions from the variable level V0.66c to the variable level V1c at time t16, and remains at the variable level V1c from time t16 to time t16.5, where time t16.5 is half the time interval between time t16 and t17.

[0170] The states S1 to S3 of the variable of RF signal 134 are repeated as each pulse period of pulse block 2 until the pulse period PPN of pulse block 2. For example, states S1 to S3 are repeated during the pulse period PP2 of pulse block 2, and then repeated again during the pulse period PP3 of pulse block 2, and so on until the pulse period PPN of pulse block 2.

[0171] In one embodiment, pulse block 1 of RF signal 134 includes any other number of states. For example, pulse block 1 includes four states or ten states.

[0172] In one embodiment, the pulse block 2 of the RF signal 134 includes any other number of states. For example, the pulse block 2 includes four states, five states, ten states, or twenty states.

[0173] Figure 6A depicts chart 400 of synchronization signal 102.

[0174] Figure 6B depicts a graph 604 illustrating the correction of the delay of the pulse block of the RF signal 132 generated by the RF generator 2 (Figure 1A) by the synchronization signal 102, such correction being, for example, removal, minimization, reduction, or deletion. Graph 604 plots the relative relationship between the variables of the RF signal 132 and time t. The variables of the RF signal 132 are plotted on the y-axis, and time t is plotted on the x-axis. The pulse block 1 of the RF signal 132 is delayed by one pulse cycle from time t0. This delay is illustrated by a diagonal line in graph 604. The state S1 of the (N-1)th part of the pulse block 1 of the RF signal 132 begins at time t9. The state S1 of the (N-1)th part of the pulse block 1 of the RF signal 132 ends at time t10, which is the time when the logic level of the synchronization signal 102 is 1. When the synchronization signal 102 is received by the RF generator 2 from, for example, the processor 106 illustrated in FIG. 1C or the RF generator 1 illustrated in FIG. 1A and 1B, state S1 of the (N-1)th part of pulse block 1 of RF signal 132 ends. Furthermore, at time t10 when the RF generator 2 receives the synchronization signal 102, the RF generator 2 does not generate states S1 to S3 of the Nth part of pulse block 1 of RF signal 132. Instead of generating states S1 to S3 of the Nth part of pulse block 1 of RF signal 132, the RF generator 2 generates state S1 of the first part of pulse block 2 at time t10.

[0175] During pulse period PP1, at time t10, the first portion of pulse block 2 of RF signal 132 transitions from variable level V0.25b to variable level V0.5b. From time t10 to time t11, the first portion of pulse block 2 of RF signal 132 is located at variable level V0.5b. Furthermore, during pulse period PP1, at time t11, the first portion of pulse block 2 of RF signal 132 transitions from variable level V0.5b to variable level V1b. From time t11 to time t12, the first portion of pulse block 2 of RF signal 132 is located at variable level V1b. At time t12, the first portion of pulse block 2 of RF signal 132 transitions from variable level V1b to variable level V0.5b.

[0176] The states S1 and S2 of the variables of RF signal 132 are repeated as each pulse period of pulse block 2 until the pulse period PPN of pulse block 2. For example, states S1 and S2 are repeated during the pulse period PP2 of pulse block 2, and then again during the pulse period PP3 of pulse block 2, and so on until the pulse period PPN of pulse block 2. As another example, due to the pulse 102B of synchronization signal 102, the Nth part of pulse block 2 of RF signal 132 ends at time t20, rather than at time t22 with a delay of one pulse period.

[0177] Figure 6C depicts a graph 606 illustrating the correction of the delay of the pulse block of the RF signal 134 generated by the RF generator z (Figure 1A) by the synchronization signal 102, such correction being, for example, removal, minimization, reduction, or deletion. Graph 606 plots the relative relationship between the variables of the RF signal 134 and time t. The variables of the RF signal 134 are plotted on the y-axis, and time t is plotted on the x-axis. Pulse block 1 of the RF signal 134 is delayed by two pulse cycles from time t0. The delay of pulse block 1 is illustrated by a diagonal line in graph 606. The state S1 of the (N-2)th part of pulse block 1 of the RF signal 134 begins at time t9. The state S1 of the (N-2)th part of pulse block 1 of the RF signal 134 ends at time t10, which is the time when the logic level of the synchronization signal 102 is 1. When the pulse 102B of the synchronization signal 102 is received by the RF generator z from, for example, the processor 106 illustrated in FIG1C, or the RF generator 1 illustrated in FIG1A, or the RF generator 2 illustrated in FIG1B, the state S1 of the (N-2)th part of the pulse block 1 of the RF signal 134 ends. Furthermore, at time t10 when the RF generator z receives the synchronization signal 102, the RF generator z does not generate states S1 and S2 of the (N-1)th part of the pulse block 1 of the RF signal 134, nor states S1 and S2 of the Nth part of the pulse block 1 of the RF signal 134. The RF generator z does not generate states S1 and S2 of each of the (N-1)th and Nth parts of the pulse block 1 of the RF signal 134, but instead generates state S2 of the first part of the pulse block 2 of the RF signal 134 at time t10.

[0178] During the pulse period PP1, at time t10, the first portion of pulse block 2 of RF signal 134 transitions from the variable level V0.33c to the variable level V1c. From time t10 to time t10.5, the first portion of pulse block 2 of RF signal 134 is located at the variable level V1c. Furthermore, during the pulse period PP1, at time t10.5, the first portion of pulse block 2 of RF signal 134 transitions from the variable level V1c to the variable level V1.66c. From time t10.5 to time t11, the first portion of pulse block 2 of RF signal 134 is located at the variable level V1.66c. At time t11, the first portion of pulse block 2 of RF signal 134 transitions from the variable level V1.66c to the variable level V0.66c. From time t11 to time t12, the first part of pulse block 2 of RF signal 134 is located at the variable level V0.66c. Pulse block 2 of RF signal 134 transitions from the variable level V0.66c to the variable level V1c at time t12.

[0179] The states S1 to S3 of the variables of RF signal 134 are repeated as each pulse period of pulse block 2 until the pulse period PPN of pulse block 2. For example, states S1 to S3 are repeated during the pulse period PP2 of pulse block 2, and then again during the pulse period PP3 of pulse block 2, and so on until the pulse period PPN of pulse block 2. As another example, due to pulse 102B of synchronization signal 102, the Nth part of pulse block 2 of RF signal 134 ends at time t20, instead of ending at time t24 with a delay of two pulse periods.

[0180] Figure 7 is a diagram illustrating an embodiment of the DSP1 of the RF generator 1, used to explain the calculation time for the generation of the pulses of the synchronization signal 102. The DSP1 receives recipe information 704 from the processor 106 (Figure 1A). The recipe information 704 includes, for example, a number of pulse periods x1 in each pulse block of the RF signal 130 to be generated by the RF generator 1. The recipe information 704 further includes the time interval y1 of each of the pulse periods x1. The DSP1 multiplies the number of pulse periods x1 by the time interval y1 to calculate or determine the time interval between two consecutive pulses of the synchronization signal 102. This time interval is determined as the result of x1 multiplied by y1. This time interval defines a predetermined frequency of these pulses of the synchronization signal 102, such as pulses 102A, 102B, and 102C. For example, the predetermined frequency between any two consecutive pulses of the synchronization signal 102 is equal to the result of x1 multiplied by y1.

[0181] DSP1 generates a synchronization signal 102 with multiple pulses. Any two consecutive pulses of the synchronization signal 102 are separated by the time interval, which is the result of x1 multiplied by y1. DSP1 sends the synchronization signal 102 to RF generators 2 to z to synchronize the operation of RF generators 2 to z with the operation of RF generator 1. For example, RF signals 130, 132, and 134 (FIG. 1A) are synchronized with the synchronization signal 102 to repeat pulse blocks 2, 3, and subsequent pulse blocks. For illustration, RF signals 130, 132, and 134 are generated at time t10 (FIG. 5A, 6B, and 6C) or with a minimum delay from time t10. To further illustrate, any of the pulse blocks 2 of RF signals 130, 132, and 134 is generated with a delay less than the pulse period of that pulse block.

[0182] In an embodiment where the synchronization signal 102 is generated by the processor 106 rather than the DSP1 of the RF generator 1, the processor 106, for example, reads the recipe information 704 from the memory device 108 (FIG. 1A) and multiplies the number of pulse periods x1 by the time interval y1 to calculate the time interval between two consecutive pulses of the synchronization signal 102 per pulse period. The processor 106 generates the synchronization signal 102 with these pulses and sends the synchronization signal 102 to the RF generator 1 to z.

[0183] Figure 8A is a diagram illustrating an embodiment of a system 800 for explaining the operation of RF generators 1 to z. System 800 includes RF generators 1 to z and a host 104. RF generator 1 includes a DSP 1, a parameter control system 1, a frequency (Freq.) control (Ctrl.) system 1, a driver system 1, an RF power supply PS 1, and an internal clock 1. The parameter control system 1 includes parameter controllers PR1S1 for state S1 of RF signal 130, up to parameter controller PR1Sn for state Sn of RF signal 130, where n is a positive integer. For example, examples of parameters used herein are voltage or power. The frequency control system 1 includes frequency controllers FC1S1 for state S1 of RF signal 130, up to frequency controller FC1Sn for state Sn of RF signal 130.

[0184] For example, an example of an internal clock used herein includes a clock circuit that generates a clock signal, such as a digital square waveform having logic level 1 and logic level 0. For illustration purposes, the clock signal transitions periodically between two logic levels 1 and 0 and has no other logic levels.

[0185] For example, the controllers used herein include processors and memory devices. The processor of the controller is coupled to the memory device of the controller. ASICs or PLCs are used instead of processors. In one embodiment, each controller includes a plurality of processors and a plurality of memory devices. The processors are coupled to the memory devices.

[0186] For example, the driver systems used herein include one or more drivers coupled to each other. For illustration, the drivers are transistors.

[0187] For example, the power supply used in this article is an example of an electronic oscillator, RF oscillator, or bulk oscillator that outputs an oscillating RF signal. An example of an oscillating RF signal is a sine wave.

[0188] DSP1 is coupled to parameter controllers PR1S1 to PR1Sn and to frequency controllers FC1S1 to FC1Sn. Internal clock 1 is coupled to DSP1, parameter controllers PR1S1 to PR1Sn and to frequency controllers FC1S1 to FC1Sn. Parameter controllers PR1S1 to PR1Sn and frequency controllers FC1S1 to FC1Sn are coupled to driver system 1, and driver system 1 is coupled to power supply PS1.

[0189] The RF generator 2 includes a DSP 2, an internal clock 2, a parameter control system 2, and a frequency control system 2. The RF generator 2 further includes a driver system 2 and a power supply PS 2. The parameter control system 2 includes complex parameter controllers PR2S1 to PR2Sm for each state of the parameters of the RF signal 132, where m is a positive integer. As an example, m is a number different from the integer n. For illustration, m is greater than or less than n. As another example, m is equal to n. The frequency control system 2 includes complex frequency controllers FC2S1 to FC2Sm for each state of the frequency of the RF signal 132.

[0190] DSP2 is coupled to parameter controllers PR2S1 to PR2Sm of parameter control system 2 and to frequency controllers FC2S1 to FC2Sm of parameter control system 2. Internal clock 2 is coupled to DSP2, parameter controllers PR2S1 to PR2Sm, and to frequency controllers FC2S1 to FC2Sm. Parameter controllers PR2S1 to PR2Sm and frequency controllers FC2S1 to FC2Sm are coupled to driver system 2, and driver system 2 is coupled to power supply PS2.

[0191] The RF generator z includes a DSP z, an internal clock z, a parameter control system z, and a frequency control system z. The RF generator z further includes a driver system z and a power supply PS z. The parameter control system z includes complex parameter controllers PRzS1 to PRzSp for each state of the parameters of the RF signal 134, where p is a positive integer. As an example, p is a number different from the integer m. For illustration, p is greater than or less than m. As another example, p is a number different from the integer n. For illustration, p is greater than or less than n. As another example, p is equal to m and / or n. The frequency control system z includes complex frequency controllers FCzS1 to FCzSp for each state of the frequency of the RF signal 134.

[0192] DSPz is coupled to parameter controllers PRzS1 to PRzSp and to frequency controllers FCzS1 to FCzSp. Internal clock z is coupled to DSPz, to parameter controllers PRzS1 to PRzSp, and to frequency controllers FCzS1 to FCzSp. Parameter controllers PRzS1 to PRzSp and frequency controllers FCzS1 to FCzSp are coupled to driver system z, and driver system z is coupled to power supply PSz.

[0193] The processor 106 is coupled to DSP1 via transmission cable 110, to DSP2 via transmission cable 112, and to DSP3 via transmission cable 114. DSP1 is coupled to DSP2 via communication cable 116 and to DSP3 via communication cable 118.

[0194] DSP1 receives recipe signal 120 from processor 106 and extracts recipe information for RF signal 130 from recipe signal 120. DSP1 sends the recipe information for RF signal 130 to parameter controllers PR1S1 to PR1Sn. For example, DSP1 sends recipe information for the state S1 of the parameters of RF signal 130 to parameter controller PR1S1 and so on until recipe information for the state Sn of the parameters of RF signal 130 is sent to parameter controller PR1Sn. Similarly, DSP1 sends recipe information for the state S1 of the frequency of RF signal 130 to frequency controller FC1S1 and so on until recipe information for the state Sn of the frequency of RF signal 130 is sent to frequency controller FC1Sn.

[0195] The parameter controller PR1S1 stores recipe information for the state S1 of the parameters of the RF signal 130 in one or more memory devices. Similarly, the parameter controller PR1Sn stores recipe information for the state Sn of the parameters of the RF signal 130 in one or more memory devices.

[0196] Furthermore, the frequency controller FC1S1 stores recipe information for the state S1 of the frequency of the RF signal 130 in one or more memory devices of the frequency controller FC1S1. Similarly, the frequency controller FC1Sn stores recipe information for the state Sn of the frequency of the RF signal 130 in one or more memory devices of the frequency controller FC1Sn.

[0197] DSP1, parameter controllers PR1S1 to PR1Sn, and frequency controllers FC1S1 to FC1Sn receive clock signal ck1 from internal clock 1. Furthermore, DSP1 receives TTL signal 128 from processor 106 via transmission cable 110 and executes the recipe information received in recipe signal 120 in response to the reception of TTL signal 128. For example, at the time of receiving TTL signal 128, DSP1 sends TTL signal 128 to parameter controllers PR1S1 to PR1Sn of RF generator 1 and to frequency controllers FC1S1 to FC1Sn of RF generator 1. Once TTL signal 128 is received from DSP1, parameter controller PR1S1 executes recipe information for the state S1 of the parameters of the RF signal 130 to be generated. For example, during clock cycle 1 of clock signal ck1, parameter controller PR1S1 sends an instruction signal containing the parameter level of state S1 for the parameters of RF signal 130 to driver system 1, for use in determining the time interval for generating state S1 of the parameters of RF signal 130. Once driver system 1 receives the instruction signal from parameter controller PR1S1 during clock cycle 1, it generates a current signal for state S1 of the parameters of RF signal 130 based on the instruction signal and sends the current signal to power supply PS1. Power supply PS1 receives the current signal for state S1 of RF signal 130 during clock cycle 1 and generates state S1 of the parameters of RF signal 130.

[0198] In this example, similarly, during clock cycle 1 of clock signal ck1, once TTL signal 128 is received from DSP1, parameter controller PR1Sn executes recipe information for the state Sn of the parameters to be generated for the RF signal 130. For illustration, during clock cycle 1 of clock signal ck1, parameter controller PR1Sn sends an instruction signal containing the parameter level for the state Sn of the parameters of RF signal 130 to driver system 1 for the time interval at which the state Sn of the parameters of RF signal 130 will be generated. Once the instruction signal is received from parameter controller PR1Sn during clock cycle 1 of clock signal ck1, driver system 1 generates a current signal for the state Sn of the parameters of RF signal 130 based on the instruction signal and sends the current signal to power supply PS1. During clock cycle 1 of clock signal ck1, power supply PS1 receives a current signal for the state Sn of parameter RF signal 130 and generates the state Sn of parameter RF signal 130.

[0199] Continuing this example, during clock cycle 1 of clock signal ck1, once TTL signal 128 is received from DSP1, frequency controller FC1Sn executes recipe information for the state Sn of the frequency of the RF signal 130 to be generated. For illustration, during clock cycle 1 of clock signal ck1, frequency controller FC1Sn sends an instruction signal containing the frequency level of the state Sn of the frequency of RF signal 130 to driver system 1 for the time interval at which the state Sn of the frequency of RF signal 130 will be generated. Once the instruction signal is received from frequency controller FC1Sn during clock cycle 1 of clock signal ck1, driver system 1 generates a current signal for the state Sn of the frequency of RF signal 130 based on the instruction signal and sends the current signal to power supply PS1. During clock cycle 1 of clock signal ck1, power supply PS1 receives a current signal for state Sn at the frequency of RF signal 130 and generates state Sn at the frequency of RF signal 130.

[0200] The states S1 to Sn of the variables of RF signal 130 are generated synchronously with the power supply PS1 and the clock signal ck1. For example, the states S1 to Sn of the parameters of RF signal 130 are repeated during clock cycle 2 of clock signal ck1. Clock cycle 2 of clock signal ck1 follows clock cycle 1 of clock signal ck1. There are no other clock cycles between clock cycle 1 and clock cycle 2 of clock signal ck1.

[0201] Similar to RF generator 1, RF generator 2 generates RF signal 132 having multiple states S1 to Sm, where m is a positive integer. For example, DSP2 receives recipe signal 122 and extracts recipe information for RF signal 132 from recipe signal 122. DSP2 sends the recipe information for RF signal 132 to parameter controllers PR2S1 to PR2Sm. For example, DSP2 sends recipe information for state S1 of parameters of RF signal 132 to parameter controller PR2S1 and so on until recipe information for state Sm of parameters of RF signal 132 is sent to parameter controller PR2Sm. Similarly, DSP2 sends recipe information for state S1 of frequency of RF signal 132 to frequency controller FC2S1 and so on until recipe information for state Sm of frequency of RF signal 132 is sent to frequency controller FC2Sm.

[0202] The parameter controller PR2S1 stores recipe information for the state S1 of the parameters of the RF signal 132 in one or more memory devices. Similarly, the parameter controller PR2Sm stores recipe information for the state Sm of the parameters of the RF signal 132 in one or more memory devices.

[0203] Furthermore, the frequency controller FC2S1 stores recipe information for the state S1 of the frequency of the RF signal 132 in one or more memory devices of the frequency controller FC2S1. Similarly, the frequency controller FC2Sm stores recipe information for the state Sm of the frequency of the RF signal 132 in one or more memory devices of the frequency controller FC2Sm.

[0204] DSP2, parameter controllers PR2S1 to PR2Sm, and frequency controllers FC2S1 to FC2Sm receive clock signal ck2 from internal clock 2. Furthermore, in response to receiving TTL signal 128 from processor 106 via transmission cable 112, DSP2 executes the recipe information received in recipe signal 122. For example, at the time of receiving TTL signal 128, DSP2 sends TTL signal 128 to parameter controllers PR2S1 to PR2Sm of RF generator 2 and to frequency controllers FC2S1 to FC2Sm of RF generator 2. Once TTL signal 128 is received from DSP2, parameter controller PR2S1 executes recipe information for the state S1 of the parameters of the RF signal 132 to be generated. For example, during clock cycle 1 of clock signal ck2, parameter controller PR2S1 sends an instruction signal containing the parameter level of state S1 for the parameters of RF signal 132 to driver system 2, for use in generating the time interval of state S1 for the parameters of RF signal 132. Once driver system 2 receives the instruction signal from parameter controller PR2S1 during clock cycle 1, it generates a current signal for state S1 of the parameters of RF signal 132 based on the instruction signal and sends the current signal to power supply PS2. Power supply PS2 receives the current signal for state S1 of RF signal 132 during clock cycle 1 and generates state S1 of the parameters of RF signal 132.

[0205] In this example, similarly, during clock cycle 1 of clock signal ck2, once TTL signal 128 is received from DSP2, parameter controller PR2Sm executes recipe information for the state Sm of the parameters of the RF signal 132 to be generated. For illustration, during clock cycle 1 of clock signal ck2, parameter controller PR2Sm sends an instruction signal containing the parameter level of the state Sm of the parameters of RF signal 132 to driver system 2 for the time interval at which the state Sm of the parameters of RF signal 132 will be generated. Once the instruction signal is received from parameter controller PR2Sm during clock cycle 1 of clock signal ck2, driver system 2 generates a current signal for the state Sm of the parameters of RF signal 132 based on the instruction signal and sends the current signal to power supply PS2. During clock cycle 1 of clock signal ck2, power supply PS2 receives a current signal for the state Sm of parameter RF signal 132 and generates the state Sm of parameter RF signal 132.

[0206] Continuing this example, during clock cycle 1 of clock signal ck2, once TTL signal 128 is received from DSP2, frequency controller FC2Sm executes recipe information for the state Sm of the frequency of the RF signal 132 to be generated. For illustration, during clock cycle 1 of clock signal ck2, frequency controller FC2Sm sends an instruction signal containing the frequency level of the state Sm of the frequency of RF signal 132 to driver system 2 for the time interval at which the state Sm of the frequency of RF signal 132 will be generated. Once the instruction signal is received from frequency controller FC2Sm during clock cycle 1 of clock signal ck2, driver system 2 generates a current signal for the state Sm of the frequency of RF signal 132 based on the instruction signal and sends the current signal to power supply PS2. During clock cycle 1 of clock signal ck2, power supply PS2 receives a current signal for state Sm of frequency of RF signal 132 and generates state Sm of frequency of RF signal 132.

[0207] The states S1 to Sm of the variables of RF signal 132 are generated synchronously by power supply PS2 and clock signal ck2. For example, the states S1 to Sm of the parameters of RF signal 132 are repeated during clock cycle 2 of clock signal ck2. Clock cycle 2 of clock signal ck2 follows clock cycle 1 of clock signal ck2. There are no other clock cycles between clock cycle 1 and clock cycle 2 of clock signal ck2.

[0208] Furthermore, similar to RF generator 1, RF generator z generates RF signal 134 having multiple states S1 to Sp, where p is a positive integer. For example, DSP z receives recipe signal 124 and extracts recipe information for RF signal 134 from recipe signal 124. DSP z sends the recipe information for RF signal 134 to parameter controllers PRzS1 to PRzSp. For example, DSP z sends recipe information for state S1 of parameters of RF signal 134 to parameter controller PRzS1 and so on until recipe information for state Sp of parameters of RF signal 134 is sent to parameter controller PRzSp. Similarly, DSP z sends recipe information for state S1 of frequency of RF signal 134 to frequency controller FCzS1 and so on until recipe information for state Sp of frequency of RF signal 134 is sent to frequency controller FCzSp.

[0209] The parameter controller PRzS1 stores recipe information for the state S1 of the parameters of the RF signal 134 in one or more memory devices. Similarly, the parameter controller PRzSp stores recipe information for the state Sp of the parameters of the RF signal 134 in one or more memory devices.

[0210] Furthermore, the frequency controller FCzS1 stores recipe information for the state S1 of the frequency of the RF signal 134 in one or more memory devices of the frequency controller FCzS1. Similarly, the frequency controller FCzSp stores recipe information for the state Sp of the frequency of the RF signal 134 in one or more memory devices of the frequency controller FCzSp.

[0211] The DSPz, parameter controllers PRzS1 to PRzSp, and frequency controllers FCzS1 to FCzSp receive clock signals ckz from the internal clock z. Furthermore, in response to receiving TTL signal 128 from processor 106 via transmission cable 114, the DSPz executes the recipe information received in recipe signal 124. For example, at the time of receiving TTL signal 128, the DSPz sends TTL signal 128 to parameter controllers PRzS1 to PRzSp of RF generator z and to frequency controllers FCzS1 to FCzSp of RF generator z. Once the TTL signal 128 is received from the DSPz, parameter controller PRzS1 executes recipe information for the state S1 of the parameters of the RF signal 134 to be generated. For example, during clock cycle 1 of clock signal ckz, parameter controller PRzS1 sends an instruction signal containing the parameter level of state S1 for parameters of RF signal 134 to driver system z, for the time interval at which state S1 of parameters of RF signal 134 will be generated. Once the instruction signal is received from parameter controller PRzS1 during clock cycle 1, driver system z generates a current signal for state S1 of parameters of RF signal 134 based on the instruction signal and sends the current signal to power supply PSz. Power supply PSz receives the current signal for state S1 of RF signal 134 during clock cycle 1 and generates state S1 of parameters of RF signal 134.

[0212] In this example, similarly, during clock cycle 1 of clock signal ckz, once TTL signal 128 is received from DSPz, parameter controller PRzSp executes recipe information for the state Sp of the parameters of the RF signal 134 to be generated. For illustration, during clock cycle 1 of clock signal ckz, parameter controller PRzSp sends an instruction signal containing the parameter level of the state Sp of the parameters of RF signal 134 to driver system z for the time interval at which the state Sp of the parameters of RF signal 134 will be generated. Once the instruction signal is received from parameter controller PRzSp during clock cycle 1 of clock signal ckz, driver system z generates a current signal for the state Sp of the parameters of RF signal 134 based on the instruction signal and sends the current signal to power supply PSz. During clock cycle 1 of clock signal ckz, power supply PSz receives the current signal for the state Sp of the parameters of RF signal 134 and generates the state Sp of the parameters of RF signal 134.

[0213] Continuing this example, during clock cycle 1 of clock signal ckz, once TTL signal 128 is received from DSPz, frequency controller FCzSp executes recipe information for the state Sp of the frequency of the RF signal 134 to be generated. For illustration, during clock cycle 1 of clock signal ckz, frequency controller FCzSp sends an instruction signal containing the frequency level of the state Sp of the frequency of RF signal 134 to driver system z for the time interval at which the state Sp of the frequency of RF signal 134 will be generated. Once the instruction signal is received from frequency controller FCzSp during clock cycle 1 of clock signal ckz, driver system z generates a current signal for the state Sp of the frequency of RF signal 134 based on the instruction signal and sends the current signal to power supply PSz. During clock cycle 1 of clock signal ckz, power supply PSz receives the current signal for the state Sp of the frequency of RF signal 134 and generates the state Sp of the frequency of RF signal 134.

[0214] The states S1 to Sp of the variables of RF signal 134 are generated synchronously with the clock signal ckz via the power supply PSz. For example, the states S1 to Sp of the parameters of RF signal 134 are repeated during clock cycle 2 of clock signal ckz. Clock cycle 2 of clock signal ckz follows clock cycle 1 of clock signal ckz. There are no other clock cycles between clock cycle 1 and clock cycle 2 of clock signal ckz.

[0215] The DSP1 of the RF generator 1 generates a synchronization signal 102 and sends the synchronization signal 102 to the parameter controllers PR1S1 to PR1Sn and to the frequency controllers FC1S1 to FC1Sn. Because there is no error caused by the internal clock 1 of the RF generator 1, there is no need to reduce the delay of the pulse blocks of the RF signal 130. Instead, the parameter control system 1 and the frequency control system 1 control the power supply PS1 in the manner described above to generate the pulse blocks of the RF signal 130, and these pulse blocks are synchronized with the synchronization signal 102. In the event of an error caused by the internal clock 1 of the RF generator 1, the pulse blocks of the RF signal 130 are synchronized with the synchronization signal 102 by means of the parameter controllers PR1S1 to PR1Sn and the frequency controllers FC1S1 to FC1Sn in the manner described below.

[0216] When DSP2 of RF generator 2 receives a pulse of synchronization signal 102 from DSP1 via communication cable 116, DSP2 sends the pulse of synchronization signal 102 to parameter controllers PR2S1 to PR2Sm and to frequency controllers FC2S1 to FC2Sm. Once the pulse of synchronization signal 102 is received, parameter controllers PR2S1 to PR2Sm and frequency controllers FC2S1 to FC2Sm do not generate instruction signals for generating one or more remaining portions of the currently generated pulse block of RF signal 132, such as the Nth portion or the (N-1)th and Nth portions. An example of the currently generated pulse block of RF signal 132 is the pulse block being generated at the time when the pulse of synchronization signal 102 is received from DSP2 by parameter controllers PR2S1 to PR2Sm and frequency controllers FC2S1 to FC2Sm. For the sake of illustration, the currently generated pulse block is pulse block 1 of RF signal 132 at time t10 when synchronization pulse 102B is received. As another explanation, the currently generated pulse block is pulse block 2 of RF signal 132 at time t20 when synchronization pulse 102C is received.

[0217] Instead of generating one or more remaining portions of the currently generated pulse block of RF signal 132 at the time when the pulse of synchronization signal 102, such as pulse 102A, is received by RF generator 2, RF generator 2 generates a continuous following pulse block of RF signal 132, such as pulse block 2. For example, referring to FIG6B, at time t10, instead of parameter controllers PR2S2, PR2S3, and PR2S1 sending the parameter levels of states S2, S3, and S1 for the Nth part of pulse block 1 of RF signal 132 to driver system 2, parameter controllers PR2S1 and PR2S2 send the parameter levels of states S1 and S2 for the first part of pulse block 2 of RF signal 132 to driver system 2. As another example, at time t10, instead of frequency controllers FC2S2, FC2S3, and FC2S1 sending the frequency levels of states S2, S3, and S1 of the Nth part of pulse block 1 for RF signal 132 to driver system 2, frequency controllers FC2S1 and FC2S2 send the frequency levels of states S1 and S2 of the first part of pulse block 2 for RF signal 132 to driver system 2.

[0218] As another example, referring to FIG6B, when the Nth part of the pulse block 1 of RF signal 132 is delayed by one or more states (e.g., state S1) of the Nth part of the pulse block 1, at time t10, instead of the parameter controller PR2S1 sending the parameter level for state S1 of the Nth part of the pulse block 1 of RF signal 132 to the driver system 2, the parameter controller PR2S1 sends the parameter level for state S1 of the first part of the pulse block 2 of RF signal 132 to the driver system 2. As another example, when the Nth part of the pulse block 1 of RF signal 132 is delayed by one or more states (e.g., state S1) of the Nth part of the pulse block 1, at time t10, instead of the frequency controller FC2S1 sending the frequency level for state S1 of the Nth part of the pulse block 1 of RF signal 132 to the driver system 2, the frequency controller FC2S1 sends the frequency level for state S1 of the first part of the pulse block 2 of RF signal 132 to the driver system 2.

[0219] Similarly, when the DSPz of the RF generator z receives a pulse of the synchronization signal 102 from the DSP1 via the communication cable 118, the DSPz sends the pulse of the synchronization signal 102 to the parameter controllers PRzS1 to PRzSp and to the frequency controllers FCzS1 to FCzSp. Once the pulse of the synchronization signal 102 is received, the parameter controllers PRzS1 to PRzSp and the frequency controllers FCzS1 to FCzSp do not generate instruction signals for generating one or more of the remaining portions of the currently generated pulse block of the RF signal 134, such as the Nth portion, or the (N-1)th and Nth portions, or the (N-2), (N-1)th and Nth portions. An example of the currently generated pulse block of the RF signal 134 is the pulse block being generated at the time when the pulse of the synchronization signal 102 is received from the DSPz by the parameter controllers PRzS1 to PRzSp and the frequency controllers FCzS1 to FCzSp. For the sake of illustration, the currently generated pulse block is pulse block 1 of RF signal 134 at time t10 when synchronization pulse 102B is received. As another explanation, the currently generated pulse block is pulse block 2 of RF signal 134 at time t20 when synchronization pulse 102C is received.

[0220] Instead of generating one or more remaining portions of the currently generated pulse block of RF signal 134 at the time when the pulse of synchronization signal 102, such as pulse 102B, is received by RF generator z, RF generator z generates a continuous following pulse block of RF signal 134, such as pulse block 2. For example, referring to FIG6C, at time t10, instead of parameter controllers PRzS2 and PRzS1 sending the parameter levels of states S2 and S1 for the (N-1)th part of pulse block 1 of RF signal 134 to driver system z, parameter controllers PRzS2, PRzS3, and PRzS1 send the parameter levels of states S2, S3, and S1 for the first part of pulse block 2 of RF signal 134 to driver system z. As another example, at time t10, instead of frequency controllers FCzS2 and FCzS1 sending the frequency levels of states S2 and S1 for the (N-1)th part of pulse block 1 of RF signal 134 to driver system z, frequency controllers FCzS2, FCzS3, and FCzS1 send the frequency levels of states S2, S3, and S1 for the first part of pulse block 2 of RF signal 134 to driver system z.

[0221] As another example, referring to FIG6C, when the Nth part of the pulse block 1 of RF signal 134 is delayed by one or more states (e.g., state S1) of the Nth part of the pulse block 1, at time t10, instead of the parameter controller PRzS1 sending the parameter level for state S1 of the Nth part of the pulse block 1 of RF signal 134 to the driver system z, the parameter controller PRzS2 sends the parameter level for state S2 of the first part of the pulse block 2 of RF signal 134 to the driver system z. As another example, if the Nth portion of pulse block 1 of RF signal 134 is delayed by one or more states (e.g., state S1) of the Nth portion of pulse block 1, at time t10, instead of frequency controller FCzS1 sending the frequency level for state S1 of the Nth portion of pulse block 1 of RF signal 134 to driver system z, frequency controller FCzS2 sends the frequency level for state S2 of the first portion of pulse block 2 of RF signal 134 to driver system z. In this way, each pulse block of RF signals 130, 132, and 134, for example, pulse block 2 or pulse block 3, is generated synchronously with synchronization signal 102.

[0222] In one embodiment, the synchronization signal 102 is generated by the processor 106, not the DSP1. The processor 106 transmits the synchronization signal 102 to the DSP1 via transmission cable 110, to the DSP2 via transmission cable 112, and to the DSPz via transmission cable 114. Once the RF generators 2 to z receive the synchronization signal 102, they operate in the same manner as described above with reference to FIG8A. When the DSP1 of the RF generator 1 receives the pulse of the synchronization signal 102 from the processor 106, the DSP1 transmits the pulse of the synchronization signal 102 to the parameter controllers PR1S1 to PR1Sn and to the frequency controllers FC1S1 to FC1Sn. Once the pulse of the synchronization signal 102 is received, the parameter controllers PR1S1 to PR1Sn and the frequency controllers FC1S1 to FC1Sn do not generate instruction signals for producing one or more of the remaining portions of the currently generated pulse block of the RF signal 130, such as the Nth portion or the (N-1)th and Nth portions. An example of a currently generated pulse block for RF signal 130 is the pulse block being generated at the time when the pulses of synchronization signal 102 are received from DSP1 by parameter controllers PR1S1 to PR1Sn and frequency controllers FC1S1 to FC1Sn. For illustrative purposes, this currently generated pulse block is pulse block 1 of RF signal 130 at time t10 when synchronization pulse 102B is received. As another example, this currently generated pulse block is pulse block 2 of RF signal 130 at time t20 when synchronization pulse 102C is received.

[0223] Continuing from the previous embodiment, instead of generating one or more remaining portions of the currently generated pulse block of RF signal 130 at the time when the pulse of synchronization signal 102, for example, pulse 102B, is received by RF generator 1, RF generator 1 generates a continuous following pulse block of RF signal 130, such as pulse block 2. For example, referring to FIG5A, when the Nth portion of pulse block 1 of RF signal 130 is delayed by one pulse period of pulse block 1, at time t10, instead of parameter controllers PR1S4, PR1S3, PR1S2, and PR1S1 sending parameter levels for the states S4, S3, S2, and S1 of the Nth portion of pulse block 1 of RF signal 130 to driver system 1, parameter controllers PR1S3, PR1S2, and PR1S2 send parameter levels for the states S3, S2, and S1 of the first portion of pulse block 2 of RF signal 130 to driver system 1. As another example, when the Nth part of the pulse block 1 of the RF signal 130 is delayed by one pulse period, at time t10, instead of the frequency controllers FC1S4, FC1S3, FC1S2, and FC1S1 sending the frequency levels of the states S4, S3, S2, and S1 for the Nth part of the pulse block 1 of the RF signal 130 to the driver system 1, the frequency controllers FC1S3, FC1S2, and FC1S1 send the frequency levels of the states S3, S2, and S1 for the first part of the pulse block 2 of the RF signal 130 to the driver system 1.

[0224] Furthermore, in this embodiment, as yet another example, referring to FIG6A, when the Nth part of the pulse block 1 of the RF signal 130 is delayed by one or more states (e.g., state S1) of the Nth part of the pulse block 1, at time t10, instead of the parameter controller PR1S1 sending the parameter level for state S1 of the Nth part of the pulse block 1 of the RF signal 130 to the driver system 1, the parameter controller PR1S3 sends the parameter level for state S3 of the first part of the pulse block 2 of the RF signal 130 to the driver system 1. As another example, referring to Figure 5A, when the Nth part of the pulse block 1 of the RF signal 130 is delayed by one or more states (e.g., state S1) of the Nth part of the pulse block 1, at time t10, instead of the frequency controller FC1S1 sending the frequency level for state S1 of the Nth part of the pulse block 1 of the RF signal 130 to the driver system 1, the frequency controller FC1S3 sends the frequency level for state S3 of the first part of the pulse block 2 of the RF signal 130 to the driver system 1.

[0225] In one embodiment, the combination of the frequency control system of the RF generator, the parameter control system of the RF generator, and the DSP of the RF generator is sometimes referred to herein as the processor system of the RF generator. The processor system includes one or more processors and one or more memory devices. The one or more processors are coupled to the one or more memory devices.

[0226] In one embodiment, one or more controllers are used in the RF generator to replace the combination of the RF generator's frequency control system, parameter control system, and DSP. For example, the one or more controllers include one or more processors and one or more memory devices. The one or more processors are coupled to the one or more memory devices. The one or more processors execute logic to implement the functions described herein as achieved by the combination of the RF generator's frequency control system, parameter control system, and DSP.

[0227] In one embodiment, the frequency of the RF signal, such as RF signal 130, 132, or 134 described herein, has a state, which is, for example, a single state. The frequency of the RF signal does not transition from one frequency level to another.

[0228] In one embodiment, the parameters of the RF signals described herein, such as RF signals 130, 132, or 134, have a state, which is, for example, a single state. The parameters of the RF signal do not transition from one parameter level to another.

[0229] Figure 8B is a diagram illustrating an embodiment of a system 850 used to transmit a synchronization signal 102 from RF generator 1 to RF generators 2 to 3. The system 850 includes a host 104 and RF generators 1 to 3.

[0230] RF generator 1 includes a communication controller 1. Similarly, RF generator 2 includes a communication controller 2 and RF generator z includes a communication controller z. The communication controller includes port PRT1. Communication controller 2 includes ports PRT2a and PRT2b. Communication controller z includes port PRT2z.

[0231] Communication controller 1 is coupled to DSP1. Communication controller 2 is coupled to DSP2, and communication controller z is coupled to DSPz.

[0232] Communication controller 1 receives synchronization signal 102 from DSP 1, extracts timing information for RF generator 2 to z from synchronization signal 102, and embeds the timing information into one or more EtherCAT frames. Communication controller 1 transmits the one or more EtherCAT frames to port PRT2a via port PRT1 and communication cable 142. During the time period during which the one or more EtherCAT frames are transmitted from port PRT2a to port PRT2b, communication controller 2 extracts the timing information of synchronization signal 102 from the one or more EtherCAT frames and sends the timing information to DSP 2 for execution of the timing information. DSP 2 executes the timing information of synchronization signal 102 by sending pulses of synchronization signal to parameter control system 2 and frequency control system 2 in the same manner as described above with reference to FIG8A.

[0233] Communication controller 2 transmits one or more EtherCAT frames to port PRT2b via port PRT2b and communication cable 144. Communication controller z retrieves the timing information of synchronization signal 102 from the one or more EtherCAT frames and sends the timing information to DSPz for execution of the timing information. DSPz executes the timing information of synchronization signal 102 by sending pulses of the synchronization signal to parameter control system z and frequency control system z in the same manner as described above with reference to FIG8A.

[0234] For the return path of the one or more EtherCAT frames, the communication controller z further transmits the one or more EtherCAT frames from PRT2b to port PRT2b via communication cable 144. The communication controller 2 transmits the one or more EtherCAT frames from port PRT2b to port PRT2a. The communication controller 2 sends the one or more EtherCAT frames from port PRT2a to port PRT1 via communication cable 142. The communication controller 1 obtains or captures the timing information of the synchronization signal 102 from the one or more EtherCAT frames and sends the timing information back to the DSP1 of the RF generator 1.

[0235] In one embodiment, the timing information of the synchronization signal 102 is the same as that of the synchronization signal 102.

[0236] The embodiments described herein can be practiced in a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. These embodiments can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units connected via a network.

[0237] In some embodiments, the controller is part of a system, which may be part of the above-described examples. Such a system includes a semiconductor processing apparatus, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, airflow systems, etc.). These systems are integrated with electronic components for controlling the operation of the system before, during, and after the processing of semiconductor wafers or substrates. These electronic components are referred to as "controllers" and can control various components or sub-parts of the system or multiple systems. Depending on the process conditions and / or the type of system, the controller is programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positioning and operation settings, wafer in / out tools, and other transfer tools and / or loading locks coupled to or interfaced with the system.

[0238] Broadly speaking, in many embodiments, a controller can be defined as an electronic component having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, performs cleaning operations, performs endpoint measurements, and so on. Integrated circuits include chips in the form of firmware storing program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions transmitted to the controller in the form of various individual settings (or program files) and define parameters, factors, variables, etc., for performing specific processes on or on a semiconductor wafer or on a system. In some embodiments, program instructions are portions of a recipe defined by a process engineer to complete one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0239] In some embodiments, the controller is part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be located in the cloud or in part of a wafer fab host system, allowing remote access to wafer processing. The computer enables remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, examine trends or performance indicators from multiple manufacturing operations, change parameters for current processing, set processing steps to follow the current process, or start a new process.

[0240] In some instances, a remote computer (e.g., a server) provides process recipes to the system via a network, which may include a local area network or the Internet. The remote computer includes a user interface that enables the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters, factors, and / or variables for each processing step to be performed during one or more operations. It should be understood that these parameters, factors, and / or variables are specific to the type of process to be performed and the type of tools that the controller is configured to interface with or control. Therefore, as described above, the controller is distributed, for example by means of one or more distributed controllers that are networked together and operate toward a common purpose, such as the process and control described herein. Examples of distributed controllers for such purposes include one or more integrated circuits on a chamber that communicate with one or more integrated circuits at a remote location (e.g., located at the platform layer or as part of a remote computer), which are combined to control the process on the chamber.

[0241] Without limitation, in many embodiments, exemplary systems applying the methods described herein include plasma etching chambers or modules, deposition chambers or film modules, spin cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems that may be associated with or used in the manufacture and / or production of semiconductor wafers.

[0242] Please note again that in some embodiments, the above operations are applied to several types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, transformer-coupled plasma chambers, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, etc. For example, one or more RF generators are coupled to an inductor within the ICP reactor. Examples of inductor shapes include solenoids, dome-shaped coils, flat coils, etc.

[0243] As mentioned above, depending on one or more processing steps to be performed using the tool, the host communicates with one or more of the following: other tool circuits or modules, other tool assemblies, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the plant, host computer, another controller, or other tools used for material transfer in the semiconductor manufacturing plant that carry wafer containers to and from tool locations and / or loading ports.

[0244] In considering the above embodiments, it should be understood that some embodiments employ multiple computers that involve data stored in a computer system to perform operations. These operations are operations that physically manipulate physical quantities. Any operations described herein that constitute part of the embodiments are useful mechanical operations.

[0245] Some embodiments also relate to hardware units or devices for performing these operations. The device is specifically configured as a special-purpose computer. When defined as a special-purpose computer, the computer performs other processing, program execution, or routines that are not for special purposes, while still being able to operate for special purposes.

[0246] In some embodiments, these operations may be processed by a computer selectively started or configured by one or more computer programs stored in computer memory, cache memory, or obtained via a computer network. When data is obtained via a computer network, the data may be processed by other computers on the computer network, such as a computing resource cloud.

[0247] One or more embodiments may also be manufactured as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit that stores data, such as memory devices, etc., which is then read by a computer system. Examples of non-transitory computer-readable media include hard disks, network-attached storage (NAS), ROM, RAM, optical disc-ROMs (CD-ROMs), recordable optical discs (CD-Rs), rewritable optical discs (CD-RWs), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes computer-readable tangible media distributed across a network-coupled computer system, such that the computer-readable code is stored and executed in a distributed manner.

[0248] Although the above method operations have been described in a specific order, it should be understood that in many embodiments, other miscellaneous operations may be performed between the two operations, or the method operations may be adjusted so that they occur at slightly different times, or they may be distributed in a system that allows the method operations to occur at many intervals, or the method operations may be performed in a different order than described above.

[0249] It should be noted again that in one embodiment, one or more features in any of the above embodiments are combined with one or more features in any other embodiment without departing from the scope of the many embodiments described in this disclosure.

[0250] Although the above embodiments have been described in some detail for clarity, it will be apparent that certain variations and modifications may be made within the scope of the appended claims. Therefore, the embodiments herein should be considered illustrative rather than restrictive, and are not limited to the details given herein. [Simplified Explanation of the Diagram]

[0017] The best understanding of the embodiments can be obtained by referring to the following description in conjunction with the accompanying drawings.

[0018] Figure 1A is a diagram illustrating an embodiment of a system for synchronizing the operation of a complex radio frequency (RF) generator using a synchronization signal.

[0019] Figure 1B is a diagram illustrating an embodiment of a system using an EtherCAT (ECAT) cable for transmitting synchronization signals.

[0020] Figure 1C is a diagram of an embodiment of a system having a processor that generates and transmits synchronization signals to an RF generator.

[0021] Figure 2A is a diagram illustrating the use of an RF generator with a capacitively coupled plasma chamber.

[0022] Figure 2B is a diagram illustrating an embodiment of a system for a transformer coupled plasma (TCP) chamber.

[0023] Figure 3A depicts a diagram used to illustrate transistor-to-transistor (TTL) signals.

[0024] Figure 3B depicts a diagram illustrating the multi-pulse blocks of the RF signal generated by the RF generator.

[0025] Figure 3C is a diagram illustrating the multi-pulse blocks of the RF signal generated by the RF generator when the RF generator does not receive a synchronization signal.

[0026] Figure 3D is a diagram illustrating the multi-pulse blocks of the RF signal generated by the RF generator when the RF generator does not receive a synchronization signal.

[0027] Figure 3E depicts a graph illustrating the forward (FWD) power of the RF signal supplied by the RF generator.

[0028] Figure 3F depicts a graph illustrating the reverse (REV) power received by the RF generator.

[0029] Figure 3G depicts a graph illustrating the positive power of the RF signal supplied by the RF generator.

[0030] Figure 3H depicts a graph to illustrate the reverse power received by the RF generator.

[0031] Figure 4A depicts a diagram used to illustrate the synchronization signal.

[0032] Figure 4B depicts a graph illustrating the reduction of delay in multi-pulse blocks of RF signals generated by an RF generator through synchronization signals.

[0033] Figure 4C depicts a graph illustrating the reduction of delay in multi-pulse blocks of RF signals generated by an RF generator through synchronization signals.

[0034] Figure 5A depicts a diagram to illustrate each pulse block of the RF signal.

[0035] Figure 5B depicts a diagram illustrating each pulse block of an RF signal.

[0036] Figure 5C depicts a diagram to illustrate each pulse block of the RF signal.

[0037] Figure 6A is a diagram depicting the synchronization signal of Figure 4A.

[0038] Figure 6B depicts a graph illustrating the reduction of delay in the pulse block of the RF signal in Figure 4B by using a synchronization signal.

[0039] Figure 6C depicts a graph illustrating the reduction of pulse block delay in the RF signal of Figure 4C by using a synchronization signal.

[0040] Figure 7 is a diagram of an embodiment of the digital signal processor of the RF generator, which is used to illustrate the calculation time for the generation of the synchronization signal pulse.

[0041] Figure 8A is a diagram illustrating an embodiment of a system for explaining the operation of an RF generator.

[0042] Figure 8B is a diagram illustrating an embodiment of a system for using EtherCAT to send synchronization signals from a master RF generator to multiple RF generators.

Claims

1. A method for synchronizing a radio frequency (RF) generator, comprising: receiving first recipe information in a first recipe signal via a first radio frequency (RF) generator, wherein the first recipe information relates to a first complex pulse block output from the first RF generator; receiving second recipe information in a second recipe signal via a second RF generator, wherein the second recipe information relates to a second complex pulse block output from the second RF generator; receiving a digital pulse signal via the first and second RF generators, wherein upon receiving the digital pulse signal, the first recipe information is executed by the first RF generator and the second recipe information is executed by the second RF generator; outputting a first pulse block in the first complex pulse block synchronously with a synchronization signal based on the first recipe information by the first RF generator; and outputting a first pulse block in the second complex pulse block synchronously with the synchronization signal based on the second recipe information by the second RF generator.

2. The method of claim 1 further comprises: generating the synchronization signal by the first RF generator; sending the synchronization signal from the first RF generator to the second RF generator; and receiving the synchronization signal from the first RF generator by the second RF generator, wherein the step of outputting the first pulse block in the second complex pulse block in sync with the synchronization signal is performed in response to the step of receiving the synchronization signal.

3. The method of claim 1, wherein the synchronization signal is generated by a processor of a host, the method further comprising: receiving the synchronization signal from the processor via the first RF generator, wherein the step of outputting a first pulse block of the first complex pulse block in sync with the synchronization signal is performed in response to the step of receiving the synchronization signal via the first RF generator; and receiving the synchronization signal from the processor via the second RF generator, wherein the step of outputting a first pulse block of the second complex pulse block in sync with the synchronization signal is performed in response to the step of receiving the synchronization signal via the second RF generator.

4. The method of claim 1, wherein the digital pulse signal is a transistor-to-transistor logic (TTL) signal.

5. The method of claim 1 further comprises: generating an Ethernet for Control Automation (ECAT) column by the first RF generator, the ECAT column including information about the synchronization signal, wherein the information about the synchronization signal includes a frequency of a pulse of the synchronization signal; transmitting the ECAT column from the first RF generator to the second RF generator; and receiving the information about the synchronization signal in the ECAT column from the first RF generator by the second RF generator.

6. The method of claim 1, further comprising: outputting the second pulse block of the second complex pulse block by the second RF generator after a delay compared to the second pulse block in the first complex pulse block, wherein the second pulse block of the second complex pulse block is output before the synchronization signal is received by the second RF generator, wherein the second pulse block of the first complex pulse block is generated before the first pulse block of the first complex pulse block is generated, wherein the second pulse block of the second complex pulse block is generated before the first pulse block of the second complex pulse block is generated, wherein the delay is equal to a time interval of a portion of any pulse block in the second complex pulse block.

7. The method of claim 1, wherein each of the first complex pulse blocks is an encapsulation of a variable of a first RF signal, wherein each of the first complex pulse blocks includes two or more states of the variable of the first RF signal, wherein each of the second complex pulse blocks is an encapsulation of a variable of a second RF signal, wherein each of the second complex pulse blocks includes two or more states of the variable of the second RF signal.

8. The method of claim 7, wherein the first complex pulse block includes a second pulse block, wherein the second pulse block in the first complex pulse block is a continuation of the first pulse block in the first complex pulse block, wherein the second complex pulse block includes a second pulse block, wherein the second pulse block in the second complex pulse block is a continuation of the first pulse block in the second complex pulse block.

9. The method of claim 1, wherein the synchronization signal comprises a complex pulse, wherein a time interval between two consecutive pulses in the complex pulse is generated based on the number of pulse cycles in one pulse block of the first complex pulse block and a time interval of one pulse cycle in one pulse block of the first complex pulse block.

10. A system for synchronizing a radio frequency (RF) generator, comprising: a first RF generator configured to receive first recipe information in a first recipe signal, wherein the first recipe information relates to a first complex pulse block output from the first RF generator; and a second RF generator configured to receive second recipe information in a second recipe signal, wherein the second recipe information relates to a second complex pulse block output from the second RF generator, wherein the first and second RF generators are configured to receive a digital pulse signal, wherein upon receiving the digital pulse signal, the first RF generator is configured to execute the first recipe information and the second RF generator is configured to execute the second recipe information, wherein during the execution of the first recipe information, the first RF generator is configured to generate a synchronization signal and provide the synchronization signal to the second RF generator, wherein the first RF generator is configured to output the first pulse block in the first complex pulse block synchronously with the synchronization signal based on the first recipe information. Once the synchronization signal is received, the second RF generator is configured to output the first pulse block in the second complex pulse block in sync with the synchronization signal based on the second recipe information.

11. The system of claim 10, wherein the first RF generator is configured to generate an Ethernet Controlled Automation (ECAT) column, the ECAT column including information about the synchronization signal, wherein the information about the synchronization signal includes a frequency of the pulse of the synchronization signal, wherein in order to provide the synchronization signal to the second RF generator, the first RF generator is configured to send the ECAT column to the second RF generator.

12. The system of claim 10, wherein the second RF generator is configured to transmit the second pulse block of the second complex pulse block after a delay compared to the second pulse block in the first complex pulse block, wherein the second pulse block of the second complex pulse block is output before the synchronization signal is received by the second RF generator, wherein the second pulse block of the first complex pulse block is generated before the first pulse block in the first complex pulse block is generated, wherein the second pulse block of the second complex pulse block is generated before the first pulse block in the second complex pulse block is generated, wherein the delay is equal to a time interval of a portion of any pulse block in the second complex pulse block.

13. The system of claim 10, wherein each of the first complex pulse blocks is an encapsulation of a variable of a first RF signal, wherein each of the first complex pulse blocks includes two or more states of the variable of the first RF signal, wherein each of the second complex pulse blocks is an encapsulation of a variable of a second RF signal, wherein each of the second complex pulse blocks includes two or more states of the variable of the second RF signal.

14. The system of claim 10, wherein the synchronization signal comprises a complex pulse, wherein a time interval between two consecutive pulses in the complex pulse is generated based on the number of pulse cycles in one pulse block of the first complex pulse block and a time interval of one pulse cycle in one pulse block of the first complex pulse block.

15. The system of claim 10, wherein the digital pulse signal is a transistor-to-transistor logic (TTL) signal.

16. The system of claim 10, wherein the synchronization signal comprises a complex number of pulses having a predetermined frequency.

17. A system for synchronizing radio frequency (RF) generators, comprising: a first RF generator configured to receive first recipe information in a first recipe signal, wherein the first recipe information relates to a first complex pulse block output from the first RF generator; a second RF generator configured to receive second recipe information in a second recipe signal, wherein the second recipe information relates to a second complex pulse block output from the second RF generator; and a host coupled to the first and second RF generators, wherein the host is configured to generate a digital pulse signal and a synchronization signal, wherein the first and second RF generators are configured to receive the digital pulse signal and the synchronization signal from the host, wherein upon receiving the digital pulse signal, the first RF generator is configured to execute the first recipe information and the second RF generator is configured to execute the second recipe information, wherein upon receiving the synchronization signal, the first RF generator is configured to output the first pulse block in the first complex pulse block synchronously with the synchronization signal based on the first recipe information. Once the synchronization signal is received, the second RF generator is configured to output the first pulse block in the second complex pulse block in sync with the synchronization signal based on the second recipe information.

18. The system of claim 17, wherein each of the first complex pulse blocks is an encapsulation of a variable of a first RF signal, wherein each of the first complex pulse blocks includes two or more states of the variable of the first RF signal, wherein each of the second complex pulse blocks is an encapsulation of a variable of a second RF signal, wherein each of the second complex pulse blocks includes two or more states of the variable of the second RF signal.

19. The system of claim 17, wherein the synchronization signal comprises a complex pulse, wherein the host is configured to determine a time interval between two consecutive pulses in the complex pulse based on the number of pulse cycles in one of the pulse blocks of the first complex pulse block and a time interval of one of the pulse cycles in one of the pulse blocks of the first complex pulse block.

20. The system of claim 17, wherein the digital pulse signal is aperiodic and the synchronization signal is periodic.

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