Method for manufacturing wiring substrate, method for manufacturing semiconductor device and resin sheet

Abstract

The present invention provides a method for manufacturing a wiring substrate (20), comprising: a step of preparing a structure (1a) on which a resin sheet (3) is mounted on a support (1) having a copper layer (2) on its surface, the resin sheet having glass fiber cloth disposed in an organic resin; a step of forming a recess (7) in a first resin layer region (4) on the surface side of the resin sheet (3) where there is no glass fiber cloth by means of an excimer laser; a step of forming an opening (8) that extends from the surface of the resin sheet (3) to the copper layer (2) on the support (1); and a step of forming a wiring layer (13) by forming copper layers (10) to (12) in the recess (7) and the opening (8).

Description

Technical Field

[0001] This invention relates to a method for manufacturing a wiring substrate, a method for manufacturing a semiconductor device, and a resin wafer. More specifically, it relates to a method for efficiently and cost-effectively manufacturing wiring substrates and semiconductor devices with high requirements for miniaturization or high density. Prior Technology

[0002] With the aim of increasing the density and performance of semiconductor packaging, a mounting method that mixes chips with different performance on a single package has been proposed, and high-density interconnect technology between chips with excellent cost performance has become important (for example, see Patent Document 1).

[0003] Package-on-package (BOP) technology, which connects different packages by stacking them on a package using flip chip mounting, is widely used in smartphones and tablets (see, for example, Non-Patent Literature 1 and Non-Patent Literature 2). As a form for higher-density mounting, there are proposed packaging technologies using organic substrates with high-density wiring (organic interposers), fan-out packaging technologies with through-mold vias (TMV) (FO-WLP), packaging technologies using silicon or glass interposers, packaging technologies using through-silicon vias (TSV), and packaging technologies that use embedded chips for inter-chip transfer.

[0004] In particular, in organic interposers or FO-WLP, when semiconductor wafers are mounted side by side, fine wiring layers are required to enable high-density conduction (e.g., see Patent Document 2).

[0005] [Patent Document 1] Japanese Patent Publication No. 2012-529770 [Patent Document 2] U.S. Patent Application Publication No. 2001 / 0221071

[0006] [Non-patent document 1] Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008 [Non-patent document 2] Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology, ECTC, 2012

[0007] The formation of the aforementioned fine wiring layer requires the following steps: sputtering to form a seed layer, forming a resist, electroplating, removing the resist, and removing the seed layer. This complicates the manufacturing process. Therefore, a further simplified method for forming the fine wiring layer is desired. Summary of the Invention

[0008] Therefore, the object of the present invention is to provide a simplified method for forming a fine wiring layer.

[0009] As one aspect of the present invention, a method for manufacturing a wiring substrate is disclosed. The method includes: a step of preparing a structure in which a resin sheet is mounted on a support having a metal layer on its surface or on a wiring layer disposed within the support, the resin sheet having glass fiber cloth disposed in an organic resin; a step of forming a recess in a first resin layer region on the surface side of the resin sheet where the glass fiber cloth is not present by an excimer laser; a step of forming an opening extending from the surface of the resin sheet to the metal layer on the support; and a step of forming a wiring layer in the recess and the opening.

[0010] In this method for manufacturing the wiring substrate, a resin sheet in which glass fiber cloth is disposed in an organic resin is used. Recesses are formed in the first resin layer region of the resin sheet where the glass fiber cloth is not present, using an excimer laser. A wiring layer is formed in these recesses. This allows for micro-processing of the recesses based on an excimer laser, making it easy to form a fine wiring layer. In this manufacturing method, the process of forming the recesses and the process of forming the openings can be performed either one first or simultaneously. Furthermore, in this manufacturing method, plating or other methods can be used to form the wiring layer in the recesses and openings.

[0011] As another aspect of the present invention, there is a method for manufacturing another wiring substrate. The method for manufacturing this wiring substrate includes: a step of preparing a structure in which a resin sheet is mounted on a support having a metal layer on its surface or on a wiring layer disposed within the support; the resin sheet having sequentially formed a first resin layer region on its outer side and a high-elasticity layer region on its inner side having an elastic modulus higher than that of the first resin layer region; a step of forming a recess on the surface side of the resin sheet and in the first resin layer region by laser or imprinting; a step of forming an opening that extends from the surface of the resin sheet to the metal layer on the support; and a step of forming a wiring layer in the recess and the opening.

[0012] In this method for manufacturing a wiring substrate, a resin sheet having a first resin layer region and a high-elasticity layer region located on the outer side is used. Recesses are formed in the first resin layer region of the resin sheet by laser or imprinting, and a wiring layer is formed in these recesses. This allows for micro-processing of the recesses based on laser or imprinting, and facilitates the formation of a fine wiring layer. In this manufacturing method, the process of forming the recesses and the process of forming the openings can be performed either one first or simultaneously. Furthermore, in this manufacturing method, plating or other methods can be used to form the wiring layer in the recesses and openings. Also, in this manufacturing method, the high-elasticity layer region can be formed by distributing at least one of inorganic fibers and organic fibers in an organic resin material. The inorganic fibers can be at least one of glass fibers, ceramic fibers, and carbon fibers, and the organic fibers can be at least one of polyaramid fibers and polyethylene fibers.

[0013] In the above-described method for manufacturing any wiring substrate, the thickness of the first resin layer region on the surface side of the resin sheet can be 20 μm or less. In this case, by making the region forming the fine wiring layer thin, a low-profile wiring substrate can be achieved. In this case, the thickness of the first resin layer region can be 5 μm or more. This allows for the formation of a recess of appropriate depth, thereby enabling the formation of a fine wiring layer with excellent conductivity.

[0014] In the above-described method for manufacturing any wiring substrate, the linewidth of the recess formed in the first resin layer region can be 0.5 μm or more and 5 μm or less. In this case, a wiring layer with excellent conductivity can be formed.

[0015] In the above-described method for manufacturing any wiring board, the resin sheet has a second resin layer region on the opposite side of the first resin layer region. In the process of preparing the structure, the structure can be prepared by attaching the resin sheet to the support or the embedded wiring layer using the second resin layer region. In this case, the structure can be prepared using simple methods such as lamination, simplifying the manufacturing process. Furthermore, in the process of preparing the structure, a structure with a resin sheet pre-mounted on the support or the embedded wiring layer can be prepared and used in subsequent processes.

[0016] In the above-described method for manufacturing any wiring substrate, when a recess is formed in the first resin layer region by an excimer laser, the pulse width of the excimer laser can be 10 nanoseconds or more and 50 nanoseconds or less, and the output of the excimer laser can be 10 mJ / pulse or more and 1000 mJ / pulse or less. In this case, finer recesses can be easily formed.

[0017] In the manufacturing method of any of the above-mentioned wiring substrates, in the step of forming the wiring layer, a metal plating layer is formed in the recess and the opening to form the wiring layer. The resin sheet may contain a component formed by heteroaromatic rings capable of coordination bonding with a metal material, and the metal material constitutes a seed layer for forming the metal plating layer. At this time, it is easy to form a finer wiring layer. In addition, for example, the component formed by heteroaromatic rings capable of coordination bonding with the metal material constituting the seed layer may be at least one compound selected from the group consisting of cis-butenediamine compounds, bis-cis-butenediamine compounds, triazole compounds, benzotriazole compounds, and benzo[a]azole compounds.

[0018] In the manufacturing method of any of the above-mentioned wiring substrates, the resin sheet or the coating layer of the resin sheet may contain a laser light-absorbing coloring component, which is formed from at least one of inorganic dyes, inorganic pigments, organic dyes, and organic pigments. This allows for more reliable processing of the laser-based recesses. Alternatively, for example, the laser light-absorbing coloring component may be at least one of graphite, graphene, carbon nanotubes, carbon fibers, carbon black, phthalocyanine, anthocyanin, alkaline earth metals, and metal complexes.

[0019] In the above-described method for manufacturing any wiring substrate, during the process of forming the wiring layer, a metal plating layer is formed by providing a seed layer based on electroless plating in the recess and the opening to form the wiring layer. The resin sheet may contain a catalyst for forming the electroless plating. This facilitates the formation of a finer wiring layer. Furthermore, the catalyst for forming the electroless plating may be at least one of palladium particles, palladium complexes, copper particles, and copper complexes.

[0020] In any of the above-described methods for manufacturing a wiring substrate, the step of forming the wiring layer may include: a step of filling the recesses and openings with conductive material and depositing conductive material on the surface of a first resin layer region excluding the recesses and openings to form a conductive layer; and a step of planarizing the conductive layer. In the planarization step, at least a first portion of the conductive layer deposited on the surface of the first resin layer region is ground, and the wiring layer can be formed from a second portion of the conductive layer, which is formed from the conductive material filled in the recesses and openings. In this case, a finer wiring layer can be formed more effectively.

[0021] The manufacturing method of any wiring board described above can further include a step of forming a concealed wiring portion having at least one concealed wiring layer on a support. In the structure preparation step, the structure can be prepared by attaching a resin sheet to the concealed wiring portion for mounting. In this case, for example, the concealed wiring layer can be composed of a build-up material, and the surface micro-wiring layer can be composed of an organic resin material such as a prepreg. This allows for the use of different materials to create a wiring board with an optimal layer structure. Furthermore, it also increases the design freedom of the wiring board.

[0022] The manufacturing method of the aforementioned arbitrary wiring substrate further includes: a step of mounting another resin sheet on a resin sheet on which a wiring layer is formed; a step of forming another recess in the first resin layer region of the other resin sheet by laser; a step of forming another opening, wherein the other opening extends from the surface of the other resin sheet to a metal plating layer or wiring layer at the opening; and a step of forming another metal plating layer in the other recess and the other opening to form another wiring layer. The steps of mounting the other resin sheet, forming the other recess, forming the other opening, and forming the other wiring layer can be repeated at least once. In this case, the manufacturing method of a wiring substrate having two or more fine wiring layers can be simplified.

[0023] In the above-described method for manufacturing any wiring substrate, the process of forming the wiring layer may include: a process of desmearing at least the opening and the recess; a process of forming a seed layer at least in the opening and the recess by electroless plating; a process of electroplating on the seed layer to form a metal plating layer; and a process of removing the seed layer and the metal plating layer from the surface of the first resin layer region to planarize the surface of the first resin layer region, the seed layer, and the metal plating layer. In this case, the conductive portion of the fine wiring layer can be formed more reliably.

[0024] As another aspect of the present invention, a method for manufacturing a semiconductor device is provided. This method includes: a step of preparing a wiring substrate manufactured by any of the above-described wiring substrate manufacturing methods; and a step of mounting semiconductor elements on a wiring layer or another wiring layer and electrically connecting the semiconductor elements to the wiring layer or another wiring layer. In this way, a semiconductor device having a wiring substrate with fine wiring layers can be manufactured using a simplified method. Furthermore, because it is manufactured using a simplified method, it is possible to increase manufacturing yield or reduce product cost. Moreover, not limited to this, when mounting a plurality of semiconductor elements (chips) (especially in high-density mounting), the semiconductor elements can be connected to each other using fine wiring layers with excellent transmission properties, providing a miniaturized semiconductor device with superior performance.

[0025] As another aspect of the present invention, a resin sheet is provided. This resin sheet is used in the manufacturing method of any of the aforementioned wiring substrates. The resin sheet includes: a first resin layer region located on the outer side; and a high-elasticity layer region located on the inner side with an elastic modulus higher than that of the first resin layer region, or a high-elasticity layer region having glass fiber cloth located on the inner side. By pre-setting such a resin sheet, the manufacturing methods of the aforementioned wiring substrates and semiconductor devices are further simplified, enabling improvements in the yield of the manufactured wiring substrates and semiconductor devices, or reductions in product cost.

[0026] The aforementioned resin sheet may further include a second resin layer region located on the opposite side of the first resin layer region, separated from the highly elastic layer region, and the second resin layer region may be adhesive. In this case, it is easier to form a structure containing the resin sheet, and the manufacturing methods of the aforementioned wiring substrate and semiconductor devices can be further simplified. [Invention Effects]

[0027] According to the present invention, a simplified manufacturing method for a wiring substrate having a fine wiring layer and a semiconductor device can be provided. Simple Explanation of the Diagram

[0028] Figures 1(a) to 1(d) are a portion of a method for manufacturing a wiring board according to one embodiment of the present invention. Figures 2(a) to 2(c) are part of a method for manufacturing a wiring board according to one embodiment of the present invention, and are diagrams of processes that continue after the process in Figure 1. Figure 3 is an example of a semiconductor device on which semiconductor elements are mounted on a wiring board manufactured by the manufacturing methods shown in Figures 1 and 2. Figure 4(a) shows a wiring substrate of a modified example, and Figure 4(b) shows a semiconductor device of a modified example. Implementation

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, identical or corresponding parts will be labeled with the same symbols, and repeated descriptions will be omitted. Furthermore, unless otherwise specified, positional relationships such as top, bottom, left, and right will follow the positional relationships shown in the accompanying drawings. Moreover, the scale of the accompanying drawings is not limited to the scale shown.

[0030] In the descriptions and requests in this specification, the terms "left," "right," "front," "back," "upper," "lower," "above," and "below" are used only for illustrative purposes and do not necessarily refer to being in that relative position at all times. Furthermore, when viewed as a plan view, the term "layer" includes not only structures forming a shape across the entire surface but also structures forming a shape in a specific area. Also, in this specification, the term "process" includes not only independent processes but also processes that cannot be clearly distinguished from others, as long as the intended function of the process is achieved. Furthermore, the numerical range indicated by "~" refers to the range encompassed by taking the values ​​before and after "~" as the minimum and maximum values, respectively.

[0031] A method for manufacturing a wiring substrate and a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. The method for manufacturing a wiring substrate and a method for manufacturing a semiconductor device according to this embodiment are preferably applicable to configurations requiring miniaturization and multi-pin configurations, but are not limited thereto. Furthermore, the method for manufacturing a semiconductor device according to this embodiment is preferably applicable to packaging configurations requiring an interposer layer for mounting different types of chips, but is not limited thereto. Additionally, for ease of explanation, the following description assumes only one semiconductor element is mounted, but the same applies to configurations mounting two or more (or two or more types) semiconductor elements.

[0032] <Structure Preparation Process> Figures 1 and 2 illustrate a method for manufacturing the wiring board of this embodiment. As shown in Figure 1(a), a structure 1a is first prepared on a support 1 on which a resin sheet 3 is mounted, with a copper layer 2 (metal layer) disposed on its surface. The resin sheet 3 is, for example, a sheet of glass fiber cloth impregnated with organic resin, having a first resin layer region 4 on the surface side without a glass sheet, a highly elastic layer region 5 located inside the first resin layer region 4, and a second resin layer region 6 located on the opposite side of the first resin layer region 4, separated from the highly elastic layer region 5 (glass fiber cloth). For example, the resin sheet 3 can be any structure containing a highly elastic material such as glass fiber cloth in organic resin, or it can be a structure with resin sheets on both sides of the glass fiber cloth. For example, the second resin layer region 6 has adhesive properties, and the resin sheet 3 is attached to the copper layer 2 of the support 1 via the second resin layer region 6 for mounting. In the preparation process of structure 1a, resin sheet 3 can be attached to copper layer 2 on support 1, or structure 1a can be prepared in advance by mounting resin sheet 3 on support 1 via copper layer 2 and then using structure 1a.

[0033] The support 1 is not particularly limited, and can be, for example, a silicon board, a glass board, a SUS board, a fiberglass cloth containing a substrate, or a semiconductor device containing a sealing resin substrate, etc., which are substrates with high rigidity. The thickness of the support 1 can be 0.2 mm or more and 2.0 mm or less. By making the support 1 0.2 mm or more, operability can be improved, and by making the support 1 2.0 mm or less, the back-mounted wiring substrate can be reduced, and material costs can be reduced, thereby reducing costs. Furthermore, the support 1 can have any shape, such as wafer or plate, and the size of the support 1 is not particularly limited. The support 1 can be a wafer with a diameter of 200 mm, 300 mm, or 450 mm, or a rectangular plate with one side of 300 mm or more and 700 mm or less.

[0034] For example, resin sheet 3 is a semi-cured film-like component such as a prepreg. To ensure electrical insulation, the organic resin material contained in resin sheet 3 may include at least one of a thermosetting material and a thermoplastic material. The thermosetting material used here is, for example, epoxy resin, and the thermoplastic resin is, for example, acrylic resin, but is not limited thereto. From the viewpoint of film thickness flatness and cost, the organic resin material contained in resin sheet 3 may be a film-like composite. Furthermore, from the viewpoint of being able to form fine recesses, the organic resin material may include a thermosetting material. The size of the filler (filler material) contained in the thermosetting material may be an average particle size of 500 nm or less. The thermosetting material may not contain filler. The first resin layer region 4 and the second resin layer region 6 of resin sheet 3 are formed by such organic resin material, becoming regions without glass fiber cloth. Since the first resin layer region 4 forms a fine groove structure in the recess formation process described later, its film thickness may be 20 μm or less, or it may be 10 μm or less. To ensure conductivity in the micro-wiring structure, the film thickness of the first resin layer region 4 can be 5 μm or more.

[0035] The glass fiber cloth contained in the resin sheet 3 is composed of woven or non-woven fabric containing glass fibers. For example, the glass fibers can be E glass, S glass, or quartz glass. For example, the thickness of the glass fiber cloth can be 0.01 μm or more and 0.2 μm or less. Such glass fiber cloth is impregnated with the aforementioned organic resin material to form the highly elastic layer region 5. That is, the highly elastic layer region 5 is composed of glass fiber cloth and an organic resin material impregnated or infiltrated into the glass fiber cloth. Because the highly elastic layer region 5 contains rigid materials such as glass, it has an elastic modulus that is higher than that of the first resin layer region 4 and the second resin layer region 6. Alternatively, at least one of other inorganic fibers and organic fibers can be impregnated in the organic resin material instead of glass fibers to form the highly elastic layer region 5. Inorganic fibers are, for example, ceramic fibers or carbon fibers, and organic fibers are, for example, polyaramid fibers or polyethylene fibers.

[0036] To improve adhesion to the seed layer formed in subsequent processes, the organic resin material contained in resin sheet 3 may include, for example, components formed from heteroaromatic rings capable of coordination bonding with metals, such as maleic anhydride compounds, bismaleimide compounds, triazole compounds, benzotriazole compounds, and benzotriazole compounds. The metals mentioned here refer to the metallic materials constituting the seed layer. This component may be included in the filler surface treatment agent. Furthermore, when forming the seed layer described later by electroless plating, palladium particles, palladium complexes, copper particles, and copper complexes, which act as catalysts in electroless plating, may be included in resin sheet 3.

[0037] To improve laser light absorption, resin sheet 3 may contain, for example, a laser light-absorbing coloring component formed from inorganic dyes or pigments such as graphite, graphene, carbon nanotubes, carbon fibers, and carbon black, or organic dyes or pigments such as phthalocyanine, anthocyanine, alkaline earth metal salts, and metal complexes. This component may be included in the filler surface treatment agent.

[0038] The resin sheet 3 has the above-described structure, for example, its thickness can be 10 μm or more and 100 μm or less. By having a thickness of 10 μm or more, operability can be improved. Furthermore, by having a thickness of 100 μm or less, the manufactured wiring substrate or semiconductor device can be configured as a thin package.

[0039] For example, the resin sheet 3 can be formed by impregnating glass fiber cloth in an organic resin (varnish) to create a structure having a first resin layer region 4, a high-elasticity layer region 5, and a second resin layer region 6. It can also be formed by laminating or pressing glass fiber cloth between the resin layer corresponding to the first resin layer region 4 and the resin layer corresponding to the second resin layer region 6. Methods for forming the laminated body of the resin sheet 3 include vacuum lamination, roll lamination, vacuum roll lamination, atmospheric pressure pressing, or vacuum pressing. Furthermore, when vacuum pressing is used, oxidation of the thermosetting material contained in the resin sheet 3 can be easily suppressed, and film thickness flatness can be further improved. Also, the forming temperature of the resin sheet 3 can be the temperature at which the thermosetting material contained in the resin sheet 3 is thermoset, for example, between 100°C and 250°C. By setting the forming temperature to 100°C or higher, the viscosity of the organic resin material in the resin sheet 3 can be reduced, thereby improving workability. By setting the forming temperature to 250°C or lower, warping of the resin sheet 3 can be suppressed.

[0040] For example, for this type of resin sheet 3, it is possible to use "MCL-E-705G, thickness 0.4mm or 0.6mm, 255mm square (manufactured by Hitachi Chemical Co., Ltd.)", or "R-1766, thickness 0.4mm or 0.6mm, 255mm square", "R-5715ES, thickness 0.4mm or 0.6mm, 255mm square", "R-5670Kj, thickness 0.4mm or 0.6mm, 255mm square (all of the above, manufactured by Panasonic Corporation)", or "GHPL830NS, thickness 0.4mm or 0.6mm, 255mm square", "830NS, thickness 0.4mm or 0.6mm, 255mm square", "830NSF, thickness 0.4mm or 0.6mm, 255mm square (all of the above, manufactured by MITSUBISHI GAS CHEMICAL)". COMPANY, INC.)".

[0041] A coating layer can also be provided on the surface of the resin sheet 3 (on the side forming the recess). For example, the coating layer can be an organic resin film including polyethylene terephthalate (PET) resin, polyethylene naphthalate (PEN) resin, polyetheretherketone (PEEK) resin, polyimide (PI) resin, or a metal foil such as Cu foil, Ni foil, or SUS foil. In order to improve the absorption of laser light, the organic resin film constituting the coating layer can contain a laser light-absorbing coloring component formed by inorganic dyes or inorganic pigments such as graphite, graphene, carbon nanotubes, carbon fibers, and carbon black, or organic dyes or organic pigments such as phthalocyanine, anthocyanine, alkaline earth metal salts, and metal complexes. Furthermore, the surface of the aforementioned metal foil can be blackened.

[0042] <Process for forming the concave area> Next, as shown in Figure 1(b), after the preparation process of structure 1a is completed, a plurality of recesses 7 are formed by excimer laser in the first resin layer region 4 on the surface side of the resin sheet 3 where there is no glass fiber cloth. A recess 7 refers to a portion that is recessed relative to the surface of the first resin layer region 4 along the thickness direction of the first resin layer region 4, including the inner wall (side wall and bottom wall, etc.) of the recessed portion. The recess 7 is formed as a groove extending in the left-right direction as shown in the figure and in the vertical direction as shown in the figure, having a shape corresponding to the fine wiring in the planar direction. When forming a recess in the first resin layer region 4, which is formed of a thermosetting or thermoplastic material, from a micro-refinement point of view, it can be processed using an excimer laser, but it can also be processed using a carbon dioxide laser or a UV-YAG laser, or by imprinting.

[0043] In the process of forming the recess 7, the recess 7 can be formed with an opening width of 0.5 μm or more and 20 μm or less. From the viewpoint of miniaturization, the recess 7 can also be formed with an opening width of 0.5 μm or more and 5 μm or less. This allows for the provision of a high-density semiconductor device formed with a fine wiring layer. As described above, an excimer laser can be used when forming such a recess with a fine opening width. The dielectric of the excimer laser used is argon / fluorine (ArF) or krypton / fluorine (KrF). From a versatility point of view, an excimer laser with KrF as the dielectric can be used. Furthermore, as processing conditions based on the excimer laser, the pulse energy can be 20 mJ or more and 100 mJ or less. The pulse repetition frequency can be 1 Hz or more and 4000 Hz or less. The pulse width can be 10 nanoseconds or more and 50 nanoseconds or less. The laser irradiation dose can be greater than 0 and 1000 mJ / cm² or less. The output of an excimer laser can be above 10 mJ / pulse and below 1000 mJ / pulse.

[0044] In the process of forming the recess 7, after forming the recess 7, the resin sheet 3 containing the first resin layer region 4 can be further heated and cured. The heating temperature can be 100°C or higher and 250°C or lower, and the heating time can be 30 minutes or higher and 3 hours or lower. Furthermore, the recess 7 is configured not to reach the highly elastic layer region 5.

[0045] <Opening Formation Process> Next, as shown in Figure 1(c), if the formation of the recess 7 is completed, an opening 8 is formed from the surface of the resin sheet 3 to the copper layer 2 of the support 1. In the process of forming the opening, the opening 8 is formed by passing through the resin sheet 3 together a highly elastic layer region 5 consisting of glass fiber cloth, a first resin layer region 4 consisting of organic resin material, and a second resin layer region 6. As a method for forming the opening 8, for example, carbon dioxide laser processing or drilling can be used, but from the viewpoint of miniaturization, carbon dioxide laser processing can be used.

[0046] In the process of forming the opening, for example, an opening 8 with a diameter of 30 μm or more and 200 μm or less is formed. With an opening 8 of this size, a high-density semiconductor device can be provided, and a semiconductor device with a fine wiring layer can be manufactured with good yield and low cost. The process of forming the opening can be performed before or after the process of forming the recess, or simultaneously; the order is not particularly limited.

[0047] <Removal of Adhesive Residue Process> Next, after the formation of the recess 7 and the opening 8 is completed, a descaling process is performed to remove the glue residue formed by the laser opening. Commercially available pretreatment solutions and descaling solutions can be used for the descaling process. For example, a swelling solution (manufactured by Atotech Japan KK, trade name: Swelling Dip Securiganth) can be used as the pretreatment solution. For example, a roughening solution (manufactured by Atotech Japan KK, trade name: Concentrate Compact CP) can be used as the descaling solution. For example, a neutralizing solution (manufactured by Atotech Japan KK, trade name: Reduction Securiganth) can be used as the neutralizing solution after descaling.

[0048] As for the swelling conditions in the degumming process, the temperature of the swelling solution is 50°C or higher and 80°C or lower, and the immersion time is 1 minute or higher and 30 minutes or lower. After the swelling treatment, the recesses 7 and openings 8 can be washed with pure water or tap water. Furthermore, after the swelling treatment, a roughening process is performed using the degumming solution. This can be performed under the following degumming conditions: the temperature of the degumming solution is 30°C or higher and 80°C or lower, and the immersion time is 1 minute or higher and 30 minutes or lower. After the degumming treatment, it can be washed with pure water or tap water. After roughening with the degumming solution, a drag-out process is performed using pure water or tap water. The drag-out temperature is 25°C or higher and 50°C or lower, and the immersion time is 1 minute or higher and 5 minutes or lower. Next, a neutralization process is performed after dragging out. The neutralization temperature is 25°C or higher and 50°C or lower, and the immersion time is 1 minute or higher and 10 minutes or lower. After the neutralization process, it can be washed with pure water or tap water. This concludes the process of removing adhesive residue.

[0049] <Seed Layer Formation Process> As shown in Figure 1(d), after the descaling process is completed, the following steps are performed: a seed layer 9 is formed on the surface of the first resin layer region 4, the sidewalls and bottom wall of the recess 7, the sidewall of the opening 8, and the surface of the copper layer 2 exposed in the opening 8. In the seed layer formation process, the seed layer 9 can be formed using a copper paste method, a sputtering method, or an electroless plating method. As a suitable method for board forming, an electroless plating method can be used.

[0050] When forming the seed layer 9, firstly, in order to adsorb palladium, which serves as a catalyst for electroless copper plating, onto the surface of the first resin layer region 4, the sidewalls and bottom wall of the recess 7, the sidewalls of the opening 8, and the surface of the copper layer 2 exposed in the opening 8 (hereinafter also referred to as "the surface of the first resin layer region 4, etc."), the surface of the first resin layer region 4 is cleaned with a pretreatment solution. For example, the pretreatment solution is a commercially available alkaline pretreatment solution containing sodium hydroxide or potassium hydroxide. The pretreatment can be carried out under conditions where the concentration of sodium hydroxide or potassium hydroxide is between 1% and 30%, the immersion time in the pretreatment solution is between 1 minute and 60 minutes, and the immersion temperature in the pretreatment solution is between 25°C and 80°C. After the pretreatment, it can be rinsed with tap water, pure water, ultrapure water, or an organic solvent to remove excess pretreatment solution.

[0051] After removing the pretreatment solution, the surface of the first resin layer region 4 is immersed and cleaned with an acidic aqueous solution to remove alkali ions. The immersion cleaning can be performed using a sulfuric acid aqueous solution, or under conditions where the concentration is between 1% and 20% and the immersion time is between 1 minute and 60 minutes. Tap water, pure water, ultrapure water, or organic solvents can be used to remove the acidic aqueous solution. Then, palladium is adhered to the first resin layer region 4 after immersion cleaning with the acidic aqueous solution. When adsorbing palladium, commercially available palladium-tin colloidal solution, aqueous solution containing palladium ions, or palladium ion suspension can be used, but an aqueous solution containing palladium ions that are effectively adsorbed into the modified layer can also be used. Immersion in an aqueous solution containing palladium ions can be performed under conditions where the temperature of the aqueous solution containing palladium ions is between 25°C and 80°C and the immersion time for adsorption is between 1 minute and 60 minutes. After palladium ions are adsorbed, they can be washed with tap water, pure water, ultrapure water or organic solvents to remove excess palladium ions.

[0052] Next, after palladium ions are adsorbed, activation is performed to allow the palladium ions to act as a catalyst. Commercially available activators (activation solutions) can be used to activate the palladium ions. The temperature of the activator used for immersion activation is between 25°C and 80°C, and the immersion time is between 1 minute and 60 minutes. After activation, the palladium ions can be rinsed with tap water, pure water, ultrapure water, or an organic solvent to remove excess activator. Then, using palladium as a catalyst, a seed layer 9 is formed by electroless plating. For example, the seed layer 9 is an electroless plating layer selected from the group consisting of a copper layer, a nickel layer, a copper-nickel alloy layer, a nickel-phosphorus alloy layer, and a copper-nickel-phosphorus alloy layer. From a cost perspective, the seed layer 9 can be made of copper.

[0053] When forming the copper layer as the seed layer 9, a commercially available electroless plating solution can be used, such as an electroless copper plating solution (manufactured by Atotech Japan KK, trade name: Copper Solution Print Gantt MSK). Electroless copper plating is formed in the electroless copper plating solution at a temperature between 20°C and 40°C. The thickness of the seed layer 9 can be 0.1 nm or more and 500 nm or less, 0.1 nm or more and 400 nm or less, or 0.1 nm or more and 300 nm or less. By setting the thickness of the seed layer 9 to 0.1 nm or more, it is easy to form wiring with a uniform thickness in the subsequent electroplating. On the other hand, by setting the thickness of the seed layer 9 to 500 nm or less, over-etching of the wiring can be prevented in the etching process of the seed layer 9, and fine wiring can be formed with good yield.

[0054] After electroless plating, the surface can be cleaned with water or an organic solvent to remove excess plating solution. To improve the adhesion between the seed layer 9 and the surface of the first resin layer region 4 after electroless plating, thermosetting (annealing: a heat-based aging curing process) can be performed. The thermosetting temperature can be 80°C or higher and 200°C or lower. To promote reactivity, the thermosetting temperature can be 120°C or higher and 200°C or lower, or 120°C or higher and 180°C or lower. The thermosetting time can be 5 minutes or more and 60 minutes or less, 10 minutes or more and 60 minutes or more and 20 minutes or less.

[0055] <Copper Layer Formation Process> As shown in Figure 2(a), after the seed layer formation process is completed, the following process is performed: copper layers 10, 11, and 12 (metal plating, conductive layers) are formed on the seed layer 9 by electroplating copper (a conductive material). More specifically, a copper layer formed without electroplating copper is used as the seed layer 9, and copper layers 10 to 12 are formed on it by electroplating copper. In this embodiment, electroplating copper is used as the method for forming copper layers 10 to 12, but electroless plating can also be used, for example.

[0056] In the copper layer formation process, a copper layer 10 (second part) is filled into the recess 7 on the surface of the first resin layer region 4, and a copper layer 11 (second part) is filled into the opening 8 that extends from the surface of the first resin layer region 4 to the copper layer 2. A copper layer 12 (first part) is formed on the surface of the first resin layer region 4, excluding the recess 7 and the opening 8. By filling the recess 7 with copper layer 10 and the opening 8 with copper layer 11, in subsequent processes, the copper layers 12, the seed layer, and the palladium adsorption layer can be planarized on the surface of the first resin layer region 4 and the recess 7 and the opening 8, respectively, simply by removing the copper layer 12, the seed layer, and the palladium adsorption layer from the surface of the first resin layer region 4, excluding the recess 7 and the opening 8, without removing the surface of the first resin layer region 4. Alternatively, after removing the copper layer, seed layer, and palladium adsorption layer, the surface of the first resin layer region 4 can be further removed to planarize the copper layers 10 and 11 formed on the surface of the first resin layer region 4, the recess 7, and the opening 8, respectively.

[0057] When copper layer 10 is filled into recess 7 or copper layer 11 is filled into opening 8 by electroplating copper, a so-called filled plating can be achieved by using copper plating in recess 7 and opening 8 such that the amount of copper deposited (plating thickness) is greater than the surface of the first resin layer region 4. Copper layers 10 and 11 may not be filled into recess 7 or opening 8, but may be formed along the inner wall (bottom wall and side wall) of recess 7 or opening 8. In this case, not only are copper layer 12, seed layer, and palladium adsorption layer removed from the surface of the first resin layer region 4 other than recess 7 and opening 8, but the surface of the first resin layer region 4 is also further removed, thereby exposing copper layer 10 in recess 7 (bottom wall of recess 7) and copper layer 11 in opening 8, and thus planarizing the surface of the first resin layer region 4 and the copper layers 10-12 formed in recess 7 and opening 8.

[0058] <Construction process of wiring layer> Next, as shown in Figure 2(b), if the formation of the copper layer is completed, the following process is performed: by removing the copper layer 12, the seed layer, and the palladium catalyst from the surface of the first resin layer region 4, excluding the recesses 7 and the openings 8, a wiring layer 13 is formed from the copper layer 10 formed in the recesses 7 and the copper layer 11 formed in the openings 8. That is, by removing the copper layer 12, the seed layer, and the palladium adsorption layer from the surface of the first resin layer region 4, copper layers 10 and 11 (specifically, including the seed layer and palladium adsorption layer corresponding to the copper layers 10 and 11) remain only in the recesses 7 and the openings 8 on the surface of the first resin layer region 4, including the recesses 7, and the wiring layer 13 is formed from the copper layers 10 and 11 in the recesses 7 and the openings 8. The main part of the wiring layer 13 is formed from the copper layers 10 formed in the plurality of recesses 7. The wiring layer 13 is connected to the connection terminals of the semiconductor element 22 described later.

[0059] When removing the copper layer 12, seed layer, and palladium adsorption layer from the surface of the first resin layer region 4, excluding the recess 7, the copper layer 10 formed on the surface of the first resin layer region 4 and in the recess 7 can be planarized. Furthermore, when removing the copper layer 12, seed layer, and palladium adsorption layer from the upper part of the first resin layer region 4, a portion in the thickness direction can be removed from the upper (surface) side of the first resin layer region 4. Methods for removing the copper layer 12, seed layer, palladium adsorption layer, and the first resin layer region 4 from the upper part of the first resin layer region 4 can utilize backgrinding, fly-cutting, or chemical mechanical polishing (CMP). Multiple removal methods can also be used simultaneously. In fly-cutting, for example, a diamond-based grinding apparatus can be used. As a specific example, an automatic surface planer (manufactured by DISCO Corporation, trade name "DAS8930") for 300mm wafers can be used. The removal of the metal layer and palladium adsorption layer based on the flying cut method is also called planarization treatment because the entire surface is uniformly ground from the upper side (surface side) of the first resin layer region 4, and the ground surface becomes flat.

[0060] When performing polishing using chemical mechanical polishing (CMP), a specific example is a CMP polishing unit (manufactured by Applied Materials, Inc., trade name "F-REX300X") suitable for 300mm wafers. During CMP polishing, polishing slurries containing abrasive particles such as silicon dioxide, aluminum oxide, and cerium dioxide can be used. Furthermore, multiple polishing slurries can be used simultaneously or sequentially. After polishing, polishing debris and excess abrasive particles can be removed using cleaning solutions such as pure water or solvents.

[0061] When proceeding to the next process, i.e. electroless plating, in order to facilitate palladium adsorption onto the seed layer and copper layer 10, the surfaces of the exposed seed layer and copper layers 10 and 11 can be roughened chemically or physically after removing the copper layer 12, seed layer, palladium adsorption layer and the first resin layer region 4 above the first resin layer region 4.

[0062] <Coating Process> Next, as shown in Figure 2(c), after completing the wiring layer formation process, capping layers 14 and 15 can be formed on the exposed seed layer, copper layers 10 and 11 (wiring layer 13), and palladium adsorption layer using electroless plating. The metal used for capping layers 14 and 15 can be any metal including Cu, Ni, Cr, and W. Through the above, a wiring substrate 20 with a fine wiring layer 13 is fabricated.

[0063] <Methods for Manufacturing Semiconductor Devices> Next, as shown in FIG3, a semiconductor element 22 is mounted on the wiring layer 13 on the wiring substrate 20, and the connection terminals of the semiconductor element 22 are electrically connected to the wiring layer 13. In this way, a semiconductor device 25 connected by a fine wiring layer 13 is fabricated.

[0064] In the above-described method for manufacturing the wiring substrate and semiconductor device of this embodiment, a resin sheet 3 in which glass fiber cloth is disposed in an organic resin is used. In the first resin layer region 4 of the resin sheet 3 where the glass fiber cloth is not present, a recess 7 is formed by excimer laser, and a wiring layer 13 is formed in the recess 7. At this time, laser-based micro-processing of the recess 7 is possible, and a fine wiring layer can be easily formed.

[0065] In the manufacturing method of the wiring substrate and semiconductor device of this embodiment, the thickness of the first resin layer region 4 on the surface side of the resin sheet 3 can be 20 μm or less. In this case, by making the layer region forming the fine wiring layer 13 thin, a low backlight profile can be achieved in the manufactured wiring substrate 20. Furthermore, in this manufacturing method, the thickness of the first resin layer region 4 can be 5 μm or more. This allows for the formation of a recess 7 of appropriate depth, thereby enabling the formation of a fine wiring layer 13 with excellent conductivity.

[0066] In the manufacturing method of the wiring substrate and semiconductor device of this embodiment, the linewidth of the recess 7 formed in the first resin layer region 4 can be 0.5 μm or more and 5 μm or less. In this case, a wiring layer 13 with excellent conductivity can be formed.

[0067] In the manufacturing method of the wiring substrate and semiconductor device of this embodiment, the resin sheet 3 has a second resin layer region 6 on the opposite side of the first resin layer region 4. In the process of preparing the structure, the resin sheet 3 is attached to the support 1 by means of the second resin layer region 6 to prepare the structure 1a. At this time, the preparation of the structure 1a can be carried out by simple methods such as lamination, which simplifies the manufacturing method.

[0068] In the manufacturing method of the wiring substrate and semiconductor device of this embodiment, the plating process includes: a process of removing adhesive residue from the surfaces of the recess 7, the opening 8, and the first resin layer region; a process of forming a seed layer 9 on the surfaces of the recess 7, the opening 8, and the first resin layer region by electroless plating; a process of forming copper layers 10-12 by electroplating on the seed layer 9; and a process of removing the seed layer 9 and copper layers 10-12 from the surface of the first resin layer region 4 to planarize the surface of the first resin layer region 4, the seed layer 9, and the copper layers 10-12. This allows for more reliable formation of the conductive portions of the fine wiring layer 13.

[0069] Furthermore, in the semiconductor device manufacturing method of this embodiment, by means of the various methods described above, a semiconductor device 25 having a wiring substrate 20 with a fine wiring layer 13 can be manufactured using a simplified method. Moreover, since the manufacturing is carried out using a simplified method, it is also possible to increase manufacturing yield or reduce product cost. Furthermore, not limited to this, when mounting multiple semiconductor elements (chips) (especially in high-density mounting), the semiconductor elements can be connected to each other using a fine wiring layer with excellent transmission properties, providing a miniaturized semiconductor device with superior performance.

[0070] The resin sheet 3 of this embodiment has a first resin layer region 4 located on the outer side and a high elasticity layer region 5 located on the inner side with an elastic modulus higher than that of the first resin layer region 4. By prefabricating such a resin sheet 3, the manufacturing method of the wiring substrate and the manufacturing method of the semiconductor device described above are further simplified, thereby enabling the production yield of the manufactured wiring substrate 20 and semiconductor device 25 to be increased or the cost of the product to be reduced.

[0071] The resin sheet 3 in this embodiment further includes a second resin layer region 6, which is located on the opposite side of the first resin layer region 4, separated by a highly elastic layer region 5. The second resin layer region 6 is adhesive. Therefore, it is easier to form a structure 1a containing the resin sheet 3, and the manufacturing method of the wiring substrate 20 and the semiconductor device 25 can be further simplified.

[0072] The embodiments of the present invention have been described in detail above, but the present invention is not limited to the above embodiments and can be applied to various embodiments. For example, in the above embodiments, as shown in Figures 1 to 3, a semiconductor device 25 is fabricated by providing a single wiring layer 13 and placing a semiconductor element 22 thereon, but the wiring layer 13 can be two or more layers. In this case, after performing the wiring layer 13 formation process shown in Figure 2(b), the following process can be repeated more than once to multiply the wiring layer 13: a process of mounting another resin sheet 3 onto the first resin layer region 4 where the wiring layer 13 is formed by bonding or the like; a process of forming another recess 7 on the first resin layer region 4 of the other resin sheet 3; a process of forming another opening 8 on the other resin sheet 3; and a process of forming another wiring layer 13 on the other recess 7 and the other opening 8. During multiplying, the other opening 8 can be formed as a copper layer 11 or a wiring layer 13 extending from the surface side of the other resin sheet 3 to the inner side of the opening 8. This enables the creation of wiring substrates and semiconductor devices with multilayered wiring layers 13.

[0073] Furthermore, as shown in Figure 4(a), the multilayer wiring substrate 30 can be formed by performing the following steps: forming an embedded wiring portion by providing one or more embedded wiring layers 31 on the support 1, forming a recess 7 by attaching a resin sheet 3 thereon; forming an opening 8; and forming a wiring layer 13. Then, as shown in Figure 4(b), a semiconductor device 35 can be mounted on the multilayer wiring substrate 30. At this time, the embedded wiring layer 31 can be formed using a layer-addition process. In this way, by multiplying the embedded wiring layer 31 using conventional methods, it is also possible to make only the surface layer (i.e., the connection portion with the semiconductor device) of the wiring layer 13 a further miniaturized wiring layer. At this time, for example, the embedded wiring layer 31 is made of a layer-addition material, and a recess is formed on the surface of the fine wiring layer 13 by laser processing of an organic resin material such as a prepreg, so that a wiring substrate with an optimal structure can be made using different materials. Furthermore, the manufacturing method of this type of variation can also increase the design freedom of the wiring board.

[0074] 1: Support body 1a: Structure 2: Copper layer (metal layer) 3: Resin sheet 4: First resin layer region 5: High elasticity layer region 6: Second resin layer region 7: concave part 8: Opening 9: Seed layer 10, 11: Copper layer (Part 2 of metal plating) 12: Copper Layer (Part 1) 13: Wiring layer 14, 15: Plated cap 20: Wiring board 22: Semiconductor components 25: Semiconductor Devices 30: Wiring board 31: Concealed wiring layer 32: Semiconductor components 35: Semiconductor devices

Claims

1. A method for manufacturing a wiring board, comprising: The process of preparing a structure includes: mounting a resin sheet on a support with a metal layer on its surface or on a wiring layer embedded within the support; the resin sheet having glass fiber cloth disposed in an organic resin; forming a recess in a first resin layer region on the surface of the resin sheet where the glass fiber cloth is not present by an excimer laser in a manner that does not reach the portion of the resin sheet where the glass fiber cloth is disposed; forming an opening that extends from the surface of the resin sheet to the metal layer on the support; and forming a wiring layer in the recess and the opening.

2. A method for manufacturing a wiring board, comprising: The process of preparing the structure includes: mounting a resin sheet on a support body with a metal layer on its surface or on a wiring layer embedded within the support body; sequentially forming a first resin layer region on the outer side and a high elasticity layer region on the inner side with an elastic modulus higher than that of the first resin layer region; forming a recess on the surface of the resin sheet and in the first resin layer region by laser or embossing in a manner that does not reach the high elasticity layer region; forming an opening that extends from the surface of the resin sheet to the metal layer on the support body; and forming a wiring layer in the recess and the opening.

3. The method for manufacturing a wiring substrate as claimed in claim 2, wherein the aforementioned highly elastic layer region is formed by disposing at least one of inorganic fibers and organic fibers in an organic resin material.

4. The method for manufacturing a wiring board as described in claim 3, wherein the aforementioned inorganic fiber is at least one of glass fiber, ceramic fiber and carbon fiber, and the aforementioned organic fiber is at least one of polyaramid fiber and polyethylene fiber.

5. A method for manufacturing a wiring substrate as described in any one of claims 1 to 4, wherein the thickness of the first resin layer region on the surface side of the aforementioned resin sheet is 5 μm or more and 20 μm or less.

6. A method for manufacturing a wiring substrate as described in any one of claims 1 to 4, wherein the linewidth of the aforementioned recess formed in the first resin layer region is 0.5 μm or more and 5 μm or less.

7. A method for manufacturing a wiring board as described in any one of claims 1 to 4, wherein the resin sheet has a second resin layer region on the opposite side of the first resin layer region, and in the process of preparing the structure, the structure is prepared by attaching the resin sheet to the support or the embedded wiring layer by means of the second resin layer region.

8. A method for manufacturing a wiring substrate as described in any one of claims 1 to 4, wherein when the aforementioned recess is formed in the first resin layer region by an excimer laser, the pulse width of the excimer laser is 10 nanoseconds or more and 50 nanoseconds or less, and the output of the excimer laser is 10 mJ / pulse or more and 1000 mJ / pulse or less.

9. A method for manufacturing a wiring substrate as described in any one of claims 1 to 4, wherein in the aforementioned step of forming the wiring layer, a metal plating layer is formed in the aforementioned recess and the aforementioned opening to form the aforementioned wiring layer, the aforementioned resin sheet comprises a component formed of heteroaryl rings capable of coordination bonding with a metal material, and the aforementioned metal material constitutes a seed layer for forming the aforementioned metal plating layer.

10. A method for manufacturing a wiring board as described in any one of claims 1 to 4, wherein the aforementioned resin sheet or the covering layer covering the aforementioned resin sheet contains a laser light-absorbing coloring component, the aforementioned laser light-absorbing coloring component being formed from at least one of inorganic dyes, inorganic pigments, organic dyes and organic pigments.

11. A method for manufacturing a wiring substrate as described in any one of claims 1 to 4, wherein in the aforementioned step of forming the wiring layer, a metal plating layer based on an electroless seed layer is formed in the aforementioned recess and the aforementioned opening to form the aforementioned wiring layer, and the aforementioned resin sheet contains a catalyst for forming the aforementioned electroless plating.

12. A method for manufacturing a wiring substrate as described in any one of claims 1 to 4, wherein the step of forming the aforementioned wiring layer comprises: filling the aforementioned recess and the aforementioned opening with a conductive material and disposing a conductive material on the surface of the aforementioned first resin layer region other than the aforementioned recess and the aforementioned opening to form a conductive layer; and a step of planarizing the aforementioned conductive layer, wherein in the aforementioned planarization step, at least a first portion of the aforementioned conductive layer disposed on the surface of the aforementioned first resin layer region is ground, and the aforementioned wiring layer is formed from a second portion of the aforementioned conductive layer, wherein the aforementioned conductive layer is formed from the aforementioned conductive material filled in the aforementioned recess and the aforementioned opening.

13. A method for manufacturing a wiring board as described in any one of claims 1 to 4, further comprising: In the process of forming a concealed wiring portion having at least one layer of the aforementioned concealed wiring layer on the aforementioned support body, in the process of preparing the aforementioned structure, the aforementioned structure is prepared by attaching the aforementioned resin sheet to the concealed wiring portion for installation.

14. A method for manufacturing a wiring board as described in any one of claims 1 to 4, further comprising: The process of mounting another resin sheet on the resin sheet prior to the formation of the aforementioned wiring layer; the process of forming another recess in the first resin layer region of the aforementioned other resin sheet by laser; the process of forming another opening, wherein the aforementioned other opening extends from the surface of the aforementioned other resin sheet to the aforementioned metal plating layer or the aforementioned wiring layer of the aforementioned opening; and the process of forming another metal plating layer in the aforementioned other recess and the aforementioned other opening to form another wiring layer, wherein the process of mounting the aforementioned other resin sheet, the process of forming the aforementioned other recess, the process of forming the aforementioned other opening and the process of forming the aforementioned other wiring layer are repeated at least once.

15. A method for manufacturing a wiring substrate as described in any one of claims 1 to 4, wherein the step of forming the wiring layer comprises: a step of removing adhesive residue from at least the opening and the recess; a step of forming a seed layer at least in the opening and the recess by electroless plating; a step of performing electroplating on the seed layer to form a metal plating layer; and a step of removing the seed layer and the metal plating layer from the surface of the first resin layer region to planarize the surface of the first resin layer region, the seed layer, and the metal plating layer.

16. A method for manufacturing a semiconductor device, comprising: A process for preparing to manufacture a wiring board by any of the manufacturing methods described in claims 1 to 15; The process of mounting a semiconductor element on the aforementioned wiring layer or the aforementioned other wiring layer and electrically connecting the aforementioned semiconductor element to the aforementioned wiring layer or the aforementioned other wiring layer.

17. A semiconductor device having a structure manufactured using the manufacturing method described in claim 16.

18. A resin sheet for manufacturing a wiring substrate according to any one of claims 1 to 15, the resin sheet comprising: a first resin layer region located on the outer side; and a high elasticity layer region located on the inner side with an elastic modulus higher than that of the first resin layer region, or a high elasticity layer region having a glass fiber cloth located on the inner side, wherein the first resin layer region comprises at least one compound selected from the group consisting of a maleic anhydride compound, a dimaleic anhydride compound, a triazole compound, a benzotriazole compound, and a benzotriazole compound.

19. The resin sheet as claimed in claim 18, further comprising a second resin layer region, the second resin layer region being located on the opposite side of the first resin layer region across the aforementioned highly elastic layer region and having adhesive properties.

20. The resin sheet as claimed in claim 18 or claim 19, wherein the aforementioned first resin layer region comprises at least one of graphite, graphene, carbon nanotubes, carbon fibers, carbon black, phthalocyanine, anthocyanin, alkaline earth metals, and metal complexes.

21. The resin sheet as claimed in claim 18 or claim 19, wherein the aforementioned first resin layer region comprises at least one of palladium particles, palladium complexes, copper particles, and copper complexes.

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