Solid-state camera elements and their manufacturing methods

Abstract

The objective of this invention is to provide a solid-state imaging element that can reduce random noise of pixels and suppress crosstalk between adjacent pixels. The disclosed solid-state imaging element comprises: a substrate; a plurality of photoelectric conversion units disposed within the substrate; a first insulating film disposed between adjacent photoelectric conversion units and within the inner wall of a trench penetrating between a first surface of the substrate and a second surface opposite to the first surface, and having a fixed charge; a second insulating film disposed within the trench and inside the first insulating film; at least one transistor disposed on the first surface of the substrate; and a third insulating film disposed along both sides of the trench or on the trench when viewed from the first surface.

Description

Technical Field

[0001] This disclosure relates to a solid-state camera element and its manufacturing method. Prior Technology

[0002] In a solid-state imaging element, there are cases where multiple adjacent pixels are physically separated by a through-channel. A fixed charge film is formed on the sidewall of such a through-channel, and the fixed charge film induces a charge accumulation region around the sidewall of the through-channel.

[0003] However, if this charge accumulation region comes into contact with the source or drain diffusion layer of the pixel's transistor, a high-concentration PN junction is formed, which generates a strong electric field. This strong electric field generates dark current, becoming a cause of random noise.

[0004] Furthermore, when a through-channel is formed before the pixel transistor is formed, the material embedded in the through-channel must be heat-resistant enough to withstand the high-temperature processing during the pixel transistor formation process. Therefore, metals with low heat resistance cannot be used; materials with high heat resistance, such as polycrystalline silicon, silicon nitride films, and silicon oxide films, must be employed. However, polycrystalline silicon, silicon nitride films, and silicon oxide films have low light-shielding properties, leading to light leakage between adjacent pixels and causing crosstalk. [Previous Technical Documents] [Patent Literature]

[0005] [Patent Document 1] International Patent Publication No. 2019 / 093150 Summary of the Invention

[0006] [The problem the invention aims to solve]

[0007] The present invention provides a solid-state imaging element that can reduce random noise of pixels and suppress light leakage between adjacent pixels. [Technical means to solve the problem]

[0008] The solid-state imaging element disclosed herein comprises: a substrate; a plurality of photoelectric conversion units disposed within the substrate; a first insulating film disposed between adjacent photoelectric conversion units and disposed on the inner wall of a trench penetrating between a first surface of the substrate and a second surface opposite to the first surface, and having a fixed charge; a second insulating film disposed within the trench and inside the first insulating film; at least one transistor disposed on the first surface of the substrate; and a third insulating film disposed along both sides of the trench or on the trench when viewed from the first surface.

[0009] The third insulating film is disposed between the charge-induced layer formed on the surface of the substrate adjacent to the first charge film and the source or drain of the transistor.

[0010] The charge-induced layer is a high-concentration charge layer of the first conductivity type, and the source or drain of the transistor is a high-concentration impurity diffusion layer of the second conductivity type.

[0011] The charge-induced layer is the first conductivity type impurity diffusion layer.

[0012] The third insulating film covers the ends of the first and second insulating films on the first side.

[0013] The ends of the first and second insulating films on the first side penetrate the third insulating film.

[0014] The solid-state camera element further comprises: a wiring layer disposed on a first surface of the substrate and electrically connected to a transistor; and a lens disposed on a second surface of the substrate.

[0015] The solid-state camera element further includes a light-shielding film, which is disposed inside the second insulating film within the trench.

[0016] When the substrate is viewed from a direction perpendicular to the first surface, the third insulating film overlaps with the first and second insulating films.

[0017] When the substrate is viewed from a direction approximately perpendicular to the first surface, the width of the third insulating film is greater than the width of the trench.

[0018] When the substrate is viewed from a direction approximately perpendicular to the first surface, the width of the third insulating film is greater than the width of the charge-induced layers located on both sides of the trench.

[0019] The depth of the third insulating film from the first surface is greater than the depth of the diffusion layer of the transistor adjacent to the third insulating film.

[0020] The method for manufacturing a solid-state imaging element disclosed herein includes: forming a plurality of photoelectric conversion units in a substrate; forming a third insulating film between adjacent photoelectric conversion units on a first surface of the substrate; forming a trench between adjacent photoelectric conversion units that connects the first surface of the substrate to a second surface opposite to the first surface; forming a first insulating film with a fixed charge on the inner wall of the trench; forming a second insulating film inside the first insulating film in the trench; and forming at least one transistor on the first surface of the substrate.

[0021] The manufacturing method of the solid-state camera element further includes: introducing a first type of conductive impurity into the inner wall of the channel to form a charge-induced layer on the inner wall of the channel.

[0022] The ditch connects to the third insulating film. Simple Explanation of the Diagram

[0023] Figure 1 is a block diagram showing an example of the configuration of a camera device, which is one example of the electronic machine disclosed herein. Figure 2 is a block diagram showing an example of the configuration of a camera element. Figure 3 is a top view showing an example of the composition of one pixel among a plurality of pixels constituting a pixel array. Figure 4 is an equivalent circuit diagram of an example of pixel configuration. Figure 5 is a cross-sectional view showing an example of the pixel configuration of this embodiment. Figure 6 is a top view showing an example of the pixel layout as viewed from the second side. Figure 7 is a cross-sectional view showing an example of a method for manufacturing a solid-state camera element according to the first embodiment. Figure 8 is a cross-sectional view showing an example of a method for manufacturing a solid-state camera element according to the first embodiment. Figure 9 is a cross-sectional view showing an example of a method for manufacturing a solid-state camera element according to the first embodiment. Figure 10 is a cross-sectional view showing an example of a method for manufacturing a solid-state camera element according to the first embodiment. Figure 11 is a cross-sectional view showing an example of a method for manufacturing a solid-state camera element according to the first embodiment. Figure 12 is a cross-sectional view showing an example of a method for manufacturing a solid-state camera element according to the first embodiment. Figure 13 is a cross-sectional view showing an example of a method for manufacturing a solid-state camera element according to the first embodiment. Figure 14 is a cross-sectional view showing an example of the pixel configuration in the second embodiment. Figure 15 is a cross-sectional view showing an example of the pixel configuration in the third embodiment. Figure 16 is a cross-sectional view showing an example of the pixel configuration in the fourth embodiment. Figure 17 is a cross-sectional view showing an example of the pixel configuration in the fifth embodiment. Figure 18 is a cross-sectional view showing an example of the pixel configuration in the sixth embodiment. Figure 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is one example of a mobile body control system to which the technology disclosed herein can be applied. Figure 20 shows an example of the camera unit's installation location. Implementation

[0024] The following description, with reference to the drawings, details specific implementations of this technology. The drawings are schematic or conceptual, and the proportions of the parts are not necessarily identical to those of the actual object. In the specification and drawings, elements identical to those described in the previously presented drawings are given the same symbols, and detailed explanations are appropriately omitted.

[0025] (First Implementation) Figure 1 is a block diagram showing an example of the configuration of a camera device, which is one example of the electronic machine disclosed herein. As shown in Figure 1, the camera device 10 includes: an optical system including a lens group 11, an image sensor 12, a DSP circuit 13 serving as a camera signal processing unit, a frame memory 14, a display unit 15, a recording unit 16, an operating system 17, and a power supply system 18. The DSP circuit 13, frame memory 14, display unit 15, recording unit 16, operating system 17, and power supply system 18 are interconnected via bus cables 19. The CPU 20 controls the various parts within the camera device 10.

[0026] Lens group 11 captures incident light (image light) from the subject and forms an image on the imaging surface of imaging element 12. Imaging element 12 converts the amount of incident light that forms an image on the imaging surface by means of lens group 11 into an electrical signal in pixel units and outputs it as a pixel signal. Imaging element 12 can be a camera element (image sensor) including pixels as described below.

[0027] The display unit 15 includes a panel-type display unit such as a liquid crystal display unit or an organic EL (electroluminescence) display unit, which displays animations or still images captured by the camera element 12. The recording unit 16 stores the animations or still images captured by the camera element 12 on recording media such as HDD (Hard Disk Drive) or SSD (Solid State Drive).

[0028] The operating system 17 issues operation commands for the various functions of the camera device under the operation of the user. The power supply system 18 provides appropriate power to the DSP circuit 13, frame memory 14, display unit 15, recording unit 16, and operating system 17.

[0029] Figure 2 is a block diagram showing an example of the configuration of the image sensor 12. The image sensor 12 is a CMOS (Complementary Metal Oxide Semiconductor) image sensor that captures images of a written object and obtains them as electrical signals. The image sensor 12 includes: a pixel array 41, a vertical driving unit 42, a horizontal processing unit 43, a horizontal driving unit 44, and a system control unit 45. The pixel array 41, the vertical driving unit 42, the horizontal processing unit 43, the horizontal driving unit 44, and the system control unit 45 are formed on a semiconductor substrate (wafer) not shown.

[0030] The pixel array section 41 has a matrix-like two-dimensional arrangement of unit pixels, each having a photoelectric conversion element that generates a photoelectric charge corresponding to the amount of incident light and stores it internally. Furthermore, in the following, the photoelectric charge corresponding to the amount of incident light may be simply referred to as "charge" and the unit pixel may be simply referred to as "pixel".

[0031] In the pixel array section 41, pixel driving lines 46 are further formed in each column along the left-right direction of the image (the arrangement direction of pixels in a pixel column) relative to the matrix-like pixel arrangement, and vertical signal lines VSL, serving as the first signal lines, are formed in each row along the up-down direction of the image (the arrangement direction of pixels in a pixel row). One end of the pixel driving line 46 is connected to the output terminal corresponding to each column of the vertical driving section 42.

[0032] The camera element 12 further includes a signal processing unit 48 and a data storage unit 49. The signal processing unit 48 and the data storage unit 49 can be external signal processing units disposed on a different substrate from the camera element 12, such as processing performed by a DSP (Digital Signal Processor) or software, or they can be mounted on the same substrate as the camera element 12.

[0033] The vertical drive unit 42 is composed of a shift register and an address decoder, etc., and is a pixel drive unit that drives each pixel of the pixel array unit 41 simultaneously or in column units. The specific structure of the vertical drive unit 42 is not shown in the figure, but it is configured to have a readout scanning system, an exclusion scanning system, or batch exclusion and batch transmission.

[0034] In order to read out signals from individual pixels, the readout scanning system sequentially selects the unit pixels of the scanning pixel array 41 in column units. In the case of column drive (rolling shutter operation), for exclusion, an exclusion scan is performed relative to the column read out by the readout scanning system, with a time fraction of the shutter speed preceding the readout scan. Furthermore, in the case of global exposure (global shutter operation), batch exclusion is performed with a time fraction of the shutter speed preceding batch transmission.

[0035] By eliminating unnecessary charge (resetting), the photoelectric conversion elements of the self-reading unit pixels are freed from unwanted charge. By eliminating (resetting) unwanted charge, the so-called electronic shutter action is performed. Here, the so-called electronic shutter action means discarding the photoelectric conversion element's photocharge and restarting the exposure (that is, starting the accumulation of photocharge).

[0036] The signal read out by the readout scan system corresponds to the amount of light incident immediately following the preceding readout action or electronic shutter action. In column drive mode, the period from the readout timing of the preceding readout action or the exclusion timing of the electronic shutter action to the readout timing of the current readout action is the photocharge accumulation period (exposure period) per pixel. In full-area exposure mode, the period from batch exclusion to batch transfer is the accumulation period (exposure period).

[0037] The pixel signals output from each unit pixel of the pixel column selected for scanning by the vertical drive unit 42 are supplied to the horizontal processing unit 43 via the vertical signal line VSL. The horizontal processing unit 43 performs specific signal processing on the pixel signals output from each unit pixel of the self-selected column of the pixel array unit 41 via the vertical signal line VSL for each pixel row and temporarily holds the processed pixel signals.

[0038] Specifically, the horizontal processing unit 43 or the signal processing unit 48 performs signal processing, at least noise removal processing, such as CDS (Correlated Double Sampling) processing. Through the CDS processing performed by the horizontal processing unit 43, fixed-pattern noise inherent in pixels, such as reset noise or threshold deviation of the amplification transistor, is removed. Furthermore, the horizontal processing unit 43 can also have, in addition to noise removal processing, functions such as AD (Analog-to-Digital) conversion to output a digital signal level.

[0039] The horizontal drive unit 44 is composed of a shift register and an address decoder, etc., and sequentially selects the unit circuits corresponding to the pixel rows of the row processing unit 43. Through the selection scan performed by the horizontal drive unit 44, the pixel signals after signal processing by the row processing unit 43 are sequentially output to the signal processing unit 48.

[0040] The system control unit 45 includes a timing generator that generates various timing signals, and performs drive control of the vertical drive unit 42, the horizontal processing unit 43, and the horizontal drive unit 44 based on the various timing signals generated by the timing generator.

[0041] The signal processing unit 48 has at least an addition processing function, performing various signal processing operations such as addition processing on the pixel signals output by the self-processing unit 43. The data storage unit 49 temporarily stores the data required for the processing during the signal processing of the signal processing unit 48.

[0042] Figure 3 is a top view showing an example of the configuration of one pixel 100 among the plurality of pixels constituting the pixel array section 41. Figure 4 is an equivalent circuit diagram showing an example of the configuration of the pixel 100. The pixel array section 41, for example, has a plurality of pixels 100 arranged in an array-like two-dimensional configuration. Each pixel 100 performs photoelectric conversion on the incident light and outputs a pixel signal of the captured image.

[0043] Pixel 100 includes: a photodiode (PD) 219, a transmission transistor (TG) 112, a reset transistor (RST) 113, an amplifying transistor (AMP) 114, and a select transistor (SEL) 115. Furthermore, in areas other than the transistors and photodiode 219, for example, a component separation region is provided for electrical separation from other pixels. The component separation region includes an insulating film. In the case of electronic readout, the component separation region can be formed by a p-type region. Transistors 112-115 can be either n-type or p-type transistors. Here, transistors 112-115 are described as n-type transistors.

[0044] The photodiode 219 converts the received light into a charge (in this case, electrons) corresponding to the amount of light and stores this charge. The anode of the photodiode 219 is connected to the ground of the pixel area, and the cathode is connected to the floating diffusion section FD, which serves as the floating diffusion region, via the transmission transistor 112. Alternatively, the cathode of the photodiode 219 can be connected to the power supply of the pixel area (pixel power supply), and the anode can be connected to the floating diffusion section FD via the transmission transistor 112. In this case, the pixel 100 becomes a hole that reads out the charge.

[0045] Transistor 112 controls the readout of photocharge from photodiode 219. The source of transistor 112 is connected to the cathode of photodiode 219. The drain of transistor 112 is connected to the floating diffuser FD. A transmission control signal is supplied to the gate of transistor 112. The readout of charge from photodiode 219 is controlled by this transmission control signal. For example, when the transmission control signal (i.e., the gate potential of transistor 112) is at a low level, transistor 112 is in an off state (non-conducting state) and does not transmit charge from photodiode 219. When the transmission control signal (i.e., the gate potential of transistor 112) is at a high level, transistor 112 is in a conducting state (conducting state), transmitting the charge accumulated in photodiode 219 to the floating diffuser FD. The floating diffusion section FD is a diffusion layer that can temporarily store charge and is disposed on the surface area of ​​the semiconductor substrate 218.

[0046] The reset transistor 113 resets the charge within pixel 100. The reset action may be, for example, removing charge (e.g., electrons) from photodiode 219 and floating diffuser FD towards the power supply VDD, or removing holes towards ground. The drain of the reset transistor 113 is connected to the power supply VDD, and the source of the reset transistor 113 is connected to the floating diffuser FD, and via the floating diffuser FD, it is connected to the drain of the transmission transistor 112. That is, the reset transistor 113 is connected between the drain of the transmission transistor 112 and the power supply VDD. Furthermore, a reset control signal is supplied to the gate of the reset transistor 113. The reset of the charge within pixel 100 is controlled by this reset control signal. For example, when the reset control signal (i.e., the gate potential of the reset transistor 113) is at a low level, the reset transistor 113 is in an off state and no reset is performed. When the reset control signal (i.e. the gate potential of the reset transistor 113) is at a high level, the reset transistor 113 becomes in the conducting state, removes the charge in the pixel 100 to the power supply VDD, and resets the floating diffuser FD and the photodiode 219.

[0047] The amplifying transistor 114 is turned on in a state corresponding to the voltage of the floating diffuser FD. The amplifying transistor 114 amplifies the voltage change of the floating diffuser FD and outputs it as an electrical signal (analog signal) to the vertical signal line VSL via the selector transistor 115. That is, the amplifying transistor 114 functions as a readout circuit to read the voltage of the floating diffuser FD. The gate of the amplifying transistor 114 is connected to the floating diffuser FD. The drain of the amplifying transistor 114 is connected to the source follower power supply voltage (VDD), and the source is connected to the drain of the selector transistor 115. That is, the amplifying transistor 114 is connected between the power supply (VDD) and the vertical signal line VSL. For example, the amplifying transistor 114 outputs the voltage of the reset level (P phase) corresponding to the potential of the reset floating diffuser FD to the selector transistor 115. Furthermore, the amplifying transistor 114 outputs the voltage of the data level (D phase) corresponding to the potential of the floating diffusion section FD which stores the signal charge from the photodiode 219 to the selecting transistor 115.

[0048] The selector transistor 115 controls the output of the electrical signal from the amplifying transistor 114 to the vertical signal line VSL. The gate of the selector transistor 115 is connected to the pixel drive line 46 in Figure 2 and receives the selector control signal. The drain of the selector transistor 115 is connected to the source of the amplifying transistor 114, and the source of the selector transistor 115 is connected to the vertical signal line VSL, which is the first signal line. That is, the selector transistor 115 is connected between the amplifying transistor 114 and the vertical signal line VSL. The amplifying transistor 114 and the selector transistor 115 are connected in series between the power supply VDD and the vertical signal line VSL. Furthermore, the selector transistor 115 controls the output of the electrical signal from the amplifying transistor 114 to the vertical signal line VSL based on the selector control signal. For example, when pixel 100 is not selected, the selector control signal (i.e., the gate potential of the selector transistor 115) is at a low level. In this case, the selector transistor 115 is turned off, and the electrical signal from the amplifying transistor 114 for the reset level or data level is not output to the vertical signal line VSL. When pixel 100 is selected, the selection control signal (i.e., the gate potential of the selector transistor 115) becomes high. In this case, the selector transistor 115 becomes on, electrically connecting the amplifying transistor 114 to the vertical signal line VSL, and outputting an electrical signal corresponding to the voltage of the floating diffuser FD to the vertical signal line VSL. The vertical signal line VSL is connected to an A / D conversion circuit located outside pixel 100, transmitting electrical signals to the A / D conversion circuit. The A / D conversion circuit performs AD conversion on the electrical signals for the reset level and data level. The horizontal processing unit 43 or the signal processing unit performs CDS processing on the converted digital signals.

[0049] As described above, each pixel 100 can output an electrical signal corresponding to the incident light to the vertical signal line VSL.

[0050] Next, the construction of pixel 100 will be explained.

[0051] Figure 5 is a cross-sectional view showing an example of the configuration of pixel 100 in this embodiment. Figure 6 is a top view showing an example of the layout of pixel 100 as viewed from the second plane F2. Figure 5 corresponds to the cross-section along AA in Figure 6.

[0052] As shown in Figure 5, the pixel 100 includes: a semiconductor substrate 218, a photodiode (PD) 219, a charge-induced layer 220, a fixed charge film 232, a pixel separation film 233, a component separation film 234, a light-shielding film 214, a planarization film 213, a color filter 212, an optical crystal carrier lens (OCL) 211, a transistor 250, wiring 261, and an interlayer insulating film 262.

[0053] The semiconductor substrate 218 is, for example, a silicon substrate. The semiconductor substrate 218 has a first surface F1 and a second surface F2 located opposite to the first surface F1. The semiconductor substrate 218 includes, for example, a photodiode 219 composed of an n-type semiconductor region and a p-type semiconductor region. The photodiode 219 is a photoelectric conversion unit that converts incident light passing through the crystal lens 211, etc., on the second surface F2 into electrical charge (e.g., electrons). The photodiode 219 also functions as a charge storage region that stores the charge converted from photoelectric conversion in the n-type semiconductor region. The photodiode 219 is separated for each pixel 100 by a fixed charge film 232 and a pixel separation film 233, and performs photoelectric conversion for each pixel 100. The photodiode 219 has a p-type semiconductor region on the second surface F2 side of the semiconductor substrate 218, but does not have a p-type semiconductor region on the first surface F1 side.

[0054] As shown in Figure 6, the fixed charge film 232 and the pixel separation film 233 are positioned between adjacent pixels 100 when viewed from a direction substantially perpendicular to the first surface F1 or the second surface F2 (Z direction), and are arranged in a grid pattern. The fixed charge film 232 and the pixel separation film 233 are disposed between adjacent photoelectric conversion units. The fixed charge film 232 and the pixel separation film 233 divide the photodiode 219 for each pixel 100, separating the electrical and optical properties of the photodiode 219 of each pixel 100. Furthermore, the pixel array section 41 of Figure 2 is formed by the square repeating arrangement of the pixels 100 in Figure 6.

[0055] A fixed charge film 232, serving as a first insulating film, is disposed within a trench TR that extends between the first surface F1 and the second surface of the semiconductor substrate 218, and covers the inner wall of the trench TR. When viewed from a direction substantially perpendicular to either the first surface F1 or the second surface F2, the trench TR is positioned between a plurality of adjacent pixels 100, dividing the pixels 100 in a grid pattern (see Figure 6). Therefore, the fixed charge film 232 is disposed along the trench TR and, similarly, between adjacent pixels 100.

[0056] The fixed charge film 232 is an insulating film with a fixed charge, such as a negative charge. Preferably, the fixed charge film 232 is a material that can generate a fixed charge and thus strengthen pinning by being deposited on the semiconductor substrate 218. By disposing the fixed charge film 232 on the inner wall of the trench TR, a charge (e.g., a positive charge) is induced in the charge-inducing layer 220 on the surface of the semiconductor substrate 218 adjacent to the fixed charge film 232.

[0057] For the fixed charge film 232, a high refractive index material film or a highly electrophoretic film with a negative charge can be used, for example. For example, the fixed charge film 232 can be a metal oxide or metal nitride containing at least one element selected from hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti). Furthermore, the fixed charge film 232 can be an oxide or nitride containing at least one element selected from lanthanum (La), tungsten (Pr), cerium (Ce), neodymium (Nd), protium (Pm), samarium (Sm), europium (Eu), thorium (Gd), tektium (Tb), dysprosium (Dy), holmium (Ho), thionium (Tm), ytterbium (Yb), argonium (Lu), and yttrium (Y). Moreover, the fixed charge film 232 can be a hafnium oxynitride film or an aluminum oxynitride film.

[0058] For the material of the fixed charge film 232, silicon (Si) or nitrogen (N) can be added to the film within a range that does not impair insulation. The concentration should be appropriately determined within a range that does not impair the insulation of the film. In this way, by adding silicon (Si) or nitrogen (N), the heat resistance of the film and its ability to prevent ion implantation during the process can be improved.

[0059] A fixed charge film 232 with a negative charge is provided on the inner wall of the trench TR and on the second surface F2 of the semiconductor substrate 218. Therefore, an inversion layer (p-type charge-induced layer) is formed on the inner wall of the trench TR and the second surface F2 of the semiconductor substrate 218 in contact with the fixed charge film 232. Since the silicon interface is pinned by the charge-induced layer, the generation of dark current is suppressed. Furthermore, during the formation of the trench TR, physical damage may occur on the inner wall of the trench TR, potentially causing pin detachment at the periphery of the trench TR. In this embodiment, by providing a fixed charge film 232 with a fixed charge on the inner wall of the trench TR, pin detachment can be suppressed.

[0060] Furthermore, the film formation method for the fixed charge film 232 may be, for example, CVD (Chemical Vapor Deposition), sputtering, ALD (Atomic Layer Deposition), etc.

[0061] The pixel separation film 233, serving as the second insulating film, is embedded within the trench TR inside the fixed charge film 232. The pixel separation film 233 is disposed along the trench TR and, similarly, between adjacent pixels 100. By embedding the trench TR, the pixel separation film 233 electrically and optically separates adjacent pixels 100. For the pixel separation film 233, it is preferable to use a material with a different refractive index than the fixed charge film 232, such as silicon oxide, silicon nitride, silicon oxynitride, or resin. Alternatively, for the pixel separation film 233, a material without positive fixed charge or with a small amount of positive fixed charge can be used.

[0062] By using a material with high insulation and light-shielding properties for the pixel separation film 233, incident light and signal charge are unlikely to leak into adjacent pixels. Therefore, leakage (crosstalk) of incident light between pixels 100 can be suppressed. Furthermore, even if signal charge exceeding the saturation charge (Qs) is generated, leakage of signal charge to adjacent pixels can be suppressed.

[0063] The charge-induced layer 220 is, for example, a p-type high-concentration charge layer, and is a positive charge layer induced by the fixed charge (e.g., negative charge) of the fixed charge film 232. The charge-induced layer 220 may be a p-type impurity diffusion layer formed by introducing p-type impurities. Alternatively, the charge-induced layer 220 may be induced by the fixed charge film 232, and may not necessarily introduce p-type impurities (see the second embodiment).

[0064] The element separation film 234, serving as the third insulating film, covers the ends of the fixed charge film 232 and the pixel separation film 233 on the first surface F1 side. As shown in FIG. 6, the element separation film 234 is provided on the first surface F1 of the semiconductor substrate 218 to define the effective area AA for forming the transistor 250, electrically separating the effective areas AA. When viewed in a direction substantially perpendicular to the first surface F1 (in the Z direction), as shown in FIG. 6, the element separation film 234 is disposed between adjacent pixels 100, coinciding with the fixed charge film 232 and the pixel separation film 233. Therefore, as shown in FIG. 6, the element separation film 234 appears on the first surface F1, while the fixed charge film 232 and the pixel separation film 233 are located below the element separation film 234 and do not appear on the first surface F1. According to this embodiment, the element separation film 234 is placed between the charge-inducing layer 220 and the source or drain of the transistor 250 by means of the ends covered with the fixed charge film 232 and the pixel separation film 233, thereby separating them. In this way, the formation of the pn junction between the charge-inducing layer 220 with a high concentration of P+ charge and the source or drain diffusion layer 252 with a high concentration of N+ charge in the pixel 100 can be suppressed.

[0065] Transistor 250 is disposed on the first surface F1 of semiconductor substrate 218 and has a diffusion layer (hereinafter also referred to as diffusion layer) 252 with gate 251, source and drain. Diffusion layer 252 is a high-concentration impurity diffusion layer with n+ type impurities having the opposite conductivity type to charge induced layer 220.

[0066] Transistor 250 is at least one of the transistors constituting pixel 100 as shown in Figure 3, and can be any one of transmission transistor 112, reset transistor 113, amplification transistor 114, and selection transistor 115.

[0067] Interlayer insulating film 262 and wiring 261 are disposed on the first surface F1. Transistor 150 is covered by interlayer insulating film 262. Wiring 261 is electrically connected to any one of transmission transistor 112, reset transistor 113, amplification transistor 114, and selection transistor 115, and reads the signal voltage corresponding to the signal charge from the selection transistor 115 to the vertical signal line VSL.

[0068] On the other hand, a fixed charge film 232 and a pixel separation film 233 are disposed on the second surface F2 of the semiconductor substrate 218, and a light-shielding film 214 is disposed thereon. When viewed from above the second surface F2 (i.e., in the Z direction), the light-shielding film 214 is disposed along the trench TR in a manner that coincides with the trench TR. The light-shielding film 214 is made of a metal material with high light-shielding properties. For example, the light-shielding film 214 can be made of a single metal material such as tungsten or aluminum, or a laminated film of aluminum and barrier metals (e.g., titanium, cobalt), a laminated film of tungsten and barrier metals (e.g., titanium, cobalt), or a laminated film of aluminum and cobalt. The light-shielding film 214 can suppress incident light from entering the through trench TR and reduce random noise of the pixel 100.

[0069] A planarization film 213 is disposed on the second surface F2 and covered with a light-shielding film 214. The surface of the planarization film 213 is planarized, giving the color filter 212 a flat surface. For example, an insulating film such as a silicon oxide film is used for the planarization film 213. Both the planarization film 213 and the color filter 212 are made of a light-transmitting material.

[0070] A color filter 212 is disposed on a planarization film 213. For example, a resin that allows light of specific colors such as RGB to pass through may be used for the color filter 212.

[0071] A crystal lens 211 is disposed on a color filter 212 so that incident light is focused onto the photodiode 219 of pixel 100.

[0072] Incident light enters from the second surface F2 and enters the photodiode 219 of pixel 100. Since the solid-state imaging element in this embodiment captures incident light from the second surface (back surface) F2, which is opposite to the first surface (front surface) F1 where the transistor 250 and wiring 261 are located, it is a back-illuminated CIS (Complementary Metal Oxide Semiconductor Image Sensor). However, this technology can also be applied to surface-illuminated CIS.

[0073] Incident light enters the photodiode 219 through the crystal lens 211, the color filter 212 and the planarization film 213, and is converted by photoelectric conversion in the photodiode 219.

[0074] The anode of photodiode 219 is grounded, positive charges (holes) are discharged to the ground, and negative charges (electrons) are accumulated in photodiode 219. The electrons accumulated in photodiode 219 are read out by a transistor and the like, and output as an electrical signal to the vertical signal line VSL in Figure 3.

[0075] Thus, according to this embodiment, the element separation film 234 is disposed along both sides of the trench TR when viewed from a direction substantially perpendicular to the first surface F1. Furthermore, the element separation film 234 is disposed on the trench TR in a manner that overlaps with the trench TR when viewed from a direction substantially perpendicular to the first surface F1. This suppresses the formation of a high-concentration pn junction within the pixel 100, which is composed of a charge-inducing layer 220 with a high concentration of P+ charge and a diffusion layer 252 with a high concentration of N+ charge.

[0076] If the element separation film 234 is not covered at the ends of the trench TR, the fixed charge film 232, and the pixel separation film 233, the charge-induced layer 220 of FIG5 is formed on the first surface F1. In this case, the charge-induced layer 220 and the diffusion layer 252 constitute a high-concentration pn junction containing a high-concentration p+ charge layer and a high-concentration n+ diffusion layer. In the presence of the high-concentration pn junction, a high electric field is generated in the high-concentration pn junction, which becomes the cause of dark current. Dark current becomes the cause of random noise in the pixel 100, and the dark current suppression effect achieved by the pinning of the fixed charge film 232 is weakened.

[0077] In this embodiment, the element separation film 234 covers the ends of the fixed charge film 232 and the pixel separation film 233 along the through-channel TR. The element separation film 234 insulatingly separates the charge-induced layer 220 from the source and drain diffusion layers 252 of the transistor 250. This suppresses the formation of high-concentration pn junctions and the generation of high electric fields. As a result, dark current is suppressed, and random noise in the pixel 100 is reduced.

[0078] Next, referring to Figure 5, the dimensions of the element separation membrane 234 will be described in more detail.

[0079] When the semiconductor substrate 218 is viewed in a direction perpendicular to the first surface F1 (i.e., in the Z direction), the element separation film 234 is disposed along both sides of the trench TR and on the trench TR in a manner coinciding with the trench TR. Furthermore, the width W234 of the element separation film 234 is greater than the width Wtr of the trench TR. The width Wtr of the trench TR is the same as or greater than the width of the fixed charge film 232 or the pixel separation film 233. Therefore, the width W234 is greater than the width of any one of the trench TR, the fixed charge film 232, and the pixel separation film 233. Moreover, as shown in FIG. 5, the widths W234 and Wtr are the widths of a cross-section on the first surface F1 in a direction substantially perpendicular to the extending direction (i.e., the X direction) of the trench TR, the fixed charge film 232, and the pixel separation film 233. Furthermore, as shown in FIG. 5, the element separation film 234 protrudes further toward the photodiode 219 side (i.e., in the ±X direction) than the charge-induced layer 220. Therefore, the width W234 of the element separation membrane 234 is greater than the width W220 of one trench TR and the two charge-induced layers 220 located on both sides of the trench TR. In this way, the formation (induction) of the charge-induced layer 220 on the side of the element separation membrane 234 is suppressed, and the element separation membrane 234 can more reliably separate the charge-induced layer 220 from the diffusion layer 252.

[0080] Furthermore, the depth (thickness) D234 of the element separation membrane 234 in the Z direction is deeper (thicker) than the depth (thickness) D252 of the diffusion layer 252. In this way, the element separation membrane 234 can further and more reliably separate the charge-induced layer 220 from the diffusion layer 252.

[0081] Next, the manufacturing method of the solid-state camera element of this embodiment will be explained.

[0082] Figures 7 to 13 are cross-sectional views showing an example of a manufacturing method of a solid-state camera element according to the first embodiment.

[0083] (Front-end steps) Processing steps are performed starting from the first surface F1 of the semiconductor substrate 218.

[0084] First, a device separation film 234 is formed on the first surface F1 side of the semiconductor substrate 218. The device separation film 234 is formed as STI (Shallow Trench Isolation) to define the effective area AA. Furthermore, in this embodiment, the device separation film 234 is formed in the trench TR formation region between adjacent pixels 100. The upper part of the semiconductor substrate 218 in the device separation region is removed using photolithography and etching techniques. Then, an insulating film such as a silicon oxide film is buried into the device separation region to form the device separation film 234. The device separation film 234 is formed to be wider than the aforementioned trench TR and charge-induced layer 220.

[0085] Next, using photolithography and etching techniques, trenches TR are formed between adjacent pixels 100. The trenches TR are formed to extend through the semiconductor substrate 218 from the first surface F1 to the second surface F2.

[0086] Secondly, p-type impurities are implanted into the inner wall of the trench TR in an inclined direction. Alternatively, p-type impurities can be introduced into the inner wall of the trench TR using plasma doping. Furthermore, p-type impurities can be introduced into the inner wall of the trench TR using solid-state diffusion. In this way, a p-type diffusion layer is formed on the sidewall of the trench TR as a charge-induced layer 220.

[0087] Next, an insulating film 301, such as a silicon oxide film, is deposited on the inner wall of the trench TR. Then, a sacrificial film 302, such as polycrystalline silicon, is used to fill the interior of the trench TR. The sacrificial film 302 is a material that can selectively etch the insulating film 301. The trench TR also extends through the central portion of the device separation film 234. Therefore, after the formation of the trench TR, the insulating film 301, and the sacrificial film 302, the trench TR portion of the device separation film 234 is backfilled with a silicon oxide film. This yields the structure shown in FIG. 7. Alternatively, the device separation film 234 can be formed after the formation of the trench TR, the insulating film 301, and the sacrificial film 302. In this case, it is not necessary to backfill the trench TR portion of the device separation film 234 with a silicon oxide film.

[0088] Next, a photodiode 219 and a transistor 250 are formed on the first surface F1. Then, an interlayer insulating film 262 and wiring 261 are formed on the transistor 250. This yields the structure shown in FIG8. During the formation of the transistor 250, source and drain diffusion layers 252 are also formed. The depth of the diffusion layer 252 is shallower than the depth of the element separation film 234.

[0089] (Backend steps) Next, processing steps are performed starting from the second surface F2 of the semiconductor substrate 218.

[0090] The semiconductor substrate 218 is polished from the second surface F2 side using CMP (Chemical Mechanical Polishing) or similar methods to thin the semiconductor substrate 218 to the desired thickness. This yields the structure shown in FIG9.

[0091] Next, as shown in Figure 10, the material of the hard mask 303 (e.g., silicon oxide film) is deposited on the second surface F2. Then, the material of the hard mask 303 is processed by using photolithography and etching techniques to open the area of ​​the trench TR.

[0092] Secondly, as shown in Figure 11, using a hard mask 303 as a mask, the sacrificial film 302 is isotropically etched using CDE (Chemical Dry Etching) and other methods to remove it. At this time, the sidewalls of the trench TR are not etched because they are covered by the insulating film 301.

[0093] Secondly, as shown in Figure 12, the insulating film 301 is removed using the CDE method, and the hard mask 303 on the second surface F2 is also removed.

[0094] Next, as shown in Figure 13, a fixed charge film 232 is deposited on the inner wall of the trench TR. At this time, the fixed charge film 232 is deposited thinly on the inner wall of the trench TR without burying the trench TR. By forming the fixed charge film 232 on the inner wall of the trench TR, a charge (positive charge) is induced in the semiconductor substrate 218 near the inner wall of the trench TR.

[0095] Next, the pixel separation film 233 is filled into the trench TR. This yields the structure shown in Figure 13.

[0096] Next, a light-shielding film 214, a planarization film 213, and a color filter 212 are formed, and then a crystal lens 211 is formed on the color filter 212. Thus, the solid-state imaging element of the first embodiment is completed.

[0097] According to this embodiment, the element separation film 234 is formed along the through trench TR such that the ends of the fixed charge film 232 and the pixel separation film 233 are covered. In this way, the charge induced layer 220 and the diffusion layer 252 can be insulated and separated, and the dark current of the pixel 100 can be suppressed.

[0098] Furthermore, according to this embodiment, in the front-end step, the trench TR is embedded by the insulating film 301 and the sacrificial film 302. The insulating film 301 and the sacrificial film 302 are formed, for example, by a material with high heat resistance such as silicon oxide film or polycrystalline silicon. Therefore, a high-temperature process can be used in the front-end step before forming the transistor 250 and wiring 261 on the first surface F1.

[0099] If a material with low heat resistance, such as a metallic material, is filled into the trench TR in the front-end process, the required high-temperature process cannot be utilized in the front-end process.

[0100] In this embodiment, the trench TR is filled with an insulating film 301 and a sacrificial film 302, which have higher heat resistance than metallic materials, in the front-end step. Therefore, a high-temperature process can be used in the front-end step.

[0101] On the other hand, in the back-end steps, a fixed charge film 232 can be formed on the inner wall of the trench TR. The fixed charge film 232 induces charges in the charge-inducing layer 220 near the inner wall of the trench TR. Thereby, dark current can be suppressed, and random noise of the pixel 100 can be suppressed.

[0102] (Second Implementation) Figure 14 is a cross-sectional view showing an example of the configuration of pixel 100 in the second embodiment. The top view of pixel 100 in the second embodiment is basically the same as that in Figure 6.

[0103] In the second embodiment, a light-shielding film 235 is disposed within the trench TR, inside the pixel separation film 233. When viewed from above the first surface F1, the light-shielding film 235 is disposed along the trench TR and extends in the Z direction between the first surface F1 and the second surface F2. Therefore, the light-shielding film 235 is disposed between adjacent pixels 100, optically separating the pixels 100. This further suppresses crosstalk between the pixels 100.

[0104] The light-shielding film 235 is made of a metallic material with high light-shielding properties. For example, a single metallic material such as tungsten or aluminum can be used for the light-shielding film 235, or a laminated film of aluminum and a barrier metal (such as titanium or cobalt), a laminated film of tungsten and a barrier metal (such as titanium or cobalt), or a laminated film of aluminum and cobalt. Other components of the second embodiment may be the same as those of the first embodiment.

[0105] In the manufacturing method of pixel 100 in the second embodiment, after forming a fixed charge film 232 in the trench TR, a pixel separation film 233 is formed on the fixed charge film 232 in the trench TR. At this time, the material of the pixel separation film 233 is formed on the fixed charge film 232 in a thin layer, and is not completely embedded in the trench TR.

[0106] Next, the material of the light-shielding film 235 is embedded inside the trench TR. In this way, a light-shielding film 235 covered by the pixel separation film 233 is formed in the center of the trench TR.

[0107] The other manufacturing methods of the second embodiment can be the same as the corresponding manufacturing methods of the first embodiment. Thus, the solid-state imaging element of the second embodiment is completed.

[0108] According to the second embodiment, a light-shielding film 235 is formed in the trench TR during the back-end step. Therefore, even if a metal material with low heat resistance is used for the light-shielding film 235, a high-temperature process can be performed in the front-end step. Furthermore, the second embodiment achieves the same effect as the first embodiment.

[0109] (Third Implementation) Figure 15 is a cross-sectional view showing an example of the configuration of pixel 100 in the third embodiment. The top view of pixel 100 in the third embodiment is basically the same as that in Figure 6.

[0110] In the third embodiment, the charge-induced layer 220 is a p-type charge layer induced by the fixed charge film 232, and it does not introduce impurities into the inner wall of the trench TR. If the fixed charge film 232 sufficiently induces a p-type charge layer in the inner wall of the trench TR, then the charge-induced layer 220 is formed even if impurities are not introduced into the area of ​​the charge-induced layer 220. This suppresses dark current. In this case, the step of introducing impurities into the inner wall of the trench TR can be omitted. Other configurations and manufacturing methods of the third embodiment are the same as those of the first embodiment.

[0111] Therefore, according to the third embodiment, the same effect as the first embodiment can be obtained. Furthermore, according to the third embodiment, the manufacturing process can be shortened compared to the first embodiment.

[0112] (Fourth Implementation) Figure 16 is a cross-sectional view showing an example of the configuration of pixel 100 in the fourth embodiment. The fourth embodiment is a combination of the second and third embodiments. Therefore, the pixel 100 in the fourth embodiment further includes a light-shielding film 235 in the trench TR, and does not introduce p-type impurities into the charge-induced layer 220. Other configurations and manufacturing methods of the fourth embodiment can be the same as those of the second or third embodiments. Therefore, the fourth embodiment can have the effects of the second and third embodiments.

[0113] (Fifth Implementation) Figure 17 is a cross-sectional view showing an example of the configuration of pixel 100 in the fifth embodiment. In pixel 100 of the fifth embodiment, the trench TR extends through the element separation film 234 from the first surface F1 and protrudes toward the interlayer insulating film 262. Simultaneously, the ends of the fixed charge film 232 and the pixel separation film 233 on the first surface F1 side extend through the element separation film 234 from the first surface F1 and protrude toward the interlayer insulating film 262.

[0114] Thus, even though the fixed charge film 232 and the pixel separation film 233 pass through the element separation film 234, the element separation film 234 is still disposed on both sides of the fixed charge film 232 and the pixel separation film 233, and is disposed along the groove TR in the first surface F1. The other configurations of the fifth embodiment can be the same as those of the first embodiment. Therefore, the solid-state imaging element of the fifth embodiment can achieve the same effect as that of the first embodiment.

[0115] In the manufacturing method of the solid-state imaging element according to the fifth embodiment, after the steps shown in Figures 7 to 11, in the step shown in Figure 12, the insulating film 301 is removed, and a portion of the element separation film 234 and the interlayer insulating film 262 is etched at the bottom of the trench TR. Thereby, the trench TR is formed to penetrate the element separation film 234 and reach the interlayer insulating film 262. Then, the solid-state imaging element of the fifth embodiment is completed through the steps described with reference to Figure 13.

[0116] (Sixth Implementation) Figure 18 is a cross-sectional view showing an example of the configuration of the pixel 100 in the sixth embodiment. In the pixel 100 of the sixth embodiment, the trench TR extends from the first surface F1 through the element separation film 234 and protrudes toward the interlayer insulating film 262. Accompanying this, the fixed charge film 232, the pixel separation film 233, and the light-shielding film 235 extend from the first surface F1 through the element separation film 234 and protrude toward the interlayer insulating film 262.

[0117] Thus, even though the fixed charge film 232, pixel separation film 233, and light-shielding film 235 pass through the element separation film 234, the element separation film 234 is also disposed on both sides of the fixed charge film 232 and pixel separation film 233, and disposed along the groove TR in the first surface F1. The other configurations of the sixth embodiment can be the same as those of the second embodiment. Therefore, the solid-state imaging element of the sixth embodiment can achieve the same effect as that of the second embodiment.

[0118] The manufacturing method of the solid-state camera element in the sixth embodiment can be easily derived from the manufacturing methods of the second and fifth embodiments, so its description is omitted.

[0119] According to the sixth embodiment, since the light-shielding film 235 also penetrates the element separation film 234 and protrudes toward the interlayer insulating film 262, the light-shielding characteristics between adjacent pixels 100 can be improved, and crosstalk can be further suppressed. (Vehicle-mounted design document)

[0120] The technology disclosed herein (the Technology) can be applied to various products. For example, the Technology disclosed herein can be implemented as a device mounted on any type of mobile body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0121] Figure 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is one example of a mobile body control system to which the technology disclosed herein can be applied.

[0122] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 19, the vehicle control system 12000 includes: a drive system control unit 12010, a vehicle body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, the integrated control unit 12050 is functionally configured as follows: a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0123] The drive system control unit 12010 controls the operation of devices associated with the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a drive force generating device such as an internal combustion engine or drive motor for generating drive force for the vehicle, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating braking force for the vehicle.

[0124] The vehicle system control unit 12020 controls the operation 864 of various devices equipped on the vehicle body according to various programs. For example, the vehicle system control unit 12020 functions as a control device for keyless access systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves emitted from a portable device that replaces the key or signals from various switches can be input to the vehicle system control unit 12020. The vehicle system control unit 12020 accepts such input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0125] The exterior information detection unit 12030 detects information about the exterior of the vehicle equipped with the vehicle control system 12000. For example, a camera unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform object detection processing or distance detection processing, such as detection of people, vehicles, obstacles, signs, or text on the road surface. The solid-state camera element 1 disclosed herein can be equipped in the camera unit 12031.

[0126] The camera unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or as distance measurement information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light. The solid-state imaging element 1 disclosed herein can be the camera unit 12031, or it can be configured as a separate unit from the camera unit 12031.

[0127] The in-vehicle information detection unit 12040 detects information inside the vehicle. A driver status detection unit 12041, for example, detecting the driver's state, is connected to the in-vehicle information detection unit 12040. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, and can also determine whether the driver is drowsy.

[0128] The microcomputer 12051 can calculate the control target values ​​of the drive force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for the purpose of realizing the functions of ADAS (Advanced Driver Assistance System), including collision avoidance or shock mitigation, distance-based following, speed maintenance, collision warning, or lane departure warning.

[0129] Furthermore, the microcomputer 12051 controls the drive force generating device, steering mechanism, or braking device based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby enabling coordinated control for purposes such as autonomous driving that does not rely on the driver's operation.

[0130] Furthermore, the microcomputer 12051 can output control commands to the vehicle system control unit 12020 based on the external information obtained by the external information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control to prevent glare, such as controlling the headlights and switching the high beams to low beams, based on the position of the preceding or oncoming vehicle detected by the external information detection unit 12030.

[0131] The audio-visual output unit 12052 transmits an output signal of at least one of sound and image to an output device that can provide visual or auditory notification information to passengers or outside the vehicle. Examples of output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display 864.

[0132] Figure 20 shows an example of the installation position of the camera unit 12031.

[0133] In Figure 20, the vehicle 12100 has camera units 12101, 12102, 12103, 12104, and 12105 as camera unit 12031.

[0134] Cameras 12101, 12102, 12103, 12104, and 12105 are located, for example, at the front of vehicle 12100, in the rearview mirrors, rear bumper, rear door, and above the windshield inside the passenger compartment. The camera 12101 at the front of the vehicle and the camera 12105 above the windshield inside the passenger compartment primarily acquire images of the front of vehicle 12100. The cameras 12102 and 12103 at the rearview mirrors primarily acquire images of the sides of vehicle 12100. The camera 12104 at the rear bumper or tailgate primarily acquires images of the rear of vehicle 12100. The images acquired by cameras 12101 and 12105 are mainly used for detecting vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lane markings ahead.

[0135] Furthermore, Figure 20 shows an example of the imaging range of camera units 12101 to 12104. Camera range 12111 shows the imaging range of camera unit 12101 located at the front nose of the vehicle; camera ranges 12112 and 12113 show the imaging ranges of camera units 12102 and 12103 located at the rearview mirrors, respectively; and camera range 12114 shows the imaging range of camera unit 12104 located at the rear bumper or tailgate. For example, by overlaying the image data captured by camera units 12101 to 12104, a top-down view of the vehicle 12100 can be obtained.

[0136] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera containing a plurality of camera elements, or a camera element having pixels for phase difference detection.

[0137] For example, the microcomputer 12051, based on distance information obtained from cameras 12101 to 12104, calculates the distances between itself and each three-dimensional object within the camera range 12111 to 12114, and the temporal changes of those distances (relative speed to vehicle 12100). It can then specifically identify the three-dimensional object closest to vehicle 12100's path of travel, and that is traveling in approximately the same direction as vehicle 12100 at a specific speed (e.g., 0 km / h or higher), as the leading vehicle. Furthermore, the microcomputer 12051 can set a pre-defined distance to be maintained for the vehicle ahead, and perform automatic braking control (including stop-and-go control), automatic acceleration control (including start-and-go control), etc. This allows for coordinated control aimed at achieving autonomous driving without driver intervention.

[0138] For example, the microcomputer 12051 can classify and capture three-dimensional object data related to three-dimensional objects based on distance information obtained from cameras 12101 to 12104, categorizing them into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For instance, the microcomputer 12051 identifies obstacles around vehicle 12100 as those visible to the driver and those difficult to see. Furthermore, the microcomputer 12051 determines the collision risk, indicating the degree of danger of colliding with each obstacle. When a collision risk exceeds a set value and a collision is possible, the microcomputer 12051 outputs an alarm to the driver via audio speaker 12061 or display unit 12062, or performs forced deceleration or evasive steering via drive system control unit 12010, thus providing driving support to avoid collisions.

[0139] At least one of the camera units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the captured images of the camera units 12101 to 12104. The pedestrian identification is performed by, for example, extracting the sequence of feature points from the captured images of the camera units 12101 to 12104, which are infrared cameras, and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian sequence. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the camera units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to overlay and display a square outline for emphasis on the identified pedestrian. Furthermore, the audio-visual output unit 12052 can also control the display unit 12062 to display pedestrian icons and the like at the desired location.

[0140] The above describes an example of a vehicle control system to which the technology disclosed herein can be applied. The solid-state camera element disclosed herein can be applied to, for example, the camera unit 12031 in the configuration described above. Thereby, the camera unit 12031 can obtain the effects of the above-described embodiment.

[0141] Furthermore, this technology can be configured as follows. (1) A solid-state camera element, comprising: substrate; A plurality of photoelectric conversion units are disposed within the aforementioned substrate; The first insulating film is disposed between adjacent photoelectric conversion units in the aforementioned plurality of photoelectric conversion units, and is disposed on the inner wall of a trench that penetrates between the first surface of the aforementioned substrate and the second surface opposite to the first surface, and has a fixed charge; The second insulating film is disposed within the aforementioned trench, inside the aforementioned first insulating film; At least one transistor is disposed on the first surface of the aforementioned substrate; and The third insulating film, when viewed from the aforementioned first surface, is disposed along both sides of the aforementioned trench or on the trench. (2) As in (1), the solid-state imaging element, wherein the aforementioned third insulating film is disposed between the charge-induced layer formed on the surface of the aforementioned substrate adjacent to the aforementioned first insulating film and the source or drain of the aforementioned transistor. (3) As in the solid-state imaging element of (2), the aforementioned charge-induced layer is a high-concentration charge layer of the first conductivity type; and The source or drain of the aforementioned transistor is a high-concentration impurity diffusion layer of the second conductivity type. (4) Such as (2) or (3) solid-state imaging element, wherein the aforementioned charge-induced layer is a first conductive impurity diffusion layer. (5) A solid-state imaging element, such as any one of (1) to (4), wherein the aforementioned third insulating film covers the ends of the aforementioned first and second insulating films on the aforementioned first surface side. (6) For example, in any one of (1) to (4), the end of the first and second insulating films on the first surface of the first insulating film passes through the third insulating film. (7) The solid-state imaging element of any one of (1) to (6) further comprises: A wiring layer, disposed on the aforementioned first surface of the substrate and electrically connected to the aforementioned transistor; and A lens is disposed on the aforementioned second surface of the substrate. (8) The solid-state imaging element of any one of (1) to (7) further comprises a light-shielding film disposed inside the aforementioned second insulating film within the aforementioned trench. (9) A solid-state imaging element, such as any one of (1) to (8), wherein when the substrate is viewed from a direction perpendicular to the first surface, the third insulating film overlaps with the first and second insulating films. (10) For any of (1) to (8) solid-state imaging elements, when the substrate is viewed from a direction substantially perpendicular to the first surface, the width of the third insulating film is greater than the width of the trench. (11) For any of (2) to (4) solid-state imaging elements, when the substrate is viewed from a direction substantially perpendicular to the first surface, the width of the third insulating film is greater than the width of the charge-induced layer located on both sides of the trench. (12) For any of (1) to (11) solid-state imaging elements, the depth of the aforementioned third insulating film from the aforementioned first surface is deeper than the depth of the diffusion layer of the aforementioned transistor adjacent to the aforementioned third insulating film. (13) A method for manufacturing a solid-state camera element, comprising: A plurality of photoelectric conversion units are formed within the substrate; On the first surface of the aforementioned substrate, a third insulating film is formed between adjacent photoelectric conversion units among the aforementioned plurality of photoelectric conversion units; A trench is formed between the aforementioned adjacent plurality of photoelectric conversion units, connecting the first surface of the aforementioned substrate to the second surface opposite to the first surface; A first insulating film with a fixed charge is formed on the inner wall of the aforementioned trench; A second insulating film is formed inside the aforementioned first insulating film within the aforementioned trench; and At least one transistor is formed on the first surface of the aforementioned substrate. (14) The method of (13) further includes: introducing a first type of conductive impurity into the inner wall of the aforementioned trench to form a charge-induced layer on the inner wall of the trench. (15) The method is as in (13) or (14), wherein the aforementioned trench penetrates the aforementioned third insulating film.

[0142] Furthermore, this disclosure is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention. Also, the effects described in this specification are ultimately illustrative and not limiting; other effects may be possible.

[0143] 10: Camera device 11: Lens Group 12: Camera element 13: DSP Circuit 14: Frame Memory 15: Display Section 16: Recording Department 17: Operating System 18: Power System 19: Busbar 41: Pixel array section 42: Vertical drive unit 43: Line Processing Department 44: Horizontal drive unit 45: System Control Department 46: Pixel drive line 48: Signal Processing Department 49: Data Storage Department 100 pixels 112: Transmission Transcript (TG) / Transistor 113: Transmission Transcript (TG) / Transistor 114: Amplifying Transistor (AMP) / Transistor 115: Select Transistor (SEL) / Transistor 211: Optical Crystal Lens (OCL) 212: Color Filter 213: Planarization film 214:Light-shielding film 218: Semiconductor substrate 219: Photodiode (PD) 220: Charge-induced layer 232: Fixed charge film 233: Component separation membrane 234: Component separation membrane 235:Light-shielding film 250: Transistor 251: Gate 252: Diffusion layer 261: Wiring 262: Interlayer insulating film 301: Insulating film 302: Sacrificial membrane 303: Hard Mask 12000: Vehicle Control System 12001: Communication Network 12010: Drive system control unit 12020: Vehicle Body System Control Unit 12030: Exterior Information Detection Unit 12040: In-vehicle information detection unit 12041: Driver Status Monitoring Department 12050: Integrated Control Unit 12051: Microcomputer 12052: Audio and Image Output Unit 12053: In-vehicle network I / F 12061: Audio Speaker 12062: Display Unit 12063: Dashboard 12100: Vehicles 12101, 12102, 12103, 12104, 12105: Camera Department 12111, 12112, 12113, 12114: Camera range AA: Valid area D234, D252: Depth (Thickness) F1: First side (front) F2: Second side (back side) FD: Floating Diffusion Section TR: Ditch VDD: Power supply / source follower power supply voltage VSL: Vertical Signal Line W220, W234, Wtr: Width X, Z: Direction

Claims

1. A solid-state imaging element comprising: a substrate; a plurality of photoelectric conversion units disposed within the substrate; a first insulating film disposed between adjacent photoelectric conversion units and disposed on the inner wall of a trench penetrating between a first surface of the substrate and a second surface opposite to the first surface, and having a fixed charge; a second insulating film disposed within the trench and inside the first insulating film; at least one transistor disposed on the first surface of the substrate; and a third insulating film disposed along both sides of or on the trench when viewed from the first surface; wherein the ends of the first and second insulating films on the first surface penetrate the third insulating film.

2. The solid-state imaging element of claim 1, wherein the aforementioned third insulating film is disposed between a charge-induced layer formed on the surface of the aforementioned substrate adjacent to the aforementioned first insulating film and the source or drain of the aforementioned transistor.

3. The solid-state imaging element of claim 2, wherein the aforementioned charge-induced layer is a high-concentration charge layer of a first conductivity type; and the source or drain of the aforementioned transistor is a high-concentration impurity diffusion layer of a second conductivity type.

4. The solid-state imaging element of claim 2, wherein the aforementioned charge-induced layer is a first conductive impurity diffusion layer.

5. The solid-state imaging element of claim 1, wherein the aforementioned third insulating film covers the ends of the aforementioned first and second insulating films on the aforementioned first surface side.

6. The solid-state imaging element of claim 1 further comprises: a wiring layer disposed on the first surface of the aforementioned substrate and electrically connected to the aforementioned transistor; and a lens disposed on the second surface of the aforementioned substrate.

7. The solid-state camera element of claim 1 further comprises a light-shielding film disposed within the aforementioned trench inside the aforementioned second insulating film.

8. The solid-state imaging element of claim 1, wherein when the substrate is viewed from a direction perpendicular to the first surface, the third insulating film overlaps with the first and second insulating films.

9. The solid-state imaging element of claim 1, wherein when the substrate is viewed from a direction substantially perpendicular to the first surface, the width of the third insulating film is greater than the width of the trench.

10. The solid-state imaging element of claim 2, wherein when the substrate is viewed from a direction substantially perpendicular to the first surface, the width of the third insulating film is greater than the width of the charge-induced layer located on both sides of the trench.

11. The solid-state imaging element of claim 1, wherein the depth of the aforementioned third insulating film from the aforementioned first surface is greater than the depth of the diffusion layer of the aforementioned transistor adjacent to the aforementioned third insulating film.

12. A method for manufacturing a solid-state imaging element, comprising: forming a plurality of photoelectric conversion portions in a substrate; forming a third insulating film on a first surface of the substrate between adjacent photoelectric conversion portions; forming a trench between the adjacent plurality of photoelectric conversion portions, extending between the first surface of the substrate and a second surface opposite to the first surface; forming a first insulating film having a fixed charge on the inner wall of the trench; forming a second insulating film inside the first insulating film in the trench; and forming at least one transistor on the first surface of the substrate.

13. The method of claim 12, further comprising: introducing a first type of conductive impurity into the inner wall of the aforementioned trench to form a charge-induced layer on the inner wall of the trench.

14. The method of claim 12, wherein the aforementioned trench penetrates the aforementioned third insulating film.

Images