Semiconductor device

Abstract

A semiconductor device includes a memory bank and a row line selection circuit. The memory bank includes a first memory block, a second memory block, and a redundant memory block. The row line selection circuit is configured to replace the first row line of the first memory block with a first redundant line of the redundant memory block when a fault occurs in the first row line of the first memory block, and to replace the second row line of the second memory block with a second redundant line of the redundant memory block.

Description

[Technical Field]

[0001] Embodiments of this disclosure relate to semiconductor devices, and more specifically, to semiconductor devices associated with performing test operations before or after a repair operation. [Previous Technology]

[0002] A semiconductor device performs a repair operation that replaces a defective memory cell (hereinafter referred to as a "faulty cell") with a redundant cell. The repair operation of the semiconductor device includes column repair operations and row repair operations. A column repair operation is performed such that, when a faulty cell exists in a memory cell connected to a column line (e.g., a word line) selected based on column address, a redundant column line is used to replace the column line connected to the faulty cell. A row repair operation is performed such that, when a faulty cell exists in a memory cell connected to a row line (e.g., a bit line) selected based on row address, a redundant row line is used to replace the row line connected to the faulty cell. [Summary of the Invention]

[0003] This application claims priority to Korean Patent Application No. 10-2021-0080445, filed on June 21, 2021, the entire contents of which are incorporated herein by reference.

[0004] According to embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device may include: a memory bank including a first memory block, a second memory block, and a redundant memory block; a row line selection circuit configured to, when a fault occurs in a first row line of the first memory block, replace the first row line of the first memory block with a first redundant line of the redundant memory block, and replace the second row line of the second memory block with a second redundant line of the redundant memory block.

[0005] Additionally, according to another embodiment of this disclosure, a semiconductor device is provided. The semiconductor device may include: a test row address generator configured to generate a first test row address and a second test row address based on row addresses; and core circuitry configured to control a first repair operation for a first memory block array and a second repair operation for a second memory block array to be performed together based on block array addresses, block addresses, and row addresses, selecting one of the row lines included in each memory block in the first memory block array based on the first test row address to output first memory block data, and selecting one of the row lines included in each memory block in the second memory block array based on the second test row address to output second memory block data.

[0006] In addition, according to another embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device may include: core circuitry configured to: control a first repair operation on a first memory block array and a second repair operation on a second memory block array to be performed together based on block array addresses, block addresses, and row addresses; select, based on a first test row address, one of the row lines of each memory block in the first memory block array to output first memory block data; select, based on a second test row address, one of the row lines of each memory block in the second memory block array to output second memory block data; and output redundant memory block data when a repair operation is performed on the first memory block array based on the first test row address or on the second memory block array based on the second test row address; input and output (input / output) control circuitry configured to generate first driving data and second driving data from the first memory block data, the second memory block data, and the redundant memory block data based on a first shift signal and a second shift signal; and a test data generator configured to compare the first driving data with first reference data to generate a first comparison signal, compare the second driving data with second reference data to generate a second comparison signal, and compress the first comparison signal and the second comparison signal to generate test data.

Implementation Method

[0008] In the following description of embodiments, when a parameter is referred to as “predetermined,” it may be intended to mean that the value of the parameter is predetermined when it is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or it may be set during the execution of the process or algorithm.

[0009] It should be understood that although the terms “first,” “second,” “third,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and are not intended to imply the order or number of elements. Therefore, without departing from the teachings of this disclosure, a first element in some embodiments may be referred to as a second element in other embodiments.

[0010] Furthermore, it should be understood that when an element is referred to as “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, there are no intermediate elements.

[0011] Logic "high" and logic "low" levels can be used to describe the logic levels of an electrical signal. Signals with a logic "high" level can be distinguished from signals with a logic "low" level. For example, when a signal with a first voltage corresponds to a signal with a logic "high" level, a signal with a second voltage corresponds to a signal with a logic "low" level. In one embodiment, a logic "high" level can be set to a voltage level higher than a logic "low" level. Furthermore, according to embodiments, the logic levels of signals can be set to different or opposite levels. For example, a signal with a logic "high" level in one embodiment can be set to a logic "low" level in another embodiment.

[0012] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0013] FIG1 is a block diagram illustrating the configuration of a semiconductor device 1 according to an embodiment of the present disclosure. As shown in FIG1, the semiconductor device 1 may include: an address decoder 10, a core circuit 11, a test row address generator 13, a shift control circuit 15, an input / output (I / O) control circuit 17, a reference data (REFD) register 18, and a test data generator 19.

[0014] The address decoder 10 can receive the address ADD from an external device (not shown) of the semiconductor device 1. The external device of the semiconductor device 1 can be one of a semiconductor controller, a host, and a test device. The address decoder 10 can decode the address ADD to generate a block array address BRADD, a block address BADD, and a row address CADD. The block array address BRADD can be configured to have logical bits for selecting one of the first memory block array (121 in FIG. 2) and the second memory block array (123 in FIG. 2) included in the memory group (101 in FIG. 2). The block address BADD can be configured to have a set of logical bits for selecting one of the memory blocks (MBs in FIG. 2) included in the selected memory block array. The number of bits included in the block address BADD can be set according to the number of memory blocks MBs included in the first memory block array 121 and the second memory block array 123. For example, when the number of memory blocks MBs included in each of the first memory block array 121 and the second memory block array 123 is 16, the block address BADD can be implemented to include 4 bits. The row address CADD may include bits representing a set of logical bits used to select one of the row lines YL of the memory block MB selected by the block address BADD. The number of bits included in the row address CADD can be set according to the number of row lines YL included in the memory block MB. For example, when the number of row lines YL included in the memory block MB is 64, the row address CADD can be implemented as 6 bits.

[0015] The core circuit 11 can receive block array address BRADD, block address BADD, and row address CADD from the address decoder 10. The core circuit 11 can receive a first test row address TCAD1 and a second test row address TCAD2 from the test row address generator 13. The first test row address TCAD1 and the second test row address TCAD2 can be generated based on the row address CADD to perform a pre-test for checking for faults that need to be repaired and a post-test for checking whether the repair operation was performed correctly. The core circuit 11 can receive a first test mode signal TM1 for performing the pre-test and a second test mode signal TM2 for performing the post-test. The first test mode signal TM1 and the second test mode signal TM2 can be generated by decoding commands (not shown) inside the semiconductor device 1, or can be received from an external device (not shown) of the semiconductor device 1. The core circuit 11 may include: a memory group 101, a row line selection circuit 103, and a fuse latch circuit 105. In this embodiment, for ease of explanation, the core circuit 11 is implemented as including a memory group 101, but according to the embodiment, it can also be implemented as including multiple memory groups.

[0016] Memory group 101 can be connected to multiple row lines YL and multiple redundant row lines RYL. As shown in FIG2, memory group 101 may include a first memory block array 121 and a second memory block array 123, which includes memory blocks MB connected to multiple row lines YL. Memory group 101 may include redundant memory blocks (RED MB) (125 in FIG2) connected to multiple redundant row lines RYL.

[0017] The row line selection circuit 103 can select one of the first memory block array 121 and the second memory block array 123 based on the block array address BRADD, and can select one of the memory blocks MB based on the block address BADD. The row line selection circuit 103 can select one of the row lines YL of the memory block MB based on the row address CADD. The row line selection circuit 103 can control at least one memory cell (not shown) connected to the row line YL of the memory block selected based on the block array address BRADD, the block address BADD, and the row address CADD. In the following, it is assumed and explained that a fault in the row line YL of the memory block MB selected based on the block array address BRADD, the block address BADD, and the row address CADD means that the memory cell connected to the row line YL of the memory block MB selected based on the block array address BRADD, the block address BADD, and the row address CADD includes a faulty cell.

[0018] Row line selection circuit 103 can receive redundant fuse data RFD and normal fuse data NFD from fuse latch circuit 105. Row line selection circuit 103 can control memory group 101 to simultaneously perform repair operations on row lines YL of multiple memory blocks MB based on redundant fuse data RFD. Row lines YL of each of the multiple memory blocks MB for which repair operations are performed simultaneously can be selected based on block array address BRADD, block address BADD, and row address CADD. Row line selection circuit 103 can control memory group 101 to perform repair operations on row lines YL of memory blocks MB selected by block array address BRADD, block address BADD, and row address CADD based on normal fuse data NFD. As used herein, the terms "simultaneous" and "at the same time" regarding a process or operation mean that the process or operation occurs over overlapping time intervals. For example, if a first process or operation occurs within a first time interval and a second process or operation occurs simultaneously within a second time interval, then the first time interval and the second time interval at least partially overlap, resulting in a time when the first process or operation and the second process or operation occur simultaneously.

[0019] When the row line selection circuit 103 receives the first test mode signal TM1, it outputs the data of a memory cell selected by the first test row address TCAD1 and connected to one of the row lines YL of the memory block MB included in the first memory block array 121 via the first local line LIO1 as first memory block data, thereby performing a pre-test to check for faulty cells that need to be repaired. Furthermore, when the row line selection circuit 103 receives the first test mode signal TM1, it outputs the data of a memory cell selected by the second test row address TCAD2 and connected to another of the row lines YL of the memory block MB included in the second memory block array 123 via the second local line LIO2 as second memory block data MBD2. In the pre-test, the first test row address TCAD1 and the second test row address TCAD2 can be set to have different sets of logic bits to select row lines YL to be repaired together.

[0020] When the row line selection circuit 103 receives the second test mode signal TM2, it outputs the data of a memory cell connected to a row line YL of a memory block MB included in the first memory block array 121, selected by the first test row address TCAD1, as first memory block data MBD1 via the first local line LIO1, thereby performing a post-test to check whether the repair operation has been performed correctly. Furthermore, when the row line selection circuit 103 receives the second test mode signal TM2, it outputs the data of a memory cell connected to a row line YL of a memory block MB included in the second memory block array 123, selected by the second test row address TCAD2, as second memory block data MBD2 via the second local line LIO2. In the post-test, the first test row address TCAD1 and the second test row address TCAD2 can be set to have the same set of logic bits to select the same row line YL. When the second test mode signal TM2 is received and one of the redundant row lines RYL is used to replace one of the row lines YL of the memory block MB included in the first memory block array 121 selected by the first test row address TCAD1, the row line selection circuit 103 can output the data of the redundant memory cell connected to one of the redundant row lines RYL as redundant memory block data RMBD via the redundant local line RLIO. On the other hand, when the second test mode signal TM2 is received and another redundant row line RYL is used to replace one of the row lines YL of the memory block MB included in the second memory block array 123 selected by the second test row address TCAD2, the row line selection circuit 103 can output the data of the redundant memory cell connected to the other redundant row line RYL as redundant memory block data RMBD via the redundant local line RLIO.

[0021] The fuse latch circuit 105 can store redundant fuse data RFD for controlling the simultaneous execution of repair operations on row lines YL of each of a plurality of memory blocks MB selected based on block array address BRADD, block address BADD, and row address CADD. The fuse latch circuit 105 can store normal fuse data NFD for controlling the repair operation, wherein another row line YL is used to replace one of the row lines YL included in one of the memory blocks MB selected based on block array address BRADD, block address BADD, and row address CADD. The fuse latch circuit 105 can apply the redundant fuse data RFD and normal fuse data NFD stored therein to the row line selection circuit 103.

[0022] The test row address generator 13 can receive row address CAD from the address decoder 10, and can also receive a first test mode signal TM1 and a second test mode signal TM2. The test row address generator 13 can generate a first test row address TCAD1 and a second test row address TCAD2 from the row address CAD based on the first test mode signal TM1 and the second test mode signal TM2. When the first test mode signal TM1 is received to perform a pre-test, the test row address generator 13 can buffer the row address CAD to generate the first test row address TCAD1, and can generate the second test row address TCAD2 by buffering the row address CAD (wherein at least one bit included in the bits of the row address CAD is buffered by inversion). One of the row lines YL selected by the first test row address TCAD1 and the other of the row lines YL selected by the second test row address TCAD2 generated during the pre-test can be configured to be repaired together after the pre-test. When the second test mode signal TM2 is received to perform the post-test, the test row address generator 13 can buffer the row address CADD to generate the first test row address TCAD1 and the second test row address TCAD2.

[0023] The shift control circuit 15 can receive redundant fuse data RFD from the fuse latch circuit 105. The shift control circuit 15 can generate a first shift signal SFT1 and a second shift signal SFT2 based on the redundant fuse data RFD. When no repair operation is performed, the shift control circuit 15 can generate a first shift signal SFT1 and a second shift signal SFT2, both of which are deactivated, based on the redundant fuse data RFD. When a memory block MB included in the first memory block array 121 contains a faulty cell and the faulty cell is repaired, the shift control circuit 15 can generate an activated first shift signal SFT1 and a deactivated second shift signal SFT2 based on the redundant fuse data RFD. When a memory block MB included in the second memory block array 123 contains a faulty cell and the faulty cell is repaired, the shift control circuit 15 can generate a deactivated first shift signal SFT1 and an activated second shift signal SFT2 based on the redundant fuse data RFD.

[0024] The input / output control circuit 17 can receive first memory block data MBD1, second memory block data MBD2, and redundant memory block data RMBD from the core circuit 11. The input / output control circuit 17 can receive first shift signal SFT1 and second shift signal SFT2 from the shift control circuit 15. When the first shift signal SFT1 is received, the input / output control circuit 17 can drive first drive data DRD1 from the first memory block data MBD1 received via the first local line LIO1, and output the first drive data DRD1 via the first global line GIL1. When the second shift signal SFT2 is received, the input / output control circuit 17 can drive second drive data DRD2 from the second memory block data MBD2 received via the second local line LIO2, and output the second drive data DRD2 via the second global line GIL2. When a memory block MB included in the first memory block array 121 includes a faulty cell and receives a first shift signal SFT1 to initiate a shift, the input / output control circuit 17 can sequentially shift a portion of the first memory block data MBD1 received via the first local line LIO1 and the redundant memory block data RMBD received via the redundant local line RLIO, drive the first drive data DRD1 from the shifted redundant memory block data RMBD and the portion of the first memory block data MBD1, and output the first drive data DRD1 via the first global line GIO1. When a memory block MB included in the second memory block array 123 includes a faulty cell and receives a second shift signal SFT2 to initiate a shift, the input / output control circuit 17 can sequentially shift the redundant memory block data RMBD received via the redundant local line RLIO and a portion of the second memory block data MBD2 received via the second local line LIO2, drive the second drive data DRD2 from the shifted redundant memory block data RMBD and the portion of the second memory block data MBD2, and output the second drive data DRD2 via the second global line GIO2.

[0025] The reference data register 18 can store first reference data REFD1 and second reference data REFD2 based on the first test mode signal TM1 and the second test mode signal TM2, and apply the stored first reference data REFD1 and second reference data REFD2 to the test data generator 19. When the first test mode signal TM1 for pre-test initiation is received, the reference data register 18 can store the first reference data REFD1, which is set to have the same set of logical bits as the first drive data DRD1 generated when no fault cell is present in the first memory block array 121, and apply the stored first reference data REFD1 to the test data generator 19. Furthermore, when the first test mode signal TM1 for pre-test initiation is received, the reference data register 18 can store the second reference data REFD2, which is set to have the same set of logical bits as the second drive data DRD2 generated when no fault cell is present in the second memory block array 123, and apply the stored second reference data REFD2 to the test data generator 19. On the other hand, when the second test mode signal TM2 for initiating post-testing is received, the reference data register 18 can store first reference data REFD1, which is configured to have the same set of logical bits as the first drive data DRD1 generated when the first memory block array 121 does not contain a faulty cell or when a faulty cell included in the first memory block array 121 is repaired, and the stored first reference data REFD1 is applied to the test data generator 19. Furthermore, when the second test mode signal TM2 for initiating post-testing is received, the reference data register 18 can store second reference data REFD2, which is configured to have the same set of logical bits as the second drive data DRD2 generated when the second memory block array 123 does not contain a faulty cell or when a faulty cell included in the second memory block array 123 is repaired, and the stored second reference data REFD2 is applied to the test data generator 19. The first reference data REFD1 and the second reference data REFD2 can be stored in the reference data register 18 through a mode register group. First reference data REFD1 and second reference data REFD2, which have different sets of logical bits, can be stored in reference data register 18 before performing pre-test or post-test.

[0026] The test data generator 19 can receive first drive data DRD1 and second drive data DRD2 from the input / output control circuit 17. The test data generator 19 can receive first reference data REFD1 and second reference data REFD2 from the reference data register 18. The test data generator 19 can generate test data TDQ from the first drive data DRD1, the second drive data DRD2, the first reference data REFD1, and the second reference data REFD2. When performing pre-tests or post-tests, the test data generator 19 can compare the first drive data DRD1 with the first reference data REFD1, compare the second drive data DRD2 with the second reference data REFD2, and compress the comparison results to generate the test data TDQ. The test data TDQ can be set to have a set of logical bits set according to information from the memory block MB including the faulty cell. Because the test data TDQ is generated by compressing the comparison results between the first drive data DRD1 and the first reference data REFD1 and the comparison results between the second drive data DRD2 and the second reference data REFD2, the test time required to perform pre-tests and post-tests can be reduced. The test data TDQ can be applied to external devices of semiconductor device 1.

[0027] FIG2 is a block diagram illustrating the configuration of the memory group 101 and the row selection circuit 103 included in the semiconductor device 1 shown in FIG1.

[0028] As shown in Figure 2, memory group 101 may include: a first memory block array 121, a second memory block array 123, and redundant memory blocks 125. One of the first memory block array 121 and the second memory block array 123 can be selected based on the block array address BRADD. As an example, the first memory block array 121 can be selected when the block array address BRADD is set to a logical "low" level bit, and the second memory block array 123 can be selected when the block array address BRADD is selected to a logical "high" level bit. Each of the first memory block array 121 and the second memory block array 123 may include multiple memory blocks MB. One of the memory blocks MB included in the first memory block array 121 and the second memory block array 123 can be selected based on the block address BADD. As an example, the Kth memory block MB included in each of the first memory block array 121 and the second memory block array 123 can be selected when the block address BADD is set to the Kth logical bit set. One row line YL of each memory block MB can be selected based on the row address CADD. When the row address CADD is set to the Lth logical bit set, the Lth row line YL of the memory block MB can be selected. Here, each of "K" and "L" can be set to a natural number. Each memory block MB may include multiple memory cells connected to each row line YL. When one row line YL is selected based on the block array address BRADD, the block address BADD, and the row address CADD, at least one memory cell connected to the row line YL can be accessed. Redundant memory block 125 may include multiple redundant row lines RYL. Redundant memory block 125 may include multiple redundant cells (not shown) respectively connected to the multiple redundant row lines RYL. At least one of the redundant cells included in redundant memory block 125 can be connected to and accessed from one of the redundant row lines RYL selected when a repair operation is performed based on the redundant fuse data RFD. To access a memory cell included in memory block MB or a redundant cell included in redundant memory block 125, a column line (e.g., a character line) should be selected based on the column address (not shown) before selecting a row line YL. However, for the sake of simplicity, a detailed description of the column line selection operation will be omitted. In the following, it is assumed and explained that the column line selection operation is performed first when a row line YL is selected and a memory cell is accessed.

[0029] As shown in Figure 2, the row line selection circuit 103 can receive block array address BRADD, block address BADD, row address CADD, redundant fuse data RFD, and normal fuse data NFD. The row line selection circuit 103 may include multiple row decoders CDEC. Each of the multiple row decoders CDEC may correspond to each of the memory block MB and redundant memory block 125 included in the first memory block array 121 and the second memory block array 123. When a repair operation is performed based on the redundant fuse data RFD, the multiple row decoders CDEC can decode the block array address BRADD, block address BADD, and row address CADD to replace at least one of the row lines YL of the selected memory block MB with at least one of the redundant row lines RYL of the redundant memory block 125. When a repair operation is performed based on normal fuse data NFD, multiple row decoders CDEC can decode block array address BRADD, block address BADD, and row address CADD to replace at least one of the row lines YL of the selected memory block MB with another redundant row line RYL of redundant memory block 125.

[0030] FIG3 is a block diagram illustrating the configuration of an example of memory block MB according to FIG2, and FIG4 is a block diagram illustrating the configuration of an example of redundant memory block 125 according to FIG2.

[0031] As shown in Figures 3 and 4, each memory block MB included in the first memory block array 121 and the second memory block array 123 may include a first row line set (1st YL SET) YL<1:32> and a second row line set (2nd YL SET) YL<33:64>, and the redundant memory block 125 may include a first redundant row line set (1st RYL SET) RYL<1:32> and a second redundant row line set (2nd RYL SET) RYL<33:64>. The first row line set YL<1:32> may include the first row line YL<1> to the thirty-second row line YL<32>, and the second row line set YL<33:64> may include the thirty-third row line YL<33> to the sixty-fourth row line YL<64>. The first set of redundant line lines RYL<1:32> may include the first redundant line line RYL<1> to the thirty-second redundant line line RYL<32>, and the second set of redundant line lines RYL<33:64> may include the thirty-third redundant line line RYL<33> to the sixty-fourth redundant line line RYL<64>.

[0032] FIG5 is a block diagram illustrating the configuration of a fuse latch circuit 105A according to an example of a fuse latch circuit 105 included in the semiconductor device shown in FIG1. ​​As shown in FIG5, the fuse latch circuit 105A may include a redundant fuse latch circuit 131 and a normal fuse latch circuit 133. Hereinafter, it is assumed and explained that each of the first memory block array 121 and the second memory block array 123 shown in FIG2 includes 16 memory blocks MB, each memory block MB includes a first row line set YL<1:32> and a second row line set YL<33:64>, as shown in FIG3 and FIG4, and the redundant memory block 125 includes a first redundant row line set RYL<1:32> and a second redundant row line set RYL<33:64>.

[0033] The redundant fuse latch circuit 131 may include a plurality of redundant fuse latches 131_1 to 131_32 to output redundant fuse data RFD. As used herein, the tilde “~” indicates a component range. For example, “131_1 to 131_32” refers to the redundant fuse latches 131_1, 131_2, ... and 131_32 shown in FIG. 5. Each of the redundant fuse latches 131_1 to 131_32 may correspond to a row line YL included in each memory block MB included in the first memory block array 121 and a row line YL included in each memory block MB included in the second memory block array 123. Each of the redundant fuse latches 131_1 to 131_32 included in the redundant fuse latch circuit 131 may store information about the row line YL and information about the memory block MB in which a fault has occurred for repair operations, and output the stored information as redundant fuse data RFD. For example, when a fault occurs in the first row line YL<1> of the first memory block MB included in the first memory block array 121, the first redundant fuse latch 131_1 can store information about the first memory block MB and the first row line YL<1> included in the first memory block array 121. As another example, when a fault occurs in the third row line YL<3> of the second memory block MB included in the second memory block array 123, the third redundant fuse latch 131_3 can store information about the second memory block MB and the third row line YL<3> included in the second memory block array 123. Each of the redundant fuse latches 131_1 to 131_32 can include multiple redundant fuses (not shown), and the set of logical bits of the redundant fuse data RFD output from the redundant fuse latch circuit 131 can be set according to whether the multiple redundant fuses are tripped. Based on the set of logical bits of the redundant fuse data RFD, information about the faulty memory block MB and row line YL can be extracted for repair operations.

[0034] As shown in Figures 5 and 6, the first redundant fuse latch 131_1 included in the fuse latch circuit 105 can correspond to the first row line YL<1> of each memory block MB included in the first memory block array 121 and the thirty-third row line YL<33> of each memory block MB included in the second memory block array 123. The second redundant fuse latch 131_2 included in the fuse latch circuit 105 can correspond to the second row line YL<2> of each memory block MB included in the first memory block array 121 and the thirty-fourth row line YL<34> of each memory block MB included in the second memory block array 123. The thirty-second redundant fuse latch 131_32 included in the fuse latch circuit 105 can correspond to the thirty-second row line YL<32> of each memory block MB included in the first memory block array 121 and the sixty-fourth row line YL<64> of each memory block MB included in the second memory block array 123. Since each of the redundant fuse latches 131_1 to 131_32 included in the redundant fuse latch circuit 131 corresponds to the plurality of row lines, the number of redundant fuse latches 131_1 to 131_32 required for repair operations can be reduced, thereby reducing the layout area of ​​the redundant fuse latch circuit 131.

[0035] As an example, a repair operation based on the redundant fuse data RFD output from the redundant fuse latch circuit 131 shown in FIG. 5 will be described. For example, when a fault occurs in a row line of the first row line set YL<1:32> of the memory block MB included in the first memory block array 121, the following repair operation is performed based on the redundant fuse data RFD: a row line of the first redundant row line set YL<1:32> of the redundant memory block 125 is used to replace a row line of the first redundant row line set YL<1:32> of the memory block MB included in the first memory block array 121; a row line of the second redundant row line set YL<33:64> of the redundant memory block 125 is used to replace a row line of the second redundant row line set YL<33:64> of the memory block MB included in the second memory block array 123. As another example, when a fault occurs in a row line of the second row line set YL<33:64> of the memory block MB included in the first memory block array 121, the following repair operations are performed together with the redundant fuse data RFD: a row line of the first redundant row line set RYL<1:32> of the redundant memory block 125 is used to replace a row line of the second row line set YL<33:64> of the memory block MB included in the first memory block array 121; a row line of the second redundant row line set RYL<33:64> of the redundant memory block 125 is used to replace a row line of the first row line set YL<1:32> of the memory block MB included in the second memory block array 123. As another example, when a fault occurs in a row line of the first row line set YL<1:32> of the memory block MB included in the second memory block array 123, the following repair operation is performed based on the redundant fuse data RFD: a row line of the second redundant row line set RYL<33:64> of the redundant memory block 125 is used to replace a row line of the first row line set YL<1:32> of the memory block MB included in the second memory block array 123; a row line of the first redundant row line set RYL<1:32> of the redundant memory block 125 is used to replace a row line of the second row line set YL<33:64> of the memory block MB included in the first memory block array 121. As another example, when a fault occurs in a row line of the second row line set YL<33:64> of the memory block MB included in the second memory block array 123, the following repair operation is performed based on the redundant fuse data RFD: a row line of the second row line set YL<33:64> of the redundant memory block 125 is used to replace a row line of the second row line set YL<33:64> of the memory block MB included in the second memory block array 123; a row line of the first row line set YL<1:32> of the redundant memory block 125 is used to replace a row line of the first row line set YL<1:32> of the memory block MB included in the first memory block array 121.The repair operation performed based on redundant fuse data RFD will be described below with reference to Figures 6 to 11.

[0036] As shown in Figures 6 and 7, the following repair operation is performed based on the redundant fuse data RFD output from the first redundant fuse latch 131_1: the first redundant row line RYL<1> of the redundant memory block 125 is used to replace the first row line YL<1> of the memory block (MB IN 121) included in the faulty first memory block array; the thirty-third redundant row line RYL<33> of the redundant memory block 125 is used to replace the thirty-third row line YL<33> of the memory block (MB IN 123) included in the second memory block array. Furthermore, based on the redundant fuse data RFD output from the second redundant fuse latch 131_2, the following repair operations are performed: the second redundant row line RYL<2> of the redundant memory block 125 is replaced with the second redundant row line RYL<2> of the memory block (MB IN 121) included in the faulty first memory block array; the thirty-fourth redundant row line RYL<34> of the redundant memory block 125 is replaced with the thirty-fourth row line RYL<34> of the memory block (MB IN 123) included in the second memory block array.

[0037] As shown in Figures 6 and 8, the following repair operation is performed based on the redundant fuse data RFD output from the thirty-two redundant fuse latches 131_32: the thirty-second redundant row line RYL<32> of the redundant memory block 125 is used to replace the thirty-second row line YL<32> of the memory block (MB IN 121) included in the faulty first memory block array; the sixty-fourth redundant row line RYL<64> of the redundant memory block 125 is used to replace the sixty-fourth row line YL<64> of the memory block (MB IN 123) included in the second memory block array.

[0038] As shown in Figures 5 and 9, the first redundant fuse latch 131_1 included in the fuse latch circuit 105 can correspond to the thirty-third row line YL<33> of each memory block MB included in the first memory block array 121 and the first row line YL<1> of each memory block MB included in the second memory block array 123. The second redundant fuse latch 131_2 included in the fuse latch circuit 105 can correspond to the thirty-fourth row line YL<34> of each memory block MB included in the first memory block array 121 and the second row line YL<2> of each memory block MB included in the second memory block array 123. The thirty-second redundant fuse latch 131_32 included in the fuse latch circuit 105 can correspond to the sixty-fourth row line YL<64> of each memory block MB included in the first memory block array 121 and the thirty-second row line YL<32> of each memory block MB included in the second memory block array 123.

[0039] As shown in Figures 9 and 10, the following repair operation is performed based on the redundant fuse data RFD output from the first redundant fuse latch 131_1: the first redundant row line RYL<1> of the redundant memory block 125 is used to replace the thirty-third row line YL<33> of the memory block (MB IN 121) included in the faulty first memory block array; the thirty-third redundant row line RYL<33> of the redundant memory block 125 is used to replace the first row line YL<1> of the memory block (MB IN 123) included in the second memory block array. Furthermore, based on the redundant fuse data RFD output from the second redundant fuse latch 131_2, the following repair operations are performed: the third fourteenth row line YL<34> of the memory block (MB IN 121) included in the faulty first memory block array is replaced with the second redundant row line RYL<2> of the redundant memory block 125; the third fourteenth redundant row line RYL<34> of the redundant memory block 125 is replaced with the second row line YL<2> of the memory block (MB IN 123) included in the second memory block array.

[0040] As shown in Figures 9 and 11, the following repair operation is performed based on the redundant fuse data RFD output from the thirty-two redundant fuse latches 131_32: the thirty-second redundant row line RYL<32> of the redundant memory block 125 is used to replace the sixty-fourth row line YL<64> of the memory block (MB IN 121) included in the faulty first memory block array; the sixty-fourth redundant row line RYL<64> of the redundant memory block 125 is used to replace the thirty-second row line YL<32> of the memory block (MB IN 123) included in the second memory block array.

[0041] As shown in Figure 5, the normal fuse latch circuit 133 may include a plurality of normal fuse latches 133_1 to 133_32 to output normal fuse data NFD. Each of the normal fuse latches 133_1 to 133_32 included in the normal fuse latch circuit 133 may correspond to each memory block MB included in the first memory block array 121 and the second memory block array 123. For example, when each of the first memory block array 121 and the second memory block array 123 includes sixteen memory blocks MB, the normal fuse latch circuit 133 may include thirty-two normal fuse latches. Here, the first memory blocks MB to the sixteenth memory blocks MB of the first memory block array 121 can correspond to the first normal fuse latches to the sixteenth normal fuse latches 133_1 to 133_16, respectively, and the first memory blocks MB to the sixteenth memory blocks MB of the second memory block array 123 can correspond to the seventeenth normal fuse latches to the thirty-second normal fuse latches 133_17 to 133_32, respectively. Information for replacing one of the faulty row lines YL in the memory blocks MB corresponding to the normal fuse latches 133_1 to 133_32 with another row line YL can be stored, and the stored information can be output as normal fuse data NFD.

[0042] As shown in Figure 12, when each memory block MB included in the first memory block array 121 and the second memory block array 123 includes a first row line set (1st YL SET) YL<1:32> and a second row line set (2nd YL SET) YL<33:64>, the first row line set (1st YL SET) YL<1:32> is divided into a first sub-row line set (1st SUB YL SET) YL<1:16> and a second sub-row line set (2nd SUB YL SET) YL<17:32>, and the second row line set (2nd YL SET) YL<33:64> is divided into a third sub-row line set (3rd SUB YL SET) YL<33:48> and a fourth sub-row line set (4th SUB YL SET) YL<33:48>. The following description, using SET)YL<49:64>, illustrates a repair operation performed based on normal fuse data NFD output from redundant fuse latch circuit 131. For example, when a fault occurs in a row of the first sub-row line set YL<1:16> of memory block MB, a repair operation can be performed based on the normal fuse data NFD, replacing a row of the first sub-row line set YL<1:16> with a row of the second sub-row line set YL<1:32>. As another example, when a fault occurs in a row of the second sub-row line set YL<17:32> of memory block MB, a repair operation can be performed based on the normal fuse data NFD, replacing a row of the second sub-row line set YL<17:32> with a row of the first sub-row line set YL<1:16>. As another example, when a fault occurs in a row of the third sub-row set YL<33:48> of memory block MB, a repair operation can be performed based on the normal fuse data NFD, replacing a row of the third sub-row set YL<49:64> with a row of the fourth sub-row set YL<43:48>. As another example, when a fault occurs in a row of the fourth sub-row set YL<49:64> of memory block MB, a repair operation can be performed based on the normal fuse data NFD, replacing a row of the fourth sub-row set YL<49:64> with a row of the third sub-row set YL<33:48>. The repair operation performed based on the normal fuse data NFD will be described below with reference to Figures 13 and 14.

[0043] As shown in Figure 13, when a fault occurs in the first row line YL<1> of memory block MB, a repair operation can be performed based on the normal fuse data NFD corresponding to memory block MB, using the seventeenth row line YL<17> of memory block MB to replace the first row line YL<1> of memory block MB. When a fault occurs in the second row line YL<2> of memory block MB, a repair operation can be performed based on the normal fuse data NFD corresponding to memory block MB, using the eighteenth row line YL<18> of memory block MB to replace the second row line YL<2> of memory block MB. When a fault occurs in the sixteenth row line YL<16> of memory block MB, a repair operation can be performed based on the normal fuse data NFD corresponding to memory block MB, using the thirty-second row line YL<32> of memory block MB to replace the sixteenth row line YL<16> of memory block MB. When a fault occurs in line YL<17> of memory block MB, a repair operation can be performed based on the normal fuse data NFD corresponding to memory block MB, replacing line YL<17> of memory block MB with line YL<1> of memory block MB. When a fault occurs in line YL<32> of memory block MB, a repair operation can be performed based on the normal fuse data NFD corresponding to memory block MB, replacing line YL<32> of memory block MB with line YL<16> of memory block MB.

[0044] As shown in Figure 14, when a fault occurs in the 33rd line YL<33> of memory block MB, a repair operation can be performed using the 49th line YL<49> of memory block MB to replace the 33rd line YL<33> of memory block MB, based on the normal fuse data NFD corresponding to memory block MB. When a fault occurs in the 34th line YL<34> of memory block MB, a repair operation can be performed using the 50th line YL<50> of memory block MB to replace the 34th line YL<34> of memory block MB, based on the normal fuse data NFD corresponding to memory block MB. When a fault occurs in the 48th line YL<48> of memory block MB, a repair operation can be performed using the 64th line YL<64> of memory block MB to replace the 48th line YL<48> of memory block MB, based on the normal fuse data NFD corresponding to memory block MB. When a fault occurs in line 49 (YL<49>) of memory block MB, a repair operation can be performed based on the normal fuse data NFD corresponding to memory block MB, using line 33 (YL<33>) of memory block MB to replace line 49 (YL<49>). When a fault occurs in line 64 (YL<64>) of memory block MB, a repair operation can be performed based on the normal fuse data NFD corresponding to memory block MB, using line 48 (YL<48>) of memory block MB to replace line 64 (YL<64>).

[0045] Figure 15 is a diagram illustrating the repair operation performed based on redundant fuse data RFD and normal fuse data NFD. As shown in Figure 15, when a fault occurs in the first row line YL<1> of the first memory block (1st MB IN 121) included in the first memory block array, the following repair operation can be performed together with the redundant fuse data RFD: the first redundant row line RYL<1> of the redundant memory block 125 is used to replace the first row line YL<1>; the thirty-third redundant row line RYL<33> of the redundant memory block 125 is used to replace the thirty-third row line YL<33> of the first memory block (1st MB IN 123) included in the second memory block array. Furthermore, when a fault occurs in the first row line YL<1> of the second memory block (2nd MB IN 121) included in the first memory block array, a repair operation can be performed based on the normal fuse data NFD to replace the first row line YL<1> using the seventeenth row line <YL<17>.

[0046] FIG16 is a block diagram illustrating the configuration of a test row address generator 13A according to an example of a test row address generator 13 included in the semiconductor device 1 shown in FIG1. ​​As shown in FIG16, the test row address generator 13A can generate a first test row address TCAD1<6:1> and a second test row address TCAD2<6:1> for performing pre-tests or post-tests from the row address CADD<6:1>. The test row address generator 13A may include inverters 141_1 to 141_7. Inverters 141_1 and 141_2 can buffer the first to fifth bits of the row address CADD<5:1> to generate the first to fifth bits of the first test row address TCAD1<5:1> and the first to fifth bits of the second test row address TCAD2<5:1>. Inverters 141_3 and 141_4 can buffer the sixth bit of the row address, CADD<6>, to generate the sixth bit of the first test row address, TCAD1<6>. Inverter 141_5 can invert the buffered first test mode signal TM1 to generate an inverted buffered signal of the first test mode signal TM1. When the first test mode signal TM1 at the logic "high" level is received, inverter 141_6 can invert the buffered sixth bit of the row address, CADD<6>, to generate the sixth bit of the second row address, TCAD2<6>, thereby performing a pre-test. Inverter 141_7 can invert the buffered second test mode signal TM2 to generate an inverted buffered signal of the second test mode signal TM2. When the second test mode signal TM2 at the logic "high" level is received, inverters 141_8 and 141_9 can buffer the sixth bit of the row address, CADD<6>, to generate the sixth bit of the second row address, TCAD2<6>, thereby performing a post-test. In the pre-test, the test row address generator 13A can generate a first test row address TCAD1<6:1> to select one of the row lines YL included in each memory block MB in the first memory block array 121, and can generate a second test row address TCAD2<6:1> to select another of the row lines YL included in each memory block MB in the second memory block array 123. As an example, in the pre-test, the test row address generator 13A can generate a first test row address TCAD1<6:1> to select a first row line YL<1> included in each memory block MB in the first memory block array 121, and can generate a second test row address TCAD2<6:1> to select a thirty-third row line YL<33> included in each memory block MB in the second memory block array 123. Since the test row address generator 13A generates the first test row address TCAD1<6:1> and the second test row address TCAD2<6:1>, the row lines selected to perform repair operations together in the pre-test can be checked for defects and need to be repaired through the pre-test.In the post-test, the test row address generator 13A can generate a first test row address TCAD1<6:1> to select one of the row lines YL included in each memory block MB in the first memory block array 121, and can generate a second test row address TCAD2<6:1> to select the same row line among the row lines YL included in each memory block MB in the second memory block array 123. As an example, in the post-test, the test row address generator 13A can generate a first test row address TCAD1<6:1> to select the first row line YL<1> included in each memory block MB in the first memory block array 121, and can generate a second test row address TCAD2<6:1> to select the thirty-third row line YL<33> included in each memory block MB in the second memory block array 123. Since the test row address generator 13A generates the first test row address TCAD1<6:1> and the second test row address TCAD2<6:1>, the row lines that are not repaired together are selected in the subsequent test. Therefore, it is possible to prevent or reduce the selection of multiple redundant row lines RYL that are repaired together at the same time, and to check whether the repair operation is performed correctly through the subsequent test.

[0047] Figures 17 and 18 are diagrams used to illustrate the pre-test operation.

[0048] As shown in FIG17, the memory group 101 may include: a first memory block array 121, a second memory block array 123, and redundant memory blocks 125. Each of the first memory block array 121 and the second memory block array 123 may include multiple memory blocks MB.

[0049] As shown in Figure 17, the row line selection circuit 103A can receive a first test mode signal TM1, a first test row address TCAD1, and a second test row address TCAD2. The row line selection circuit 103A may include multiple row decoders CDEC. When performing a pre-test and receiving the first test mode signal TM1, based on the first test row address TCAD1 and the second test row address TCAD2 generated from the row address CADD, the row line selection circuit 103A can select one row line YL included in each memory block MB in the first memory block array 121, and can select another row line YL included in each memory block MB in the second memory block array 123.

[0050] As shown in Figure 18, when the row address CAD for selecting the first row line YL<1> is input in the pre-test, the first memory block data MBD1 can be output from the first row line YL<1> of the memory block MB included in the first memory block array 121 through the first test row address TCAD1 generated from the row address CAD. Additionally, when the row address CAD for selecting the first row line YL<1> is input, the second memory block data MBD2 can be output from the thirty-third row line YL<33> of the memory block MB included in the second memory block array 123 through the second test row address TCAD2 generated from the row address CAD. Thereafter, row address CADs for selecting the second row line YL<2> to those for selecting the sixty-fourth row line YL<64> are sequentially input, and the first memory block data MBD1 and the second test row address TCAD2 generated according to each row address CAD can be sequentially generated and output.

[0051] Figures 19 and 20 are diagrams of the test operation after the illustration.

[0052] As shown in FIG19, the memory group 101 may include a first memory block array 121, a second memory block array 123, and redundant memory blocks 125. Each of the first memory block array 121 and the second memory block array 123 may include multiple memory blocks MB.

[0053] As shown in Figure 19, the row line selection circuit 103B can receive a second test mode signal TM2, a first test row address TCAD1, a second test row address TCAD2, redundant fuse data RFD, and normal fuse data NFD. The row line selection circuit 103B may include multiple row decoders CDEC. When a post-test is performed and the second test mode signal TM2 is received, based on the first test row address TCAD1 and the second test row address TCAD2 generated from the row address CADD, the row line selection circuit 103B can select one row line YL included in each memory block MB in the first memory block array 121 and can select the same row line YL included in each memory block MB in the second memory block array 123. The row line selection circuit 103B can select one row line YL included in each memory block MB in the defective first memory block array 121 by replacing the row line with one of the redundant row lines RYL of the redundant memory block RED MB, based on the redundant fuse data RFD. Row line selection circuit 103B can select one row line YL of each memory block MB included in the defective second memory block array 123 by replacing a row line with one of the redundant row lines RYL of the redundant memory block RED MB, based on redundant fuse data RFD. Row line selection circuit 103B can also select one row line YL of each memory block MB included in the defective first memory block array 121 by replacing a row line with another row line from the row lines YL of the memory block MB, based on normal fuse data NFD. Row line selection circuit 103B can also select one row line YL of the memory block MB included in the defective second memory block array 123 by replacing a row line with another alternative row line from the row lines YL of the memory block MB, based on normal fuse data NFD.

[0054] As shown in Figure 20, in the subsequent test, when the row address CAD used to select the first row line YL<1> is input, the first memory block data MBD1 can be output from the first row line YL<1> of the memory block MB included in the first memory block array 121 through the first test row address TCAD1 generated from the row address CAD. Simultaneously, if one of the first row lines YL<1> of the memory block MB included in the first memory block array 121 fails and one of the redundant row lines RYL of the redundant memory block 125 is used to replace the faulty row line, the redundant memory block data RMBD can be output from the redundant memory block 125. Furthermore, when the row address CAD used to select the first row line YL<1> is input, the second memory block data MBD2 can be output from the first row line YL<1> of the memory block MB included in the second memory block array 123 through the second test row address TCAD2 generated from the row address CAD. Furthermore, if a fault occurs in one of the first row lines YL<1> of the memory block MB in the second memory block array 123, and the faulty row line is replaced by a redundant row line RYL of the redundant memory block 125, redundant memory block data RMBD can be output from the redundant memory block 125. Subsequently, row address CAD for selecting the second row line YL<2> to row address CAD for selecting the sixty-fourth row line YL<64> are sequentially input, and based on the first test row address TCAD1 and the second test row address TCAD2 generated according to each row address CAD, first memory block data MBD1, second memory block data MBD2, and redundant memory block data RMBD can be sequentially generated and output.

[0055] FIG21 is a block diagram illustrating the configuration of a shift control circuit 15A according to an example of the shift control circuit 15 shown in FIG1. ​​As shown in FIG21, the shift control circuit 15A may include a fuse data decoder 151 and a shift signal generator 153.

[0056] The fuse data decoder 151 can generate a fuse flag FLAG, fuse row data FCAD, and fuse latch signal FLAT based on redundant fuse data RFD. The fuse flag FLAG can be activated depending on whether a fault has occurred. For example, when a fault occurs in at least one of the memory blocks MB included in the first memory block array 121 or the memory blocks MB included in the second memory block array 123, the fuse flag FLAG can be activated to a logic "high" level. The fuse row data FCAD can include information about the row set of the memory block MB in which the fault occurred. For example, when a fault occurs in the first row set (1st YL SET) of the memory block MB, the fuse row data FCAD can be set to a logic "low" level, and when a fault occurs in the second row set (2nd YL SET) of the memory block MB, the fuse row data FCAD can be set to a logic "high" level. The fuse latch signal FLAT can include information about the memory blocks MB that are being repaired together. As an example, when the first row line set (1st YL SET) of memory blocks MB included in the first memory block array 121 and the second row line set (2nd YL SET) of memory blocks MB included in the second memory block array 123 are repaired together, the fuse latch signal FLAT can be set to the logic "low" level, and when the second row line set (2nd YL SET) of memory blocks MB included in the first memory block array 121 and the first row line set (1st YL SET) of memory blocks MB included in the second memory block array 123 are repaired together, the fuse latch signal FLAT can be set to the logic "high" level.

[0057] The shift signal generator 153 can generate a first shift signal SFT1 and a second shift signal SFT2 based on the fuse flag FFLAG, the fuse row data FCAD, and the fuse latch signal FLAT. When a fault in a memory block MB included in the first memory block array 121 is repaired, the shift signal generator 153 can generate the first shift signal SFT1, which is activated to the logic "high" level. For example, when a fault occurs in the first row line set (1st YL SET) of memory blocks MB included in the first memory block array 121, and the first row line set (1st YL SET) of memory blocks MB included in the first memory block array 121 and the second row line set (2nd YL SET) of memory blocks MB included in the second memory block array 123 are repaired together, the shift signal generator 153 can receive the fuse flag FFLAG activated to the logic "high" level, the fuse row data FCAD at the logic "low" level, and the fuse latch signal FLAT at the logic "low" level to generate a first shift signal SFT1 activated to the logic "high" level. As another example, when a fault occurs in the second row line set (2nd YL SET) of memory blocks MB included in the first memory block array 121, and the second row line set (2nd YL SET) of memory blocks MB included in the first memory block and the first row line set (1st YL SET) of memory blocks MB included in the second memory block array 123 are repaired together, the shift signal generator 153 can receive the fuse flag FFLAG activated to the logic "high" level, the fuse row data FCAD activated to the logic "high" level, and the fuse latch signal FLAT activated to the logic "high" level to generate a first shift signal SFT1 activated to the logic "high" level.

[0058] When a fault in a memory block MB included in the second memory block array 123 is repaired, the shift signal generator 153 can generate a second shift signal SFT2 activated to the logic "high" level. As an example, when a fault occurs in the first row line set (1st YL SET) of the memory block MB included in the second memory block array 123, and the first row line set (1st YL SET) of the memory block MB included in the second memory block array 123 and the second row line set (2nd YL SET) of the memory block MB included in the first memory block array 121 are repaired together, the shift signal generator 153 can receive the fuse flag FFLAG activated to the logic "high" level, the fuse row data FCAD activated to the logic "low" level, and the fuse latch signal FLAT activated to the logic "high" level to generate the second shift signal SFT2 activated to the logic "high" level. As another example, when a fault occurs in the second row line set (2nd YL SET) of memory blocks MB included in the second memory block array 123, and the second row line set (2nd YL SET) of memory blocks MB included in the second memory block array 123 and the first row line set (1st YL SET) of memory blocks MB included in the first memory block array 121 are repaired together, the shift signal generator 153 can receive the fuse flag FFLAG activated at the logic "high" level, the fuse row data FCAD at the logic "high" level, and the fuse latch signal FLAT at the logic "low" level to generate a second shift signal SFT2 activated at the logic "high" level.

[0059] FIG22 is a circuit diagram illustrating the configuration of a shift signal generator 153A according to an example of the shift signal generator 153 shown in FIG21.

[0060] As shown in Figure 22, the shift signal generator 153A may include: inverters 154_1~154_5, transmission gates 155_1 and 155_2, inverse gates 156_1 and 156_2, inverse OR gates 157_1 and 157_2, PMOS transistors 158_1 and 158_2, and NMOS transistors 159_1 and 159_2. Inverter 154_1 can invert the buffered fuse latch signal FLAT to output the inverted buffered signal of the fuse latch signal FLAT. When the fuse latch signal FLAT is at the logic "low" level, inverter 154_2 can invert the buffered fuse row data FCAD to output the inverted buffered signal of the fuse row data FCAD to node n154_1. Inverter 154_3 can invert the buffered fuse flag FFLAG to output the inverted buffered signal of the fuse flag FFLAG. When the fuse latch signal FLAT is at the logic "high" level, inverter 154_4 can invert the buffered fuse row data FCAD to output the inverted buffered signal of the fuse row data FCAD to node n154_2. Inverter 154_5 can invert the buffered fuse flag FFLAG to output the inverted buffered signal of the fuse flag FFLAG. When the fuse latch signal FLAT is at the logic "high" level, transmission gate 155_1 can output the fuse row data FCAD to node n154_1. When the fuse latch signal FLAT is at the logic "low" level, transmission gate 155_2 can output the fuse row data FCAD to node n154_2. Inverting gate 156_1 can perform a logic inversion operation on the signals of node n154_1 and the fuse flag FFLAG to generate the first pull-up signal PU1. Inverting gate 156_2 can perform a logical inverse operation on the signal and fuse flag FFLAG of node n154_2 to generate a second pull-up signal PU2. Inverting gate 157_1 can perform a logical NOR operation on the signal of node n154_1 and the output signal of inverter 154_3 to generate a first pull-down signal PD1. Inverting gate 157_2 can perform a logical NOR operation on the signal of node n154_2 and the output signal of inverter 154_5 to generate a second pull-down signal PD2. PMOS transistor 158_1 can receive the first pull-up signal PU1 activated to a logic "high" level to drive the first shift signal SFT1 to a logic "high" level. PMOS transistor 158_2 can receive the second pull-up signal PU2 activated to a logic "low" level to drive the second shift signal SFT2 to a logic "high" level. NMOS transistor 159_1 can receive a first pull-down signal PD1 activated to a logic "high" level to drive the first shift signal SFT1 to a logic "low" level. NMOS transistor 159_2 can receive a second pull-down signal PD2 activated to a logic "high" level to drive the second shift signal SFT2 to a logic "low" level.

[0061] The operation of the shift signal generator 153A will be described with reference to Figures 22 and 23.

[0062] When a fault occurs in the first row line set (1st YL SET) of memory blocks MB included in the first memory block array 121, and the first row line set (1st YL SET) of memory blocks MB included in the first memory block array 121 and the second row line set (2nd YL SET) of memory blocks MB included in the second memory block array 123 are repaired together, a fuse flag FFLAG that is activated to a logic "high" level and fuse latch signal FLAT and fuse row data FCAD that are both set to a logic "low" level are generated. When both fuse latch signal FLAT and fuse row data FCAD are set to a logic "low" level, inverter 154_2 sets node n154_1 to a logic "high" level, and transmission gate 155_2 sets node n154_2 to a logic "low" level. Based on node n154_1 set to logic "high" level, inverse gate 156_1 generates a first pull-up signal PU1 activated to logic "low" level, and inverse gate 157_1 generates a first pull-down signal PD1 deactivated to logic "low" level. A first shift signal SFT1 activated to logic "high" level is generated via PMOS transistor 158_1, which is turned on by the first pull-up signal PU1 activated to logic "low" level.

[0063] When the second row line set (2nd YL SET) of memory block MB included in the second memory block array 123 fails, and the second row line set (2nd YL SET) of memory block MB included in the second memory block array 123 and the first row line set (1st YL SET) of memory block MB included in the first memory block array 121 are repaired together, a fuse flag FFLAG, a fuse latch signal FLAT, and fuse row data FCAD, which are activated to the logic "high" level, are generated. When the fuse latch signal FLAT is set to the logic "low" level and the fuse row data FCAD is set to the logic "low" level, the inverter 154_2 sets node n154_1 to the logic "low" level, and the transmission gate 155_2 sets node n154_2 to the logic "high" level. Based on node n154_2 set to logic "high" level, inverse gate 156_2 generates a second pull-up signal PU2 activated to logic "low" level, and inverse gate 157_2 generates a second pull-down signal PD2 deactivated to logic "low" level. A second shift signal SFT2 activated to logic "high" level is generated via PMOS transistor 158_2, which is turned on by the second pull-up signal PU2 activated to logic "low" level.

[0064] When the second row line set (2nd YL SET) of memory blocks MB included in the first memory block array 121 fails, and the second row line set (2nd YL SET) of memory blocks MB included in the first memory block array 121 and the first row line set (1st YL SET) of memory blocks MB included in the second memory block array 123 are repaired together, a fuse flag FFLAG that is activated to the logic "high" level and a fuse latch signal FLAT and fuse row data FCAD that are both set to the logic "high" level are generated. When both the fuse latch signal FLAT and the fuse row data FCAD are set to the logic "high" level, the transmission gate 155_1 sets node n154_1 to the logic "high" level, and the inverter 154_4 sets node n154_2 to the logic "high" level. Based on node n154_1 set to logic "high" level, inverse gate 156_1 generates a first pull-up signal PU1 activated to logic "low" level, and inverse gate 157_1 generates a first pull-down signal PD1 deactivated to logic "low" level. A first shift signal SFT1 activated to logic "high" level is generated via PMOS transistor 158_1, which is turned on by the first pull-up signal PU1 activated to logic "low" level.

[0065] When a fault occurs in the first row line set (1st YL SET) of memory blocks MB included in the second memory block array 123, and the first row line set (1st YL SET) of memory blocks MB included in the second memory block array 123 and the second row line set (2nd YL SET) of memory blocks MB included in the first memory block array 121 are repaired together, a fuse flag FFLAG, a fuse latch signal FLAT, and fuse row data FCAD, which are activated to the logic "high" level, are generated. When the fuse latch signal FLAT is set to the logic "high" level and the fuse row data FCAD is set to the logic "low" level, the transmission gate 155_1 sets node n154_1 to the logic "low" level, and the inverter 154_4 sets node n154_2 to the logic "high" level. Based on node n154_2 set to logic "high" level, inverse gate 156_2 generates a second pull-up signal PU2 activated to logic "low" level, and inverse gate 157_2 generates a second pull-down signal PD2 deactivated to logic "low" level. A second shift signal SFT2 activated to logic "high" level is generated via PMOS transistor 158_2, which is turned on by the second pull-up signal PU2 activated to logic "low" level.

[0066] FIG24 is a block diagram illustrating the configuration of an input / output control circuit 17A according to an example of the input / output control circuit 17 shown in FIG1. ​​As shown in FIG24, the input / output control circuit 17A may include: a first input / output shift circuit 161, a first drive circuit 163, a second input / output shift circuit 165, and a second drive circuit 167.

[0067] The first input / output shift circuit 161 can output the first memory block data MBD1 received via the first local line LIO1 to the first drive circuit 163 based on the first shift signal SFT1, or it can shift a portion of the redundant memory block data RMBD and the first memory block data MBD1 received via the redundant local line RLIO to output the shifted data to the first drive circuit 163. For example, when a fault in the memory block MB included in the first memory block 121 is repaired, the first input / output shift circuit 161 receives the first shift signal SFT1 activated to the logic "high" level, and the first input / output shift circuit 161 can sequentially shift the redundant memory block data RMBD and a portion of the first memory block data MBD1 to output the shifted data to the first drive circuit 163. As another example, when the memory block MB included in the first memory block array 121 does not contain a fault, the first input / output shift circuit 161 receives a deactivated first shift signal SFT1, and the first input / output shift circuit 161 can output the first memory block data MBD1 to the first drive circuit 163.

[0068] The first driving circuit 163 can drive the first driving data DRD1 based on the signal received from the first input / output shift circuit 161. For example, when a fault in a memory block MB included in the first memory block array 121 is repaired, causing a sequentially shifted portion of the first memory block data MBD1 and the redundant memory block data RMBD to be output from the first input / output shift circuit 161, the first driving circuit 163 can drive the first driving data DRD1 based on the shifted and received portions of the first memory block data MBD1 and the redundant memory block data RMBD. As another example, when the memory block MB included in the first memory block array 121 does not contain a fault and the first memory block data MBD1 is output from the first input / output shift circuit 161, the first driving circuit 163 can drive the first driving data DRD1 based on the received first memory block data MBD1.

[0069] The second input / output shift circuit 165 can output the second memory block data MBD2 received via the second local line LIO2 to the second drive circuit 167 based on the second shift signal SFT2, or it can shift a portion of the redundant memory block data RMBD and the second memory block data MBD2 received via the redundant local line RLIO to output the shifted data to the second drive circuit 167. As an example, when a fault in the memory block MB included in the second memory block 123 is repaired, the second input / output shift circuit 165, which receives the second shift signal SFT2 activated at the logic "high" level, can sequentially shift the redundant memory block data RMBD and a portion of the second memory block data MBD2 to output the shifted data to the second drive circuit 167. As another example, when the memory block MB included in the second memory block array 123 does not contain a fault, the second input / output shift circuit 165, which receives the deactivated second shift signal SFT2, can output the second memory block data MBD2 to the second drive circuit 167.

[0070] The second driving circuit 167 can drive the second driving data DRD2 based on the signal received from the second input / output shift circuit 165. As an example, when a fault in the memory block MB included in the second memory block array 123 is repaired, causing the sequentially shifted portion of the second memory block data MBD2 and the redundant memory block data RMBD to be output from the second input / output shift circuit 165, the second driving circuit 167 can drive the second driving data DRD2 based on the shifted and received portion of the second memory block data MBD2 and the redundant memory block data RMBD. As another example, when the memory block MB included in the second memory block array 123 does not have a fault, causing the second memory block data MBD2 to be output from the second input / output shift circuit 165, the second driving circuit 167 can drive the second driving data DRD2 based on the received second memory block data MBD2.

[0071] FIG25 is a diagram illustrating the configuration of the first input / output shift circuit 161A and the first drive circuit 163A according to the examples of the first input / output shift circuit 161 and the first drive circuit 163 shown in FIG24, respectively.

[0072] As shown in Figure 25, the first input / output shift circuit 161A may include an inverter 160 and MOS transistors 163_1 to 163_5. The inverter 160 may invert the buffered first shift signal SFT1 to generate a first inverted shift signal SFT1B. NMOS transistors 163_1, 163_3, and 163_4 may be turned on by receiving the first inverted shift signal SFT1B, which is set to a logic "high" level, when the first shift signal SFT1 is deactivated to a logic "low" level. When NMOS transistor 163_1 is turned on, the first bit MBD1<1> of the first memory block data received via the first line LIO1<1> of the first local line may be output to the first driver DRV of the first drive circuit 163A. When NMOS transistor 163_3 is turned on, the second bit MBD1<2> of the first memory block data received via the second line LIO1<2> of the first local line can be output to the second driver DRV of the first driving circuit 163A. When NMOS transistor 163_4 is turned on, the sixteenth bit MBD1<16> of the first memory block data received via the sixteenth line LIO1<16> of the first local line can be output to the sixteenth driver DRV of the first driving circuit 163A. When the first shift signal SFT1 is activated, NMOS transistors 163_2 and 163_5 can be turned on. When NMOS transistor 163_2 is turned on, the second bit MBD1<2> of the first memory block data received via the second line LIO1<2 of the first local line can be output to the first driver DRV of the first driving circuit 163A. When NMOS transistor 163_5 is turned on, the redundant memory block data RMBD received via the redundant local line RLIO can be output to the sixteenth driver DRV of the first driving circuit 163A. The first input / output shift circuit 161A can shift the second to sixteenth bits (MBD1<2:16>) of the first memory block data and the redundant memory block data (RMBD) to output the shifted bits and data to the first driver circuit 163A via NMOS transistors 163_2 and 163_5, which are turned on when the first shift signal SFT1 is activated. The first input / output shift circuit 161A can also output the first to sixteenth bits (MBD1<1:16>) of the first memory block data to the first driver circuit 163A via NMOS transistors 163_1, 163_3, and 163_4, which are turned on when the first shift signal SFT1 is deactivated.

[0073] As shown in FIG25, the first driving circuit 163A may include a plurality of drivers DRV. Based on the signal received from the first input / output shift circuit 161A, each of the plurality of drivers DRV in the first driving circuit 163A can drive the first bit to the sixteenth bit DRD1<1:16> of the first driving data. Based on the shift and reception of the second bit to the sixteenth bit MBD1<2:16> of the first memory block data and the redundant memory block data RMBD when the first shift signal SFT1 is activated, the first driving circuit 163A can drive the first bit to the sixteenth bit DRD1<1:16> of the first driving data. Based on the first bit to the sixteenth bit MBD1<1:16> of the first memory block data received when the first shift signal SFT1 is deactivated, the first driving circuit 163A can drive the first bit to the sixteenth bit DRD1<1:16> of the first driving data.

[0074] Figures 26 and 27 are diagrams illustrating the shift operation performed by the first shift signal SFT1 shown in Figure 25.

[0075] As shown in Figure 26, when the first shift signal SFT1 is deactivated to the logic "low" level, NMOS transistors 163_1, 163_3, and 163_4 are turned on, and NMOS transistors 163_2 and 163_5 are turned off. This allows the first input / output shift circuit 161A to output the first to sixteenth bits MBD1<1:16> of the first memory block data to the first driver circuit 163A. The first driver circuit 163A can drive the first to sixteenth bits DRD1<1:16> of the first driver data based on the received first to sixteenth bits MBD1<1:16> of the first memory block data.

[0076] As shown in Figure 27, when the first shift signal SFT1 is activated to the logic "high" level, NMOS transistors 163_1, 163_3, and 163_4 are turned off, and NMOS transistors 163_2 and 163_5 are turned on. This allows the first input / output shift circuit 161A to shift the first to sixteenth bits MBD1<1:16> of the first memory block data and the redundant memory block data RMBD, so as to output the shifted bits and data to the first driving circuit 163A. The first driving circuit 163A can drive the first to sixteenth bits DRD1<1:16> of the first driving data based on the shifted and received first to sixteenth bits MBD1<1:16> of the first memory block data and the redundant memory block data RMBD.

[0077] FIG28 is a diagram illustrating the configuration of the second input / output shift circuit 165A and the second drive circuit 167A according to the examples of the second input / output shift circuit 165 and the second drive circuit 167 shown in FIG24, respectively.

[0078] As shown in Figure 28, the second input / output shift circuit 165A may include an inverter 171 and NMOS transistors 173_1 to 173_5. The inverter 171 may invert the buffered second shift signal SFT2 to generate a second inverted shift signal SFT2B. The NMOS transistors 173_1, 173_3, and 173_4 may receive the second inverted shift signal SFT2B, which is set to a logic "high" level, when the second shift signal SFT2 is turned on by being deactivated to a logic "low" level. When the NMOS transistor 173_1 is turned on, the second input / output shift circuit 165A may output the first bit MBD2<1> of the second memory block data received via the first line LIO2<1> of the second local line to the first driver DRV of the second drive circuit 167A. When NMOS transistor 173_3 is turned on, the second input / output shift circuit 165A can output the second bit MBD2<2> of the second memory block data received via the second line LIO2<2> of the second local line to the second driver DRV of the second driver circuit 167A. When NMOS transistor 173_4 is turned on, the second input / output shift circuit 165A can output the sixteenth bit MBD2<16> of the second memory block data received via the sixteenth line LIO2<16> of the second local line to the sixteenth driver DRV of the second driver circuit 167A. When the second shift signal SFT2 is activated, NMOS transistors 173_2 and 173_5 can be turned on. When NMOS transistor 173_2 is turned on, the second input / output shift circuit 165A can output the second bit MBD2<2> of the second memory block data received via the second line LIO2<2> of the second local line to the first driver DRV of the second driver circuit 167A. When NMOS transistor 173_5 is turned on, the second input / output shift circuit 165A can output the redundant memory block data RMBD received via the redundant local line RLIO to the sixteenth driver DRV of the second driver circuit 167A. The second input / output shift circuit 165A can shift the second to sixteenth bits MBD2<2:16> of the second memory block data and the redundant memory block data RMBD, so that the shifted bits and data are output to the second driver circuit 167A via NMOS transistors 173_2 and 173_5, which are turned on when the second shift signal SFT2 is enabled. The second input / output shift circuit 165A can output the first to sixteenth bits MBD2<1:16> of the second memory block data to the second driver circuit 167A via NMOS transistors 173_1, 173_3, and 173_4, which are turned on when the second shift signal SFT2 is disabled.

[0079] As shown in FIG28, the second driving circuit 167A may include a plurality of drivers DRV. Based on the signal received from the second input / output shift circuit 165A, each of the plurality of drivers DRV included in the second driving circuit 167A can drive the first to sixteenth bits of the second driving data DRD2<1:16>. When the second shift signal SFT2 is activated, the second driving circuit 167A can drive the first to sixteenth bits of the second driving data DRD2<1:16> based on the shifted and received second memory block data second to sixteenth bits MBD2<2:16> and redundant memory block data RMBD. When the second shift signal SFT2 is deactivated, the second driving circuit 167A can drive the first to sixteenth bits of the second driving data DRD2<1:16> based on the received second memory block data first to sixteenth bits MBD2<1:16>.

[0080] Figures 29 and 30 are diagrams illustrating the shift operation performed by the second shift signal SFT2 in Figure 28.

[0081] As shown in Figure 29, when the second shift signal SFT2 is deactivated to the logic "low" level, NMOS transistors 173_1, 173_3, and 173_4 are turned on, and NMOS transistors 173_2 and 173_5 are turned off. This allows the second input / output shift circuit 165A to output the first to sixteenth bits MBD2<1:16> of the second memory block data to the second driver circuit 167A. The second driver circuit 167A can drive the first to sixteenth bits DRD2<1:16> of the second driver data based on the received first to sixteenth bits MBD2<1:16> of the second memory block data.

[0082] As shown in Figure 30, when the second shift signal SFT2 is activated to the logic "high" level, NMOS transistors 173_1, 173_3, and 173_4 are turned off, and NMOS transistors 173_2 and 173_5 are turned on. This allows the second input / output shift circuit 165A to shift the second to sixteenth bits of the second memory block data (MBD2<2:16>) and the redundant memory block data (RMBD) to output the shifted bits and data to the second driver circuit 167A. The second driver circuit 167A can drive the first to sixteenth bits of the second driving data (DRD2<1:16>) based on the shifted and received second to sixteenth bits of the second memory block data (MBD2<2:16>) and the redundant memory block data (RMBD).

[0083] FIG31 is a block diagram illustrating the configuration of a test data generator 19A according to an example of the test data generator 19 shown in FIG1. ​​As shown in FIG31, the test data generator 19A may include: a first comparator 181, a second comparator 183, and a compression circuit 185.

[0084] The first comparator 181 can compare the first driving data DRD1 with the first reference data REFD1 to generate a first comparison signal COM1. When performing a pre-test or post-test, the first comparator 181 can compare the first driving data DRD1 with the first reference data REFD1 to generate a first comparison signal COM1 having a set of logical bits set according to the comparison result. As an example, when the set of logical bits of the first driving data DRD1 is the same as the set of logical bits of the first reference data REFD1, the first comparator 181 can generate a first comparison signal COM1 including a set of logical bits set to a logical "low" level. As another example, when the set of logical bits of the first driving data DRD1 is different from the set of logical bits of the first reference data REFD1, the first comparator 181 can generate a first comparison signal COM1 set to have a set of logical bits, which includes at least one set of bits set to a logical "high" level.

[0085] The second comparator 183 can compare the second driving data DRD2 with the second reference data REFD2 to generate a second comparison signal COM2. When performing a pre-test or post-test, the second comparator 183 can compare the second driving data DRD2 with the second reference data REFD2 to generate a second comparison signal COM2 having a set of logical bits set according to the comparison result. For example, when the set of logical bits of the second driving data DRD2 is the same as the set of logical bits of the second reference data REFD2, the second comparator 183 can generate a second comparison signal COM2 including a set of logical bits set to a logical "low" level. As another example, when the set of logical bits of the second driving data DRD2 is different from the set of logical bits of the second reference data REFD2, the second comparator 183 can generate a second comparison signal COM2 set to have a set of logical bits, which includes at least one set of bits set to a logical "high" level.

[0086] Compression circuit 185 can receive a first comparison signal COM1 from a first comparator 181 and a second comparison signal COM2 from a second comparator 183. Compression circuit 185 can compress the first comparison signal COM1 and the second comparison signal COM2 to generate test data TDQ. In one example, compression circuit 185 can compress one bit included in the first comparison signal COM1 and one bit included in the second comparison signal COM2 to generate test data TDQ. In another example, compression circuit 185 can compress multiple bits included in the bits of the first comparison signal COM1 and multiple bits included in the bits of the second comparison signal COM2 to generate test data TDQ.

[0087] FIG32 is a circuit diagram of a first comparator 181A according to an example of the first comparator 181 shown in FIG31. As shown in FIG32, the first comparator 181A may include a plurality of mutual exclusion OR operators 191_1 to 191_16. Mutual exclusion OR operator 191_1 can perform a logical mutual exclusion OR operation on the first bit of the first driving data DRD1<1> and the first bit of the first reference data REFD1<1> to generate the first bit of the first comparison data COM1<1>. Mutual exclusion OR operator 191_1 can generate the first bit of the first comparison data set to the logic "low" level when the first bit of the first driving data DRD1<1> and the first bit of the first reference data REFD1<1> have the same logic level, and can generate the first bit of the first comparison data set to the logic "high" level when the first bit of the first driving data DRD1<1> and the first bit of the first reference data REFD1<1> have different logic levels. The OR operator 191_2 performs a logical OR operation on the second bit of the first driving data DRD1<2> and the second bit of the first reference data REFD1<2> to generate the second bit of the first comparison data COM1<2>. The OR operator 191_2 generates the second bit of the first comparison data set to the logical "low" level when the second bits of the first driving data DRD1<2> and the second bits of the first reference data REFD1<2> have the same logical level, and generates the second bit of the first comparison data COM1<2> set to the logical "high" level when the second bits of the first driving data DRD1<2> and the second bits of the first reference data REFD1<2> have different logical levels. The OR operator 191_16 performs a logical OR operation on the sixteenth bit of the first driving data DRD1<16> and the sixteenth bit of the first reference data REFD1<16> to generate the sixteenth bit of the first comparison data COM1<16>. The mutex OR operator 191_16 can generate the sixteenth bit of the first comparison data COM1<16> set to the logic "low" level when the sixteenth bit of the first driving data DRD1<16> and the sixteenth bit of the first reference data REFD1<16> have the same logic level, and can generate the sixteenth bit of the first comparison data COM1<16> set to the logic "high" level when the sixteenth bit of the first driving data DRD1<16> and the sixteenth bit of the first reference data REFD1<16> have different logic levels.

[0088] FIG33 is a circuit diagram of a second comparator 183A according to an example of the second comparator 183 shown in FIG31. As shown in FIG33, the second comparator 183A may include a plurality of mutual exclusion OR operators 193_1 to 193_16. Mutual exclusion OR operator 193_1 can perform a logical mutual exclusion OR operation on the first bit DRD2<1> of the second driving data and the first bit REFD2<1> of the second reference data to generate the first bit COM2<1> of the second comparison signal. Mutual exclusion OR operator 193_2 can perform a logical mutual exclusion OR operation on the second bit DRD2<2> of the second driving data and the second bit REFD2<2> of the second reference data to generate the second bit COM2<2> of the second comparison signal. Mutual exclusion OR operator 193_16 can perform a logical mutual exclusion OR operation on the sixteenth bit DRD2<16> of the second driving data and the sixteenth bit REFD2<16> of the second reference data to generate the sixteenth bit COM2<16> of the second comparison signal.

[0089] FIG34 is a circuit diagram of a compression circuit 185A according to an example of the compression circuit 185 shown in FIG31. As shown in FIG34, the compression circuit 185A may include a plurality of mutual exclusion OR operators 195_1 to 195_16. Mutual exclusion OR operator 195_1 can perform a logical mutual exclusion OR operation on the first bit COM1<1> of the first comparison signal COM1 and the first bit COM2<1> of the second comparison signal COM2 to generate the first bit TD1<1> of the first test data. Mutual exclusion OR operator 195_2 can perform a logical mutual exclusion OR operation on the second bit COM1<2> of the first comparison signal COM1 and the second bit COM2<2> of the second comparison signal COM2 to generate the second bit TD1<2> of the test data. Mutual exclusion OR operator 195_16 can perform a logical mutual exclusion OR operation on the sixteenth bit COM1<16> of the first comparison signal COM1 and the sixteenth bit COM2<16> of the second comparison signal COM2 to generate the sixteenth bit TD1<16> of the test data.

[0090] Figures 35 and 36 are diagrams illustrating the operation of the compression circuit 185A shown in Figure 34.

[0091] As shown in Figure 35, when the first to sixteenth bits of the first comparison signal COM1<1:16> are all set to a logic "low" level, and the first to sixteenth bits of the second comparison signal COM2<1:16> are all set to a logic "low" level, the first to sixteenth bits of the test data TDQ<1:16> are all generated as logic "low" levels. Based on the first to sixteenth bits of the test data TDQ<1:16> that are all generated as logic "low" levels, it can be confirmed that the memory blocks MB included in the first memory block array 121 and the memory blocks MB included in the second memory block array 123 do not contain faults. More specifically, based on the first to sixteenth bits of the test data generated in the pre-test being all set to a logic "low" level, it can be confirmed that the memory blocks MB included in the first memory block array 121 and the memory blocks MB included in the second memory block array 123 do not contain faults. Furthermore, since the first to sixteenth bits of the test data generated in the subsequent test were all set to the logic "low" level, it can be confirmed that the faults in the memory block MB included in the first memory block array 121 and the memory block MB included in the second memory block array 123 have been properly repaired.

[0092] As shown in Figure 36, when the first bit of the first comparison signal COM1<1> is set to a logic "high" level, the second to sixteenth bits of the first comparison signal COM1<2:16> are all set to a logic "low" level, and the first to sixteenth bits of the second comparison signal COM2<1:16> are all set to a logic "low" level. The first bit of the test data TDQ<1> is generated as a logic "high" level, and the second to sixteenth bits of the test data TDQ<2:16> are all generated as logic "low" levels. Based on the fact that the first bit of the test data TDQ<1> is generated as a logic "high" level, it can be confirmed that the first memory block MB included in the first memory block array 121 and the first memory block MB included in the second memory block array 123 contain faults. More specifically, based on the first bit TDQ<1> of the test data generated at the logic "high" level in the pre-test, it can be confirmed that faults exist in the first memory block MB included in the first memory block array 121 and the first memory block MB included in the second memory block array 123. Furthermore, based on the first bit TDQ<1> of the test data generated at the logic "high" level in the subsequent test, it can be confirmed that the faults in the first memory block MB included in the first memory block array 121 and the first memory block MB included in the second memory block array 123 have not been properly repaired.

[0093] As described above, the semiconductor device of this disclosure reduces the number of redundant fuses required for repair operations by implementing redundant fuses corresponding to multiple row lines, thereby reducing the layout area required for implementing redundant fuses. Furthermore, before performing a repair operation, the semiconductor device of this disclosure compresses the data output from the memory block from which the repair operation is performed and confirms the presence of faulty cells, thereby reducing the time required to perform pre-tests to check for faulty cells that need repair. Moreover, after performing a repair operation, the semiconductor device of this invention compresses the data output from the same row line of multiple memory blocks to confirm the presence of faulty cells, thereby reducing the time required to perform post-tests to confirm whether the repair operation of the faulty cells has been correctly performed.

[0094] The concept has been disclosed in conjunction with some embodiments as described above. It will be understood by those skilled in the art to which this invention pertains that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a limiting rather than illustrative perspective. The scope of the concept is not limited to the above description but is defined by the claims appended, and all distinctive features within the equivalent scope should be interpreted as being included in the concept. [Simplified Explanation of the Diagram]

[0007] [Fig. 1] is a block diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure. [Fig. 2] is a block diagram illustrating the configuration of an example of a memory group included in the semiconductor device shown in Fig. 1 and an example of a row line selection circuit. [Fig. 3] is a block diagram illustrating the configuration of an example of a memory block included in the memory group shown in Fig. 2. [Fig. 4] is a block diagram illustrating the configuration of an example of a redundant memory block included in the memory group shown in Fig. 2. [Fig. 5] is a block diagram illustrating the configuration of an example of a fuse latch circuit included in the semiconductor device shown in Fig. 1. [Figs. 6, 7, 8, 9, 10 and 11] are diagrams for illustrating a repair operation performed based on redundant fuse data in the semiconductor device shown in Fig. 1. [Figs. 12, 13 and 14] are diagrams for explaining a repair operation performed based on normal fuse data in the semiconductor device shown in Fig. 1. [Fig. 15] is a diagram illustrating a repair operation performed based on redundant fuse data and normal fuse data. [Figure 16] is a block diagram illustrating the configuration of an example of a test row address generator included in the semiconductor device shown in Figure 1. [Figures 17 and 18] are diagrams illustrating pre-test operations performed before a repair operation. [Figures 19 and 20] are diagrams illustrating post-test operations performed after a repair operation. [Figure 21] is a block diagram illustrating the configuration of an example of a shift control circuit included in the semiconductor device shown in Figure 1. [Figure 22] is a circuit diagram illustrating an example of a shift signal generator included in the shift control circuit shown in Figure 21. [Figure 23] is a table illustrating the operation of the shift control circuit shown in Figures 21 and 22. [Figure 24] is a block diagram illustrating the configuration of an example of an input / output control circuit included in the semiconductor device shown in Figure 1. [Figure 25] is a diagram illustrating the configuration of an example of a first input / output shift circuit and a first drive circuit shown in Figure 24. [Figures 26 and 27] are diagrams for explaining the shift operation performed based on the first shift signal in Figure 25. [Figure 28] is a diagram illustrating the configuration of an example of the second input / output shift circuit and the second drive circuit shown in Figure 24. [Figures 29 and 30] are diagrams for explaining the shift operation performed based on the second shift signal in Figure 28. [Figure 31] is a block diagram illustrating the configuration of an example of a test data generator included in the semiconductor device shown in Figure 1. [Figure 32] is a circuit diagram of an example of a first comparator included in the test data generator shown in Figure 31. [Figure 33] is a circuit diagram of an example of a second comparator included in the test data generator shown in Figure 31. [Figure 34] is a circuit diagram of an example of a compression circuit included in the test data generator shown in Figure 31. [Figures 35 and 36] are diagrams for illustrating the operation of the compression circuit shown in Figure 34.

Claims

1. A semiconductor device, comprising: The memory block includes a first memory block, a second memory block, and a redundant memory block; And a row line selection circuit, configured to: when a fault occurs in the first row line of the first memory block, control a first repair operation to replace the first row line of the first memory block with a first redundant line of the redundant memory block, and simultaneously execute a second repair operation to replace the second row line of the second memory block with a second redundant line of the redundant memory block, wherein when the first repair operation and the second repair operation are executed simultaneously, the first repair operation is executed within a first time interval, the second repair operation is executed within a second time interval, and the first time interval and the second time interval at least partially overlap each other.

2. The semiconductor device as claimed in claim 1, wherein, The memory group includes a first memory block array and a second memory block array, wherein the first memory block is included in the first memory block array and the second memory block is included in the second memory block array.

3. The semiconductor device as claimed in claim 2, wherein, The row selection circuit selects at least one of the first memory block array and the second memory block array based on the block array address.

4. The semiconductor device as claimed in claim 1, wherein, The row selection circuit selects at least one of the first memory block and the second memory block based on the block address.

5. The semiconductor device as claimed in claim 1, wherein, The row line selection circuit selects one of the first row line and the second row line based on the row address, wherein the first row line is selected when the row address has a first set of logic bits, and the second row line is selected when the row address has a second set of logic bits, and wherein the second set of logic bits is set by inverting at least one bit in the first set of logic bits.

6. The semiconductor device as claimed in claim 1, wherein, The row line selection circuit selects one of the first row line and the second row line based on the row address, wherein the first row line is selected when the row address has a first set of logic bits, and the second row line is selected when the row address has a second set of logic bits, and wherein the second set of logic bits is set by inverting the most significant bit in the bits included in the first set of logic bits.

7. The semiconductor device as claimed in claim 1, wherein, The first memory block includes a first set of row lines and a second set of row lines, and the second memory block includes a third set of row lines and a fourth set of row lines, wherein when the most significant bit of the row address is at a first logic level, the first set of row lines and the third set of row lines are selected, and when the most significant bit of the row address is at a second logic level, the second set of row lines and the fourth set of row lines are selected.

8. The semiconductor device as claimed in claim 7, wherein, When the first row line is included in the first row line set, the second row line is included in the fourth row line set.

9. The semiconductor device as claimed in claim 7, wherein, When the first row line is included in the second row line set, the second row line is included in the third row line set.

10. The semiconductor device of claim 1, further comprising redundant fuse latches corresponding to the first row line and the second row line, wherein, The redundant fuse latch stores redundant fuse data including information about the first memory block and information about the first row line, and applies the redundant fuse data to the row line selection circuit.

11. The semiconductor device as claimed in claim 1, wherein, When a fault occurs in the second row line of the first memory block, the row line selection circuit uses the first redundant line of the redundant memory block to replace the second row line of the first memory block, and uses the second redundant line of the redundant memory block to replace the first row line of the second memory block.

12. A semiconductor device, comprising: A test row address generator is configured to generate a first test row address and a second test row address based on the row address; The system also includes a core circuit configured to control the simultaneous execution of a first repair operation for a first memory block array and a second repair operation for a second memory block array based on block array addresses, block addresses, and row addresses. The system selects one of the row lines of each memory block in the first memory block array based on the first test row address to output first memory block data, and selects one of the row lines of each memory block in the second memory block array based on the second test row address to output second memory block data. When the first repair operation and the second repair operation are executed simultaneously, the first repair operation is executed within a first time interval, the second repair operation is executed within a second time interval, and the first time interval and the second time interval at least partially overlap.

13. The semiconductor device as claimed in claim 12, wherein, In the pre-test performed before the first repair operation and the second repair operation, the test line address generator generates the first test line address and the second test line address, which are configured to have different sets of logical bits.

14. The semiconductor device as claimed in claim 13, wherein, The test row address generator generates the first test row address based on the row address, and transforms at least one of the bits included in the row address to generate the second test row address.

15. The semiconductor device as claimed in claim 12, wherein, In the post-test performed after the first repair operation and the second repair operation, the test line address generator generates the first test line address and the second test line address, which are set to have the same set of logical bits.

16. The semiconductor device as claimed in claim 12, wherein, The core circuit includes a memory group, wherein the memory group includes: a first memory block included in the first memory block array, a second memory block included in the second memory block array, and a redundant memory block.

17. The semiconductor device as claimed in claim 12, wherein, The core circuit includes a row line selection circuit, wherein when a fault occurs in a first row line of the first memory block included in the first memory block array, the row line selection circuit controls a first repair operation and a second repair operation to be performed together, the first repair operation using a first redundant line of a redundant memory block to replace the first row line of the first memory block, and the second repair operation using a second redundant line of the redundant memory block to replace the second row line of the second memory block included in the second memory block array.

18. The semiconductor device as claimed in claim 17, wherein, The row line selection circuit selects one of the first row line and the second row line based on the row address, wherein the first row line is selected when the row address has a first set of logic bits, and the second row line is selected when the row address has a second set of logic bits, and wherein the second set of logic bits is set by inverting at least one bit in the first set of logic bits.

19. The semiconductor device as claimed in claim 17, wherein, The first memory block includes a first set of row lines and a second set of row lines, and the second memory block includes a third set of row lines and a fourth set of row lines, wherein when the most significant bit of the row address is at a first logic level, the first set of row lines and the third set of row lines are selected, and when the most significant bit of the row address is at a second logic level, the second set of row lines and the fourth set of row lines are selected.

20. The semiconductor device as claimed in claim 19, wherein, When the first row line is included in the first row line set, the second row line is included in the fourth row line set.

21. The semiconductor device as claimed in claim 19, wherein, When the first row line is included in the second row line set, the second row line is included in the third row line set.

22. The semiconductor device as claimed in claim 17, wherein, The core circuit further includes a redundant fuse latch, wherein the redundant fuse latch corresponds to the first row line and the second row line, stores redundant fuse data including information about the first memory block and information about the first row line, and applies the redundant fuse data to the row line selection circuit.

23. The semiconductor device as claimed in claim 17, wherein, When a fault occurs in the second row line of the first memory block, the row line selection circuit controls a third repair operation and a fourth repair operation to be performed together. The third repair operation uses the first redundant line of the redundant memory block to replace the second row line of the first memory block, and the fourth repair operation uses the second redundant line of the redundant memory block to replace the first row line of the second memory block.

24. The semiconductor device as claimed in claim 12, wherein, The core circuit repairs at least one memory block and outputs redundant memory block data, in which a fault has occurred in a row line selected based on the first test row address included in the first memory block array.

25. The semiconductor device of claim 24, further comprising shift control circuitry, wherein, The shift control circuit generates a first shift signal, which is activated when at least one memory block included in the first memory block array contains a faulty cell and the faulty cell is repaired based on the first test row address.

26. The semiconductor device of claim 24, further comprising input / output control circuitry, wherein, The input / output control circuit includes a first input / output shift circuit, which outputs the first memory block data based on the first shift signal, or shifts and outputs the redundant memory block data and a portion of the first memory block data.

27. The semiconductor device as claimed in claim 26, wherein, When the first shift signal is deactivated, the input / output control circuit outputs the first memory block data, and when the first shift signal is activated, the input / output control circuit shifts and outputs the redundant memory block data and a portion of the first memory block data.

28. The semiconductor device as claimed in claim 26, wherein, The input / output control circuit further includes a first driving circuit, wherein the first driving circuit generates a first driving signal based on the first memory block data received when the first shift signal is deactivated, and generates the first driving signal based on a portion of the redundant memory block data and the first memory block data that are shifted and received when the first shift signal is activated.

29. The semiconductor device as claimed in claim 12, wherein, The core circuit is configured to: repair at least one memory block that has failed in a row line selected based on the first test row address among the memory blocks included in the first memory block array; or output redundant memory block data when repairing at least one memory block that has failed in a row line selected based on the second test row address among the memory blocks included in the second memory block array.

30. The semiconductor device of claim 29, further comprising shift control circuitry, wherein, The shift control circuit includes: a fuse data decoder that generates a fuse flag, fuse row data, and fuse latch signal based on the redundant fuse data; and a shift signal generator that generates a first shift signal and a second shift signal based on the fuse flag, the fuse row data, and the fuse latch signal.

31. The semiconductor device as claimed in claim 29, further comprising input / output control circuitry, wherein, The input / output control circuit generates first drive data and second drive data from the first memory block data, the second memory block data, and the redundant memory block data based on the first shift signal and the second shift signal.

32. The semiconductor device of claim 31, further comprising a test data generator, wherein, The test data generator compares the first driving data with the first reference data to generate a first comparison signal, compares the second driving data with the second reference data to generate a second comparison signal, and compresses the first comparison signal and the second comparison signal to generate test data.

33. A semiconductor device, comprising: The core circuit is configured to: control the simultaneous execution of a first repair operation on a first memory block array and a second repair operation on a second memory block array based on the block array address, block address, and row address; select one of the row lines of each memory block included in the first memory block array based on a first test row address to output first memory block data; select one of the row lines of each memory block included in the second memory block array based on a second test row address to output second memory block data; and output redundant memory block data when the repair operation is performed on the first memory block array based on the first test row address or on the second memory block array based on the second test row address. An input / output control circuit configured to generate first drive data and second drive data from first memory block data, second memory block data, and redundant memory block data based on a first shift signal and a second shift signal; and a test data generator configured to compare the first drive data with first reference data to generate a first comparison signal, compare the second drive data with second reference data to generate a second comparison signal, and compress the first comparison signal and the second comparison signal to generate test data, wherein when the first repair operation and the second repair operation are performed simultaneously, the first repair operation is performed within a first time interval, the second repair operation is performed within a second time interval, and the first time interval and the second time interval at least partially overlap each other.

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