Package comprising metal layer configured for electromagnetic interference shield and heat dissipation

Abstract

A package includes a substrate, an integrated device coupled to the substrate, an encapsulation layer on the substrate, at least one encapsulation layer interconnect in the encapsulation layer, and a metal layer on the encapsulation layer. The substrate includes at least one dielectric layer and a plurality of interconnects. The encapsulation layer interconnects are coupled to the substrate. The metal layer is configured as an electromagnetic interference (EMI) shield for the package. The metal layer is located on the back side of the integrated device.

Description

[Technical Field]

[0001] This patent application claims priority and benefit to non-provisional application S / N. 17 / 191,550 filed on March 3, 2021, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein in their entirety and for all applicable purposes.

[0002] Various features relate to the packaging of integrated devices and substrates. [Previous Technology]

[0003] Figure 1 illustrates a package 100 including a substrate 102, an integrated device 104, and an integrated device 106. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. A plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. A plurality of solder interconnects 164 are coupled to the substrate 102 and the integrated device 106. When the integrated devices 104 and 106 are operated, they generate heat. The accumulation of heat can affect the performance of the integrated devices 104 and 106. Therefore, there is a need for a package that can adequately and sufficiently dissipate heat from the integrated device. [Summary of the Invention]

[0004] Various features relate to the packaging of integrated devices and substrates.

[0005] One example provides a package including a substrate, an integrated device coupled to the substrate, an encapsulation layer on the substrate, at least one encapsulation layer interconnect in the encapsulation layer, and at least one metal layer on the encapsulation layer. The substrate includes at least one dielectric layer and a plurality of interconnects. The encapsulation layer interconnects are coupled to the substrate. The at least one metal layer is configured as an electromagnetic interference (EMI) shield for the package. The at least one metal layer is located on the back side of the integrated device.

[0006] Another example provides an apparatus including a substrate, an integrated device coupled to the substrate, an encapsulation device located on the substrate, an encapsulation layer interconnection device located within the encapsulation device, and an electromagnetic interference (EMI) shielding device located on the encapsulation layer. The substrate includes at least one dielectric layer and a plurality of interconnections. The encapsulation layer interconnection device is coupled to the substrate. The EMI shielding device is located on the back side of the integrated device.

[0007] Another example provides a package including a substrate, an integrated device coupled to the substrate, an encapsulation layer on the substrate, at least one encapsulation layer interconnect in the encapsulation layer, wherein the encapsulation layer interconnect is coupled to the substrate; and at least one thermal dielectric layer on the encapsulation layer, wherein the at least one thermal dielectric layer is located on the back side of the integrated device. The substrate includes at least one dielectric layer and a plurality of interconnects.

[0008] Another example provides a method for manufacturing a package. The method provides a substrate including at least one dielectric layer and a plurality of interconnects. The method couples an integrated device to the substrate. The method forms an encapsulation layer over the substrate. The method forms at least one encapsulation layer interconnect within the encapsulation layer, wherein the at least one encapsulation layer interconnect is coupled to the substrate. The method forms at least one metal layer over the encapsulation layer. The at least one metal layer is configured as an electromagnetic interference (EMI) shield for the package. The at least one metal layer is located on the back side of the integrated device.

[0009] Another example provides a package including a substrate, an integrated device coupled to the substrate, an encapsulation layer on the substrate, at least one encapsulation layer interconnect in the encapsulation layer, and at least one electrical dielectric layer on the encapsulation layer. The substrate includes at least one dielectric layer and a plurality of interconnects. The encapsulation layer interconnects are coupled to the substrate. The at least one electrical dielectric layer is configured as a thermal management layer for the package. The at least one electrical dielectric layer is located on the back side of the integrated device.

Implementation Method

[0026] In the following description, specific details are provided to provide a thorough understanding of the various forms of this invention. However, those skilled in the art will understand that these forms can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring these forms in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring these forms of this invention.

[0027] This application describes a package including a substrate, an integrated device coupled to the substrate, an encapsulation layer located on the substrate, at least one encapsulation layer interconnect located in the encapsulation layer, and at least one metal layer located on the encapsulation layer. The substrate includes at least one dielectric layer and a plurality of interconnects. The encapsulation layer interconnects are coupled to the substrate. The package may also include at least one thermal dielectric layer located between the at least one metal layer and the integrated device. The at least one metal layer is configured as an electromagnetic interference (EMI) shield for the package. The at least one metal layer is located on the back side of the integrated device. The at least one metal layer is coupled to ground. The integrated device generates heat as an undesirable byproduct during normal operation. In some implementations, most of the heat generated by the integrated device is dissipated via thermal conduction through (i) the back side of the integrated device, (ii) at least one metal layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects on the substrate. Therefore, the package described in this case describes a configuration that helps protect the package from EMI and helps reduce and dissipate heat that can be generated by the integrated device, which in turn helps maintain optimal operation of the integrated device and the package. An exemplary package includes a substrate, an integrated device, and a metal layer configured for electromagnetic interference (EMI) shielding and heat dissipation.

[0028] Figure 2 illustrates a cross-sectional view of a package 200 including a substrate 202, integrated device 204, integrated device 206, integrated device 208, passive component 207, encapsulation layer 209, and metal layer 210. In some implementations, package 200 may be an integrated circuit (IC) package, such as a system-in-package (SiP) or a wafer-level package (CSP). In some implementations, package 200 may be configured as a radio frequency front-end (RFFE) package including a radio frequency (RF) filter.

[0029] The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnects 221 (e.g., substrate interconnects). The substrate 202 may also include a solder mask layer 226 located above the bottom of the substrate 202. A plurality of solder interconnects 230 are coupled to the bottom of the substrate 202. The plurality of solder interconnects 230 may be coupled to a plurality of interconnects 221. Different implementations may include different types of substrates. The substrate 202 may include a cored substrate, a coreless substrate, a ceramic substrate, and / or a laminated substrate.

[0030] Integrated devices 204, 206, 208, and passive components 207 (e.g., individual capacitors) are coupled to a first surface (e.g., top surface) of substrate 202. Integrated device 204 is coupled to a plurality of interconnects 221 of substrate 202 via a plurality of solder interconnects 240. Integrated device 206 is coupled to a plurality of interconnects 221 of substrate 202 via a plurality of solder interconnects 260. Integrated device 208 is coupled to a plurality of interconnects 221 of substrate 202 via a plurality of solder interconnects 280. Passive component 207 is coupled to a plurality of interconnects 221 of substrate 202. In some implementations, a plurality of solder pillar interconnects and solder interconnects may be used to couple the integrated devices (e.g., 204, 206, 208) to the plurality of interconnects 221.

[0031] Package 200 also includes a plurality of through-hole vias (TMVs) 211 and a plurality of wire bonds 212. The plurality of TMVs 211 and / or the plurality of wire bonds 212 are examples of a plurality of encapsulation interconnects (e.g., means for encapsulation interconnects). The plurality of TMVs 211 are coupled to substrate 202. Specifically, the plurality of TMVs 211 are coupled to a plurality of interconnects 221. Similarly, the plurality of wire bonds 212 are coupled to substrate 202. Specifically, the plurality of wire bonds 212 are coupled to a plurality of interconnects 221. The plurality of through-hole vias 211 (TMVs) and the plurality of wire bonds 212 are located (e.g., embedded) in encapsulation layer 209. A plurality of through-holes 211 (TMVs) and a plurality of wire bonds 212 may be at least partially encapsulated by an encapsulation layer 209. The plurality of through-holes 211 (TMVs) and / or the plurality of wire bonds 212 are located on the sides of the integrated device(s) (e.g., 204, 206, 208) and the passive component 207.

[0032] As will be further described below, a plurality of through-hole vias 211 (TMVs) and / or a plurality of wire bonds 212 may laterally surround one or more integrated devices, such as forming a fence or boundary around one or more integrated devices. At least one encapsulation interconnect (e.g., TMV 211, wire bond 212) is configured as at least one compartmentalized EMI shield for package 200. The plurality of through-hole vias 211 (TMVs) and / or a plurality of wire bonds 212 are configured to couple to ground. The plurality of through-hole vias 211 (TMVs) and / or a plurality of wire bonds 212 are configured to operate as a conformal EMI shield for package 200. Furthermore, as will be further described below, the plurality of through-hole vias 211 (TMVs) and / or a plurality of wire bonds 212 are configured to facilitate heat dissipation (e.g., aiding in heat dissipation from one or more integrated devices).

[0033] Encapsulation layer 209 is located on a first surface of substrate 202. Encapsulation layer 209 may at least partially encapsulate integrated devices (e.g., 204, 206, 208), passive components 207, a plurality of through-hole vias 211 (TMVs), and / or a plurality of wire bonds 212. Encapsulation layer 209 may encapsulate at least one encapsulation layer interconnect (e.g., TMV 211, wire bond 212). Encapsulation layer 209 may comprise molding compound, resin, and / or epoxy resin. Compression molding, transfer molding, or liquid molding processes may be used to form encapsulation layer 209. Encapsulation layer 209 may be photoetchable. Encapsulation layer 209 may be a device for encapsulation.

[0034] The metal layer 210 is located on the top surface of the encapsulation layer 209 and / or the back side of the integrated devices 204 and 206. The metal layer 210 is coupled to the encapsulation layer 209 and the back side of the integrated devices 204 and 206. Furthermore, the metal layer 210 is coupled to a plurality of TMVs 211 and a plurality of wire bonds 212. Thus, the metal layer 210 is coupled to at least one encapsulation layer interconnect. The metal layer 210 is located on the side surface of the substrate 200. For example, the metal layer 210 is located on and / or coupled to the side surface of the encapsulation layer 209 and / or the side surface of the substrate 202. The metal layer 210 may include one or more metal layers.

[0035] Metal layer 210 is configured to operate as an electromagnetic interference (EMI) shielding element for package 200 (e.g., a device for EMI shielding, a conformal EMI shielding element, a device for conformal EMI shielding). Metal layer 210 is configured to be coupled to ground. Metal layer 210 is also configured to dissipate heat from one or more integrated devices (e.g., 204, 206) via conduction.

[0036] Different implementations may use different materials for metal layer 210. For example, metal layer 210 may include copper. In some implementations, metal layer 210 may be replaced by at least one electrical medium layer (e.g., one or more electrical medium layers). The electrical medium layer may replace any other metal layer (e.g., 410) described herein. The at least one electrical medium layer may perform the same function as the metal layer (e.g., 210, 410). The at least one electrical medium layer may be configured as a thermal management layer for packaging. A means for electromagnetic interference (EMI) shielding may include at least one electrical medium layer.

[0037] Integrated devices (e.g., 204, 206) are configured to generate heat. Heat buildup in integrated devices can lead to suboptimal integrated device performance and / or device failure. Therefore, it is important to reduce and dissipate heat from integrated devices. The package 200 is designed and configured such that the metal layer 210, a plurality of TMVs 211, a plurality of wire bonds 212, and / or a plurality of interconnects 221 provide thermal paths for efficient and effective heat dissipation from the integrated device. In some implementations, most of the heat generated (e.g., individually and / or collectively) by the integrated devices (e.g., 204, 206) is dissipated via thermal conduction through (i) the back side of the integrated devices (e.g., 204, 206), (ii) the metal layer 210, (iii) at least one encapsulation layer interconnect (e.g., TMV 211, wire bond 212), and / or (iv) a plurality of interconnects 221 of the substrate 202. In some implementations, at least twenty percent (20%) of the heat generated (e.g., individually and / or collectively) by the integrated devices (e.g., 204, 206) is dissipated via thermal conduction through (i) the back side of the integrated devices (e.g., 204, 206), (ii) the metal layer 210, (iii) at least one encapsulation layer interconnect (e.g., TMV 211, wire bonding 212), and / or (iv) a plurality of interconnects 221 of the substrate 202. Examples of thermal paths and / or heat fluxes in the package are further illustrated and described below, at least in Figures 9 and 10.

[0038] Integrated devices (e.g., 204, 206, 208) may include dies (e.g., semiconductor bare dies). Integrated devices may include: radio frequency (RF) devices, passive devices, filters, capacitors, inductors, resistors, antennas, transmitters, receivers, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon carbide (SiC) based integrated devices, GaAs-based integrated devices, GaN-based integrated devices, processors, memory, power amplifiers, switches, system-on-a-chip, integrated circuit devices, microelectromechanical systems (MEMS) devices, nanoelectromechanical systems (NEMS) devices, and / or combinations thereof. Integrated devices (e.g., 204, 206, 208) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0039] For example, when an integrated device (e.g., 204, 206, 208) is configured as a semiconductor integrated circuit die, the integrated device may include a substrate and a device layer including transistors configured to perform operations (e.g., logic operations). In another example, when an integrated device (e.g., 204, 206, 208) is configured as a bare die filter (e.g., a SAW filter, a BAW filter), the integrated device may include a piezoelectric substrate and at least one metal layer formed on and located on the piezoelectric substrate, the at least one metal layer being configured as at least one transducer (e.g., an interdigital transducer (IDT)).

[0040] Figure 3 illustrates a package 300 including a metal layer configured for EMI shielding and heat dissipation. Package 300 is similar to package 200 of Figure 2 and includes the same or similar components as package 200 of Figure 2. Package 300 is configured in a similar manner to that described for package 200. Package 300 also includes a thermal dielectric layer 310. Thermal dielectric layer 310 is located above encapsulation layer 209 and integrated devices 204 and 206. Thermal dielectric layer 310 is located between encapsulation layer 209 and metal layer 210. Thermal dielectric layer 310 is also located between integrated devices 204 and 206 and metal layer 210. The thermal dielectric layer 310 is coupled to the top surface of the encapsulation layer 209, the back side of the integrated device 204 (e.g., the first integrated device), the back side of the integrated device 206 (e.g., the second integrated device), a plurality of TMVs 211, and a plurality of wire bonds 212.

[0041] The thermal dielectric layer 310 is a dielectric layer configured not to conduct current, but configured to efficiently conduct heat. The thermal dielectric layer 310 is a poor conductor of electricity, but a good or above-average conductor of heat. The thermal dielectric layer 310 improves package performance by reducing electromagnetic coupling toward ground. In some implementations, the thermal dielectric layer 310 has a dielectric constant (k) of less than 40. In some implementations, the thermal dielectric layer 310 has a dielectric constant (k) of less than 15. In some implementations, the thermal dielectric layer 310 has a dielectric constant (k) of less than 10. The thermal dielectric layer 310 may have a higher thermal conductivity than the encapsulation layer 209. The thermal dielectric layer 310 may have a higher thermal conductivity than the substrate of the integrated device (e.g., 204, 206). Examples of substrates for integrated devices include LiTaO3 (with a thermal conductivity of approximately 6.69 W / (m·k)), LiNbO3 (with a thermal conductivity of approximately 4.19 W / (m·k)), and silicon (Si) (with a thermal conductivity of approximately 150 W / (m·k)). The thermal dielectric layer 310 may have a thermal conductivity greater than 4 W / (m·k). The thermal dielectric layer 310 may include refractory carbides, nitrides, and borides, and / or combinations thereof (e.g., carbonitrides). The thermal dielectric layer 310 may include oxides, such as Al2O3 (with a thermal conductivity of approximately 30 W / (m·k)). The thermal dielectric layer 310 may include AlN having a thermal conductivity of approximately 200 W / (m·k). Note that the thermal dielectric layer 310 may include one or more thermal dielectric layers. The electrical dielectric layer may have properties similar to those of the thermal dielectric layer 310.

[0042] The design and configuration of package 300 enable the metal layer 210, thermal dielectric layer 310, a plurality of TMVs 211, a plurality of wire bonds 212 and / or a plurality of interconnects 221 to provide thermal paths for efficient and effective heat dissipation from the integrated device. In some implementations, most of the heat generated (e.g., individually and / or collectively) by the integrated devices (e.g., 204, 206) is dissipated via thermal conduction through (i) the back side of the integrated devices (e.g., 204, 206), (ii) the thermal dielectric layer 310, (iii) the metal layer 210, (iv) at least one encapsulation layer interconnect (e.g., TMV 211, wire bond 212), and / or (v) a plurality of interconnects 221 of substrate 202. In some implementations, at least 20 percent (20%) of the heat generated (e.g., individually and / or collectively) by the integrated devices (e.g., 204, 206) is dissipated via thermal conduction through (i) the back side of the integrated devices (e.g., 204, 206), (ii) the thermal dielectric layer 310, (iii) the metal layer 210, (iv) at least one encapsulation layer interconnect (e.g., TMV 211, wire bonding 212), and / or (v) a plurality of interconnects 221 of the substrate 202. Examples of thermal paths and / or heat fluxes in the package are further illustrated and described below, at least in Figures 9 and 10.

[0043] FIG4 illustrates a package 400 including a metal layer configured for EMI shielding and heat dissipation. Package 400 is similar to package 300 of FIG3 and includes the same or similar components as package 300 of FIG3. Package 400 is configured in a similar manner to that described for package 300. In FIG4, package 400 includes a metal layer 410 that is not located above the side surfaces of encapsulation layer 209 and the side surfaces of substrate 202. As shown in FIG4, metal layer 410 is located above the top surfaces of encapsulation layer 209 and thermal dielectric layer 310. Metal layer 410 is similar to metal layer 210, as described in FIG2 and 3.

[0044] FIG. 5 illustrates a package 500 including a metal layer configured for EMI shielding and heat dissipation. Package 500 is similar to package 200 of FIG. 2 and includes the same or similar components as package 200 of FIG. 2. Package 500 is configured in a similar manner to that described for package 200. In FIG. 5, package 500 includes a metal layer 410 that is not located above the side surfaces of encapsulation layer 209 and the side surfaces of substrate 202. As shown in FIG. 5, metal layer 410 is located above the top surface of encapsulation layer 209. Metal layer 410 is similar to metal layer 210, as described in FIG. 2.

[0045] Figure 6 illustrates a package 600 including a thermal dielectric layer. Package 600 is similar to package 300 of Figure 3 and includes the same or similar components as package 300 of Figure 3. Package 600 is configured in a similar manner to that described for package 300. In Figure 6, package 600 includes a thermal dielectric layer 310. However, there is no metal layer on top of the thermal dielectric layer 310. This configuration helps limit the effects of grounding, which helps improve the performance of package 600.

[0046] FIG7 illustrates a package 700 including a thermal dielectric layer. Package 700 is similar to package 600 of FIG6 and includes the same or similar components as package 600 of FIG6. Package 700 is configured in a similar manner to that described for packages 300 and 600. In FIG7, a portion of the thermal dielectric layer 310 above the TMV 211 and / or wire bond 212 has been removed, thereby forming at least one trench 711 in the thermal dielectric layer 310. A laser process (e.g., laser ablation) may be used to remove a portion of the thermal dielectric layer 310. Removal of a portion of the thermal dielectric layer 310 is not limited to package 700. The trench 711 in the thermal dielectric layer 310 may be implemented in any package including the thermal dielectric layer 310 described herein.

[0047] This application describes a TMV and / or wire bond configured for EMI shielding within an encapsulation layer. However, in some implementations, other types of materials and / or structures may be used for EMI shielding. For example, the TMV and / or wire bond may be replaced by and / or used in combination with a pre-metallized frame, pre-metallized wall, metal can, and / or surface mount device (SMD).

[0048] Figure 8 illustrates a package 800 comprising various materials and / or structures configured for EMI shielding. Package 800 is similar to package 300 of Figure 3 and includes the same or similar components as package 300 of Figure 3. However, package 800 includes a metallized frame 811 configured for EMI shielding. Therefore, the metallized frame 811 replaces the functionality of TMV 211 and / or wire bonding 212. Part or all of the metallized frame 811 may be configured to be coupled to ground. The metallized frame 811 may be a single component or several components. The metallized frame 811 may comprise one or more materials. The metallized frame 811 is an example of one or more encapsulation interconnects (e.g., means for encapsulation interconnects). The metallized frame 811 may include a lead frame or a portion thereof.

[0049] Figures 9 and 10 illustrate examples of thermal paths and / or heat fluxes. Note that these thermal paths and / or heat fluxes do not imply that all possible thermal paths and / or heat fluxes are shown. Instead, Figures 9 and 10 are intended to show only one or more possible thermal paths and / or heat fluxes for the package. Therefore, the thermal paths and / or heat fluxes are not limited to those shown in Figures 9 and 10.

[0050] Figure 9 illustrates an example of how heat from the integrated device 204 of package 200 is dissipated (e.g., via conduction) via the back side of integrated device 204, via metal layer 210, via at least one TMV 211, and via a plurality of interconnects 221 of substrate 202. In some implementations, at least a portion of the heat may be dissipated via at least one solder interconnect 230.

[0051] FIG9 also illustrates an example of how heat from the integrated device 206 of package 200 is dissipated (e.g., via conduction) via the back side of integrated device 206, via metal layer 210, via at least one wire bond 212, and via a plurality of interconnects 221 of substrate 202. In some implementations, at least some of the heat may be dissipated via at least one solder interconnect 230.

[0052] Figure 10 illustrates an example of how heat from the integrated device 204 of package 300 is dissipated (e.g., via conduction) via the back side of integrated device 204, via thermal dielectric layer 310, via metal layer 210, via at least one TMV 211, and via a plurality of interconnects 221 of substrate 202. In some implementations, at least a portion of the heat may be dissipated via at least one solder interconnect 230.

[0053] Figure 10 also illustrates an example of how heat from the integrated device 206 of package 300 is dissipated (e.g., via conduction) via the back side of integrated device 206, via thermal dielectric layer 310, via metal layer 210, via at least one wire bond 212, and via a plurality of interconnects 221 of substrate 202. In some implementations, at least a portion of the heat may be dissipated via at least one solder interconnect 230. Other packages described in this invention can dissipate heat in a similar manner. Thus, other packages may have a heat flux that travels in a manner similar to that described in Figures 9 and 10.

[0054] The configuration and design of the package described in this application can reduce the junction temperature of an integrated device (e.g., 204, 206) by 100 Kelvin (K). Thus, for example, an integrated device in which the back side is not coupled to a metal layer or a thermal dielectric layer can achieve a junction temperature (e.g., integrated device surface temperature) 100 K higher than that of the same integrated device as described in this application, in which the back side is coupled to a metal layer and / or a thermal dielectric layer. For example, an integrated device in which the back side is not coupled to a metal layer or a thermal dielectric layer can achieve a junction temperature of approximately 300 Kelvin (e.g., integrated device surface temperature), while the same integrated device as described in this application, in which the back side is coupled to a metal layer and / or a thermal dielectric layer, can achieve a junction temperature of only 190 Kelvin (a difference of more than 100 Kelvin). The lower temperature of the integrated device helps the integrated device and package perform optimally over a longer period of time and contributes to providing a more reliable integrated device and / or package.

[0055] Another advantage of the TMV 211, wire bond 212 and / or metallization frame 811 (which are examples of encapsulation layer interconnects) is that the TMV 211, wire bond 212 and / or metallization frame 811 can be configured as EMI shielding components (e.g., compartmented EMI shielding components, devices for compartmented EMI shielding).

[0056] Figure 11 illustrates a plan view of a package 200 illustrating how TMV 211 and / or wire bonding 212 are arranged in the encapsulation layer 209. As shown in Figure 8, a plurality of TMV 211 are coupled to a substrate 202 such that the plurality of TMV 211 laterally surround the integrated device 204. The plurality of TMV 211 form a fence, boundary, and / or cage around the integrated device 204. The plurality of TMV 211 are configured to be coupled to ground. The size, shape, spacing, and / or number of TMV 211 surrounding the integrated device 204 may vary depending on the implementation. Even with gaps between the TMV 211, the plurality of TMV 211 can still provide effective EMI shielding, and the plurality of TMV 211 can still be considered to be laterally surrounding the integrated device 204.

[0057] As shown in FIG11, a plurality of wire bonds 212 are coupled to a substrate 202 such that the plurality of wire bonds 212 laterally surround an integrated device 206. The plurality of wire bonds 212 form a fence, boundary, and / or cage around the integrated device 206. The plurality of wire bonds 212 are configured to be coupled to ground. The size, shape, spacing, and / or number of wire bonds 212 surrounding the integrated device 206 may vary in different implementations. Even with gaps between the wire bonds 212, the plurality of wire bonds 212 can still provide effective EMI shielding, and the plurality of wire bonds 212 can still be considered to laterally surround the integrated device 206. In some implementations, a metallization frame 811 may laterally surround the integrated device in a similar manner. Therefore, one or more metallization frames 811 may be used instead of a plurality of TMVs 211 and / or a plurality of wire bonds 212.

[0058] Note that different packages can have different numbers of integrated devices and components. Therefore, the package is not limited by the number of integrated devices. A package may include more than two integrated devices. Furthermore, packages can mix and match different combinations of TMV, wire bonding, metallized frames, and / or SMD for EMI shielding and heat dissipation. In some implementations, only TMV is used for EMI shielding and heat dissipation. In some implementations, only wire bonding is used for EMI shielding and heat dissipation. In some implementations, only (e.g.) metallized frames are used for EMI shielding and heat dissipation.

[0059] Various packages have been described, and the processes for manufacturing the packages will now be described below. Exemplary processes for manufacturing a package including a substrate, an integrated device, and a metal layer configured for EMI shielding and heat dissipation.

[0060] Figures 12A–12D illustrate exemplary steps for providing or manufacturing a package including a metal layer configured for EMI shielding and heat dissipation. In some implementations, the steps of Figures 12A–12D may be used to provide or manufacture the package 300 of Figure 3, or any package described in this case (e.g., 200, 400, 500, 600, 700, 800).

[0061] It should be noted that the processes in Figures 12A-12D may be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of these processes may be substituted or replaced without departing from the spirit of this invention.

[0062] As shown in FIG12A, stage 1 illustrates the state after the substrate 202 has been provided or manufactured. The substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 221 (e.g., traces, pads, vias), and a solder mask layer 226. Examples of substrate manufacturing are shown and described in FIGS14A–14C. Substrate manufacturing may include lamination and plating processes. Examples of processes used for manufacturing substrates include semi-additive process (SAP) and modified semi-additive process (mSAP). However, different implementations may manufacture substrates differently. Different implementations may provide different types of substrates (e.g., coreless substrates, core substrates, embedded trace substrates (ETS), laminated substrates, ceramic substrates).

[0063] Phase 2 illustrates the state after the device and / or component is coupled to the substrate 202. For example, integrated device 204 is coupled to the substrate 202 via a plurality of solder interconnects 240. Integrated device 206 is coupled to the substrate 202 via a plurality of solder interconnects 260. Integrated device 208 is coupled to the substrate 202 via a plurality of solder interconnects 280. Passive component 207 (e.g., capacitor) may be coupled to the substrate 202. Pick-and-place processes may be used to couple the device and / or component. Reflow soldering processes may be used to couple the integrated device and / or component.

[0064] Stage 3 illustrates the state after wire bonding. During wire bonding, a plurality of wire bonds 212 may be coupled to substrate 202. The plurality of wire bonds 212 may be coupled to a plurality of interconnects 221. The plurality of wire bonds 212 may laterally surround at least one integrated device (e.g., 206). When a metallization frame (e.g., 811) is used, the metallization frame may be coupled to substrate 202.

[0065] As shown in FIG12B, stage 4 illustrates an encapsulation layer 209 formed over substrate 202, integrated device 204, and integrated device 206. Encapsulation layer 209 may be an encapsulation device. Compression molding, transfer molding, or liquid molding processes may be used to form encapsulation layer 209. Encapsulation layer 209 may at least partially encapsulate integrated device 204, integrated device 206, and wire bond 212.

[0066] Stage 5 illustrates the state after a portion of the encapsulation layer 209 has been removed. The encapsulation layer 209 can be removed via a polishing process. In some implementations, some portions of the encapsulation layer 209 can be polished so that the encapsulation layer 209 is flush with the back side of one or more integrated devices. The encapsulation layer 209 can at least partially encapsulate integrated device 204, integrated device 206, and wire bond 212.

[0067] Stage 6 illustrates the state after a plurality of cavities 911 have been formed in the encapsulation layer 209. Laser processing and / or etching processes may be used to form the plurality of cavities. The cavities 911 may extend through the encapsulation layer 209 and expose a portion of the substrate 202.

[0068] As shown in FIG12C, stage 7 illustrates the state after a plurality of TMVs 211 have been formed in a plurality of cavities 911 of the encapsulation layer 209. A plating process may be applied to the plurality of TMVs 211. The plurality of TMVs 211 may laterally surround at least one integrated device (e.g., 204). In some implementations, a polishing process may be used to remove portions of the encapsulation layer 209, portions of the plurality of wire bonds 212, and / or portions of the TMVs 211, such that the encapsulation layer 209, the plurality of TMVs 211, and the plurality of wire bonds 212 are flush with the back side of at least one integrated device (e.g., 204, 206).

[0069] Stage 8 illustrates a state after the thermal dielectric layer 310 is optionally formed on the back side of the encapsulation layer 209, at least one integrated device (e.g., 204, 206), a plurality of TMVs 211, and a plurality of wire bonds 212. A deposition process can be used to form the thermal dielectric layer 310 and couple it to the back side of the encapsulation layer 209, at least one integrated device (e.g., 204, 206), a plurality of TMVs 211, and a plurality of wire bonds 212. In some implementations, the thermal dielectric layer 310 may include several dielectric layers. Stage 8 may illustrate a package 600 as described in FIG. 6. In some implementations, a laser process may be used to remove portions of the thermal dielectric layer 310 to fabricate a package 700 as described in FIG. 7.

[0070] As shown in FIG12D, stage 9 illustrates the state after a metal layer 210 has been formed over the thermal dielectric layer 210, the encapsulation layer 209, the back side of at least one integrated device (e.g., 204, 206), a plurality of TMVs 211, and a plurality of wire bonds 212. Electroplating and / or sputtering processes can be used to form the metal layer 210 and couple it to the thermal dielectric layer 310. When the thermal dielectric layer 310 is not present, the metal layer 210 can be formed and coupled to the encapsulation layer 209, the back side of at least one integrated device (e.g., 204, 206), a plurality of TMVs 211, and a plurality of wire bonds 212. In the example of stage 9 in FIG12D, the metal layer 210 can also optionally be formed over the side surface of the encapsulation layer 209 and the side surface of the substrate 202. However, the metal layer 210 can be formed differently on the package via different implementations. As mentioned above, metal layer 210 can be configured for EMI shielding and heat dissipation. Stage 9 can be illustrated as package 300 as depicted in Figure 3.

[0071] Stage 10 illustrates the state after the plurality of solder interconnects 230 are coupled to the substrate 202. The plurality of solder interconnects 230 may be coupled to the plurality of interconnects 221 via a reflow soldering process. Stage 10 may illustrate the package 300 as described in FIG3. An exemplary flowchart of a method for manufacturing a package including a substrate, an integrated device, and a metal layer configured for EMI shielding and heat dissipation.

[0072] In some implementations, manufacturing a package including a metal layer configured for EMI shielding and heat dissipation includes several processes. Figure 13 illustrates an exemplary flowchart of a method 1300 for providing or manufacturing a package including a metal layer configured for EMI shielding and heat dissipation. In some implementations, method 1300 of Figure 13 can be used to provide or manufacture the package 300 of Figure 3 described in this document. However, method 1300 can be used to provide or manufacture any package described in this document (e.g., 200, 400, 500, 600, 700, 800).

[0073] It should be noted that the processes in Figure 13 can be combined into one or more processes to simplify and / or clarify the method used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified.

[0074] The method (at 1305) provides a substrate (e.g., 202). This substrate may be provided or manufactured. The substrate may include at least one dielectric layer 220, a plurality of interconnects 221 (e.g., traces, pads, vias), and a solder mask layer 226. Examples of substrate fabrication are shown and described in Figures 14A–14C. Substrate fabrication may include lamination and plating processes. Examples of processes used for substrate fabrication include semi-additive process (SAP) and modified semi-additive process (mSAP). However, different implementations may fabricate substrates differently. Different implementations may provide different types of substrates (e.g., coreless substrates, core substrates, embedded trace substrates (ETS), laminated substrates, ceramic substrates). Stage 1 of Figure 12A illustrates and describes an example of a substrate.

[0075] The method (at 1310) couples at least one device (e.g., 204, 206, 208) to a substrate (e.g., 202). A passive component (e.g., 207) may also be coupled to substrate 202. A pick-and-place process may be used to couple at least one integrated device and at least one component to the substrate. Phase 2 of FIG12A illustrates and describes an example of coupling an integrated device and a component to a substrate.

[0076] Optionally, the method may (at 1315) provide wire bonding (e.g., 212). Providing wire bonding includes coupling a plurality of wire bonds 212 to a substrate 202. The plurality of wire bonds 212 may be coupled to a plurality of interconnects 221. The plurality of wire bonds 212 may laterally surround at least one integrated device (e.g., 206). Stage 3 of FIG12A illustrates and describes an example of providing wire bonding. In some implementations, the method may (at 1315) couple a metallization frame (e.g., 811) and / or an SMD to the substrate 202.

[0077] This method (at 1320) forms an encapsulation layer (e.g., 209) on a substrate. The encapsulation layer 209 may be formed on the substrate 202, the integrated device 204, and the integrated device 206. Compression molding, transfer molding, or liquid molding processes may be used to form the encapsulation layer 209. In some implementations, some of the encapsulation layers 209 may be polished such that the encapsulation layer 209 is flush with the back side of one or more integrated devices. The encapsulation layer 209 may at least partially encapsulate the integrated device 204, the integrated device 206, and the wire bond 212. Stages 4 and 5 of FIG12B illustrate and describe examples of forming and polishing the encapsulation layer.

[0078] This method (at 1325) forms cavities (e.g., 911) in an encapsulation layer (e.g., 209). Laser processing and / or etching processes can be used to form a plurality of cavities 911. The plurality of cavities 911 may extend through the encapsulation layer 209 and expose a portion of the substrate 202. Stage 6 of FIG12B illustrates and describes an example of forming cavities in an encapsulation layer.

[0079] The method (at 1330) forms at least one encapsulation interconnect in a cavity of the encapsulation layer. Forming the encapsulation interconnect may include forming a plurality of TMVs 211 in a plurality of cavities 911 of the encapsulation layer 209. A plating process may be used for the plurality of TMVs 211. The plurality of TMVs 211 may laterally surround at least one integrated device (e.g., 204). In some implementations, a polishing process may be used to remove portions of the encapsulation layer 209, portions of the plurality of wire bonds 212, and / or portions of the TMVs 211, such that the encapsulation layer 209, the plurality of TMVs 211, and the plurality of wire bonds 212 are flush with the back side of at least one integrated device (e.g., 204, 206). Stage 7 of FIG12C illustrates and describes an example of forming an encapsulation interconnect.

[0080] This method (at 1335) may optionally form a thermal dielectric layer 310 over the encapsulation layer 209, the back side of at least one integrated device (e.g., 204, 206), a plurality of TMVs 211, and a plurality of wire bonds 212. A deposition process may be used to form the thermal dielectric layer 310 and couple it to the encapsulation layer 209, the back side of at least one integrated device (e.g., 204, 206), the plurality of TMVs 211, and the plurality of wire bonds 212. In some implementations, several thermal dielectric layers may be formed. Stage 8 of Figure 12C illustrates and describes an example of forming a thermal dielectric layer.

[0081] The method (at 1335) may optionally form a metal layer 210 over the thermal dielectric layer 310, the encapsulation layer 209, the back side of at least one integrated device (e.g., 204, 206), a plurality of TMVs 211, and a plurality of wire bonds 212. Electroplating and / or sputtering processes may be used to form the metal layer 210 and couple it to the thermal dielectric layer 310. When the thermal dielectric layer 310 is not present, the metal layer 210 may be formed and coupled to the encapsulation layer 209, the back side of at least one integrated device (e.g., 204, 206), a plurality of TMVs 211, and a plurality of wire bonds 212. In the example of stage 9 of FIG. 12D, the metal layer 210 may also optionally be formed over the side surface of the encapsulation layer 209 and the side surface of the substrate 202. The method may form several metal layers. However, the metal layer 210 can be formed differently on the package via different implementations. As mentioned above, the metal layer 210 can be configured for EMI shielding and heat dissipation. In some implementations, the method can (at 1335) form at least one dielectric layer over the encapsulation layer 209, the back side of at least one integrated device (e.g., 204, 206), a plurality of TMVs 211, and a plurality of wire bonds 212. Stage 9 of Figure 12C illustrates and describes an example of forming a metal layer configured for EMI shielding and heat dissipation.

[0082] This method 1300 can also couple a plurality of solder interconnects 230 to a substrate 202. The plurality of solder interconnects 230 can be coupled to a plurality of interconnects 221 via a reflow soldering process. Step 10 of Figure 12C illustrates and describes an example of solder interconnects coupled to a substrate. Exemplary process for manufacturing a substrate.

[0083] Figures 14A-14C illustrate exemplary processes for providing or manufacturing a substrate. In some implementations, the sequence of Figures 14A-14C can be used to provide or manufacture the substrate 202 of Figure 3 or any substrate described herein. As mentioned above, different implementations may use different substrates, including laminated substrates and coreless substrates (e.g., embedded trace substrates). The substrates shown in Figures 14A-14C are examples of possible substrates that can be used.

[0084] It should be noted that the processes in Figures 14A-14C may be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of these processes may be substituted or replaced without departing from the spirit of this invention.

[0085] As shown in Figure 14A, stage 1 illustrates the state after the carrier 1400 is provided. The carrier 1400 may be a substrate.

[0086] Stage 2 illustrates the state after interconnect 1402 is formed on the carrier 1400. Interconnect 1402 can be an interconnect from a plurality of interconnects 221. A plating process can be used to form interconnect 1402.

[0087] Stage 3 illustrates the state after the dielectric layer 1420 is formed on the interconnect 1402 and the carrier 1400. Deposition and / or lamination processes can be used to form the dielectric layer 1420.

[0088] Stage 4 illustrates the state after one or more cavities 1421 are formed in the dielectric layer 1420. Laser processing (e.g., laser ablation) or photolithography (e.g., photolithography) can be used to form one or more cavities 1421.

[0089] Stage 5 illustrates the state after interconnect 1422 is formed on dielectric layer 1420. Interconnect 1422 can be an interconnect from a plurality of interconnects 221. A plating process can be used to form interconnect 1422.

[0090] As shown in Figure 14B, stage 6 illustrates the state after the dielectric layer 1430 is formed on the dielectric layer 1420. The dielectric layer 1430 may be made of the same material as the dielectric layer 1420. Deposition and / or lamination processes may be used to form the dielectric layer 1430.

[0091] Stage 7 illustrates the state after one or more cavities 1431 are formed in the dielectric layer 1430. Laser processing (e.g., laser ablation) or photolithography (e.g., photolithography) can be used to form one or more cavities 1431.

[0092] Stage 8 illustrates the state after interconnect 1432 is formed on dielectric layer 1430. Interconnect 1432 can be an interconnect from a plurality of interconnects 221. A plating process can be used to form interconnect 1432.

[0093] As shown in FIG14C, stage 9 illustrates the state after dielectric layer 1440 is formed on dielectric layer 1430. The dielectric layer 1440 may be made of the same material as dielectric layer 1430. Deposition and / or lamination processes may be used to form dielectric layer 1440.

[0094] Stage 10 illustrates the state after one or more cavities 1441 are formed in the dielectric layer 1440. Laser processing (e.g., laser ablation) or photolithography (e.g., photolithography) can be used to form one or more cavities 1441.

[0095] Stage 11 illustrates the state after interconnect 1442 is formed on dielectric layer 1440. Interconnect 1442 can be an interconnect from a plurality of interconnects 221. A plating process can be used to form interconnect 1442.

[0096] Stage 12 illustrates the state after the removal of the carrier 1400. Stage 12 may illustrate a portion of the substrate 202. Dielectric layer 220 may represent dielectric layers 1420, 1430, and 1440. Interconnect 221 may represent interconnects 1402, 1422, 1432, and 1442.

[0097] It should be noted that some stages can be repeatedly performed in an iterative manner to form additional dielectric and / or metal layers (e.g., for interconnection). Exemplary electronic device

[0098] Figure 15 illustrates various electronic devices that can integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, chips, interposers, packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1502, laptop device 1504, fixed-location terminal device 1506, wearable device 1508, or motor vehicle 1510 may include the device 1500 as described herein. Device 1500 may be any of the devices and / or integrated circuit (IC) packages described herein, for example. Devices 1502, 1504, 1506, and 1508, and vehicle 1510 illustrated in Figure 15 are merely exemplary. Other electronic devices may also be characterized by device 1500, including but not limited to the group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0099] One or more of the components, programs, features, and / or functions illustrated in Figures 2-11, 12A-12D, 13, 14A-14C, and / or 15 may be rearranged and / or combined into a single component, program, feature, or function, or implemented in several components, programs, or functions. Additional components, programs, and / or functions may also be added without departing from this invention. It should also be noted that Figures 2-11, 12A-12D, 13, 14A-14C, and / or 15 and their corresponding descriptions in this invention are not limited to dies and / or ICs. In some implementations, Figures 2-11, 12A-12D, 13, 14A-14C, and / or 15 and their corresponding descriptions may be used to manufacture, build, provide, and / or produce apparatus and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, a heat dissipation device, and / or an intermediary.

[0100] Note that the accompanying drawings in this application may represent actual and / or conceptual representations of various components, parts, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are illustrated for clarity. In some instances, the positioning, location, size, and / or shape of the various components and / or parts in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0101] The term "exemplary" is used herein to mean "used as an example, illustration, or diagram." Any implementation or manner described herein as "exemplary" need not be construed as superior to or better than other manners in this case. Similarly, the term "manner" does not require that all manners in this case include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact. The term "electrical coupling" can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transferred between the two objects. Electrically coupled objects may or may not have current transferred between them. The use of the terms "first," "second," "third," and "fourth" (and / or anything higher than fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "around" means that an object can partially or completely surround another object. The term "enclose" means that an object can partially or completely enclose another object. The terms "top" and "bottom" are arbitrary. A component located at the top can be situated on top of a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this case, a first component situated "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another instance, a first component can be situated above (e.g., above) a first surface of a second component, while a third component can be situated above (e.g., below) a second surface of a second component, where the second surface is opposite the first surface. Further note that the term "above," as used in this case in the context of a component being above another component, can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, "above a second component" can mean: (1) the first component is above the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. The terms "about 'value X'" or "approximately value X" as used in this case mean within ten percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0102] In some implementations, an interconnect is an element or component in a device or package that allows or facilitates an electrical connection between two points, components, and / or components. In some implementations, an interconnect may include traces, vias, pads, solder pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. In some implementations, an interconnect is a conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may be part of a circuit. Different implementations may use different processes and / or steps to form interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0103] It should also be noted that the various disclosures contained herein can be described as programs illustrated as flowcharts, diagrams, block diagrams, or block diagrams. Although a flowchart can describe operations as a sequential procedure, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The program terminates when its operations are completed.

[0104] Further examples are described below to facilitate understanding of the invention.

[0105] Sample 1: A package includes a substrate, an integrated device coupled to the substrate, an encapsulation layer located on the substrate, at least one encapsulation layer interconnect located in the encapsulation layer, and at least one metal layer located on the encapsulation layer. The substrate includes at least one dielectric layer and a plurality of interconnects. The at least one encapsulation layer interconnect is coupled to the substrate. The at least one metal layer is configured as an electromagnetic interference (EMI) shield for the package. The at least one metal layer is located on the back side of the integrated device.

[0106] State 2: Package as in State 1, wherein the at least one metal layer is configured as a conformal EMI shield for the package, wherein the at least one encapsulation layer interconnect is configured as a compartmentalized EMI shield for the package.

[0107] State 3: Packages as in States 1 to 2, wherein the at least one encapsulation layer interconnect includes at least one through-hole (TMV) and / or at least one wire bond.

[0108] State 4: Package as in State 3, wherein the at least one through-hole (TMV) and / or at least one wire bond is coupled to a plurality of interconnects of the substrate.

[0109] State 5: Packages as in States 1 to 4, wherein the package includes a plurality of integrated devices coupled to a substrate.

[0110] State 6: Packages as in States 1 to 5, wherein the interconnect of the at least one metal layer and the at least one encapsulation layer is configured to be coupled to ground.

[0111] State 7: Packages as in States 1 to 6, wherein the at least one metal layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) at least one metal layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects of the substrate.

[0112] State 8: Package as in State 7, wherein most of the heat generated by the integrated device is dissipated via thermal conduction through (i) the back side of the integrated device, (ii) at least one metal layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects of the substrate.

[0113] State 9: Package as in State 7, wherein at least 20 percent (20%) of the heat generated by the integrated device is dissipated via thermal conduction through (i) the back side of the integrated device, (ii) at least one metal layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects of the substrate.

[0114] State 10: Packages as in States 1 to 9, further comprising a second integrated device coupled to a substrate, wherein the at least one metal layer is located on the back side of the second integrated device, wherein the at least one metal layer is configured as an EMI shield for the integrated device and the second integrated device, wherein the at least one metal layer is configured to be coupled to ground, and wherein the at least one metal layer is further configured to dissipate heat from the integrated device and the second integrated device.

[0115] State 11: Package as in State 10, wherein the at least one encapsulation layer interconnect includes: a plurality of through-holes (TMVs) at least partially surrounding the integrated device; and a plurality of wire bonds at least partially surrounding the second integrated device.

[0116] State 12: Package as in State 11, wherein the at least one metal layer and the plurality of TMVs are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the metal layer, (iii) the plurality of TMVs, and (iv) a first plurality of interconnects of the substrate, wherein the at least one metal layer and the plurality of wire bonds are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the at least one metal layer, (iii) the plurality of wire bonds, and (iv) a second plurality of interconnects of the substrate.

[0117] State 13: Package as in State 10, wherein most of the heat generated by the integrated device and the second integrated device is dissipated via thermal conduction through (i) at least one metal layer, (ii) at least one encapsulation layer interconnect, and (iii) a plurality of interconnects of the substrate.

[0118] State 14: Packages as in States 1 to 13, wherein the integrated device includes a die, radio frequency (RF) device, passive device, filter, capacitor, inductor, resistor, surface acoustic wave (SAW) filter, bulk acoustic wave (BAW) filter, processor, memory, power amplifier, switch, system-on-chip, integrated circuit device, MEMS device, NEMS device and / or combinations thereof.

[0119] State 15: The package of states 1 to 15 further includes at least one thermal dielectric layer located between at least one metal layer and the back side of the integrated device.

[0120] State 16: Package as in State 15, wherein the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) at least one thermal dielectric layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects of the substrate.

[0121] State 17: Package as in States 15 to 16, wherein the at least one metal layer, the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) at least one thermal dielectric layer, (iii) at least one metal layer, (iv) at least one encapsulation layer interconnect, and (v) a plurality of interconnects of the substrate.

[0122] State 18: Package as in State 17, wherein most of the heat generated by the integrated device is dissipated via thermal conduction through (i) the back side of the integrated device, (ii) at least one thermal dielectric layer, (iii) at least one metal layer, (iv) at least one encapsulation layer interconnect, and (v) a plurality of interconnects of the substrate.

[0123] State 19: Package as in States 15 to 18, wherein the at least one thermal dielectric layer is located on top of the encapsulation layer.

[0124] State 20: Packages such as states 15 to 19, wherein the at least one thermal dielectric layer is coupled to the back side of the integrated device and at least one encapsulation layer interconnect.

[0125] State 21: Package as in States 1 to 20, wherein the at least one metal layer is located on the side surface of the encapsulation layer and the side surface of the substrate.

[0126] State 22: Package as in States 1 to 21, wherein the at least one encapsulation layer interconnect comprises a plurality of encapsulation layer interconnects laterally surrounding the integrated device.

[0127] Sample 23: An apparatus includes a substrate, an integrated device coupled to the substrate, an encapsulation device located on the substrate, an encapsulation layer interconnection device located in the encapsulation device, and an electromagnetic interference (EMI) shielding device located on the encapsulation device. The substrate includes at least one dielectric layer and a plurality of interconnections. The encapsulation layer interconnection device is coupled to the substrate. The EMI shielding device is located on the back side of the integrated device.

[0128] State 24: The apparatus of state 23, wherein the means for encapsulation layer interconnection includes at least one through-hole (TMV) and / or at least one wire bond.

[0129] Style 25: The apparatus of Styles 23 to 24, wherein the means for electromagnetic interference (EMI) shielding includes at least one metal layer, and wherein the means for encapsulation layer interconnection includes at least one encapsulation layer interconnection.

[0130] State 26: The equipment as in State 25, wherein the interconnect of the at least one metal layer and the at least one encapsulation layer is configured to be coupled to ground.

[0131] State 27: The apparatus of state 25, wherein the at least one metal layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) at least one metal layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects of the substrate.

[0132] State 28: The apparatus of state 27, wherein most of the heat generated by the integrated device is dissipated by thermal conduction via (i) the back side of the integrated device, (ii) at least one metal layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects of the substrate.

[0133] State 29: The apparatus of state 25 further includes a second integrated device coupled to a substrate, wherein the at least one metal layer is located on the back side of the second integrated device, wherein the at least one metal layer is configured as an EMI shielding member for the integrated device and the second integrated device, wherein the at least one metal layer is configured to be coupled to ground, and wherein the at least one metal layer is further configured to dissipate heat from the integrated device and the second integrated device.

[0134] Style 30: an apparatus as in style 29, wherein the at least one encapsulation layer interconnect includes: a plurality of through-holes (TMVs) at least partially surrounding the integrated device; and a plurality of wire bonds at least partially surrounding the second integrated device.

[0135] State 31: The apparatus of state 30, wherein the metal layer and the plurality of TMVs are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the metal layer, (iii) the plurality of TMVs, and (iv) a first plurality of interconnects of the substrate, wherein the at least one metal layer and the plurality of wire bonds are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) at least one metal layer, (iii) the plurality of wire bonds, and (iv) a second plurality of interconnects of the substrate.

[0136] State 32: an apparatus as in State 29, wherein most of the heat generated by the integrated device and the second integrated device is dissipated via thermal conduction through (i) at least one metal layer, (ii) at least one encapsulation layer interconnect, and (iii) a plurality of interconnects of the substrate.

[0137] State 33: Equipment as in States 23 to 32, wherein the integrated device includes a die, radio frequency (RF) device, passive device, filter, capacitor, inductor, resistor, surface acoustic wave (SAW) filter, bulk acoustic wave (BAW) filter, processor, memory, power amplifier, switch, system-on-a-chip, integrated circuit device, MEMS device, NEMS device and / or combinations thereof.

[0138] State 34: The equipment of states 23 to 33 further includes at least one thermal dielectric layer located between at least one metal layer and the back side of the integrated device.

[0139] State 35: an apparatus as in State 34, wherein the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) at least one thermal dielectric layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects of the substrate.

[0140] State 36: The apparatus of state 34, wherein the at least one metal layer, the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) at least one thermal dielectric layer, (iii) at least one metal layer, (iv) at least one encapsulation layer interconnect, and (v) a plurality of interconnects of the substrate.

[0141] State 37: The apparatus of state 36, wherein most of the heat generated by the integrated device is dissipated by thermal conduction via (i) the back side of the integrated device, (ii) at least one thermal dielectric layer, (iii) at least one metal layer, (iv) at least one encapsulation layer interconnect, and (v) a plurality of interconnects of the substrate.

[0142] State 38: an apparatus as in state 34, wherein the at least one thermal dielectric layer is located on the encapsulation device.

[0143] State 39: The apparatus of state 34, wherein the at least one thermal dielectric layer is coupled to the back side of the integrated device and interconnected with at least one encapsulation layer.

[0144] Format 40: Equipment as described in Formats 23 to 39, wherein the equipment includes devices selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0145] Form 41: A package includes a substrate; an integrated device coupled to the substrate; an encapsulation layer located on the substrate; at least one encapsulation layer interconnect located in the encapsulation layer, wherein the at least one encapsulation layer interconnect is coupled to the substrate; and at least one thermal dielectric layer located on the encapsulation layer, wherein the at least one thermal dielectric layer is located on the back side of the integrated device. The substrate includes at least one dielectric layer; and a plurality of interconnects.

[0146] State 42: Package as in State 41, wherein the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) at least one thermal dielectric layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects of the substrate.

[0147] State 43: Packages as in States 41 to 42, wherein the at least one thermal dielectric layer includes a trench located above at least one encapsulation layer interconnect.

[0148] Patent 44: Packages of types 41 to 43, wherein the at least one encapsulation layer interconnect includes through-hole (TMV), wire bonding, metallization frame and / or surface mount device (SMD).

[0149] State 45: Packages such as states 41 to 44, wherein the package includes a plurality of integrated devices coupled to a substrate.

[0150] Sample 46: A method for manufacturing a package. The method provides a substrate including at least one dielectric layer and a plurality of interconnects. The method couples an integrated device to the substrate. The method forms an encapsulation layer on the substrate. The method forms at least one encapsulation layer interconnect in the encapsulation layer, wherein the encapsulation layer interconnect is coupled to the substrate. The method forms at least one metal layer on the encapsulation layer. The at least one metal layer is configured as an electromagnetic interference (EMI) shield for the package. The at least one metal layer is located on the back side of the integrated device.

[0151] State 47: The method of State 46, wherein the at least one metal layer is configured as a conformal EMI shield for packaging, wherein the at least one encapsulation layer interconnect is configured as a compartmentalized EMI shield for packaging.

[0152] State 48: The method of states 46 to 47, wherein forming at least one encapsulation layer interconnect includes forming a through-hole (TMV) in the encapsulation layer and / or forming at least one wire bond.

[0153] State 49: The method of states 46 to 48 further includes forming at least one thermal dielectric layer on the back side of the integrated device, wherein forming at least one metal layer includes forming at least one metal layer on the at least one thermal dielectric layer.

[0154] State 50: The method of State 49 further includes forming at least one thermal dielectric layer on the encapsulation layer, wherein the at least one thermal dielectric layer is coupled to at least one encapsulation layer interconnect.

[0155] Form 51: A package includes a substrate; an integrated device coupled to the substrate; an encapsulation layer located on the substrate; at least one encapsulation layer interconnect located in the encapsulation layer, wherein the at least one encapsulation layer interconnect is coupled to the substrate; and at least one electrical dielectric layer located on the encapsulation layer, wherein the at least one electrical dielectric layer is located on the back side of the integrated device. The substrate includes at least one dielectric layer; and a plurality of interconnects.

[0156] State 52: Package as in State 51, wherein the at least one electrical medium layer is configured as a thermal management layer for the package, and wherein the encapsulation layer interconnect is configured as a compartmented EMI shield for the package.

[0157] State 53: Packages as in States 51 to 52, wherein the at least one encapsulation layer interconnect includes at least one through-hole (TMV) and / or at least one wire bond.

[0158] State 54: Packages as in States 51 to 53, wherein the at least one electrical medium layer and the at least one encapsulation layer interconnect are configured to be coupled to ground.

[0159] Style 55: Packages as in Styles 51 to 54, wherein the at least one electrical medium layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) at least one electrical medium layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects of the substrate.

[0160] State 56: Package as in State 55, wherein most of the heat generated by the integrated device is dissipated via thermal conduction through (i) the back side of the integrated device, (ii) at least one dielectric layer, (iii) at least one encapsulation layer interconnect, and (iv) a plurality of interconnects of the substrate.

[0161] State 57: Packages as in States 51 to 56, wherein the package includes a plurality of integrated devices coupled to a substrate.

[0162] Sample 58: A method for manufacturing a package. The method provides a substrate including at least one dielectric layer and a plurality of interconnects. The method couples an integrated device to the substrate. The method forms an encapsulation layer on the substrate. The method forms at least one encapsulation layer interconnect in the encapsulation layer, wherein the encapsulation layer interconnect is coupled to the substrate. The method forms at least one electrical dielectric layer on the encapsulation layer. The at least one electrical dielectric layer is located on the back side of the integrated device.

[0163] State 59: The method of State 58, wherein forming at least one encapsulation layer interconnect includes forming a through-hole (TMV) in the encapsulation layer and / or forming at least one wire bond.

[0164] Sample 60: A method for manufacturing a package. The method provides a substrate including at least one dielectric layer and a plurality of interconnects. The method couples an integrated device to the substrate. The method forms an encapsulation layer on the substrate. The method forms at least one encapsulation layer interconnect in the encapsulation layer, wherein the encapsulation layer interconnect is coupled to the substrate. The method forms at least one thermal dielectric layer on the encapsulation layer. The at least one thermal dielectric layer is located on the back side of the integrated device.

[0165] State 61: The method of State 60, wherein forming at least one encapsulation layer interconnect includes forming a through-hole (TMV) in the encapsulation layer and / or forming at least one wire bond.

[0166] The various features of the present case described herein can be implemented in different systems without departing from the present case. It should be noted that the above states in this case are instances only and should not be construed as limiting this case. The description of the various forms in this case is intended to be illustrative and not to limit the scope of the attached claim. Thereby, the teachings of the present case can be readily applied to other types of devices, and many substitutions, modifications, and deformations will be obvious to those with usual knowledge in the field to which the invention belongs. [Brief explanation of the diagram]

[0010] The various features, essences and advantages will become apparent when understanding the detailed descriptions elaborated below in conjunction with the drawings, in which similar component symbols are always marked accordingly.

[0011] illustrates a cross-sectional view of a package including a substrate and an integrated device.

[0012] Figure 2 illustrates a cross-sectional view of a package including a substrate, an integrated device, an encapsulation layer, and a metal layer configured as an electromagnetic interference (EMI) mask.

[0013] FIG.

[0014] FIG.

[0015] FIG.

[0016] Figure 6 illustrates a cross-sectional view of another package including a substrate, an integrated device, an envelope layer, and a thermodielectric layer.

[0017] FIG.

[0018] Figure 8 illustrates a cross-sectional view of another package including a substrate, an integrated device, an encapsulation layer, and a metallized frame.

[0019] FIG.

[0020] Figure 10 illustrates an exemplary heat flux of a package including a substrate, an integrated device, an encapsulation layer, a thermal dielectric layer, and a metal layer configured as an EMI shield.

[0021] Figure 11 illustrates a plan view of a package including a substrate, an integrated device, an encapsulation layer, and a metal layer configured as an EMI shield.

[0022] Figures 12A–12D illustrate exemplary processes for manufacturing a package that includes a substrate, an integrated device, an encapsulation layer, a thermal dielectric layer, and a metal layer configured as an EMI shield.

[0023] Figure 13 illustrates an exemplary flowchart of a method for manufacturing a package including a substrate, an integrated device and an encapsulation layer having a controlled undercut.

[0024] Figures 14A-14C illustrate exemplary processes for manufacturing a substrate.

[0025] Figure 15 illustrates various electronic devices that can integrate the chips, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. [Biomaterial Storage]

[0168] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A packaged integrated device, comprising: A substrate comprising: at least one dielectric layer; and a plurality of interconnects; an integrated device coupled to the substrate via at least a plurality of solder interconnects; an encapsulation layer on the substrate; at least one encapsulation layer interconnect located in the encapsulation layer, wherein the at least one encapsulation layer interconnect is coupled to the substrate, wherein the at least one encapsulation layer interconnect includes at least one wire bond coupled to and contacting at least one metal layer and the substrate, and wherein a top surface of the at least one wire bond is flush with a surface of the back side of the integrated device; the at least one metal layer coupled to the encapsulation layer and coupled to a back side of the integrated device; and at least one thermal dielectric layer located between the at least one metal layer and the back side of the integrated device, wherein the at least one wire bond is coupled to the metal layer via the at least one thermal dielectric layer, wherein the at least one metal layer is configured as an electromagnetic interference (EMI) shield for the package.

2. The packaged integrated device as claimed in claim 1, wherein the package includes a plurality of integrated devices coupled to the substrate.

3. The packaged integrated device as claimed in claim 1, wherein the interconnect of the at least one metal layer and the at least one encapsulation layer is configured to be coupled to ground.

4. The packaged integrated device as claimed in claim 1, wherein the at least one metal layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the at least one metal layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate.

5. The packaged integrated device as claimed in claim 4, wherein most of the heat generated by the integrated device is dissipated via thermal conduction through (i) the back side of the integrated device, (ii) the at least one metal layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate.

6. The packaged integrated device of claim 4, wherein at least 20 percent (20%) of the heat generated by the integrated device is dissipated by thermal conduction via (i) the back side of the integrated device, (ii) the at least one metal layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate.

7. The packaged integrated device of claim 1, further comprising a second integrated device coupled to the substrate, wherein the at least one metal layer is located on a back side of the second integrated device, wherein the at least one metal layer is configured as an EMI shielding member for the integrated device and the second integrated device, wherein the at least one metal layer is configured to be coupled to ground, and wherein the at least one metal layer is further configured to dissipate heat from the integrated device and the second integrated device.

8. The packaged integrated device as claimed in claim 7, wherein the at least one encapsulation layer interconnect comprises: At least partially surrounding the plurality of through-holes (TMVs) of the integrated device; and at least partially bonded to a plurality of leads surrounding the second integrated device.

9. The packaged integrated device of claim 8, wherein the at least one metal layer and the plurality of TMVs are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the metal layer, (iii) the plurality of TMVs, and (iv) a first plurality of interconnects of the substrate, and wherein the at least one metal layer and the plurality of wire bonds are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the at least one metal layer, (iii) the plurality of wire bonds, and (iv) a second plurality of interconnects of the substrate.

10. The packaged integrated device of claim 7, wherein at least 20 percent (20%) of the heat generated by the integrated device and the second integrated device is dissipated via thermal conduction through (i) the at least one metal layer, (ii) the at least one encapsulation layer interconnect, and (iii) the plurality of interconnects of the substrate.

11. The packaged integrated device as claimed in claim 1, wherein the integrated device includes a die, a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, a resistor, a surface acoustic wave (SAW) filter, an integrated acoustic wave (BAW) filter, a processor, a memory, a power amplifier, a switch, a system-on-a-chip, an integrated circuit device, a MEMS device, a NEMS device, and / or combinations thereof.

12. The packaged integrated device of claim 1, wherein the at least one metal layer is further coupled to one side surface of the substrate.

13. The packaged integrated device as claimed in claim 1, wherein the at least one encapsulation layer interconnect comprises a plurality of encapsulation layer interconnects laterally surrounding the integrated device.

14. A packaged integrated device, comprising: A substrate includes: at least one dielectric layer; and a plurality of interconnects; an integrated device coupled to the substrate; an encapsulation layer located on the substrate; at least one encapsulation layer interconnect located in the encapsulation layer, wherein the at least one encapsulation layer interconnect is coupled to the substrate; at least one metal layer coupled to the encapsulation layer and coupled to a back side of the integrated device, wherein the at least one metal layer is configured as an electromagnetic interference (EMI) shield for the package; and at least one thermal dielectric layer located between the at least one metal layer and the back side of the integrated device, wherein at least one wire bond is coupled to the metal layer via the at least one thermal dielectric layer, wherein the integrated device is coupled to the substrate via a plurality of pillar interconnects and a plurality of solder interconnects; wherein the at least one metal layer is configured as a conformal EMI shield for the package, wherein the at least one encapsulation layer interconnect includes at least one wire bond, the at least one wire bond being coupled to the plurality of interconnects on the substrate. The top surface of the at least one wire bond is flush with a surface on the back side of the integrated device, and the at least one wire bond is configured as a compartmentalized EMI shield for the package.

15. The packaged integrated device of claim 14, wherein the at least one encapsulation layer interconnect further includes at least one through-mold via (TMV).

16. The packaged integrated device of claim 15, wherein the at least one through-hole (TMV) and / or the at least one wire bond is coupled to the plurality of interconnects of the substrate.

17. The packaged integrated device of claim 14, wherein the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate.

18. The packaged integrated device of claim 14, wherein the at least one metal layer, the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one metal layer, (iv) the at least one encapsulation layer interconnect, and (v) the plurality of interconnects of the substrate; and wherein a majority of the heat generated by the integrated device is dissipated via thermal conduction via (i) the back side of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one metal layer, (iv) the at least one encapsulation layer interconnect, and (v) the plurality of interconnects of the substrate.

19. The packaged integrated device of claim 14, wherein the at least one thermal dielectric layer is located on the encapsulation layer, and wherein the at least one thermal dielectric layer is coupled to the back side of the integrated device and interconnected with the at least one encapsulation layer.

20. A packaging apparatus, comprising: A substrate comprising: at least one dielectric layer; and a plurality of interconnects; an integrated device coupled to the substrate via at least a plurality of solder interconnects; an encapsulation device located on the substrate; an encapsulation layer interconnection device located on the encapsulation device, wherein the encapsulation layer interconnection device is coupled to the substrate, wherein the encapsulation layer interconnection device includes at least one wire bond coupled to the substrate; an electromagnetic interference (EMI) shielding device coupled to the encapsulation device, wherein the EMI shielding device is located on and coupled to a back side of the integrated device, wherein the EMI shielding device contacts the at least one wire bond, and wherein a top surface of the at least one wire bond is flush with a surface of the back side of the integrated device; and at least one thermal dielectric layer located between the EMI shielding device and the back side of the integrated device, wherein the at least one wire bond is coupled to the EMI shielding device via the at least one thermal dielectric layer.

21. The packaging apparatus of claim 20, wherein the means for encapsulation layer interconnection further includes at least one through-hole (TMV).

22. The packaging apparatus of claim 20, wherein the means for electromagnetic interference (EMI) shielding includes at least one metal layer coupled to the back side of the integrated device, wherein the means for encapsulation layer interconnection includes at least one encapsulation layer interconnection, and wherein the at least one wire bond is coupled to the plurality of interconnections of the substrate.

23. The packaging apparatus of claim 22, wherein the interconnect of the at least one metal layer and the at least one encapsulation layer is configured to be coupled to ground.

24. The packaging apparatus of claim 22, wherein the at least one metal layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the at least one metal layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate.

25. The packaging apparatus of claim 24, wherein most of the heat generated by the integrated device is dissipated via thermal conduction through (i) the back side of the integrated device, (ii) the at least one metal layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate.

26. The packaging apparatus of claim 22 further includes at least one thermal dielectric layer located between the at least one metal layer and the back side of the integrated device.

27. The packaging apparatus of claim 26, wherein the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate.

28. The packaging apparatus of claim 26, wherein the at least one metal layer, the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device via (i) the back side of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one metal layer, (iv) the at least one encapsulation layer interconnect, and (v) the plurality of interconnects of the substrate.

29. The packaging apparatus of claim 28, wherein at least 20 percent (20%) of the heat generated by the integrated device is dissipated by thermal conduction via (i) the back side of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one metal layer, (iv) the at least one encapsulation layer interconnect, and (v) the plurality of interconnects of the substrate.

30. The packaged equipment as claimed in claim 22, wherein the equipment includes a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

31. A method for manufacturing a packaged integrated device, comprising the steps of: providing a substrate, the substrate comprising: At least one dielectric layer; and multiple interconnections; An integrated device is coupled to the substrate via at least a plurality of solder interconnects; A sealing layer is formed on the substrate; Forming at least one encapsulation layer interconnect located in the encapsulation layer, wherein the encapsulation layer interconnect is coupled to the substrate, wherein forming at least one encapsulation layer interconnect includes forming at least one wire bond coupled to the substrate; At least one metal layer is formed coupled to the encapsulation layer and to a back side of the integrated device; and at least one thermal dielectric layer is formed between the at least one metal layer and the back side of the integrated device, wherein the at least one wire bond is coupled to the metal layer via the at least one thermal dielectric layer, wherein a top surface of the at least one wire bond is flush with a surface of the back side of the integrated device, and wherein the at least one metal layer is configured as an electromagnetic interference (EMI) shield for the packaged integrated device.

32. The method of claim 31, wherein the at least one metal layer is configured as a conformal EMI shield for the packaged integrated device; and wherein the at least one encapsulation layer interconnect is configured as a compartmentalized EMI shield for the packaged integrated device.

33. The method of claim 31, wherein forming the at least one encapsulation layer interconnect includes forming a through-hole (TMV) in the encapsulation layer and / or forming at least one wire bond.

34. The method of claim 31 further includes forming at least one thermal dielectric layer on the back side of the integrated device, wherein forming the at least one metal layer includes forming the at least one metal layer on the at least one thermal dielectric layer.

35. The method of claim 34 further includes forming at least one thermal dielectric layer on the encapsulation layer, wherein the at least one thermal dielectric layer is coupled to the at least one encapsulation layer interconnect.

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