Ceramic electronic device and manufacturing method of the same

Abstract

The objective of this invention is to provide a ceramic electronic component that combines high insulation resistance and high electrostatic capacitance, and a method for manufacturing the same. The ceramic electronic component of this invention is characterized by having a multilayer structure, wherein the multilayer structure is formed by alternating layers of a plurality of internal electrode layers and three or more dielectric layers primarily composed of ceramic. The three or more dielectric layers contain Sn, and in at least two of the three or more dielectric layers, the Sn concentration of the dielectric layer at the end of the multilayer stacking direction is lower than the Sn concentration of the dielectric layer at the center of the multilayer stacking direction.

Description

[Technical Field]

[0001] This invention relates to a ceramic electronic component and its manufacturing method. [Previous Technology]

[0002] Multilayer ceramic capacitors and other multilayer ceramic electronic components have a structure in which internal electrode layers are stacked with dielectric layers in between. By utilizing the ferroelectric properties of the dielectric layer regions sandwiched between the internal electrode layers, ceramic electronic components can achieve a large electrostatic capacitance density (see, for example, Patent Document 1). [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2014 / 024538 [Summary of the Invention]

[0004] [The problem the invention aims to solve]

[0005] Sometimes, the metal contained in the internal electrode layer diffuses and dissolves into the main component ceramic of the dielectric layer during the calcination process. If the metal contained in the internal electrode layer dissolves into the main component ceramic of the dielectric layer, oxygen defects may be formed in the main component ceramic of the dielectric layer, reducing the insulation of the dielectric layer and shortening the life of ceramic electronic components.

[0006] Thus, by making Sn solid-dissolve relative to the main component ceramic of the dielectric layer, the solid-dissolved metal of the internal electrode layer in the main component ceramic of the dielectric layer can be suppressed, thereby improving the insulation of the dielectric layer and extending its lifespan.

[0007] However, Sn promotes the sintering of the dielectric layer and promotes the spheroidization of the internal electrode layer. Therefore, the insulation of the dielectric layer can be improved by adding Sn, but on the other hand, it will cause the electrostatic capacitance to decrease due to the disorder of the stacked structure caused by the spheroidization of the internal electrode layer.

[0008] This invention was made in view of the above-mentioned problems, and its object is to provide a ceramic electronic component that can simultaneously possess high insulation resistance and high electrostatic capacitance, and a method for manufacturing the same. [Technical Means for Solving the Problem]

[0009] The ceramic electronic component of the present invention is characterized in that it has a multilayer structure, which is formed by alternating layers of a plurality of internal electrode layers and three or more dielectric layers with ceramic as the main component, wherein the three or more dielectric layers contain Sn, and in the relationship of at least two of the three or more dielectric layers, the Sn concentration of the dielectric layer at the end side of the stacking direction is lower than the Sn concentration of the dielectric layer at the center side of the stacking direction.

[0010] In the above-mentioned ceramic electronic components, from the dielectric layer at the center of the stacking direction to the dielectric layer at the far end of the stacking direction, the Sn concentration of the far end dielectric layer can also be the lowest.

[0011] In the above-mentioned ceramic electronic component, the Sn concentration of each of the plurality of dielectric layers from the far end to the center side in the above-mentioned stacking direction may also be lower than the Sn concentration of each of the other dielectric layers on the center side in the above-mentioned stacking direction.

[0012] In the above-mentioned ceramic electronic components, the Sn concentration of each dielectric layer from the center of the dielectric layer in the above-mentioned stacking direction to the dielectric layer at the end of the above-mentioned stacking direction may also increase gradually or stepwise from the dielectric layer in the center of the above-mentioned stacking direction to the dielectric layer at the end of the above-mentioned stacking direction.

[0013] In the above-mentioned ceramic electronic components, the ratio of the minimum Sn concentration to the maximum Sn concentration of each dielectric layer with three or more layers can be 2:3 or less.

[0014] In the above-mentioned ceramic electronic components, the main component ceramic of the above-mentioned three or more dielectric layers has a perovskite structure, and the difference between the minimum Sn / B site element ratio and the maximum Sn / B site element ratio for the Sn concentration of each of the above-mentioned three or more dielectric layers can be 0.001 or more.

[0015] In the above-mentioned ceramic electronic components, the main component of the dielectric layer of the three or more layers may be barium titanate, and the main component of the plurality of internal electrode layers may be nickel.

[0016] In the above-mentioned ceramic electronic components, the thickness of the dielectric layer of the above-mentioned three or more layers may also be less than 5 μm.

[0017] In the above-mentioned ceramic electronic components, the Sn concentration in the dielectric layers of the above-mentioned three or more layers may also be less than 5 at%.

[0018] In the above-mentioned ceramic electronic components, the Sn concentration in the above-mentioned internal electrode layers of 3 or more layers may also be 0.1 at% or more.

[0019] The method for manufacturing ceramic electronic components of the present invention is characterized by comprising: a step of forming a multilayer unit by forming an internal electrode pattern containing metal powder on a dielectric blank containing ceramic powder and a Sn source; a step of forming a multilayer body by stacking three or more of the multilayer units; and a step of calcining the multilayer body; wherein, in at least two layers of the dielectric blank before calcination, the concentration of Sn relative to the main component ceramic in the dielectric blank at the end of the dielectric blank in the stacking direction is reduced in advance compared to the dielectric blank on the center side of the stacking direction. [Effects of the Invention]

[0020] According to the present invention, a ceramic electronic component that can have both high insulation resistance and high electrostatic capacitance and a method for manufacturing the same can be provided.

Implementation Method

[0022] Hereinafter, the embodiments will be described with reference to the drawings.

[0023] (Embodiment Embodiment) FIG1 is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100 according to the embodiment. FIG2 is a cross-sectional view along line AA of FIG1. ​​FIG3 is a cross-sectional view along line BB of FIG1. ​​As illustrated in FIG1 to 3, the multilayer ceramic capacitor 100 includes: a multilayer wafer 10 having a generally rectangular parallelepiped shape; and external electrodes 20a and 20b disposed on either of two opposing end faces of the multilayer wafer 10. Furthermore, of the four surfaces of the multilayer wafer 10 other than the two end faces, the two surfaces other than the upper surface and the lower surface in the stacking direction are referred to as side surfaces. The external electrodes 20a and 20b extend from the upper surface, the lower surface and the two side surfaces in the stacking direction of the multilayer wafer 10. However, the external electrodes 20a and 20b are spaced apart from each other.

[0024] The multilayer wafer 10 has a configuration consisting of alternating layers of dielectric layers 11 comprising a ceramic material that functions as a dielectric, and three or more internal electrode layers 12 comprising a base metal material. The ends of each internal electrode layer 12 are alternately exposed at the end face where the external electrode 20a of the multilayer wafer 10 is disposed and at the end face where the external electrode 20b is disposed. Thus, each internal electrode layer 12 is alternately connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration consisting of a plurality of dielectric layers 11 separated by internal electrode layers 12. Furthermore, in the multilayer body of dielectric layers 11 and internal electrode layers 12, the internal electrode layer 12 is disposed on the outermost layer in the stacking direction, and the upper and lower surfaces of this multilayer body are covered by a capping layer 13. The capping layer 13 is primarily composed of a ceramic material. For example, the material of the capping layer 13 is the same as the primary component of the ceramic material of the dielectric layer 11.

[0025] The dimensions of the multilayer ceramic capacitor 100 are, for example, a length of 0.25 mm, a width of 0.125 mm, and a height of 0.125 mm, or a length of 0.4 mm, a width of 0.2 mm, and a height of 0.2 mm, or a length of 0.6 mm, a width of 0.3 mm, and a height of 0.3 mm, or a length of 1.0 mm, a width of 0.5 mm, and a height of 0.5 mm, or a length of 3.2 mm, a width of 1.6 mm, and a height of 1.6 mm, or a length of 4.5 mm, a width of 3.2 mm, and a height of 2.5 mm, but are not limited to these dimensions.

[0026] The internal electrode layer 12 is mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). As the internal electrode layer 12, precious metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold) or alloys containing these metals may also be used.

[0027] The dielectric layer 11 is, for example, mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. Furthermore, this perovskite structure contains ABO3-α, which deviates from the stoichiometric composition. For example, as this ceramic material, BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), and Ba1-x-yCaxSryTi1-zZrzO3 (0≦x≦1, 0≦y≦1, 0≦z≦1) forming the perovskite structure can be used. The thickness of each dielectric layer 11 is, for example, 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less.

[0028] As illustrated in Figure 2, the regions where the inner electrode layer 12 connected to the external electrode 20a and the inner electrode layer 12 connected to the external electrode 20b face each other are regions in the multilayer ceramic capacitor 100 that generate capacitance. Here, the region that generates this capacitance is referred to as the capacitance region 14. That is, the capacitance region 14 is the region where adjacent inner electrode layers 12 connected to different external electrodes face each other.

[0029] The region where the internal electrode layers 12 connected to the external electrode 20a are connected to the internal electrode layers 12 of the external electrode 20b without any separation between them is called the end edge 15. Similarly, the region where the internal electrode layers 12 connected to the external electrode 20b are connected to the internal electrode layers 12 of the external electrode 20a without any separation between them is also called the end edge 15. In other words, the end edge 15 is the region where the internal electrode layers 12 connected to the same external electrode are connected to the internal electrode layers 12 of different external electrodes without any separation between them. The end edge 15 is a region that does not generate capacitance.

[0030] As illustrated in FIG3, in the stacked wafer 10, the region extending from the two sides of the stacked wafer 10 to the internal electrode layer 12 is referred to as the side edge 16. That is, the side edge 16 is a region provided in such a way that it covers the ends of the plurality of internal electrode layers 12 stacked in the above-described stacked structure that extend to the two sides. The side edge 16 is also a region that does not generate capacitance.

[0031] The multilayer wafer 10 can be obtained by stacking layers formed of powdered material and then calcining them. However, the main component metal of the internal electrode layer 12 sometimes dissolves in the main component ceramic of the dielectric layer 11 during the calcination process. For example, when the internal electrode layer 12 contains Ni, a portion of the Ni will oxidize during the calcination process, and the ionized Ni will dissolve in the main component ceramic of the dielectric layer 11. If the main component metal of the internal electrode layer 12 dissolves in the main component ceramic of the dielectric layer 11, oxygen defects may form in the main component ceramic of the dielectric layer 11, reducing the insulation of the dielectric layer 11 and shortening the lifespan of the multilayer ceramic capacitor 100.

[0032] Thus, by making Sn solid-dissolve relative to the main component ceramic of the dielectric layer 11, the solid-dissolved metal of the internal electrode layer 12 in the main component ceramic of the dielectric layer 11 can be suppressed, thereby improving the insulation of the dielectric layer 11 and extending the life of the multilayer ceramic capacitor 100.

[0033] However, Sn promotes the sintering of the dielectric layer 11 and promotes the spheroidization of the inner electrode layer 12. Therefore, the insulation of the dielectric layer 11 can be improved by adding Sn, but on the other hand, the electrostatic capacitance of the multilayer ceramic capacitor 100 is reduced due to the disorder of the multilayer structure caused by the spheroidization of the inner electrode layer 12. In particular, since the heat of the calcining furnace is conducted from the outside to the inside of the multilayer wafer before calcination, a thermal gradient is easily generated. For example, a thermal gradient is easily generated at high-speed heating of 100°C / min or higher. When a thermal gradient is generated, sintering on the outside is easier than sintering on the inside, so the inner electrode layer on the outside is more likely to spheroidize. Furthermore, since the residual carbon of the binder that hinders sintering is sequentially vaporized from the outside and dispersed into the calcining furnace environment, sintering on the outside is easier than sintering on the inside. Sintering is particularly easily promoted in the outermost inner electrode layer. Therefore, the multilayer ceramic capacitor 100 of this embodiment has a structure that can simultaneously possess high insulation resistance and high electrostatic capacitance.

[0034] In the multilayer ceramic capacitor 100 of this embodiment, each dielectric layer 11 contains Sn. For example, Sn is dissolved in the main component ceramic of each dielectric layer 11. This suppresses the dissolution of the main component metal of the internal electrode layer 12 into the main component ceramic of the dielectric layer 11 during calcination. As a result, the insulation of the dielectric layer 11 can be improved, and the lifespan of the multilayer ceramic capacitor 100 can be extended. Furthermore, in the relationship of at least two of the three or more dielectric layers 11, the Sn concentration of the dielectric layer 11 at the end side in the stacking direction is lower than the Sn concentration of the dielectric layer 11 at the center side in the stacking direction. The lifespan extension effect can be effectively obtained in the dielectric layer 11 at the center side in the stacking direction, and the spheroidization of the internal electrode layer 12 is suppressed in the dielectric layer 11 at the end side in the stacking direction, effectively suppressing the decrease in continuity and suppressing the disorder of the stacked structure, thereby effectively obtaining the effect of improving electrostatic capacitance. Based on the above, it can possess both high insulation and high electrostatic capacitance. Furthermore, if the number of dielectric layers 11 is even, then the central dielectric layer in the stacking direction is the central second dielectric layer in the stacking direction. If the number of dielectric layers 11 is odd, then the central dielectric layer in the stacking direction is the central first dielectric layer in the stacking direction.

[0035] For example, as illustrated in FIG4(a), it is preferable that the Sn concentration of the dielectric layer 11 at the very end of the stacking direction is the lowest among the dielectric layers 11 at the center of the stacking direction to the dielectric layers 11 at the very end of the stacking direction. With this configuration, the effect of suppressing sintering can be significantly obtained. Furthermore, in FIG4(a), by highlighting the dielectric layer 11 at the very end of the stacking direction in black, it is indicated that the Sn concentration of the dielectric layer 11 at the very end is the lowest.

[0036] For example, as illustrated in Figure 4(b), it is preferable that the Sn concentration of each of the plurality of dielectric layers 11 (outer region dielectric layers 11) from the outermost end to the center side in the stacking direction is lower than the Sn concentration of each of the remaining dielectric layers 11 (center region dielectric layers 11) on the center side in the stacking direction. For example, in the case of a total of 400 dielectric layers 11, the Sn concentration is higher in the 200 dielectric layers 11 at the center in the stacking direction, and lower in the 100 dielectric layers 11 at each end in the stacking direction. With this configuration, the effect of suppressing sintering can be significantly obtained. Furthermore, in Figure 4(b), the dielectric layers 11 with lower Sn concentration are highlighted in black.

[0037] In the configuration shown in Figure 4(b), if the outer layer region with a lower Sn concentration is too narrow, there is a risk that the effect of suppressing sintering may not be sufficiently obtained. Therefore, it is preferable to set a lower limit on the range of the outer layer region. For example, the outer layer region should exceed 0% from the upper and lower ends towards the center in the stacking direction of the entire dielectric layer 11, preferably 5% or more, and more preferably 10% or more.

[0038] On the other hand, if the outer layer region with a low Sn concentration is too wide, there is a risk that the effect of extending the lifetime may not be fully achieved. Therefore, it is preferable to set an upper limit on the range of the outer layer region. For example, in the entire dielectric layer 11, from the upper and lower ends in the stacking direction to the center, the outer layer region is preferably less than 40%, more preferably less than 30%, and even more preferably less than 20%.

[0039] For example, as illustrated in Figure 5, preferably, the Sn concentration of each dielectric layer 11 from the center of the dielectric layer 11 in the stacking direction to the outermost dielectric layer 11 in the stacking direction decreases gradually or progressively from the inner electrode layer 12 in the center of the stacking direction to the outermost inner electrode layer 12. With this configuration, since the Sn concentration of the dielectric layer 11 at the edge in the stacking direction is lower, the effect of suppressing sintering can be significantly obtained. Furthermore, since the Sn concentration of the dielectric layer 11 in the center in the stacking direction is higher, the effect of extending the lifetime can be significantly obtained. Moreover, "gradually decreasing" includes a continuous decrease (monotonically decreasing), and includes a decrease in Sn concentration overall, although fluctuating repeatedly, when the Sn concentration is measured at multiple sampling points from the center of the dielectric layer 11 to the outermost dielectric layer 11 in the stacking direction.

[0040] The thickness of each internal electrode layer 12 is, for example, 0.01 μm or more and 5 μm or less, or 0.05 μm or more and 3 μm or less, or 0.1 μm or more and 1 μm or less. For example, when the thickness of the internal electrode layer 12 is 1 μm or less, the continuity is easily reduced due to breakage during calcination, thus significantly enhancing the effect of the configuration of this embodiment. In the multilayer ceramic capacitor 100, the number of layers of the internal electrode layer 12 is, for example, 10 to 5000, 50 to 4000, or 100 to 3000.

[0041] If the Sn concentration in each dielectric layer 11 is too high, there is a risk that the internal electrode layers 12 will become spherical, and the electrostatic capacitance of the multilayer ceramic capacitor 100 will decrease. Therefore, it is preferable to set an upper limit on the Sn concentration in each dielectric layer 11. For example, the Sn concentration in each dielectric layer 11 is preferably 5 at% or less, more preferably 3 at% or less, and even more preferably 2 at% or less. Furthermore, the at% of Sn refers to the atomic ratio of Sn when the main component ceramic is set to 100 at%. When the main component ceramic of the dielectric layer 11 has a perovskite structure, the at% of Sn refers to the atomic ratio of Sn when the B site element of the main component ceramic is set to 100 at%.

[0042] On the other hand, if the Sn concentration of each dielectric layer 11 is too low, there is a risk that the diffusion of the metal components contained in the internal electrode layer 12 into the dielectric layer 11 may not be sufficiently suppressed. In this regard, it is preferable to set a lower limit for the Sn concentration of each dielectric layer 11. For example, the Sn concentration of each dielectric layer 11 is preferably 0.1 at% or more, more preferably 0.5 at% or more, and even more preferably 1 at% or more.

[0043] For example, regarding the Sn concentration of each dielectric layer 11, the ratio of the minimum Sn concentration to the maximum Sn concentration is preferably 2:3 or less, more preferably 1:3 or less, and even more preferably 1:5 or less. Furthermore, regarding the Sn concentration of each dielectric layer 11, the difference between the minimum Sn / B site element ratio and the maximum Sn / B site element ratio is preferably 0.001 or more, more preferably 0.005 or more, and even more preferably 0.01 or more.

[0044] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 6 is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 100.

[0045] (Raw Material Powder Preparation Steps) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure, exhibiting a high dielectric constant. BaTiO3 can generally be obtained by reacting titanium raw materials such as titanium dioxide with barium raw materials such as barium carbonate to synthesize barium titanate. Various methods are known for synthesizing the ceramic as the main component of the dielectric layer 11, such as solid-state methods, sol-gel methods, and hydrothermal methods. In this embodiment, any of these methods can be used.

[0046] A specified additive compound is added to the obtained ceramic powder according to the purpose. Examples of additive compounds include oxides of tin (Sn), magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), thionium (Gd), tbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thionium (Tm) and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium or silicon.

[0047] For example, a compound containing additives is wet-mixed into ceramic raw material powder, and then dried and pulverized to prepare ceramic materials. For example, the ceramic materials obtained as described above can also be pulverized to adjust the particle size, or the particle size can be adjusted by grading and combining, as needed. Through the above steps, dielectric materials can be obtained.

[0048] (Lamination Step) Next, binders such as polyvinyl butyral (PVB) resin, organic solvents such as ethanol and toluene, and plasticizers are added to the obtained dielectric material and wet-mixed. Using the obtained slurry, a dielectric preform 52 is coated onto the substrate 51, for example by die coating or blade coating, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0049] Next, as illustrated in FIG7(a), an internal electrode pattern 53 is formed on the dielectric preform 52. In FIG7(a), for example, four layers of internal electrode patterns 53 are formed on the dielectric preform 52 by leaving a predetermined interval. The film formation method is not particularly limited, for example, an electrode paste containing the main component metal of the internal electrode layer 12 can be used. Alternatively, vacuum film formation such as sputtering using a target material employing the main component metal of the internal electrode layer 12 can also be used. The dielectric preform 52 on which the internal electrode pattern 53 is formed is used as a stacking unit.

[0050] Next, the dielectric preform 52 is peeled off from the substrate 51, and as illustrated in FIG7(b), three or more lamination units are laminated. In this case, in at least two of the dielectric preforms, the concentration of Sn relative to the main component ceramic is reduced in the dielectric preforms at the ends of the dielectric preforms in the lamination direction compared to the dielectric preforms on the center side of the lamination direction. The Sn concentration of each dielectric preform can also be adjusted to obtain the Sn concentration distributions shown in FIG4(a) to FIG5.

[0051] Next, a specified number (e.g., 2 to 10 layers) of cover sheets are deposited on top and bottom of the laminate obtained by stacking stacking units, and then thermally bonded and cut into a specified wafer size (e.g., 1.0 mm × 0.5 mm). In the example of FIG7(b), the cutting is performed along the dotted line. The cover sheets and dielectric blank 52 may be of the same composition or may have different added compounds.

[0052] (Calcination Step) After the ceramic multilayer obtained in this way is treated with a debinding agent in a N2 atmosphere, a metal paste is applied by impregnation to form the underlayer of the external electrodes 20a and 20b. The multilayer ceramic capacitor 100 is then calcined at 1100 to 1300°C for 10 minutes to 2 hours in a reducing atmosphere with an oxygen partial pressure of 10⁻⁵ to 10⁻⁸ atm.

[0053] (Re-oxidation treatment step) Subsequently, re-oxidation treatment can also be carried out in an N2 gas atmosphere at 600℃~1000℃.

[0054] (Plating process step) Subsequently, Cu, Ni, Sn and other metals can be coated on the external electrodes 20a and 20b by plating process.

[0055] According to the manufacturing method of this embodiment, in a relationship of at least two layers from the central dielectric layer 11 in the stacking direction to the outermost dielectric layer 11 in the stacking direction, the dielectric layer 11 with a lower Sn concentration is disposed at the end closer to the stacking direction than the dielectric layer 11 with a higher Sn concentration. This allows the multilayer ceramic capacitor 100 to possess both high insulation and high electrostatic capacitance.

[0056] Furthermore, in the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but it is not limited thereto. For example, other electronic components such as rheostats or thermal resistors may also be used. [Example]

[0057] Hereinafter, a multilayer ceramic capacitor according to the embodiment will be manufactured and its characteristics will be investigated.

[0058] (Example 1) Additives were added to barium titanate powder, and the mixture was thoroughly wet-mixed and pulverized using a ball mill to obtain a dielectric material. Butyraldehyde as an organic binder, toluene and ethanol as solvents were added to the dielectric material, and a dielectric preform was coated onto a PET substrate using a doctor blade method. Next, an internal electrode pattern was formed on the dielectric preform using a paste containing Ni powder.

[0059] Next, the dielectric preform is peeled off from the substrate, and the stacking units are stacked. The number of stacked layers is set to 400. Next, a predetermined number of cover sheets are stacked on top and bottom of the stacked body obtained by stacking the stacking units, and then thermally bonded. Afterward, it is cut into a predetermined wafer size (1.0 mm × 0.5 mm × 0.5 mm). In the 200-layer (central region) dielectric preform in the center of the stacking direction, the Sn-Ti ratio is set to 0.50 at%. In the 100-layer (outer layer) dielectric preform above the stacking direction and the 100-layer (outer layer) dielectric preform below the stacking direction, the Sn-Ti ratio is set to 0.25 at.

[0060] The ceramic multilayer obtained in this way is treated with a debinding agent under a N2 atmosphere, and then coated with a metal paste to form the bottom layer of the external electrode by an impregnation method, and calcined under a reducing atmosphere.

[0061] After calcination, in the 200 dielectric layers (central region) at the center of the stacking direction, the atomic concentration ratio of Sn to Ti is 0.004. In the 100 dielectric layers (outer layers) above and below the stacking direction, the atomic concentration ratio of Sn to Ti is 0.001. Regarding the Sn to Ti elemental concentration ratio, the area near the center of the wafer was cut using a slicing machine, and its cross-section was polished using an ion milling device until a clean cross-section was obtained. Elemental determination was performed on the wafer cross-section using laser ablation ICP (Inductively Coupled Plasma) quality analysis of the target area. The diameter of the heated laser spot was 3 μm.

[0062] (Example 2) In Example 2, in the 200-layer (central region) dielectric blank in the center of the stacking direction, the Sn-Ti ratio is set to 1.00 at%. In the 100-layer (outer layer) dielectric blank above the stacking direction and the 100-layer (outer layer) dielectric blank below the stacking direction, the Sn-Ti ratio is set to 0.50 at%. Other conditions are the same as in Example 1.

[0063] After calcination, in the 200 dielectric layers (central region) at the center of the stacking direction, the atomic concentration ratio of Sn to Ti is 0.009. In the 100 dielectric layers (outer layer) above the stacking direction and the 100 dielectric layers (outer layer) below the stacking direction, the atomic concentration ratio of Sn to Ti is 0.004.

[0064] (Example 3) In Example 3, in the 200-layer (central region) dielectric preform in the center of the stacking direction, the Sn-Ti ratio is set to 2.00 at%. In the 100-layer (outer layer) dielectric preform above the stacking direction and the 100-layer (outer layer) dielectric preform below the stacking direction, the Sn-Ti ratio is set to 1.00 at%. Other conditions are the same as in Example 1.

[0065] After calcination, in the 200 dielectric layers (central region) at the center of the stacking direction, the atomic concentration ratio of Sn to Ti is 0.019. In the 100 dielectric layers (outer layer) above the stacking direction and the 100 dielectric layers (outer layer) below the stacking direction, the atomic concentration ratio of Sn to Ti is 0.010.

[0066] (Example 4) In Example 4, in the 200-layer (central region) dielectric preform in the center of the stacking direction, the Sn-Ti ratio is set to 2.00 at%. In the 100-layer (outer layer) dielectric preform above the stacking direction and the 100-layer (outer layer) dielectric preform below the stacking direction, the Sn-Ti ratio is set to 1.50 at%. Other conditions are the same as in Example 1.

[0067] After calcination, in the 200 dielectric layers (central region) at the center of the stacking direction, the atomic concentration ratio of Sn to Ti is 0.020. In the 100 dielectric layers (outer layer) above the stacking direction and the 100 dielectric layers (outer layer) below the stacking direction, the atomic concentration ratio of Sn to Ti is 0.016.

[0068] (Comparative Example 1) In Comparative Example 1, the Sn-to-Ti ratio was set to 0.00 at% in the 200-layer (central region) dielectric preform at the center of the stacking direction. The Sn-to-Ti ratio was also set to 0.00 at% in the 100-layer (outer layer) dielectric preform above and below the stacking direction. That is, no Sn was added to any of the dielectric preforms. All other conditions were the same as in Example 1.

[0069] After calcination, in the 200 dielectric layers (central region) at the center of the stacking direction, the atomic concentration ratio of Sn to Ti is 0.000. In the 100 dielectric layers (outer layer) above the stacking direction and the 100 dielectric layers (outer layer) below the stacking direction, the atomic concentration ratio of Sn to Ti is 0.000.

[0070] (Comparative Example 2) In Comparative Example 2, the Sn-Ti ratio in the 200-layer (central region) dielectric preform in the center of the stacking direction was set to 0.50 at%. The Sn-Ti ratio in the 100-layer (outer layer) dielectric preform above and below the stacking direction was set to 1.00 at%. Other conditions were the same as in Example 1.

[0071] After calcination, in the 200 dielectric layers (central region) at the center of the stacking direction, the atomic concentration ratio of Sn to Ti is 0.005. In the 100 dielectric layers (outer layers) above and below the stacking direction, the atomic concentration ratio of Sn to Ti is 0.010.

[0072] (Comparative Example 3) In Comparative Example 3, the Sn-Ti ratio was set to 1.00 at% in the 200-layer (central region) dielectric preform in the center of the stacking direction. The Sn-Ti ratio was also set to 1.00 at% in the 100-layer (outer layer) dielectric preform above and below the stacking direction. Other conditions were the same as in Example 1.

[0073] After calcination, in the 200 dielectric layers (central region) at the center of the stacking direction, the atomic concentration ratio of Sn to Ti is 0.009. In the 100 dielectric layers (outer layer) above the stacking direction and the 100 dielectric layers (outer layer) below the stacking direction, the atomic concentration ratio of Sn to Ti is 0.010.

[0074] (Comparative Example 4) In Comparative Example 4, the Sn-Ti ratio in the 200-layer (central region) dielectric preform in the center of the stacking direction was set to 1.00 at%. The Sn-Ti ratio in the 100-layer (outer layer) dielectric preform above and below the stacking direction was set to 2.00 at%. Other conditions were the same as in Example 1.

[0075] After calcination, in the 200 dielectric layers (central region) at the center of the stacking direction, the atomic concentration ratio of Sn to Ti is 0.011. In the 100 dielectric layers (outer layer) above the stacking direction and the 100 dielectric layers (outer layer) below the stacking direction, the atomic concentration ratio of Sn to Ti is 0.018.

[0076] (Comparative Example 5) In Comparative Example 5, the Sn-Ti ratio in the 200-layer (central region) dielectric preform in the center of the stacking direction was set to 2.00 at%. The Sn-Ti ratio in the 100-layer (outer layer) dielectric preform above and below the stacking direction was also set to 2.00 at%. Other conditions were the same as in Example 1.

[0077] After calcination, in the 200 dielectric layers (central region) at the center of the stacking direction, the atomic concentration ratio of Sn to Ti is 0.020. In the 100 dielectric layers (outer layers) above and below the stacking direction, the atomic concentration ratio of Sn to Ti is 0.020.

[0078] (Comparative Example 6) In Comparative Example 6, the Sn-Ti ratio in the 200-layer (central region) dielectric preform in the center of the stacking direction was set to 2.00 at%. The Sn-Ti ratio in the 100-layer (outer layer) dielectric preform above the stacking direction and the 100-layer (outer layer) dielectric preform below the stacking direction was set to 4.00 at%. Other conditions were the same as in Example 1.

[0079] After calcination, in the 200 dielectric layers (central region) at the center of the stacking direction, the atomic concentration ratio of Sn to Ti is 0.021. In the 100 dielectric layers (outer layers) above and below the stacking direction, the atomic concentration ratio of Sn to Ti is 0.037.

[0080] For each of Examples 1-4 and Comparative Examples 1-6, the lifetime (50% value) was measured. The measurement method was to apply 8 V DC (direct current) in a constant temperature bath at 120°C and measure the lifetime of each wafer when the current value exceeded 2 mA. 100 wafers of each type were measured.

[0081] For each of Examples 1-4 and Comparative Examples 1-6, the electrostatic capacitance was measured. The measurement method was to use an LCR meter (Inductance Capacitance and Resistance Meter) at 120 Hz and 0.5 Vrms. The measurement was performed after being kept in a constant temperature bath at 150°C for 1 hour, then restored to room temperature, and performed 24 hours later.

[0082] Regarding Examples 1-4 and Comparative Examples 1-6, the continuity of the internal electrode layer in the central region of the stacking direction was measured, and the continuity of the internal electrode layer in the outer layer was measured. The measurement method involved cutting a wafer near the center using a slicer and then polishing its cross-section using an ion milling device until a clean cross-section was achieved. The observed area was photographed using a SEM (Scanning Electron Microscope) on the wafer cross-section, and the continuity was calculated by dividing the total length of the electrodes in each electrode layer by the width of the SEM image. Furthermore, the SEM was performed at 5kx magnification, offsetting the area within the stacking plane, and three images were taken at each location. The number n was set to 5, and the average value of 15 SEM images was used.

[0083] The results of each measurement are shown in Table 1. If the lifetime is increased by more than 10% and the capacitance reduction rate is less than 10% compared to Comparative Example 1 without Sn, it is judged as acceptable "0". In Comparative Examples 2 to 6, the lifetime is improved compared to Comparative Example 1. This can be attributed to the absence of Sn in the dielectric layer. However, in Comparative Examples 2 to 6, the capacitance reduction rate exceeds 10% compared to Comparative Example 1, and it is judged as unacceptable "×". This can be attributed to the fact that the Sn concentration in the outer layer is greater than the Sn concentration in the central region, resulting in spheroidization of the outer inner electrode layer and thus increasing the disorder of the stacked structure. In contrast, in Examples 1 to 4, the lifetime is improved compared to Comparative Example 1, and the capacitance reduction rate is less than 10%, and it is judged as acceptable "0". This can be attributed to the fact that the Sn concentration in the outer layer is less than the Sn concentration in the central region, resulting in the suppression of spheroidization of the outer inner electrode layer. Furthermore, since Comparative Example 1 did not achieve a sufficient service life, it was deemed unqualified "×". [Table 1] Sn addition amount in the central area (at%) Sn addition amount in the outer layer (at%) 50% lifespan value (minute) electrostatic capacitor (μF) Central region Sn / Ti Sn / Ti at the top and bottom ends Continuity Central Region (%) Continuity outer layer (%) determination Example 1 0.50 0.25 344 4.13 0.004 0.001 91 95 〇 Example 2 1.00 0.50 355 4.06 0.009 0.004 90 93 〇 Example 3 2.00 1.00 368 3.94 0.019 0.010 89 92 〇 Actual example 4 2.00 1.50 372 3.84 0.020 0.016 89 90 〇 Comparative Example 1 0.00 0.00 312 4.21 0.000 0.000 92 96 × Comparative Example 2 0.50 1.00 353 3.78 0.005 0.010 91 92 × Comparative Example 3 1.00 1.00 362 3.74 0.009 0.010 90 92 × Comparative Example 4 1.00 2.00 370 3.66 0.011 0.018 90 90 × Comparative Example 5 2.00 2.00 375 3.74 0.020 0.020 89 89 × Comparative Example 6 2.00 4.00 370 3.45 0.021 0.037 88 87 ×

[0084] The embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments. Various changes and modifications can be made within the scope of the spirit of the present invention as described in the claims. [Simplified Explanation of the Diagram]

[0021] Figure 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. Figure 2 is a cross-sectional view along line AA in Figure 1. Figure 3 is a cross-sectional view along line BB in Figure 1. Figures 4(a) and (b) are diagrams illustrating Sn concentration. Figure 5 is a diagram illustrating Sn concentration. Figure 6 is a flowchart illustrating the manufacturing method of a multilayer ceramic capacitor. Figures 7(a) and (b) are diagrams illustrating the multilayering steps.

Claims

1. A ceramic electronic component, characterized in that: it has a multilayer structure, which is formed by alternating layers of a plurality of internal electrode layers and three or more dielectric layers with ceramic as the main component, wherein the three or more dielectric layers contain Sn, and in the relationship of at least two of the three or more dielectric layers, the Sn concentration of the dielectric layer at the end side of the multilayer direction is lower than the Sn concentration of the dielectric layer at the center side of the multilayer direction.

2. The ceramic electronic component of claim 1, wherein the Sn concentration of the dielectric layer at the outermost end of the dielectric layer from the center of the stacking direction to the outermost end of the stacking direction is the lowest.

3. The ceramic electronic component of claim 1, wherein the Sn concentration of each of the plurality of dielectric layers from the far end to the center side in the aforementioned stacking direction is lower than the Sn concentration of each of the remaining dielectric layers on the center side of the aforementioned stacking direction.

4. The ceramic electronic component of claim 1, wherein the Sn concentration of each dielectric layer from the center of the dielectric layer in the stacking direction to the outermost dielectric layer in the stacking direction decreases gradually or progressively from the center of the dielectric layer in the stacking direction to the outermost dielectric layer in the stacking direction.

5. For any of the ceramic electronic components described in claims 1 to 4, the ratio of the minimum Sn concentration to the maximum Sn concentration for each of the three or more dielectric layers is 2:3 or less.

6. For any of the ceramic electronic components described in claims 1 to 4, wherein the main component ceramic of the three or more dielectric layers has a perovskite structure, and the difference between the minimum Sn / B site element ratio and the maximum Sn / B site element ratio for the Sn concentration of each of the three or more dielectric layers is 0.001 or more.

7. A ceramic electronic component as claimed in any of claims 1 to 4, wherein the main component of the three or more dielectric layers is barium titanate ceramic, and the main component of the plurality of internal electrode layers is nickel metallic.

8. For any of the ceramic electronic components described in claims 1 to 4, the thickness of the dielectric layers of the three or more layers mentioned above is less than 5 μm.

9. For any of the ceramic electronic components described in claims 1 to 4, wherein the Sn concentration in the dielectric layers of the three or more layers is less than 5 at%.

10. The ceramic electronic component of any one of claims 1 to 4, wherein the Sn concentration in the dielectric layers of the above three or more layers is 0.1 at% or more.

11. A method for manufacturing a ceramic electronic component, characterized by comprising: The process includes the following steps: forming a stacked unit by forming an internal electrode pattern containing metal powder on a dielectric preform containing ceramic powder and Sn source; stacking three or more of the stacked units to form a stacked body; and calcining the stacked body; wherein, in at least two of the dielectric preforms before calcination, the concentration of Sn relative to the main component ceramic is reduced in the dielectric preforms at the ends of the stacking direction compared to the dielectric preforms at the center side of the stacking direction.

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