Image sensor and method of fabricating the same

Abstract

A method of manufacturing an image sensor includes: forming a semiconductor substrate of a first conductivity type; forming pixel isolation trenches in the semiconductor substrate to define pixel regions; forming a pad insulating layer in the pixel isolation trenches; doping the pad insulating layer with a dopant of the first conductivity type; forming a semiconductor layer on the pad insulating layer after doping with the dopant to fill the pixel isolation trenches; and performing a thermal processing on the semiconductor substrate.

Description

Technical Field

[0001] This disclosure relates to an image sensor and a method of manufacturing the image sensor, and more particularly to an image sensor having improved electrical and optical characteristics and a method of manufacturing the image sensor. [Cross-reference to related applications]

[0002] This application claims priority to Korean Patent Application No. 10-2021-0104097, filed on August 6, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

Background Art

[0003] An image sensor is a device that converts an optical signal into an electrical signal. With the development of the computer and communication industries, the demand for high-performance image sensors for various applications (such as digital cameras, camcorders, personal communication systems, game consoles, security cameras, micro cameras for medical applications, and robots) is increasing.

[0004] Image sensors are generally classified into charge-coupled device (CCD) and complementary metal-oxide semiconductor (CMOS) image sensors. Since CMOS image sensors have lower complexity compared to CCD image sensors, and the circuits of CMOS image sensors can be integrated on a single chip, the size of the corresponding products can be minimized. In addition, since CMOS image sensors consume less power, they can be applied to electronic devices with limited battery capacity. Furthermore, CMOS image sensors have low manufacturing costs, and CMOS image sensors can capture images with high resolution.

Summary of the Invention

[0005] At least one embodiment of the inventive concept provides an image sensor having improved electrical and optical characteristics.

[0006] At least one embodiment of the inventive concept provides a method of manufacturing an image sensor having improved electrical and optical characteristics.

[0007] According to an embodiment of the inventive concept, a method of manufacturing an image sensor includes: forming a semiconductor substrate of a first conductivity type; forming pixel isolation grooves defining pixel regions in the semiconductor substrate; forming a pad insulating layer in the pixel isolation grooves; doping the pad insulating layer with a dopant of the first conductivity type; after doping the dopant, forming a semiconductor layer on the pad insulating layer to fill the pixel isolation grooves; and performing a thermal treatment process on the semiconductor substrate. The thermal treatment process may cause the dopant contained in the pad insulating layer to diffuse into the semiconductor layer.

[0008] According to an embodiment of the inventive concept, a method of manufacturing an image sensor includes: forming a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first surface and a second surface opposite the first surface; forming a device isolation layer near the first surface of the semiconductor substrate; forming a pixel isolation structure to penetrate the device isolation layer and the semiconductor substrate and define a plurality of pixel regions; forming photoelectric conversion regions of a second conductivity type in the semiconductor substrate and in the pixel regions, respectively; and in each of the pixel regions, forming a pixel gate electrode and a transfer gate electrode on the first surface of the semiconductor substrate. Forming the pixel isolation structure may include: patterning the device isolation layer and the semiconductor substrate to form pixel isolation grooves; depositing a pad insulating layer on the surface of the pixel isolation grooves; doping the pad insulating layer with a dopant of the first conductivity type; after forming the pad insulating layer doped with the dopant, forming an undoped polysilicon layer to fill the pixel isolation grooves; etching the polysilicon layer to form a polysilicon pattern having a top surface positioned at a level lower than the first surface of the semiconductor substrate; and performing a thermal treatment process on the semiconductor substrate. The thermal treatment process may cause the dopant contained in the pad insulating layer to diffuse into the polysilicon pattern.

[0009] According to an embodiment of the inventive concept, an image sensor includes: a semiconductor substrate of a first conductivity type; and a pixel isolation structure disposed in the semiconductor substrate to define a plurality of pixel regions. The pixel isolation structure includes: a semiconductor pattern penetrating the semiconductor substrate in a vertical direction; and a pad insulating pattern sandwiched between the semiconductor pattern and the semiconductor substrate. The semiconductor pattern and the pad insulating pattern contain a dopant of the first conductivity type, and the concentration of the dopant of the first conductivity type is higher in the pad insulating pattern than in the semiconductor pattern.

[0010] According to an embodiment of the inventive concept, an image sensor includes a semiconductor substrate, a pixel isolation structure, a photoelectric conversion region, a backside contact plug, a conductive pad, a color filter, and a microlens. The semiconductor substrate is of a first conductivity type. The semiconductor substrate has a first surface and a second surface opposite the first surface. The semiconductor substrate includes a light receiving region, a light blocking region, and a pad region. The pixel isolation structure is positioned in the light receiving region and the light blocking region of the semiconductor substrate to define a plurality of pixel regions. The pixel isolation structure includes a semiconductor pattern and a pad insulating pattern. The semiconductor pattern penetrates the semiconductor substrate in a vertical direction, and the pad insulating pattern is sandwiched between the semiconductor pattern and the semiconductor substrate. The photoelectric conversion region is positioned in the light receiving region, the light blocking region, and the semiconductor substrate of the pixel region. The backside contact plug is positioned in a part of the light blocking region and is adjacent to the second surface of the semiconductor substrate, and is in contact with a part of the semiconductor pattern. The conductive pad is positioned in the pad region and in the second surface of the semiconductor substrate. The color filter is positioned on the second surface of the semiconductor substrate to correspond to the pixel region. The microlens is disposed on the color filter. The semiconductor pattern and the pad insulating pattern of the pixel isolation structure may include a dopant of the first conductivity type. The concentration of the dopant of the first conductivity type may be higher in the pad insulating pattern than in the semiconductor pattern.

Embodiment

[0012] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0013] FIG. 1 is a block diagram showing an image sensor according to an embodiment of the inventive concept.

[0014] Referring to FIG. 1, the image sensor may include an active pixel sensor array 1, a column decoder 2 (e.g., a circuit), a column driver 3 (e.g., a circuit), a row decoder 4 (e.g., a circuit), a timing generator 5 (e.g., a timing controller or a control circuit), a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7, and an input / output (I / O) buffer 8.

[0015] The active pixel sensor array 1 may include a plurality of unit pixels arranged two-dimensionally to convert an optical signal into an electrical signal. The active pixel sensor array 1 may be driven by a plurality of driving signals (e.g., pixel selection signals, reset signals, and charge transfer signals) transmitted from the column driver 3. The converted electrical signal may be provided to the CDS 6.

[0016] The column driver 3 may be configured to provide a driving signal for driving the plurality of unit pixels to the active pixel sensor array 1 based on the result decoded by the column decoder 2. In the case where the unit pixels are arranged in a matrix shape (i.e., arranged in columns and rows), the driving signal may be provided to the corresponding columns.

[0017] The timing generator 5 may be configured to provide timing and control signals to the column decoder 2 and the row decoder 4.

[0018] The CDS 6 may be configured to receive an electrical signal generated in the active pixel sensor array 1 and perform a holding and sampling operation on the received electrical signal. For example, the CDS 6 may perform a double sampling operation on specific noise levels and signal levels of the electrical signal, and may output a difference level corresponding to the difference between the noise level and the signal level.

[0019] The ADC 7 may be configured to convert an analog signal corresponding to the difference level output from the CDS 6 into a digital signal, and then output the converted digital signal to the I / O buffer 8.

[0020] The I / O buffer 8 may be configured to latch the digital signal based on the result decoded by the row decoder 4 and sequentially output the latched digital signal to an image signal processing unit (not shown).

[0021] FIGS. 2A and 2B are circuit diagrams showing unit pixels of an image sensor according to an embodiment of the inventive concept.

[0022] Referring to FIG. 2A, the unit pixel P may include a first photoelectric conversion device PD1 and a second photoelectric conversion device PD2, a first transfer transistor TX1 and a second transfer transistor TX2, and four pixel transistors.

[0023] The pixel transistors may include a reset transistor RX, a source follower transistor SF, a selection transistor SX, and a dual conversion gain transistor DCX. In an embodiment, each of the unit pixels P is shown as including four pixel transistors, but the inventive concept is not limited to this example. That is, the number of pixel transistors in each of the unit pixels P may be changed in various ways.

[0024] In an embodiment, the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 may be configured to generate charges in response to incident light. In this embodiment, the generated charges may be accumulated in the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2. The first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 may be, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), and combinations thereof.

[0025] The first transfer transistor TX1 and the second transfer transistor TX2 may be configured to transfer the charges stored in the first photoelectric conversion device PD1 and the second photoelectric conversion device PD2 to the first floating diffusion region FD1. The first transfer transistor TX1 and the second transfer transistor TX2 may be controlled by a first transfer signal TG1 and a second transfer signal TG2. The first transfer transistor TX1 and the second transfer transistor TX2 may share the first floating diffusion region FD1.

[0026] The first floating diffusion region FD1 may be configured to receive the charges generated in the first photoelectric conversion device PD1 or the second photoelectric conversion device PD2 and store the charges in an accumulated manner. The source follower transistor SF may be controlled by the amount of the photocharges stored in the first floating diffusion region FD1.

[0027] The reset transistor RX may periodically reset the charges stored in the first floating diffusion region FD1 and the second floating diffusion region FD2 in response to a reset signal applied to the reset gate electrode RG. In an embodiment, the reset transistor RX may include a drain terminal and a source terminal, the drain terminal being connected to the dual conversion gain transistor DCX, and the source terminal being connected to the pixel power supply voltage VPIX. If the reset transistor RX and the dual conversion gain transistor DCX are turned on, the pixel power supply voltage VPIX may be applied to the first floating diffusion region FD1 and the second floating diffusion region FD2. Accordingly, the charges stored in the first floating diffusion region FD1 and the second floating diffusion region FD2 may be discharged, and as a result, the first floating diffusion region FD1 and the second floating diffusion region FD2 may be reset.

[0028] The dual-conversion gain transistor DCX can be disposed between the first floating diffusion region FD1 and the second floating diffusion region FD2 to connect them to each other. The dual-conversion gain transistor DCX can be connected in series to the reset transistor RX via the second floating diffusion region FD2. In other words, the dual-conversion gain transistor DCX can be disposed between the first floating diffusion region FD1 and the reset transistor RX to connect them to each other. The dual-conversion gain transistor DCX can be configured to change the first capacitance C FD1 of the first floating diffusion region FD1 in response to the dual-conversion gain control signal DCG, and thereby change the conversion gain of the unit pixel P.

[0029] Specifically, during the imaging process, not only high-intensity light may be incident on the pixel array, but also low-intensity light may be incident on the pixel array. Therefore, the conversion gain in each pixel can vary depending on the incident light. For example, when the dual-conversion gain transistor DCX is turned off, the unit pixel can have a first conversion gain, and when the dual-conversion gain transistor DCX is turned on, the unit pixel can have a second conversion gain higher than the first conversion gain. That is, depending on the operation of the dual-conversion gain transistor DCX, the conversion gain in the first conversion gain mode (or high-brightness mode) can have a value different from that in the second conversion gain mode (or low-brightness mode).

[0030] When the dual-conversion gain transistor DCX is turned off, the first floating diffusion region FD1 can have a capacitance corresponding to the first capacitance C FD1. When the dual-conversion gain transistor DCX is turned on, the first floating diffusion region FD1 can be connected to the second floating diffusion region FD2, and the capacitance of the first floating diffusion region FD1 and the second floating diffusion region FD2 can be the sum of the first capacitance C FD1 and the second capacitance C FD2. That is, when the dual-conversion gain transistor DCX is turned on, the capacitance of the first floating diffusion region FD1 or the second floating diffusion region FD2 can increase to reduce the conversion gain, and when the dual-conversion gain transistor DCX is turned off, the capacitance of the first floating diffusion region FD1 can decrease to increase the conversion gain.

[0031] The source follower transistor SF can be a source follower buffer amplifier, which is configured to generate a source-drain current proportional to the amount of charge of the first floating diffusion region FD1 to be input to the source follower gate electrode. The source follower transistor SF can amplify the potential change of the floating diffusion region FD to generate an amplified signal, and can output the amplified signal to the output line Vout via the selection transistor SX. The source follower transistor SF can include a source terminal and a drain terminal, the source terminal is connected to the pixel power supply voltage VPIX, and the drain terminal is connected to the source terminal of the selection transistor SX.

[0032] The selection transistor SX can be used to select a column in the unit pixel P to be read out during a read operation. When the selection transistor SX is turned on by a selection signal SG applied to the selection gate electrode, the electrical signal output to the drain electrode of the source follower transistor SF can be output to the output line Vout.

[0033] Referring to FIGS. 2B and 4, the unit pixel P may include a photoelectric conversion circuit 10 and a pixel circuit 20. As described with reference to FIG. 2A, the photoelectric conversion circuit 10 may include a first photoelectric conversion device PD1, a second photoelectric conversion device PD2, a third photoelectric conversion device PD3, a fourth photoelectric conversion device PD4, a first transfer transistor TX1, a second transfer transistor TX2, a third transfer transistor TX3, a fourth transfer transistor TX4, and a first floating diffusion region FD1. Similar to the embodiment shown in FIG. 2A, the pixel circuit 20 may include four pixel transistors (e.g., RX, DCX, SF, and SX).

[0034] The first transfer transistor to the fourth transfer transistor TX1, TX2, TX3, and TX4 may share the first floating diffusion region FD1. The transfer gate electrodes of the first transfer transistor to the fourth transfer transistor TX1, TX2, TX3, and TX4 may be controlled by a first transfer signal to a fourth transfer signal TG1, TG2, TG3, and TG4, respectively.

[0035] FIG. 3 is a plan view of an image sensor according to an embodiment of the concept of the present invention. FIG. 4 is a cross-sectional view of the image sensor taken along the line I-I' shown in FIG. 3 to show an embodiment of the concept of the present invention.

[0036] FIGS. 5A and 5B are enlarged cross-sectional views showing a portion "P1" shown in FIG. 4. FIG. 6A is a graph showing a doping profile curve in a region taken along the line A-A' shown in FIG. 5A. FIG. 6B is a graph showing a doping profile curve in a semiconductor pattern of an image sensor according to an embodiment of the concept of the present invention.

[0037] Referring to FIGS. 3 and 4, when observed in a vertical cross-section, the image sensor according to an embodiment of the concept of the present invention may include a photoelectric conversion layer 10, a readout circuit layer 20, and an optically transparent layer 30.

[0038] When observed in a vertical cross-section, the photoelectric conversion layer 10 may be disposed between the readout circuit layer 20 and the optically transparent layer 30. The photoelectric conversion layer 10 may be configured to convert light incident from the outside into an electrical signal. The photoelectric conversion layer 10 may include a semiconductor substrate 100, a pixel isolation structure PIS, and a photoelectric conversion region PD.

[0039] In an embodiment, the semiconductor substrate 100 has a first surface or top surface 100a and a second surface or bottom surface 100b opposite to the first surface or top surface 100a. The semiconductor substrate 100 may be a substrate including a bulk silicon substrate and an epitaxial layer, and the bulk silicon substrate and the epitaxial layer are stacked in sequence and are of a first conductivity type (e.g., p-type). In an embodiment where the bulk silicon substrate is removed during the manufacturing process of the image sensor, the semiconductor substrate 100 may be composed only of a p-type epitaxial layer. In an embodiment, the semiconductor substrate 100 may be a bulk semiconductor substrate including a well of a first conductivity type.

[0040] In each of the pixel regions PR, a device isolation layer 105 may be disposed adjacent to the first surface 100a of the semiconductor substrate 100. The device isolation layer 105 may be disposed in a device isolation trench T1 formed by recessing the first surface 100a of the semiconductor substrate 100. For example, a recess may be formed in the first surface 100a, and the recess may be filled with the device isolation layer 105. The device isolation layer 105 may be formed of or include an insulating material. In an embodiment, the device isolation layer 105 may include a pad oxide layer, a pad nitride layer, and a gap-fill oxide layer. The pad oxide layer and the pad nitride layer are formed to conformally cover the surface of the device isolation trench T1, and the gap-fill oxide layer is formed to fill the device isolation trench T1 in which the pad oxide layer and the pad nitride layer are disposed. The device isolation layer 105 may define an active portion in the semiconductor substrate 100 and is located near the first surface 100a. In an embodiment, the device isolation layer 105 may define a first active portion ACT1 and a second active portion ACT2 in the semiconductor substrate 100. In each of the pixel regions PR, the first active portion ACT1 and the second active portion ACT2 may be spaced apart from each other and may have different sizes from each other. For example, in FIG. 3, the first active portion ACT1 has an L shape, while the second active portion ACT2 has a rectangular shape, but the embodiments of the inventive concept are not limited thereto.

[0041] A pixel isolation structure PIS may be disposed in the semiconductor substrate 100 to define a plurality of pixel regions PR. The pixel isolation structure PIS may extend in a vertical direction from the first surface 100a of the semiconductor substrate 100 to the second surface 100b. The pixel isolation structure PIS may penetrate a part of the device isolation layer 105.

[0042] The pixel isolation structure PIS may include a first part and a second part. The first part extends in a first direction D1 and is parallel to each other. The second part extends in a second direction D2 and is parallel to each other to cross the first part. When observed in a plan view, the pixel isolation structure PIS may be arranged to surround each of the pixel regions PR or each of the photoelectric conversion regions PD.

[0043] The pixel isolation structure PIS may have an upper width at the level of the first surface 100a of the semiconductor substrate 100 and may have a lower width at the level of the second surface 100b (e.g., bottom surface) of the semiconductor substrate 100. The lower width may be substantially equal to or less than the upper width. In an embodiment, the width of the pixel isolation structure PIS may gradually decrease in a direction from the first surface 100a of the semiconductor substrate 100 toward the second surface 100b. The pixel isolation structure PIS may have a length in a direction perpendicular to the top surface 100a of the semiconductor substrate 100 (i.e., a third direction D3). The length of the pixel isolation structure PIS may be substantially equal to the vertical thickness of the semiconductor substrate 100.

[0044] More specifically, referring to FIGS. 5A and 5B, the pixel isolation structure PIS may be disposed in a pixel isolation trench T2 formed in the semiconductor substrate 100. The pixel isolation structure PIS may include a pad insulating pattern 111, a semiconductor pattern 113, and a gap filling insulating pattern 115. The pixel isolation structure PIS may have an aspect ratio of about 10:1 to about 15:1.

[0045] The pad insulating pattern 111 may be disposed between the semiconductor pattern 113 and the semiconductor substrate 100. The pad insulating pattern 111 may be in direct contact with the semiconductor substrate 100. In an embodiment, the pad insulating pattern 111 has a refractive index lower than that of the semiconductor substrate 100. For example, the pad insulating pattern 111 may be formed of or include at least one of a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high-k dielectric material (e.g., hafnium oxide and / or aluminum oxide). In an embodiment, the pad insulating pattern 111 may include multiple layers formed of different materials. The pad insulating pattern 111 may have a thickness of about 30 angstroms to 350 angstroms.

[0046] When observed in a plan view, the pad insulating pattern 111 may be provided to surround each of the pixel regions PR. The pad insulating patterns 111 surrounding the pixel regions PR may be spaced apart from each other.

[0047] The semiconductor pattern 113 can be disposed as a single body in the semiconductor substrate 100. That is, the semiconductor pattern 113 can be composed of a single layer. The semiconductor pattern 113 composed of a single layer can have a discontinuous interface 113s (e.g., a seam or a void) formed in its central portion. The top surface 113t of the semiconductor pattern 113 can be positioned at a different level from the top surface of the semiconductor substrate 100. Referring to FIG. 5A, the top surface 113t of the semiconductor pattern 113 can be positioned at substantially the same level as the bottom surface of the device isolation layer 105. As an alternative, referring to FIG. 5B, the top surface 113t of the semiconductor pattern 113 can be positioned at a different level from the bottom surface of the device isolation layer 105. For example, the top surface 113t of the semiconductor pattern 113 can be positioned lower than the bottom surface of the device isolation layer 105.

[0048] The semiconductor pattern 113 can include a first portion and a second portion. The first portion extends parallel to each other in a first direction D1, and the second portion extends parallel to each other in a second direction D2 and intersects the first portion. The semiconductor pattern 113 can continuously extend in the first direction D1 and the second direction D2.

[0049] The pad insulating pattern 111 and the semiconductor pattern 113 can contain a dopant of a first conductivity type. The dopant of the first conductivity type can include at least one of, for example, boron (B), phosphorus (P), arsenic (As), gallium (Ga), indium (In), antimony (Sb), or aluminum (Al).

[0050] As an example, the pad insulating pattern 111 and the semiconductor pattern 113 can contain boron, and the doping concentration of boron in the pad insulating pattern 111 can range from about 1×10^15 per cubic centimeter to about 1×10^17 per cubic centimeter.

[0051] In an embodiment, as shown in FIG. 6A, the concentration of the dopant of the first conductivity type in the pad insulating pattern 111 can be higher than that in the semiconductor pattern 113. In an embodiment, the doping concentration of the dopant of the first conductivity type in the pad insulating pattern 111 can have a maximum value. As an alternative, the dopant of the first conductivity type can have substantially the same concentration in the pad insulating pattern 111 and the semiconductor pattern 113.

[0052] In addition, the concentration of the dopant in the semiconductor pattern 113 can be about 1 to 10 times the concentration of the dopant of the first conductivity type in the semiconductor substrate 100. In an exemplary embodiment, the concentration of the dopant of the first conductivity type in the semiconductor pattern 113 is about 8 to 9 times the concentration of the dopant of the first conductivity type in the semiconductor substrate 100.

[0053] Referring to FIG. 6B, the concentration of the dopant in the upper region of the semiconductor pattern 113 adjacent to the first surface 100a of the semiconductor substrate 100 may be higher than or substantially equal to the concentration in the lower region of the semiconductor pattern 113 adjacent to the second surface 100b of the semiconductor substrate 100.

[0054] The gap-fill insulating pattern 115 may be disposed on the top surface 113t of the semiconductor pattern 113, and the top surface of the gap-fill insulating pattern 115 may be positioned at substantially the same level as the top surface of the device isolation layer 105. The bottom surface of the gap-fill insulating pattern 115 may be positioned at a level lower than or equal to the level of the bottom surface of the device isolation layer 105.

[0055] The bottom surface of the gap-fill insulating pattern 115 may have a rounded shape. The gap-fill insulating pattern 115 may be formed of or include at least one of silicon oxide, silicon oxynitride, or silicon nitride.

[0056] Referring back to FIGS. 3 and 4, the photoelectric conversion regions PD may be respectively disposed in the semiconductor substrate 100 in the pixel region PR. The photoelectric conversion regions PD may generate photo charges proportional to the intensity of the incident light. The photoelectric conversion regions PD may be formed by injecting impurities into the semiconductor substrate 100, and the impurities are of a second conductivity type different from that of the semiconductor substrate 100. The photoelectric conversion regions PD of the second conductivity type and the semiconductor substrate 100 of the first conductivity type may form a pn junction serving as a photodiode.

[0057] In an embodiment, each of the photoelectric conversion regions PD may be arranged to have a doping concentration difference between the portions adjacent to the first surface 100a and the second surface 100b, whereby there is a non-vanishing potential gradient between the first surface 100a and the second surface 100b of the semiconductor substrate 100. For example, the photoelectric conversion region PD may include a plurality of impurity regions stacked in the vertical direction.

[0058] The readout circuit layer 20 may be disposed on the first surface 100a of the semiconductor substrate 100. The readout circuit layer 20 may include a readout circuit (e.g., a metal-oxide semiconductor (MOS) transistor), and the readout circuit is electrically connected to the photoelectric conversion region PD. For example, the readout circuit layer 20 may include the reset transistor RX, the selection transistor SX, the dual conversion gain transistor DCX, and the selection transistor SX described with reference to FIGS. 2A and 2B.

[0059] In each of the pixel regions PR, a transfer gate electrode TG may be provided on the first active portion ACT1 of the semiconductor substrate 100. When observed in a plan view, the transfer gate electrode TG may be positioned at the center portion of each pixel region PR. A part of the transfer gate electrode TG may be provided in the semiconductor substrate 100, and a gate insulating layer GIL may be interposed between the transfer gate electrode TG and the semiconductor substrate 100. For example, a first portion of the gate insulating layer GIL may contact the left exposed side of the transfer gate electrode TG, and a second other portion of the gate insulating layer GIL may contact the right exposed side of the transfer gate electrode TG.

[0060] A floating diffusion region FD may be provided in a part of the first active portion ACT1 positioned on one side of the transfer gate electrode TG. The floating diffusion region FD may be formed by injecting impurities into the semiconductor substrate 100. In an embodiment, the conductivity type of the floating diffusion region FD is different from the conductivity type of the semiconductor substrate 100. For example, the floating diffusion region FD may be an n-type impurity region.

[0061] In each of the pixel regions PR, at least one pixel transistor may be provided on the second active portion ACT2. The pixel transistor provided in each pixel region PR may be one of the reset transistor RX, source follower transistor SF, dual conversion gain transistor DCX, and selection transistor SX described with reference to FIGS. 2A and 2B.

[0062] The pixel transistor may include a pixel gate electrode PG and source / drain regions, the pixel gate electrode PG being provided to cross the second active portion ACT2, and the source / drain regions being provided in parts of the second active portion ACT2 positioned on both sides of the pixel gate electrode PG.

[0063] The pixel gate electrode PG may have a bottom surface parallel to the top surface of the second active portion ACT2. The pixel gate electrode PG may be formed of or include at least one of, for example, doped polysilicon, a metal material, a conductive metal nitride, a conductive metal silicide material, a conductive metal oxide material, or a combination thereof.

[0064] A gate insulating layer GIL may be provided between the pixel gate electrode PG and the second active portion ACT2. The gate insulating layer GIL may be formed of or include at least one of silicon oxide, silicon oxynitride, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The source / drain regions of the pixel transistor may contain impurities of a second conductivity type. As an example, the source / drain regions may contain n-type impurities.

[0065] An interlayer insulating layer 210 may be disposed on the first surface 100a of the semiconductor substrate 100 to cover the transfer gate electrode TG and the pixel gate electrode PG.

[0066] The interlayer insulating layer 210 may be provided with interconnection structures 221 and 223 connected to the readout circuit. The interconnection structures 221 and 223 may include metal wires 223 and contact plugs 221 that connect the metal wires 223 to each other.

[0067] An optically transparent layer 30 may be disposed on the second surface 100b of the semiconductor substrate 100. The optically transparent layer 30 may include a planarizing insulating layer 310, a lattice structure 320, a protective layer 330, a color filter 340, a microlens 350, and a passivation layer 360. The optically transparent layer 30 may be configured to perform operations of focusing and filtering light incident from the outside and provide the light to the photoelectric conversion layer 10.

[0068] Specifically, the planarizing insulating layer 310 may cover the second surface 100b of the semiconductor substrate 100. The planarizing insulating layer 310 may be formed of a transparent insulating material and may include multiple layers. In an embodiment, the planarizing insulating layer 310 is formed of an insulating material having a refractive index different from that of the semiconductor substrate 100. The planarizing insulating layer 310 may be formed of or include at least one of a metal oxide and / or silicon oxide.

[0069] The lattice structure 320 may be disposed on the planarizing insulating layer 310. When observed in a plan view, similar to the pixel isolation structure PIS, the lattice structure 320 may have a lattice shape. When observed in a plan view, the lattice structure 320 may overlap with the pixel isolation structure PIS. That is, the lattice structure 320 may include a first portion and a second portion, the first portion extending in a first direction D1, and the second portion extending in a second direction D2 to intersect the first portion. The width of the lattice structure 320 may be substantially equal to or less than the minimum width of the pixel isolation structure PIS.

[0070] The lattice structure 320 may include a conductive pattern and / or a low-refraction pattern. The light-blocking pattern may be formed of or include at least one of a metal material (e.g., titanium, tantalum, or tungsten). In an embodiment, the low-refraction pattern is formed of a material having a refractive index lower than that of the light-blocking pattern or includes the material. The low-refraction pattern may be formed of an organic material. In an embodiment, the low-refraction pattern has a refractive index of about 1.1 to 1.3. For example, the lattice structure 320 may be a polymer layer containing silicon dioxide nanoparticles.

[0071] The protective layer 330 may be disposed on the planarized insulating layer 310 to conformally cover the surface of the lattice structure 320 (i.e., to achieve a substantially uniform thickness). The protective layer 330 may be a single-layer or multi-layer structure, and the single-layer or multi-layer structure includes at least one of an aluminum oxide layer and a silicon carbon oxide layer.

[0072] The color filter 340 may be formed to correspond to the pixel region PR, respectively. The color filter 340 may be disposed to fill the empty region defined by the lattice structure 320. The color filter 340 may include a red, green, or blue color filter or a magenta, cyan, or yellow color filter, and its color is determined based on the position of the unit pixel.

[0073] The microlens 350 may be disposed on the color filter 340. The microlens 350 may have a convex shape and may have a specific radius of curvature. The microlens 350 may be formed of or include the optically transparent resin.

[0074] The passivation layer 360 may be formed to conformally cover the surface of the microlens 350. The passivation layer 360 may be formed of or include at least one of, for example, inorganic oxide materials.

[0075] FIGS. 7, 8, and 9 are cross-sectional views, and each of the cross-sectional views is taken along line I-I' shown in FIG. 3 to show an image sensor according to an embodiment of the inventive concept.

[0076] In the embodiments shown in FIGS. 7, 8, and 9, for simplicity of illustration, the elements previously described with reference to FIGS. 3 and 4 may be identified by the same reference numerals and will not be described again.

[0077] Referring to FIG. 7, a potential barrier region PBR may be provided in a part of the semiconductor substrate 100 adjacent to the side surface of the pixel isolation structure PIS. The potential barrier region PBR contains impurities of a second conductivity type. The potential barrier region PBR may contain impurities of the same conductivity type as the semiconductor substrate 100 (e.g., a first conductivity type or p-type). The potential barrier region PBR may be in contact with the side surface of the pad insulating pattern 111 of the pixel isolation structure PIS. The potential barrier region PBR may contain impurities of the same type as the impurities in the pad insulating pattern 111. In an embodiment, the impurity concentration of the potential barrier region PBR is higher than the impurity concentration of the semiconductor substrate 100. Electron-hole pairs (EHP) that cause dark current may be generated due to surface defects formed during the process of forming the pixel isolation trench T2 in the pixel isolation trench T2. However, according to an embodiment of the present invention concept, the dark current can be reduced by the potential barrier region PBR.

[0078] Referring to FIG. 8, the pixel isolation structure PIS may have a first width near the first surface 100a of the semiconductor substrate 100 and a second width greater than the first width near the second surface 100b of the semiconductor substrate 100. Additionally, the width of the pixel isolation structure PIS may gradually increase in the direction from the first surface 100a of the semiconductor substrate 100 toward the second surface 100b.

[0079] As described above, the pixel isolation structure PIS may include a pad insulating pattern 111, a semiconductor pattern 113, and a gap-fill insulating pattern 115.

[0080] The pixel isolation structure PIS may be in contact with the device isolation layer 105. In an embodiment, a part of the pad insulating pattern 111 of the pixel isolation structure PIS may be in contact with the device isolation layer 105. The said part of the pad insulating pattern 111 may be positioned between the device isolation layer 105 and the semiconductor pattern 113.

[0081] Referring to FIG. 9, the pixel isolation structure PIS may include a first pixel isolation structure PIS1 and a second pixel isolation structure PIS2. Here, the first pixel isolation structure PIS may be configured to have substantially the same characteristics as the pixel isolation structure PIS described previously with reference to FIGS. 3 and 4. A part of the pad insulating pattern 111 may be in contact with the second pixel isolation structure PIS2 and may be provided between the second pixel isolation structure PIS2 and the semiconductor pattern 113.

[0082] The second pixel isolation structure PIS2 may have a planar structure substantially the same as that of the first pixel isolation structure PIS1. When observed in a plan view, the second pixel isolation structure PIS2 may overlap with the first pixel isolation structure PIS1. That is, the second pixel isolation structure PIS2 may include a first portion and a second portion, the first portion extending in a first direction D1, and the second portion extending in a second direction D2 to intersect the first portion.

[0083] The second pixel isolation structure PIS2 may extend from the second surface 100b of the semiconductor substrate 100 in a vertical direction D3 and may be disposed in the semiconductor substrate 100. The second pixel isolation structure PIS2 may be disposed in a trench recessed from the second surface 100b of the semiconductor substrate 100. For example, a recess may be formed in the second surface 100b, and the recess may be filled with the second pixel isolation structure PIS2.

[0084] The second pixel isolation structure PIS2 may have a bottom surface positioned between the first surface 100a and the second surface 100b of the semiconductor substrate 100. That is, the second pixel isolation structure PIS2 may be spaced apart from the first surface 100a of the semiconductor substrate 100. The second pixel isolation structure PIS2 may be in contact with the first pixel isolation structure PIS1. For example, the bottom surface of the second pixel isolation structure PIS2 may be in contact with the bottom surface of the first pixel isolation structure PIS1.

[0085] The second pixel isolation structure PIS2 may have a second upper width at the level of the second surface 100b of the semiconductor substrate 100 and may have a second lower width at the level of its bottom surface. The second lower width may be less than or substantially equal to the second upper width. The width of the second pixel isolation structure PIS2 may gradually decrease from the second surface 100b of the semiconductor substrate 100 toward the first surface 100a.

[0086] When measured in the vertical direction D3, the length of the second pixel isolation structure PIS2 may be different from the length of the first pixel isolation structure PIS1. In an embodiment, the length of the second pixel isolation structure PIS2 may be less than or equal to the length of the first pixel isolation structure PIS1.

[0087] The second pixel isolation structure PIS2 may be formed of or include at least one of high-k dielectric materials having a dielectric constant higher than that of the silicon oxide layer. As an example, the second pixel isolation structure PIS2 may include a metal oxide or a metal fluoride containing at least one metal element selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanum (La). For example, the second pixel isolation structure PIS2 may include an aluminum oxide layer and a hafnium oxide layer stacked in sequence.

[0088] FIG. 10 is a flowchart showing a method of forming a pixel isolation structure of an image sensor according to an embodiment of the inventive concept. FIGS. 11 to 21 are cross-sectional views taken along line I-I' shown in FIG. 3 to show a method of manufacturing an image sensor according to an embodiment of the inventive concept.

[0089] Referring to FIGS. 5 and 11, a semiconductor substrate 100 of a first conductivity type (e.g., p-type) may be formed or provided. The semiconductor substrate 100 may have a first surface 100a and a second surface 100b opposite to the first surface 100a. The semiconductor substrate 100 may include a bulk silicon substrate and an epitaxial layer, the bulk silicon substrate being of the first conductivity type, and the epitaxial layer being formed on the bulk silicon substrate and being of the first conductivity type. Here, the bulk silicon substrate may be used as a seed to form the epitaxial layer by a selective epitaxial growth (SEG) process, and during the epitaxial growth process, the epitaxial layer may be doped with impurities of the first conductivity type. For example, the epitaxial layer may contain p-type impurities.

[0090] In an embodiment, the semiconductor substrate 100 may be a bulk semiconductor substrate including a well of the first conductivity type. In an embodiment, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, or a silicon-germanium substrate.

[0091] Device isolation trenches T1 may be formed by patterning the first surface 100a of the semiconductor substrate 100. The device isolation trenches T1 may define a first active portion ACT1 and a second active portion ACT2 in each of the pixel regions PR. The forming of the device isolation trenches T1 may include: forming a buffer layer BFL and a mask pattern MP on the first surface 100a of the semiconductor substrate 100, and anisotropically etching the semiconductor substrate 100 using the mask pattern MP as an etching mask.

[0092] The buffer layer BFL can be formed by performing a deposition process or a thermal oxidation process on the first surface 100a of the semiconductor substrate 100. The buffer layer BFL can include a silicon oxide layer.

[0093] The mask pattern MP can include a silicon nitride layer or a silicon oxynitride layer.

[0094] Next, the device isolation insulating layer 103 can be formed to fill the device isolation trench T1. The device isolation insulating layer 103 can be formed by thickly depositing an insulating material on the semiconductor substrate 100 provided with the device isolation trench T1. The device isolation insulating layer 103 can fill the device isolation trench T1 and can cover the mask pattern MP.

[0095] Thereafter, referring to FIGS. 5, 10, and 12, a pixel isolation trench T2 is formed in the semiconductor substrate 100 to define a pixel region (in S10). For example, the pixel region is formed in the semiconductor substrate 100.

[0096] The pixel isolation trench T2 can be formed by patterning the device isolation insulating layer 103 and the first surface 100a of the semiconductor substrate 100. The plurality of first pixel regions and the plurality of second pixel regions can be arranged in a matrix shape, or the plurality of first pixel regions and the plurality of second pixel regions can be arranged in a first direction D1 and a second direction D2 that intersect each other.

[0097] Specifically, the forming of the pixel isolation trench T2 can include: forming a second mask pattern (not shown) on the device isolation insulating layer 103 and anisotropically etching the semiconductor substrate 100 using the second mask pattern as an etching mask.

[0098] The pixel isolation trench T2 can extend in a vertical direction from the first surface 100a of the semiconductor substrate 100 toward the second surface 100b to expose a part of the side surface of the semiconductor substrate 100. The pixel isolation trench T2 can be formed deeper than the device isolation trench T1 and can penetrate a part of the device isolation trench T1. The pixel isolation trench T2 can be a deep trench having an aspect ratio of about 10:1 to 15:1.

[0099] When observed in a plan view, the pixel isolation trench T2 can include a plurality of first regions and a plurality of second regions. The plurality of first regions extend in the first direction D1 and have a uniform width, and the plurality of second regions extend in a second direction D2 that intersects the first direction D1 and have a uniform width.

[0100] Since the pixel isolation groove T2 is formed by performing an anisotropic etching process, the pixel isolation groove T2 may have a gradually decreasing width in a direction from the first surface 100a of the semiconductor substrate 100 toward the second surface 100b. That is, the pixel isolation groove T2 may have one or more inclined side surfaces. The bottom surface of the pixel isolation groove T2 may be spaced apart from the second surface 100b of the semiconductor substrate 100.

[0101] After forming the pixel isolation groove T2, the second mask pattern may be removed.

[0102] Referring to FIGS. 5, 10, and 13, a preliminary pad insulating layer 110a is formed in the pixel isolation groove T2 (in S20). For example, the preliminary pad insulating layer 110a may be formed to cover the inner surface of the pixel isolation groove T2.

[0103] The preliminary pad insulating layer 110a may conformally cover the inner surface of the pixel isolation groove T2 and the top surface of the device isolation insulating layer 103. The preliminary pad insulating layer 110a may be deposited by a deposition method having good step-coverage properties. The preliminary pad insulating layer 110a may be formed of or include at least one of, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. In an embodiment, the preliminary pad insulating layer 110a may be deposited to have a thickness of about 30 angstroms to 350 angstroms.

[0104] Referring to FIGS. 5, 10, and 14, a doping process is performed on the preliminary pad insulating layer 110a (in S30).

[0105] The doping process may include doping the preliminary pad insulating layer 110a with a dopant of a first conductivity type. As a result of doping the preliminary pad insulating layer 110a, a pad insulating layer 110b of the first conductivity type may be formed.

[0106] The doping process may be, for example, a beam line ion implantation process or a plasma doping process (PLAD). In the case of the plasma doping process, a gaseous source material may be supplied to the process chamber. The source material may be ionized by plasma, and then, the ionized source material may be injected into the preliminary pad insulating layer 110a by applying a high voltage bias to an electrostatic chuck (not shown) on which the semiconductor substrate 100 is placed.

[0107] In the case of the plasma doping process, a uniform doping distribution curve can be achieved even at a deep level, and the process time of the doping process can be reduced. In this case, a uniform doping concentration can be achieved regardless of the position in the preliminary pad insulating layer 110a. More specifically, the preliminary pad insulating layer 110a may include a first region and a second region, the first region being adjacent to the first surface 100a of the semiconductor substrate 100, and the second region being adjacent to the second surface 100b of the semiconductor substrate 100. The concentration of the dopant of the first conductivity type in the first region of the preliminary pad insulating layer 110a may be substantially equal to the doping concentration of the second region of the preliminary pad insulating layer 110a.

[0108] For the beam-line ion implantation process, it may be difficult to uniformly dope the pad insulating layer 110b regardless of the vertical depth because the device isolation trench T1 is formed to have a large depth and a small width. In other words, in the case where the doping process is performed by the beam-line ion implantation process, the doping concentration in the pad insulating layer 110b may vary depending on the vertical depth. For example, the doping concentration of the upper portion of the pad insulating layer 110b may be higher than the doping concentration of the lower portion of the pad insulating layer 110b.

[0109] In an embodiment, a gas-phase doping process may be performed as the doping process. The gas-phase doping process may include supplying a doping gas onto the inner surface of the preliminary pad insulating layer 110a. Here, the doping gas may contain an element in Group III (for example, aluminum (Al), boron (B), indium (In), and / or gallium (Ga)). As an example, the doping gas may contain a boron-containing gas (for example, boron trichloride BCl3 or diborane B2H6). As another example, the doping gas may contain boron trifluoride BF3. After the doping process, the range of the doping concentration of boron in the pad insulating layer 110b may be between about 1×10^15 cm^-3 and about 1×10^17 cm^-3.

[0110] Referring to FIGS. 5, 10, and 15, a semiconductor layer 112 is formed on the pad insulating layer 110b to fill the pixel isolation trench T2 (in S40). The forming of the semiconductor layer 112 may be performed after doping the pad insulating layer 110b. In an embodiment, the semiconductor layer 112 may be an undoped polysilicon layer.

[0111] The semiconductor layer 112 can be formed by a film formation process having good step coverage properties (e.g., a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process). In such a case, in the pixel isolation trench T2, the semiconductor layer 112 can cover the sidewalls and the bottom portion of the pad insulating layer 110b. When the semiconductor layer 112 is formed by a deposition process, as shown in FIG. 5A, a discontinuous interface (e.g., a seam or a void) can be formed in the semiconductor layer 112.

[0112] Referring to FIGS. 5, 10, and 16, the semiconductor pattern 113 can be formed by etching a portion of the semiconductor layer 112 located on the top surface of the device isolation insulating layer 103 and in the upper region of the pixel isolation trench T2.

[0113] The top surface of the semiconductor pattern 113 can be positioned at a level higher than or equal to the bottom surface of the device isolation trench T1. That is, the semiconductor pattern 113 can be formed to fill the lower region of the pixel isolation trench T2. In an embodiment, the top surface of the semiconductor pattern 113 is positioned at a level lower than the bottom surface of the device isolation trench T1.

[0114] Next, a heat treatment process (in S50) is performed on the semiconductor substrate 100.

[0115] In an embodiment, the heat treatment process can be performed in a temperature range of about 550 °C to 800 °C. During the heat treatment process, nitrogen N2, argon Ar, hydrogen H2, or oxygen O2 gas can be used as the process gas.

[0116] The dopant of the first conductivity type in the pad insulating layer 110b can be diffused into the semiconductor pattern 113 by the heat treatment process. That is, the semiconductor pattern 113 can be doped with the dopant diffused from the pad insulating layer 110b. As a result, a doped polysilicon pattern can be formed in the pixel isolation trench T2.

[0117] As described above, since the semiconductor pattern 113 is doped with the dopant, the semiconductor pattern 113 can have a reduced resistance. In addition, by applying a specific voltage to the semiconductor pattern 113 doped with the dopant, the dark current caused by defects at the interface between the semiconductor substrate 100 and the pixel isolation trench T2 can be reduced.

[0118] After the heat treatment process, the doping concentration in the pad insulating layer 110b can be higher than the doping concentration in the semiconductor pattern 113. As an alternative, after the heat treatment process, the doping concentration in the pad insulating layer 110b can be substantially equal to the doping concentration in the semiconductor pattern 113. As an example, after the heat treatment process, the concentration range of the first conductivity type dopant in the pad insulating layer 110b can be between about 1×10^15 cm^-3 and about 1×10^17 cm^-3, while the concentration range of the first conductivity type dopant in the semiconductor pattern 113 can be between about 1×10^13 cm^-3 and about 1×10^17 cm^-3. After the heat treatment process, the concentration of the first conductivity type dopant in the semiconductor pattern 113 can be about 8 to 9 times the concentration of the first conductivity type dopant in the semiconductor substrate 100.

[0119] Referring to FIGS. 5, 10, and 17, an insulating gap filling layer 114 can be formed to fill the pixel isolation trench T2 provided with the semiconductor pattern 113.

[0120] The insulating gap filling layer 114 can be formed on the first surface 100a of the semiconductor substrate 100 to cover the pad insulating layer 110b. The insulating gap filling layer 114 can be formed of or include at least one of, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0121] A layer formation method having good step coverage properties (e.g., a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method) can be used to form the insulating gap filling layer 114. In this case, in the pixel isolation trench T2, the insulating gap filling layer 114 can cover the sidewall portion and the top surface of the pad insulating layer 110b.

[0122] In an embodiment, a deposition method having poor step coverage properties can be used to form the insulating gap filling layer 114. For example, a physical vapor deposition method can be used to form the insulating gap filling layer 114.

[0123] Next, referring to FIGS. 5, 10, and 18, the pad insulating layer 110b and the insulating gap filling layer 114 can be planarized to expose the top surface of the mask pattern MP. As a result, the pad insulating pattern 111, the semiconductor pattern 113, and the gap filling insulating pattern 115 can be formed in the pixel isolation trench T2. Thus, the pixel isolation structure PIS can be formed in the pixel isolation trench T2.

[0124] The mask pattern MP can be removed after forming the pixel isolation structure PIS, and the device isolation layer 105 can be formed in the device isolation trench T1 by planarizing the device isolation insulating layer 103 to expose the first surface 100a of the semiconductor substrate 100. Since the planarization process is performed to expose the first surface 100a of the semiconductor substrate 100, the pixel isolation structure PIS can have a top surface that is substantially coplanar with the top surface of the device isolation layer 105.

[0125] Referring to FIGS. 5 and 18, a photoelectric conversion region PD of the second conductivity type can be formed in the semiconductor substrate 100.

[0126] The photoelectric conversion region PD can be formed by injecting impurities into the semiconductor substrate 100, and the impurities are of the second conductivity type (e.g., n-type) different from the first conductivity type. The photoelectric conversion region PD can be spaced apart from the first surface 100a and the second surface 100b of the semiconductor substrate 100.

[0127] An example of forming the photoelectric conversion region PD after forming the pixel isolation structure PIS is described, but in the embodiment, the photoelectric conversion region PD can be formed before forming the pixel isolation structure PIS.

[0128] Next, referring to FIGS. 5, 10, and 19, MOS transistors constituting the readout circuit can be formed on the first surface 100a of the semiconductor substrate 100.

[0129] Specifically, transfer gate electrodes TG can be respectively formed on the pixel regions PR. The forming of the transfer gate electrodes TG can include: patterning the semiconductor substrate 100 to form gate recessed regions in each of the pixel regions PR; forming a gate insulating layer to conformally cover the inner surfaces of the gate recessed regions; forming a gate conductive layer to fill the gate recessed regions; and patterning the gate conductive layer. For example, gate recessed regions can be formed in the first surface 100a.

[0130] In addition, when forming the transfer gate electrodes TG by patterning the gate conductive layer, gate electrodes of the readout transistors can also be formed in each of the pixel regions PR.

[0131] After forming the transfer gate electrodes TG, floating diffusion regions FD can be formed in parts of the semiconductor substrate 100, and each of the parts is located at one side of the transfer gate electrode TG. The floating diffusion regions FD can be formed by an ion implantation process of injecting impurities of the second conductivity type into the semiconductor substrate 100. In addition, when forming the floating diffusion regions FD, impurity regions serving as source / drain electrodes of the readout transistors can be formed.

[0132] An interlayer insulating layer 210, and internal connection structures 221 and 223 can be formed on the first surface 100a of the semiconductor substrate 100.

[0133] The interlayer insulating layer 210 can be formed to cover the transfer transistor and the logic transistor. The interlayer insulating layer 210 can be formed of a material having good gap filling properties and can be formed to have a substantially flat top surface.

[0134] A contact plug 221 connected to the floating diffusion region FD or the readout transistor can be formed in the interlayer insulating layer 210. A metal wire 223 can be formed between the interlayer insulating layers 210. The contact plug 221 and the metal wire 223 can be formed of or include at least one of, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), and their alloys.

[0135] Referring to FIGS. 5, 10, and 20, a thinning process can be performed to remove a part of the semiconductor substrate 100 or reduce the vertical thickness of the semiconductor substrate 100. The thinning process can include grinding or polishing the second surface 100b of the semiconductor substrate 100 and anisotropically and isotropically etching the semiconductor substrate 100. For the thinning process, the semiconductor substrate 100 can be inverted.

[0136] As an example, a grinding or polishing process can be performed to remove the bulk silicon substrate of the semiconductor substrate 100 and expose the epitaxial layer of the semiconductor substrate 100. Thereafter, an anisotropic or isotropic etching process can be performed to remove surface defects that may exist on the exposed surface of the epitaxial layer. The exposed surface of the epitaxial layer can correspond to the second surface 100b of the semiconductor substrate 100.

[0137] A thinning process of the semiconductor substrate 100 can be performed to expose the semiconductor pattern 113 of the pixel isolation structure PIS near the second surface 100b of the semiconductor substrate 100. As a result, the semiconductor pattern 113 and the pad insulating pattern 111 can have surfaces positioned at substantially the same level as the second surface 100b of the semiconductor substrate 100.

[0138] Next, a planarization insulating layer 310 may be formed on the second surface 100b of the semiconductor substrate 100. The planarization insulating layer 310 may cover the surface of the semiconductor pattern 113 and the second surface 100b of the semiconductor substrate 100. The planarization insulating layer 310 may be formed by depositing a metal oxide layer (e.g., aluminum oxide and / or hafnium oxide).

[0139] Referring to FIGS. 5, 10, and 21, a lattice structure 320 may be formed on the planarization insulating layer 310. The lattice structure 320 may include a light-blocking pattern and / or a low-refractive-index pattern. The light-blocking pattern may be formed of or include at least one of metal materials (e.g., titanium, tantalum, or tungsten). The low-refractive-index pattern may be formed of or include a material having a refractive index lower than that of the light-blocking pattern. The low-refractive-index pattern may be formed of an organic material and may have a refractive index of about 1.1 to 1.3. For example, the lattice structure 320 may be a polymer layer including silicon dioxide nanoparticles.

[0140] The lattice structure 320 may extend in a first direction D1 and a second direction D2 to have a lattice shape. When observed in a plan view, the lattice structure 320 may overlap with the semiconductor pattern 113.

[0141] A protective layer 330 may be formed on the planarization insulating layer 310 to conformally cover the surface of the lattice structure 320 (i.e., to have a substantially uniform thickness). The protective layer 330 may be a single-layer or multi-layer structure including at least one of an aluminum oxide layer and a silicon carbon oxide layer.

[0142] Thereafter, a color filter 340 may be disposed on the protective layer 330 to correspond to the first pixel region and the second pixel region, respectively. The color filter 340 may include blue, red, and green color filters.

[0143] Next, microlenses 350 may be respectively formed on the color filter 340. The microlenses 350 may have a convex shape and may have a specific radius of curvature. The microlenses 350 may be formed of or include an optically transparent resin.

[0144] A passivation layer 360 may conformally cover the top surface of the microlenses 350. The passivation layer 360 may be formed of or include an inorganic oxide material, for example.

[0145] FIG. 22 is a schematic plan view of an image sensor including a semiconductor device according to an embodiment of the inventive concept. FIGS. 23 and 24 are cross-sectional views, each of which is taken along line II-II' shown in FIG. 22 to show the image sensor according to an embodiment of the inventive concept.

[0146] Referring to FIGS. 22 and 23, the image sensor may include a sensor chip C1 and a logic chip C2. The sensor chip C1 may include a pixel array region R1 and a pad region R2.

[0147] The pixel array region R1 may include a plurality of unit pixels P arranged two-dimensionally in two different directions (e.g., in a first direction D1 and a second direction D2). Each of the unit pixels P may include a photoelectric conversion device and a readout device. An electrical signal generated by incident light may be output from each of the unit pixels P in the pixel array region R1.

[0148] The pixel array region R1 may include a light receiving region AR and a light blocking region OB. When observed in a plan view, the light blocking region OB may be arranged to surround the light receiving region AR. For example, when observed in a plan view, the light blocking region OB may be arranged to surround the light receiving region AR in four different directions (e.g., up, down, left, and right directions). In an embodiment, a reference pixel where light is not incident may be provided in the light blocking region OB. In such a case, by comparing the amount of charge obtained from the unit pixels P in the light receiving region AR with the reference charge generated in the reference pixel, the magnitude of the electrical signal sensed from the unit pixels P can be calculated.

[0149] A plurality of conductive pads CP for inputting or outputting control signals and optoelectronic signals may be provided in the pad region R2. When observed in a plan view, the pad region R2 may be arranged to surround the pixel array region R1. In such a case, the electrical connection between the image sensor and an external device can be facilitated. The conductive pads CP can be used to transmit the electrical signals generated in the unit pixels P to an external device.

[0150] In the light receiving region AR, the sensor chip C1 may be configured to have the same technical features as the above-described image sensor. That is, when observed in the vertical direction, the sensor chip C1 may include the readout circuit layer 20, the optically transparent layer 30, and the photoelectric conversion layer 10 located between the readout circuit layer 20 and the optically transparent layer 30 as described above. The photoelectric conversion layer 10 of the sensor chip C1 may include the semiconductor substrate 100, the pixel isolation structure PIS defining the pixel region, and the photoelectric conversion region PD provided in the pixel region as described above. The pixel isolation structure PIS may have substantially the same structure on the light receiving region AR and the light blocking region OB.

[0151] The optically transparent layer 30 may include a light blocking pattern OBP provided on the light blocking region OB, a backside contact plug PLG, a contact pattern CT, an organic layer 355, and a passivation layer 360.

[0152] A portion of the pixel isolation structure PIS can be connected to the backside contact plug PLG on the light blocking region OB.

[0153] Specifically, the semiconductor pattern 113 can be connected to the backside contact plug PLG on the light blocking region OB. A negative bias voltage can be applied to the semiconductor pattern 113 via the contact pattern CT and the backside contact plug PLG. Thus, the dark current generated at the interface between the pixel isolation structure PIS and the semiconductor substrate 100 can be reduced.

[0154] In an embodiment, the backside contact plug PLG has a width greater than the width of the pixel isolation structure PIS. The backside contact plug PLG can be formed of or include at least one of a metal material and / or a metal nitride. For example, the backside contact plug PLG can be formed of or include at least one of titanium and / or titanium nitride.

[0155] The contact pattern CT can be buried in the contact hole in which the backside contact plug PLG is disposed. The contact pattern CT can include a material different from that of the backside contact plug PLG. For example, the contact pattern CT can be formed of or include aluminum (Al).

[0156] The contact pattern CT can be electrically connected to the semiconductor pattern 113 of the pixel isolation structure PIS. A negative bias voltage can be applied to the semiconductor pattern 113 of the pixel isolation structure PIS via the contact pattern CT, and the negative bias voltage can be transmitted from the light blocking region OB to the light receiving region AR.

[0157] In the light blocking region OB, the light blocking pattern OBP can continuously extend from the backside contact plug PLG and can be disposed on the top surface of the planarized insulating layer 310. That is, the light blocking pattern OBP can be formed of or include the same material as the backside contact plug PLG. The light blocking pattern OBP can be formed of or include at least one of a metal material and / or a metal nitride material. For example, the light blocking pattern OBP can be formed of or include at least one of titanium and / or titanium nitride. In an embodiment, the light blocking pattern OBP does not extend to the light receiving region AR of the pixel array region R1.

[0158] The light blocking pattern OBP can prevent light from entering the photoelectric conversion region PD disposed on the light blocking region OB. The photoelectric conversion region PD in the reference pixel of the light blocking region OB can be configured to output a noise signal instead of a photoelectric signal. The noise signal may be generated by electrons due to heat or dark current.

[0159] The protective layer 330 can extend from the pixel array region R1 to the pad region R2. The protective layer 330 can cover the top surface of the light blocking pattern OBP.

[0160] A filter layer 345 can be disposed on the light blocking region OB to cover the protective layer 330. The filter layer 345 can be configured to block light having a wavelength different from the wavelength blocked by the color filter 340. For example, the filter layer 345 can block infrared light. In an embodiment, the filter layer 345 can include a blue color filter, but the inventive concept is not limited to this example.

[0161] The organic layer 355 and the passivation layer 360 can be disposed on the protective layer 330 in the light blocking region OB and the pad region R2. The organic layer 355 can be formed of or include the same material as the microlens 350.

[0162] A first through-conductive pattern 511 can be disposed in the light blocking region OB to penetrate the semiconductor substrate 100, and the first through-conductive pattern 511 can be electrically connected to the metal wire 223 of the readout circuit layer 20 and the interconnection structure 1111 of the logic chip C2. The first through-conductive pattern 511 can have a first bottom surface and a second bottom surface located at different levels. A first gap filling pattern 521 can be disposed in the first through-conductive pattern 511. The first gap filling pattern 521 can be formed of or include at least one of low refractive index materials and can have insulating properties.

[0163] The conductive pad CP can be disposed in a portion of the semiconductor substrate 100 located in the pad region R2 and adjacent to the second surface 100b. The conductive pad CP can be buried in a portion of the semiconductor substrate 100 near the second surface 100b. In an embodiment, the conductive pad CP can be disposed in a pad trench formed in the second surface 100b of the semiconductor substrate 100 and located in the pad region R2. The conductive pad CP can be formed of or include at least one of metal materials (e.g., aluminum, copper, tungsten, titanium, tantalum, or an alloy thereof). During the installation of the image sensor, a bonding wire can be bonded to the conductive pad CP. The conductive pad CP can be electrically connected to an external device via the bonding wire.

[0164] On the pad region R2, a second through-conductive pattern 513 may be provided to penetrate the semiconductor substrate 100, and the second through-conductive pattern 513 may be electrically connected to the interconnection structure 1111 of the logic chip C2. The second through-conductive pattern 513 may extend to a region on the second surface 100b of the semiconductor substrate 100 and may be electrically connected to the conductive pad CP. A part of the second through-conductive pattern 513 may cover the bottom surface and the side surface of the conductive pad CP. A second gap-fill pattern 523 may be provided in the second through-conductive pattern 513. The second gap-fill pattern 523 may be formed of or include at least one of low-refractive-index materials and may have insulating properties. The first pixel isolation structure PIS1 and the second pixel isolation structure PIS2 may be provided on the pad region R2 to surround the second through-conductive pattern 513.

[0165] The logic chip C2 may include a logic semiconductor substrate 1000, logic circuits (TR), an interconnection structure 1111 connected to the logic circuits, and a logic interlayer insulation layer 1100. The uppermost layer in the logic interlayer insulation layer 1100 may be coupled to the readout circuit layer 20 of the sensor chip C1. The logic chip C2 may be electrically connected to the sensor chip C1 via the first through-conductive pattern 511 and the second through-conductive pattern 513.

[0166] In an embodiment, the sensor chip C1 and the logic chip C2 are shown to be electrically connected to each other via the first through-conductive pattern 511 and the second through-conductive pattern 513, but the inventive concept is not limited to this example.

[0167] In the embodiment shown in FIG. 24, the first through-conductive pattern and the second through-conductive pattern shown in FIG. 23 may be omitted, and the sensor chip C1 and the logic chip C2 may be electrically connected to each other by directly connecting bonding pads respectively provided in the uppermost metal layers of the sensor chip C1 and the logic chip C2.

[0168] Specifically, the sensor chip C1 of the image sensor may include a first bonding pad BP1 provided in the uppermost metal layer of the readout circuit layer 20, and the logic chip C2 may include a second bonding pad BP2 provided in the uppermost metal layer of the interconnection structure 1111. The first bonding pad BP1 and the second bonding pad BP2 may be formed of or include at least one of, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN).

[0169] The first bonding pad BP1 of the sensor chip C1 and the second bonding pad BP2 of the logic chip C2 can be directly connected and electrically connected to each other in a hybrid bonding manner. Here, the hybrid bonding manner may mean a bonding manner of fusing two elements into a single element at the interface between two elements containing the same material. For example, in the case where the first bonding pad BP1 and the second bonding pad BP2 are formed of copper (Cu), they can be physically and electrically connected to each other in a Cu-Cu bonding manner. In addition, the insulating layer of the sensor chip C1 and the insulating layer of the logic chip C2 can be bonded to each other in a dielectric-dielectric bonding manner.

[0170] According to an embodiment of the inventive concept, a dopant can be used to pre-dope the pad insulating layer in the pixel isolation groove, a semiconductor material formed by a single deposition process can be used to fill the pixel isolation groove, and then, a heat treatment process can be performed to form a doped semiconductor pattern. Therefore, even when the pixel isolation groove has a high aspect ratio, a doped semiconductor pattern can be formed in the pixel isolation groove.

[0171] Therefore, the complexity and cost in the process of manufacturing an image sensor can be reduced, the dark current characteristics of the image sensor can be improved, and the resistance of the semiconductor pattern can be reduced.

[0172] Although exemplary embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art should understand that changes in form and detail can be made thereto without departing from the spirit and scope of the appended claims.

Brief Description of the Drawings

[0011] FIG. 1 is a block diagram showing an image sensor according to an embodiment of the concept of the present invention. FIGS. 2A and 2B are circuit diagrams showing a unit pixel of an image sensor according to an embodiment of the concept of the present invention. FIG. 3 is a plan view showing an image sensor according to an embodiment of the concept of the present invention. FIG. 4 is a cross-sectional view taken along line I-I' shown in FIG. 3 to show an image sensor according to an embodiment of the concept of the present invention. FIGS. 5A and 5B are enlarged cross-sectional views showing part "P1" shown in FIG. 4. FIG. 6A is a graph showing a doping distribution curve in a region taken along line A-A' shown in FIG. 5A. FIG. 6B is a graph showing a doping distribution curve in a semiconductor pattern of an image sensor according to an embodiment of the concept of the present invention. FIGS. 7, 8, and 9 are cross-sectional views, each of which is taken along line I-I' shown in FIG. 3 to show an image sensor according to an embodiment of the concept of the present invention. FIG. 10 is a flowchart showing a method of forming a pixel isolation structure of an image sensor according to an embodiment of the concept of the present invention. FIGS. 11 to 21 are cross-sectional views taken along line I-I' shown in FIG. 3 to show a method of manufacturing an image sensor according to an embodiment of the concept of the present invention. FIG. 22 is a schematic plan view of an image sensor including a semiconductor device according to an embodiment of the concept of the present invention. FIGS. 23 and 24 are cross-sectional views, each of which is taken along line II-II' shown in FIG. 22 to show an image sensor according to an embodiment of the concept of the present invention.

Claims

1. A method for manufacturing an image sensor, comprising: A semiconductor substrate of the first conductivity type is formed; Pixel isolation trenches defining pixel regions are formed in the semiconductor substrate; A padding insulating layer is formed in the pixel isolation trench; The pad insulating layer is doped with a dopant of the first conductivity type; after doping with the dopant, a semiconductor layer is formed on the pad insulating layer to fill the pixel isolation trench; and a heat treatment process is performed on the semiconductor substrate to diffuse the dopant of the first conductivity type in the pad insulating layer to the semiconductor layer, wherein after the heat treatment process, the semiconductor layer and the pad insulating layer are doped with the same dopant.

2. The method as described in request item 1, wherein, After the heat treatment process, the concentration of the dopant in the pad insulating layer is higher than the concentration of the dopant in the semiconductor layer.

3. The method of claim 1 further comprises etching the semiconductor layer prior to the heat treatment process such that the top surface of the semiconductor layer is at a level lower than the top surface of the semiconductor substrate.

4. The method of claim 1, wherein doping the dopant includes performing a plasma doping process, a wireline ion implantation process, or a vapor phase doping process.

5. The method as described in request item 1, wherein, After the heat treatment process, the concentration of the dopant of the first conductivity type in the semiconductor layer is about 8 to 9 times that of the dopant of the first conductivity type in the semiconductor substrate.

6. The method of claim 1, wherein the pixel isolation trench has an aspect ratio of about 10:1 to 15:

1.

7. The method of claim 1, wherein the semiconductor layer is composed of a single polycrystalline silicon layer.

8. A method for manufacturing an image sensor, comprising: A semiconductor substrate of a first conductivity type is prepared, the semiconductor substrate having a first surface and a second surface opposite to the first surface; A device isolation layer is formed near the first surface of the semiconductor substrate; a pixel isolation structure is formed to pass through the device isolation layer and the semiconductor substrate and define a plurality of pixel regions; photoelectric conversion regions of a second conductivity type are formed in the semiconductor substrate and in the pixel regions respectively; and in each of the pixel regions, a pixel gate electrode and a transfer gate electrode are formed on the first surface of the semiconductor substrate, wherein forming the pixel isolation structure includes: patterning the device isolation layer and the semiconductor substrate to form a pixel isolation trench; depositing a pad insulating layer on the surface of the pixel isolation trench; doping the pad insulating layer with a dopant of the first conductivity type; and after forming the pad insulating layer doped with the dopant, forming an undoped polysilicon layer to fill the pixel isolation trench. The polysilicon layer is etched to form a polysilicon pattern having a top surface located at a level lower than the first surface of the semiconductor substrate; and a heat treatment process is performed on the semiconductor substrate to diffuse the dopant of the first conductivity type in the pad insulating layer into the polysilicon pattern, wherein after the heat treatment process, the polysilicon pattern is doped with the same dopant as the pad insulating layer.

9. The method of claim 8, wherein after the heat treatment process, the concentration of the dopant in the pad insulating layer is higher than the concentration of the dopant in the polycrystalline silicon pattern.

10. The method of claim 8, wherein after the heat treatment process, the concentration of the dopant of the first conductivity type in the polycrystalline silicon pattern is about 8 to 9 times the concentration of the dopant of the first conductivity type in the semiconductor substrate.

11. The method of claim 8, wherein forming the pixel isolation structure further comprises forming a gap-filling insulating pattern on the polysilicon pattern after the heat treatment process, and the top surface of the gap-filling insulating pattern is coplanar with the top surface of the device isolation layer.

12. The method of claim 8 further comprises forming a planarization insulating layer on the second surface of the semiconductor substrate, wherein the planarization insulating layer is in contact with the bottom surface of the pad insulating layer and the bottom surface of the polysilicon pattern.

13. The method as described in claim 12, further comprising: A color filter is formed on the planarized insulating layer to correspond to the pixel area; And forming microlenses on the color filter.

14. The method of claim 8 further includes forming a back-side contact plug coupled to a portion of the polysilicon pattern.

15. The method of claim 8, wherein the pixel isolation trench includes a plurality of first regions and a plurality of second regions, the plurality of first regions extending in a first direction, the plurality of second regions extending in a second direction intersecting the first direction and intersecting the first regions, and the polycrystalline silicon pattern extending continuously in the first direction and the second direction.

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