Feedback control systems for impedance matching

Abstract

This paper describes a system, method, and medium for a feedback control system used for impedance matching. A computer program product for impedance matching and power distribution networks is disclosed. This computer program product may include a plurality of computer-executable instructions that obtain a plurality of current values ​​of a plurality of variable reactances associated with a processing station in a processing room at the present time, wherein the plurality of variable reactances are associated with a first feedback control system for impedance matching of the processing room, wherein frequency modulation is performed on an RF generator in the processing room associated with a second feedback control system for impedance matching of the processing room. The plurality of computer-executable instructions may, at least in part, determine, based on an error associated with the second feedback control system, the plurality of updated values ​​of the plurality of variable reactances for the processing station to be used in conjunction with the first feedback control system.

Description

Impedance matching feedback control system This invention relates to a feedback control system for impedance matching. Semiconductor manufacturing can utilize plasma systems. Plasma can be generated using a radio frequency (RF) generator that supplies RF signals to the processing chamber. Because the load impedance can vary at different times, the amount of reflected power may also vary. Furthermore, in cases where multiple processing stations are associated with a processing chamber, the amount of power delivered to each station may vary. However, it can be difficult to design a feedback control system that performs impedance matching with the goal of minimizing reflected power and / or controlling the power balance of the RF power delivered to each station. The background information provided herein is intended to provide a general overview of the invention. References to the inventor's work in this background section, and descriptions that are not considered prior art at the time of application, are not intended to represent, expressly or implicitly, any prior art as opposed to the present invention by the inventor. The article discloses the system, method, and medium for impedance matching in feedback control systems. According to some embodiments, a computer program product for impedance matching and power distribution networks may include a non-transient computer-readable medium on which a plurality of computer-executable instructions are provided. The plurality of computer-executable instructions may obtain a plurality of current values ​​of a plurality of variable reactances associated with a processing station in a processing room at the present time, wherein the plurality of variable reactances are associated with a first feedback control system for impedance matching of the processing room, wherein frequency modulation is performed on an RF generator in the processing room associated with a second feedback control system for impedance matching of the processing room. The plurality of computer-executable instructions may determine, at least in part, based on an error associated with the second feedback control system, a plurality of updated values ​​of the plurality of variable reactances for the processing station to be used in conjunction with the first feedback control system. In some instances, the error associated with the second feedback control system comprises a difference between a measured frequency at the processing station and a target frequency associated with the processing chamber. In some instances, the frequency at the processing station is determined using one or more sensing circuits. In some instances, the updated values ​​of the complex variable reactances can be used to modify the complex positions of one or more variable reactance elements associated with the processing chamber to minimize reflected power associated with the processing station. In some instances, the one or more variable reactance elements include at least one of the following: a series capacitor or a parallel capacitor. In some instances, modifying the complex positions of the one or more variable reactance elements associated with the first feedback control system causes the second feedback control system to drive the frequency toward the target frequency. In some instances, the target frequency corresponds to a frequency specified for a step in a formulation performed at the present time. In some instances, the complex computer-executable instructions further utilize a calibration table and, at least in part, the updated values ​​of the complex variable reactance to determine the complex position of one or more variable reactance elements. In some instances, the complex variable reactance includes a series reactance associated with the processing station of the processing chamber. In some instances, the complex variable reactance includes a parallel reactance associated with the processing chamber. In some instances, the complex variable reactance includes a variable series reactance, wherein an updated series reactance is determined based on a correction to a target series reactance, wherein the correction includes the error associated with the second feedback control system. In some instances, the complex variable reactance includes a variable shunt reactance, wherein an updated shunt reactance is determined at least in part based on the error associated with the second feedback control system without needing to determine a target shunt reactance. In some instances, the first feedback control system uses the multiple updated values ​​of the complex variable reactance to respond to compliance with one or more criteria. In some instances, the one or more criteria include: a reflected power associated with the processing room exceeding a reflected power threshold; a power balance ratio associated with multiple processing stations in the processing room exceeding a power balance threshold; and an error associated with the second feedback control system exceeding an error threshold. In some instances, the multiple updated values ​​of the complex variable reactance are modified before use to respond to a determination that a difference between the current value and the updated value of the complex variable reactance falls within a jitter threshold. In some instances, the updated value of the complex variable reactance is determined for the processing station based at least in part on the error associated with the second feedback control system in response to the following determination: a mode has been activated in one of the formulations used at the present time, which is related to controlling the first feedback control system based on the error associated with the second feedback control system. The following terms are used in this specification: The terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially manufactured integrated circuit" are used interchangeably. Those skilled in the art will understand that "partially manufactured integrated circuit" can refer to a semiconductor wafer at any stage of the many stages in which integrated circuits are manufactured on a semiconductor wafer. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, 300 mm, or 450 mm. Besides semiconductor wafers, other workpieces that may benefit from embodiments of the invention include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices, or components such as backplanes for pixelated display devices, flat panel displays, micromechanical devices, etc. Workpieces can have various shapes, sizes, and materials. The term "semiconductor device manufacturing operation" as used herein refers to operations performed during the manufacture of semiconductor devices. Generally, the entire manufacturing process comprises multiple semiconductor device manufacturing operations, each performed within its own semiconductor manufacturing equipment, such as plasma reactors, electroplating tanks, chemical mechanical planarization equipment, wet etching equipment, etc. Types of semiconductor device manufacturing operations include subtractive processes such as etching and planarization, and additive processes such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etching, substrate etching includes the etching of mask layers, and more generally, the etching of any material layers previously deposited and / or otherwise disposed on the substrate surface. Such etching processes can etch film stacks within the substrate. "Manufacturing equipment" refers to equipment in which manufacturing processes take place. Manufacturing equipment typically has a processing chamber in which the workpiece is located during processing. Generally, when manufacturing equipment is used, it performs one or more semiconductor device manufacturing operations. Examples of manufacturing equipment for semiconductor device manufacturing include deposition reactors such as electroplating tanks, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, as well as subtractive processing reactors such as dry etching reactors (e.g., chemical and / or physical etching reactors), wet etching reactors, and ashing equipment. Impedance matching feedback control system Plasma-based reactors can be used for plasma-based semiconductor operations (such as plasma deposition and / or plasma etching). Such reactors or processing chambers can have multiple (e.g., two, four, eight, sixteen, etc.) processing stations. An RF generator can provide RF signals to the processing stations (multiple processing stations) within the processing chamber, where the RF signals are used to generate plasma within the processing stations for plasma-based operations. In the case of a processing chamber using multiple processing stations, a power splitter can be used to provide power to the multiple processing stations. Matching networks can be used, for example, for impedance matching, taking into account load impedance. Such matching networks (e.g., for impedance matching) can transmit maximum power from the RF generator to each processing station by eliminating reflected power. In some cases, the matching network may use a first feedback control system that modulates one or more variable reactance elements for impedance matching. These variable reactance elements may include variable capacitors, variable inductors, etc. In some cases, the position of the variable reactance elements can be adjusted to achieve a target or desired reactance value, calculated to eliminate reflected power. The system may additionally use a second feedback control system that performs frequency modulation on the RF generator in the processing room for impedance matching. Because impedance matching (i.e., minimizing or eliminating reflected power) requires manipulating two independent dimensions (i.e., the real and imaginary parts of the impedance), adjusting the frequency alone may modulate one dimension to the desired value, but may not modulate both independent dimensions to the desired value. Therefore, frequency modulation may reduce reflected power but may not eliminate it. Since adjusting variable reactance elements (e.g., by stepper motors) may take milliseconds or tens of milliseconds, the first feedback control system may be relatively slow. In contrast, frequency modulation can be much faster than modulation of a variable reactance element, for example, in the order of microseconds or tens of microseconds. In other words, a first feedback control system that modulates a variable reactance element can eliminate reflected power relatively slowly, while a second feedback control system using frequency modulation can only provide a reduction in reflected power, but several orders of magnitude faster than the first feedback control system. The techniques described herein are for coordinating a first feedback control system and a second feedback control system, wherein the first feedback control system uses modulation of a variable reactance element and the second feedback control system performs frequency modulation on an RF generator. In particular, the new or updated value of the reactance element in the first feedback control system can be determined based on the error of the second feedback control system. In some embodiments, the error may be the difference between the frequency measured at each processing station in the processing chamber (or the average of various measured frequencies at that processing station) and the target frequency. By coordinating the first and second feedback control systems, the advantages of each feedback control system can be combined, thereby eliminating reflected power more quickly. The techniques described herein are particularly advantageous at formulation step changes, where the RF signal characteristics are stepped (e.g., with one or more discontinuous parameters). Furthermore, during the steady-state portion of the formulation steps, the techniques described herein can drive the frequency at each processing station toward the target frequency specified in the formulation steps. Figure 1A shows a substrate processing apparatus for depositing thin films on a semiconductor substrate using any number of processes. The apparatus 100 of Figure 1A uses a single processing station 102 within a processing chamber, which has a single substrate support 108 (such as a platform) within its internal volume, which can be maintained under vacuum by a vacuum pump 108. A gas delivery system 101 and a spray head 106 are also fluidly coupled to the processing chamber to, for example, deliver thin film precursors, carrier gases, and / or cleaning and / or processing gases, second reactants, etc. Figure 1A also shows apparatus for generating plasma within the processing chamber. The apparatus schematically shown in Figure 1A is suitable for plasma-enhanced CVD, in particular. For simplicity, processing equipment 100 is shown as a separate processing station (102) within a processing room, which is used to maintain a low-pressure environment. However, it will be understood that multiple processing stations can be included in a shared processing environment, such as a common reaction chamber as described herein. For example, Figure 1C shows an embodiment of a multi-station processing equipment, which will be discussed in more detail later. Furthermore, it will be understood that in some embodiments, one or more hardware parameters of processing equipment 100, including those discussed herein, can be programmed by one or more system controllers. The processing station 102 in the processing chamber is in fluid communication with the gas delivery system 101, which is used to deliver the processed gas to the dispersion spray head 106. The gas delivery system 101 includes a mixing container 104 for mixing and / or adjusting the processed gas to be delivered to the spray head 106. One or more mixing container inlet valves 120 can control the introduction of the processed gas into the mixing container 104. Certain reactants may be stored in a liquid state before evaporation and subsequent delivery to processing station 102 in the processing chamber. The embodiment of Figure 1A includes an evaporation point 103 for evaporating the liquid reactants to be supplied to mixing vessel 104. In some embodiments, evaporation point 103 may be a heated liquid injection module. In some other embodiments, evaporation point 103 may include a heated evaporator. In still other embodiments, evaporation point 103 may be omitted from the processing station. In some embodiments, a flow controller (LFC) upstream of evaporation point 103 may be provided to control the mass flow rate of the evaporated liquid delivered to processing station 102. Spray head 106 disperses process gases and / or reactants (such as thin film precursors) toward substrate 112 at the processing station. The process gases and / or reactant streams may be controlled by one or more valves (such as valves 120, 120A, 105) upstream of the spray head. In the embodiment shown in FIG. 1A, substrate 112 is located below spray head 106 and is shown seated on pedestal 108. Spray head 106 may have any suitable shape and may include any suitable number and configuration of interfaces to disperse process gases to substrate 112. In some embodiments involving two or more stations, gas delivery system 101 includes valves or other flow control structures upstream of the spray head that can independently control the process gases and / or reactant streams delivered to each station, allowing gas to flow to one station but not to another. Furthermore, the gas delivery system 101 can be used to independently control the processing gas and / or reactants delivered to each station in the multi-station equipment, so that the composition of the gas delivered to different stations is different, for example, the partial pressure of one of the gas components varies between different stations at the same time. Volume 107 is located below spray head 106. In some embodiments, stage 108 may be raised or lowered to expose substrate 112 to volume 107 and / or to change the size of volume 107. Optionally, stage 108 may be lowered and / or raised during partial deposition processing to modulate processing pressure, reactant concentration, etc., within volume 107. In Figure 1A, the spray head 106 and the base 108 are electrically coupled to an RF power supply 114 and a matching network 116 that supply power to the plasma generator. In some embodiments, the plasma energy can be controlled by controlling one or more of the following: processing station pressure, gas concentration, RF power supply, etc. (e.g., by a system controller with appropriate machine-readable instructions and / or control logic). For example, the RF power supply 114 and the matching network 116 can be operated at any suitable power to generate a plasma with the desired composition of free radical species. Similarly, the RF power supply 114 can provide RF power with any suitable frequency or frequency group and power. In some embodiments, plasma ignition and sustaining conditions are controlled by appropriate hardware and / or appropriate machine-readable instructions in a system controller, which provides control instructions via a sequence of input / output control (IOC) instructions. In one example, instructions for setting plasma conditions for ignition or sustaining the plasma are provided in the form of a plasma activation formulation of a processing formulation. In some cases, processing formulations may be configured sequentially, so that some of the instructions for the processing are executed concurrently with the processing. In some embodiments, instructions for setting one or more plasma parameters may be included in a formulation preceding a plasma processing. For example, a first formulation may include instructions for setting the flow rate of an inert gas (such as helium) and / or reactant gas, instructions for setting the plasma generator to a power setpoint, and time delay instructions for the first formulation. A subsequent second formulation may include instructions for enabling the plasma generator and time delay instructions for the second formulation. A third formulation may include instructions for disabling the plasma generator and time delay instructions for the third formulation. It should be understood that, within the scope of this invention, these formulations may be further divided and / or repeated in any suitable manner. In some deposition processes, plasma firing lasts for several seconds or longer. In some embodiments described herein, much shorter plasma firings can be applied during a processing cycle. Such plasma firing durations can be in the range of less than about 50 milliseconds, and in certain instances, about 25 milliseconds. For simplicity, the processing equipment 100 is shown in FIG1A as a stand-alone station (102) for maintaining a low-pressure environment in the processing room. However, it should be understood that, as shown in FIG1B, a multi-station processing equipment environment may include multiple processing stations, and FIG1B shows a schematic diagram of one embodiment of a multi-station processing equipment. Processing apparatus 130 utilizes integrated circuit fabrication chamber 132, which includes a plurality of fabrication processing stations, each of which can be used to perform processing operations on a substrate supported on a pedestal 108 as shown in FIG. 1A at a specific processing station. In the embodiment of FIG. 1B, integrated circuit fabrication chamber 132 is shown as having four processing stations 133, 134, 135, and 136. Depending on the embodiment and desired levels of parallel wafer processing, size / space constraints, cost constraints, etc., other similar multi-station processing apparatuses may have more or fewer processing stations. FIG. 1B also shows a substrate handling robot 138, which can operate under the control of system controller 140 to move substrates from a wafer cassette (not shown in FIG. 1B) from the loading interface into integrated circuit fabrication chamber 132 and then to one of processing stations 133, 134, 135, and 136. Figure 1B also shows an embodiment of a system controller 140 for controlling the processing conditions and hardware states of the processing device 130. The system controller 140 may include one or more memory devices, one or more mass storage devices, and one or more processors. The one or more processors may include a central processing unit, analog and / or digital input / output connections, a stepper motor controller board, etc. In some embodiments, the system controller 140 controls all activities of the processing device 130. The system controller 140 may execute system control software stored in the mass storage devices and loaded into the memory devices on its hardware processor. The software executed by the processor of the system controller 140 may include instructions for controlling: timing, gas mixtures, pressure of the manufacturing chamber and / or station, temperature of the manufacturing chamber and / or station, wafer temperature, substrate stage, chuck and / or base position, number of cycles performed on one or more substrates, and other parameters of the specific program executed by the processing device 130. These programmed processes can include various types of processes, including, but not limited to: processes related to determining the accumulation on the surface inside the chamber, processes related to depositing thin films on the substrate involving multiple cycles, and processes related to cleaning the chamber. The system control software executed by one or more processors of the system controller 140 can be configured in any suitable manner. For example, subroutines or control objects for various processing device elements can be written to control the operation of the processing device elements used to perform various device processes. In some embodiments, the software executed by the processor of system controller 140 may include input / output (IOC) sequence instructions for controlling the various parameters described above. For example, each deposition stage and deposition cycle of the substrate may include one or more instructions executed by system controller 140. Instructions for setting the processing conditions of the ALD / CFD deposition process may be included in the corresponding ALD / CFD deposition formulation stage. In some embodiments, formulation stages may be configured sequentially so that all instructions of a processing stage are executed simultaneously with that processing stage. In some embodiments, other computer software and / or programs stored on a mass storage device of the system controller 140 and / or accessible in the memory of the system controller 140 may be used. Examples of programs or program segments for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs. The substrate positioning program may include program code for certain processing device elements used to load the substrate onto the stage 108 (FIG. 1A) and control the distance between the substrate and other components of the processing device 130. The substrate positioning program may include instructions for properly moving the substrate into and out of the reaction chamber as necessary for depositing a thin film onto the substrate and cleaning the chamber. The process gas control program may include code for controlling the gas composition and flow rate, and code for controlling the gas flowing into one or more processing stations before deposition to stabilize the pressure in the processing stations. In some embodiments, the process gas control program includes instructions for introducing gas during thin film formation on a substrate in the reaction chamber. This may include introducing gas in different numbers of cycles for one or more substrates within a batch. The pressure control program may include code for controlling the pressure in the processing station by adjusting, for example, a throttle valve in the processing station's exhaust system, the gas flowing into the processing station, etc. The pressure control program may include instructions for maintaining the same pressure during different numbers of deposition cycles on one or more substrates during batch processing. The heater control program may include code for controlling the current flowing to the heating unit 110 used to heat the substrate. Alternatively, the heater control program may control the delivery of heat transfer gas (such as helium) to the substrate. In some embodiments, there is a user interface associated with the system controller 140. The user interface may include a display screen, a graphical software display of the device and / or processing conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc. In some embodiments, the parameters adjusted by the system controller 140 may be related to processing conditions. Non-limiting examples include processing gas composition and flow rate, temperature, pressure, plasma conditions, etc. These parameters may be provided to the user in the form of a formulation, accessible through a user interface. A formulation for a batch of substrates may include the number of compensation cycles for one or more substrates within the batch to account for thickness trends during the processing batch. Signals from various processing device sensors for monitoring processing can be provided via analog and / or digital input connections of system controller 140. Signals for controlling processing are output via analog and digital output connections of processing device 130. Non-limiting examples of processing device sensors that can be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Sensors may also be included and used to monitor and determine accumulations on one or more surfaces inside the chamber and / or the thickness of material layers on the substrate within the chamber. Processing conditions can be maintained using appropriately programmed feedback and control algorithms and data from these sensors. The system controller 140 can provide program instructions for performing the deposition process described above. The program instructions can control various processing parameters such as DC power level, pressure, temperature, number of substrate cycles, and amount of material accumulated on at least one surface inside the chamber. The instructions can control parameters to operate the in-situ thin film stacking deposition according to the various embodiments described herein. For example, the system controller may include logic control to perform the techniques described herein, such as determining the current amount of accumulated deposited material on at least one internal region inside the deposition chamber, applying the determined amount of accumulated deposited material or a parameter derived therefrom to the relationship between (i) and (ii), to obtain the number of ALD cycles required to achieve the target deposition thickness at the current amount of accumulated deposited material on the internal region inside the deposition chamber, and performing the number of ALD cycles required to achieve the target deposition thickness on one or more substrates in a batch of substrates, where (i) is the number of ALD cycles required to achieve the target deposition thickness, and (ii) is a variable representing the amount of accumulated deposited material. The system may also include control logic to determine that the accumulation in the chamber has reached the accumulation limit and to stop the processing of the batch of substrates in response to the determination and to clean the interior of the chamber. In addition to the functions and / or operations performed by the system controller 140 of Figure 1B, the controller may additionally control and / or manage the operation of the RF subsystem, which generates RF power and delivers it to the integrated circuit fabrication chamber 132 via the RF input interface 137. As further explained herein, such operations may relate to, for example: determining upper and lower threshold values ​​for the RF power to be delivered to the integrated circuit fabrication chamber 132, determining the actual (e.g., real-time) level of the RF power delivered to the integrated circuit fabrication chamber 132, RF power activation / deactivation time, RF power on / off period, operating frequency, etc. In a particular embodiment, the integrated circuit fabrication chamber 132 may include input interfaces in addition to input interface 137 (the additional input interfaces are not shown in FIG. 1B). Therefore, the integrated circuit fabrication chamber 132 may use eight RF input interfaces. In a particular embodiment, each of the processing stations 133-136 of the integrated circuit fabrication chamber 132 may use a first and a second input interface, wherein the first input interface may transmit a signal having a first frequency and the second input interface may transmit a signal having a second frequency. Using dual frequencies can result in enhanced plasma characteristics, which can achieve deposition rates within specific limits and / or more easily controlled deposition rates. Dual frequencies can achieve other desired results not described herein. In some embodiments, frequencies between about 300 kHz and about 300 MHz may be used. In Figure 1B, the RF power from RF signal source 142 can be divided among four output channels, which can be coupled to corresponding input interfaces 137 of integrated circuit fabrication chamber 132. In at least certain embodiments, it is useful to divide the RF power from signal source 142 into relatively equal portions (with a difference of approximately +1%). Thus, in one example, if RF signal source 142 provides 1000 W of output power, approximately 250 W (+1%) is delivered to each input interface 137 of fabrication chamber 132. Figure 1C block diagram shows various components of a system for performing semiconductor manufacturing processes according to Embodiment 151. In Figure 1C, an excitation signal is generated using an RF signal generator 160, which can generally form plasma within processing stations 102A, 102B, 102C, and 102D of the processing chamber. Processing stations 102A, 102B, 102C, and 102D correspond to processing stations in the semiconductor processing chamber as described above with reference to Figure 1A. Note that in some embodiments, multiple RF signal generators may be used, such as a first RF generator for generating a relatively low-frequency signal, such as about 400 kHz, and a second RF generator for generating a relatively high-frequency signal, such as about 27.12 MHz. However, it should be understood that these are merely illustrative frequencies. In other embodiments, different radio frequencies may be generated, and the embodiments are not limited to signals of 400 kHz and 27.12 MHz. For example, in certain cases, relatively low frequencies may correspond to frequencies between 360 kHz and 440 kHz. In another case, relatively high frequencies may correspond to frequencies between 26.5 MHz and 27.5 MHz. In Figure 1C, an RF transmission line couples RF signal generator 160 to matching network 163. The RF transmission line may involve a characteristic impedance of approximately 50 ohms. However, other embodiments may use transmission lines with different characteristic impedances, such as 70 ohms, 300 ohms, etc. In the embodiment of Figure 1C, matching network 163 operates to match the load represented by power splitter 170 with the output impedance of RF signal generator 160. This type of matching generally couples the maximum power transfer from RF signal generator 160 to power splitter 170. Therefore, even when power splitter 170 represents a highly reactive load (e.g., a complex impedance with a relatively small real part and a large reactive part), the maximum power transfer from RF signal generator 160 to power splitter 170 is still possible. Matching network 163 may use various reactive elements such as inductors and / or capacitors, which operate to compensate for the highly reactive load represented by power splitter 170. It should be understood that, in some embodiments, the matching network 163 and the power splitter 170 may be combined in the integrated system. In certain embodiments, the elements of matching network 163 can be configured to match the specific impedances represented by the low-frequency and high-frequency input interfaces of power splitter 170, which is operable to provide power for plasma generation via interfaces 171, 172, 173, and 174. However, during etching operations of a plasma system, or during other plasma system processes (e.g.), a reactive load represented by plasma formed in processing stations 102A, 102B, 102C, and 102D of the processing chamber may begin to change or drift. Therefore, for example, during the initial period of plasma generation (e.g., the initial 30-60 seconds), the amplitudes of the output signals from interfaces 171-174 may correspond to substantially equal amounts. However, as plasma generation continues, the amplitudes of the output signals from interfaces 171-174 may begin to differ. Variations in the reactive load represented by processing stations 102A-102D of the processing chamber may cause such differences. Therefore, in some cases, the actual power coupled from the power splitter interfaces 171-174 may vary from 0.0% to 100.0% in response to changes in the reactive load represented by the processing stations 102A-102D in the processing room. These variations are limited by the sum of the power transmitted to each processing station being 100%. Furthermore, the RF power flowing to a processing station can be set to 0.0 or other negligible amounts by using an input of 0.0 watts as a setpoint. Alternatively, the capacitance of the variable capacitor can be adjusted to a value that brings the current close to or near 0.0 amperes. It may be difficult to ensure that the power transmitted from the power splitter 170 to the processing stations 102A-102D is constant and uniform. In some embodiments (e.g., instances where the matching network and power splitter are integrated), the first feedback control system is operable to provide real-time closed-loop modulation of the reactive elements within the matching network 163 in response to changes in the reactive load represented by the processing stations 102A-102D. In some embodiments, the first feedback control system can modulate one or more reactive components or elements within the matching network 163 by adjusting the position of one or more reactive elements (such as variable capacitors). Such position adjustments can be performed by one or more stepper motors. The first feedback control system can provide substantial or complete control to minimize reflected power and / or balance the power delivered to each station. In some embodiments, the second feedback control system is operable to provide frequency modulation on the RF signal generator 160, which is part of a second impedance matching control system. Because the second feedback control system adjusts the frequency, it is possible to optimize only a single dimension of the impedance toward a desired or target value. The second feedback control system can reduce reflected power without eliminating reflected power. Because the first feedback control system utilizes the modulation of reactive components, its operation is slower in time compared to the second feedback control system. For example, the first feedback control system can adjust in the tens or hundreds of milliseconds, while the second feedback control system operates in the microseconds. In other words, the first feedback control system can perform impedance matching, minimization of reflected power, and power balancing more accurately and completely than the second feedback control system, but it is slower in time. The longer time required by the first feedback control system is particularly problematic during the step-by-step changes in the RF signal condition settings. The technique described herein, implemented in the first feedback control system (modulating the reactive element), enables the operation of the first feedback control system to be coordinated with the second feedback control system (performing frequency modulation). In particular, using the technique described herein, the first feedback control system can modulate the reactive element by taking into account the error of the second feedback control system. This error can be the difference between the measured frequency and the target frequency specified in the implemented formula, wherein the measured frequency corresponds to the resulting frequency of frequency modulation performed by the second feedback control system. Referring back to Figure 1C, in some embodiments, the reactance determination engine 180 may provide input to the matching network 163, indicating the reactance value to be used by the matching network 163 for impedance matching using the first feedback control system. In some embodiments, the reactance determination engine 180 may receive phase, voltage, current, and / or frequency information from a phase / voltage / current / frequency sensing circuit 182. For example, the phase / voltage / current / frequency sensing circuit 182 may measure voltage and / or current at one or more processing stations in the processing room. Continuing this example, the reactance determination engine 180 may determine the reactance value based on voltage and / or current, phase, and / or frequency information associated with the RF signal provided to the processing station. It should be noted that the phase / voltage / current / frequency sensing circuit is sometimes referred to herein as a "VI probe". More detailed techniques that the reactance determination engine 180 may perform are shown and illustrated in Figures 3, 4, and 5 and their associated descriptions. Figure 2 shows the various circuit elements used in the impedance matching process during plasma enhancement according to Embodiment 200. It should be understood that, for example, any number of RF power control circuits (such as 225A, 225B), phase / voltage / current sensing circuits (such as 215, 235A, 235B), and processing stations (such as 102A, 102B) can be used. In Figure 2, the matching reflection optimization device 220 includes a variable capacitor C220. Although not shown in Figure 2, the matching reflection optimization device 220 may include an inductor with a value selected to provide the admittance range represented by the combination of C220 and the inductor in series. In a particular embodiment, C220 represents a variable capacitor with a value that can be controlled by a remote signal, such as a signal from a reactance determination engine (as shown and described with reference to Figure 1C) or other controller. Thus, the capacitance value represented by C220 can be adjusted to present sufficient admittance so that the measured VSWR returns to a value below a predetermined threshold (e.g., 1.15:1, 1.10:1, etc.) in response to an increase in conductance represented by the combination of the phase / voltage / circuit sensing circuitry 225A-225N (e.g., by measuring the voltage standing wave ratio (VSWR)). Such adjustments to capacitor C220, and any necessary adjustments to other reactive components (such as 225A), can substantially increase the power transfer from signal generator 205 to processing stations 102A and 102B. RF power control circuit 225A may include a series impedance represented by C225A. RF power control circuit 225A may also include an inductor, which may be a static element with a value selected to provide a range of impedances represented by the combination of C225A and the inductor. In a particular embodiment, C225A represents a variable capacitor with a value that can be controlled by a remote signal, such as from a signal reactance determination engine (as illustrated and shown with reference to Figure 1C). Thus, capacitor C225A can be adjusted to substantially achieve maximum power transfer between the RF generator and processing stations 102A and 102B in response to changes in impedance of processing station 102A measured by phase / voltage / current sensing circuit 235A. A similar adjustment can be made to variable capacitor C225B based on a signal from phase / voltage / current sensing circuit 235B. In some embodiments, the first feedback control system can be adjusted by adjusting a variable reactance element associated with the first feedback control system. Using the techniques described herein, an updated value associated with the variable reactance element can be determined based on the current value of the variable reactance element, the error associated with the second feedback control system, and / or measurements from VI probes (which may include voltage, current, frequency, and / or phase measurements or judgments). The error associated with the second feedback control system is used for frequency modulation to provide impedance matching to the system. In some embodiments, the error associated with the second feedback control system may be the difference between a measured frequency and a target frequency. In some embodiments, the variable reactance element may comprise one or more series reactances, each associated with a specific processing station in the processing chamber (as shown and described with reference to Figure 2). In some embodiments, the updated series reactance value may be determined based on the current series reactance value and the modified target series reactance value. In some embodiments, the modified target series reactance value may be determined by first determining the target series reactance (generally referred to herein as Xd) as the target series reactance that minimizes reflected power for the specific processing station associated with the series reactance element. The target series reactance may be determined using a circuit model, VI probe measurements from one or more VI probes associated with the processing station (which may include magnitude and / or phase information), and the desired power ratio for each processing station (which may be determined based on the recipe set point). The target series reactance value may then be modified to compensate for uncertainties in the circuit model by using the estimated value of the current series reactance (generally referred to herein as Xn). The estimated value of the current series reactance can be determined based on the circuit model, information on magnitude and / or phase obtained from one or more VI probes associated with each station, and VI probe measurements (which may include magnitude and / or phase) from upstream VI probes in the network. The obtained value can then be further modified based on errors associated with the second feedback control system. In particular, the obtained value can be modified based on the error between the frequency measured at the processing station associated with the series reactance element and the target frequency. The target frequency can be the frequency specified in the recipe, such as the target frequency specified in a specific step of the recipe that is being performed or will be performed. In some embodiments, the variable reactance element may comprise one or more parallel reactances. For example, as shown and described with reference to FIG2, one or more parallel reactances may be associated with a matched reflection optimization device. In some embodiments, the updated parallel reactance value may be determined based on the current parallel reactance value and the error associated with the second feedback control system. For example, the error associated with the second feedback control system may be the difference between a measured frequency (such as the average of frequencies measured at each station) and a target frequency. The target frequency may be the frequency specified in the recipe, such as the target frequency specified in a recipe-specific step that is being performed or will be performed. It should be understood that in some embodiments, when the processing chamber is operating in a static mode (e.g., not at a step transition of a recipe being performed in the processing chamber), modulating the parallel reactance to the updated parallel reactance value may cause the frequency to drive toward the target frequency because the frequency error when setting the updated parallel reactance value is taken into account. Furthermore, as will be explained in more detail below with reference to Figure 3, the updated parallel reactance value can be determined based on the frequency error without determining the target parallel reactance value, which can drive the frequency toward the target frequency. It should be understood that while the techniques and systems described herein generally refer to adjusting the parallel reactance based on the frequency error to drive the frequency toward the target frequency and adjusting the series reactance based on the calculated target reactance, in some embodiments, the reverse may be true. In other words, in some embodiments, the series reactance can be used to drive the frequency toward the target frequency, and the parallel reactance can be adjusted based on the calculated target reactance. Figure 3 illustrates a flowchart of an exemplary process 300 of a two-feedback control system for coordinating impedance matching processing according to certain embodiments. It should be understood that one or more processors and / or one or more controllers associated with the processing chamber, as shown and described in Figure 1A, can execute blocks of process 300. In some embodiments, the blocks of process 300 may be performed in a sequence other than that shown in Figure 3. In some embodiments, two or more blocks of process 300 may be performed substantially in parallel. In some embodiments, one or more blocks of process 300 may be omitted. Process 300 can begin at 302, determining the current series and / or parallel reactance values ​​associated with one or more processing stations in the processing room. As described and illustrated above in the description and illustration related to Figure 2, there are multiple series control reactance elements, each associated with one processing station in the processing room. As described and illustrated above in the description and illustration related to Figure 2, parallel reactance elements can be associated with all processing stations in the processing room. In the case where a series reactance element is associated with a specific processing station j, the current series reactance value associated with processing station j can be X. ser (j) represents. The current shunt reactance value can be X. shuIn some embodiments, a calibration table or lookup table can be used to determine the current series reactance value and / or the current parallel reactance value. For example, in the case where the reactance element (whether related to series or parallel reactance) is a variable capacitor, the current reactance value associated with the current position can be identified by using the current position of the variable capacitor as the key to the calibration table, and the current reactance value (such as the current series reactance value and / or the current parallel reactance value) can be determined. At 304, process 300 can determine frequency information representing the frequency at one or more processing stations in the processing room at the present time. In some embodiments, the frequency information may include the frequency measured at each processing station in the processing room. In some embodiments, the frequency may be measured at a specific processing station using a VI probe associated with that processing station. It should be understood that in some embodiments, the frequency may be measured only for the high-frequency (HF) signal provided to the processing station. At 306, process 300 may obtain a target frequency associated with the RF generator providing the RF signal to one or more processing stations in the processing chamber. In some embodiments, the target frequency may be the frequency specified in a recipe-specific step performed in the processing chamber. It should be understood that in the absence of frequency modulation (e.g., the second feedback control system is disabled), the target frequency can be identified as the frequency output by the RF generator. Using the target frequency output by the RF generator in the absence of frequency modulation can be backward matched to the method of process 300 performed in the absence of frequency modulation and / or when frequency modulation is disabled for a specific recipe or recipe step. At 308, process 300 may determine the updated series and / or parallel reactance value based at least in part on the difference between the current series and / or parallel reactance value and the measured frequency and the target frequency. In some embodiments, for a specific processing station j, can be based on the processing station The current series reactance value X of j ser (j) (as determined at block 302), the modified target series reactance value, and the difference between the average frequency measured across one or more processing stations and the target frequency (as determined at block 306 and generally referred to in this text as Δ). f), determine the updated series reactance value. This can be achieved by determining X. d(j) represents the target or desired series reactance value of the processing station, and the modified target series reactance value is determined accordingly. In some embodiments, the target series reactance value of the processing station can be determined based on the circuit model, VI probe measurements from one or more VI probes associated with the processing station (which may include magnitude and / or phase information), and the desired power ratio of each processing station (which may be determined based on the recipe set point). Then, based on X... n (j) Modify the target series reactance value of the processing station based on the current estimated value of the series reactance of the processing station. The current estimated value of the series reactance of the processing station can be determined based on measurements from VI probes associated with the processing station and / or measurements from VI probes upstream of the network. Magnitude and / or phase information (such as that related to the RF signal supplied to the processing station) can be determined using measurements from VI probes. Modifying the target or desired series reactance value using measurements from VI probes can compensate for uncertainties in the circuit model. For example, in some embodiments, the processing station The updated series reactance value of j X new_ser ( j) This can be determined in the following ways: In the equation above, X ser ( j) represents the processing station j is the current series reactance value (e.g., as determined at block 302). X d ( j) represents the processing station The target or desired series reactance value of j X n ( j) Represents the processing station determined based on the circuit model and / or VI probe information. The estimated current series reactance value of j, and Δ f represents the difference between the average frequency measured at each processing station and the target frequency (such as that obtained at block 306). Furthermore, in the equation above, dampX represents the damping constant. k ser This represents a weighting constant that weighs the importance of the error in the second feedback control system when updating the series reactance value. In some embodiments, the current shunt reactance value (generally referred to herein as...) can be used as a basis. X shuThe updated parallel reactance value (usually referred to in this text as the average frequency measured at each processing station and the target frequency) is determined by comparing the average frequency measured at each processing station with the target frequency. X new_shu For example, in some embodiments, the updated shunt reactance value can be determined in the following manner: In the equation above, Δ f represents the difference between the average frequency measured at each processing station and the target frequency (such as that obtained at block 306). Furthermore, in the equation above, k ser This represents a weighting constant that weighs the importance of the error in the second feedback control system when updating the parallel reactance value. It should be understood that the above equations used to determine the updated series reactance value and the updated shunt reactance value can be interchanged when using a series reactance to drive the frequency toward the target frequency and when using a shunt reactance to drive the reactance toward the target reactance. In some embodiments, updated series reactance values ​​(complex reactance values) and updated parallel reactance values ​​(complex reactance values) can be used to modify the position of the variable reactance element to adjust the current series reactance value (complex value) and / or the current parallel reactance value toward the updated reactance value. For example, the updated reactance value (whether it is an updated series reactance value or an updated parallel reactance value) can be used as a key in a calibration table or lookup table to identify the position of the variable reactance element (such as a variable capacitor) to achieve the updated reactance value. In some embodiments, the variable reactance element can then be actuated, for example, using a stepper motor, to reach the identified position. In some embodiments, as described above, the updated series reactance value and / or the updated parallel reactance value can be determined. In some embodiments, it can be determined whether to use the updated series reactance value and / or the updated parallel reactance value (e.g., by adjusting one or more variable reactance elements associated with the processing chamber to positions corresponding to the updated reactance value). In some embodiments, the updated series reactance value and / or the updated parallel reactance value can be used to respond to the satisfaction of one or more criteria. The one or more criteria may include: the reflected power associated with the processing chamber exceeds a reflected power threshold or falls outside the range of reflected power; the power balance of the power delivered to the two or more processing stations in the processing chamber exceeds a power balance threshold or falls outside the power balance range; and the error associated with the second feedback control system exceeds an error threshold or falls outside the error range. It should be understood that in certain situations, when the reflected power falls within the reflected power range, the power balance falls within the power balance range, and the error associated with the second feedback control system falls within the error range, but there is a difference between the updated reactance value and the current reactance value, the position of the reactance element (such as a capacitor) can be maintained to avoid unnecessary jittering of the reactance element, which can prevent unnecessary wear and tear of the reactance element. Figure 4 shows a flowchart of an exemplary process 400 for determining whether to use an updated series reactance value and / or an updated parallel reactance value, according to certain embodiments. It should be understood that one or more processors and / or one or more controllers associated with the processing chamber, as shown and described in Figure 1A, can execute the blocks of process 400. In some embodiments, the blocks of process 400 may be performed in a sequence other than that shown in Figure 4. In some embodiments, two or more blocks of process 400 may be performed substantially in parallel. In some embodiments, one or more blocks of process 400 may be omitted. It should be understood that in some embodiments, process 400 may be performed after determining the updated series reactance value and / or the updated parallel reactance value (e.g., as described above with block 308 in Figure 3) and before adjusting the series reactance elements and / or the parallel reactance elements to achieve the updated series reactance value and / or the updated parallel reactance value, respectively. Processing 400 can begin with 402, targeting a specific processing station. j obtains the updated series reactance value ( X new_ser ( j) and / or the updated shunt reactance value ( X new_shu For example, the updated series reactance value and / or the updated parallel reactance value can be those determined above at block 308 in Figure 3. At 404, process 400 may determine whether to use the updated series reactance value and / or the updated shunt reactance value. For example, process 400 may decide to use the updated series reactance value and / or the updated shunt reactance value in response to a determination that one or more criteria are met. In some embodiments, one or more criteria may include a measured power ratio of the processing station representing the balance of power delivered to the processing station in the processing chamber exceeding a power balance threshold or falling outside the power balance range. The power balance threshold may be any suitable percentage (e.g., 0.1%, 0.5%, 1%, etc.) deviating from the power balance setpoint. In some embodiments, one or more criteria may include a measure representing the amount of reflected power exceeding a reflected power threshold. For example, in the case where the reflection coefficient is represented by Γ, the measure representing the reflected power may be |Γ|. 2 In other words, the reflection coefficient is a complex number, and the measure of reflected power can be the square of the reflection coefficient. This measure represents the ratio of reflected power to the transmitted feedforward power. Continuing this example, if |Γ| 2 A power value greater than the reflected power threshold (e.g., 0.001, 0.005, 0.01, etc.) can be considered to meet one or more criteria. In some embodiments, one or more criteria may be based on an error associated with the second feedback control system exceeding an error threshold, where the error is the difference between the measured frequency and the target frequency. For example, the criteria may include the average frequency at one or more processing stations in the processing room exceeding a frequency threshold (e.g., deviation from the target frequency greater than 0.1%, deviation from the target frequency greater than 0.5%, deviation from the target frequency greater than 1%, etc.). Conversely, processing 400 may decide not to use the updated series reactance value and / or the updated shunt reactance value in response to the determination that one or more criteria are not met. It should be understood that in some embodiments, the determination of whether to use the updated shunt reactance value may not consider criteria related to the power balance between different processing stations in the processing room (e.g., as shown and described in the example of Figure 2, where shunt reactance is used for all processing stations in the processing room). If at 404, process 400 decides not to use the updated series reactance value and / or the updated parallel reactance value ("No" at 404), then process 400 can proceed to block 406 and maintain the current series reactance value and / or the current parallel reactance value. Conversely, if at 404, process 400 decides to use the updated series reactance value and / or the updated shunt reactance value ("Yes" at 404), then process 400 can proceed to block 408 and can set the new series reactance value to the updated series reactance value for each processing station and / or can set the new shunt reactance value to the updated shunt reactance value. The updated values ​​can be used to adjust the position of variable reactance elements such as variable capacitors. It should be understood that in some embodiments, the updated series reactance value and / or the updated parallel reactance value may be modified or adjusted before use. For example, if the difference between the updated reactance value and the current reactance value (whether it is a series reactance or a parallel reactance) is less than a jitter threshold, the updated reactance value may be modified using the jitter threshold. For example, the updated reactance value may be modified such that the change to the current reactance value is less than the jitter threshold (e.g., half the jitter threshold). It should also be understood that, in some embodiments, the updated series reactance value can be considered separately from the updated shunt reactance value. For example, the updated series reactance value can be modified based on a jitter threshold, but the updated shunt reactance value cannot be modified based on a jitter threshold, and vice versa. It should be understood that the processing described with reference to Figures 3 and 4 generally describes the variable series reactance associated with each processing station in the processing room and the parallel reactance associated with all processing stations in the processing room. Also, the variable reactance element is generally described as a variable capacitor. However, it should be understood that other configurations can be applied to coordinate the first feedback control system and the second feedback control system, the first feedback control system using variable reactance for impedance matching and the second feedback control system performing frequency modulation for impedance matching. Figure 5 illustrates a flowchart of an exemplary processing 500 for coordinating the first feedback control system and the second feedback control system according to some embodiments, the first feedback control system using variable reactance for impedance matching and the second feedback control system performing frequency modulation for impedance matching. It should be understood that one or more processors and / or one or more controllers associated with the processing room, as shown and described in Figure 1A, can execute the blocks of processing 500. In some embodiments, the blocks of processing 500 can be performed in a sequence other than that shown in Figure 5. In some embodiments, two or more blocks of processing 500 can be performed substantially in parallel. Process 500 may begin at 502, obtaining the current value of a variable reactance associated with one of the processing stations in the processing chamber at the present time. This variable reactance is associated with a first feedback control system for impedance matching of the processing chamber, and frequency modulation is performed on an RF generator in the processing chamber, associated with a second feedback control system for impedance matching of the processing chamber. It should be understood that the variable reactance may comprise any combination of series and / or parallel reactance elements. The reactance element may be associated with a specific processing station in the processing chamber, or it may be associated with all processing stations in the processing chamber. Examples of variable reactance elements may include variable capacitors and / or variable inductors. The variable reactance element may be a vacuum variable capacitor actuated by a stepper motor. In some embodiments, the variable reactance element may be a solid-state reactance element. In some embodiments, the current value of the variable reactance may be determined using a calibration table or lookup table as shown in FIG3. At 504, process 500 may determine, at least in part, the updated value of the variable reactance used by the processing station to be associated with the first feedback control system, based on errors associated with the second feedback control system. For example, as shown with reference to FIG3, the error associated with the second feedback control system may be the difference between a frequency measured at one or more processing stations (e.g., the average of measured frequencies across one or more processing stations) and a target frequency. In some embodiments, the frequency may be measured using a VI probe. In some embodiments, the variable reactance may be determined based on a combination of the error associated with the second feedback control system and the target or desired value of the variable reactance element. In some embodiments, the target or desired value of the variable reactance element may be determined based on a circuit model. In some embodiments, the target or desired value of the variable reactance element may be modified based on measured magnitude and / or phase information (e.g., measured using a VI probe) to compensate for errors or inaccuracies in the circuit model. In some embodiments, modifying the variable reactance element to have an updated value of variable reactance can have the effect of minimizing or eliminating reflected power and balancing the power delivered to one or more processing stations in the processing chamber. Furthermore, modifying the variable reactance element can cause the measured frequency at each processing station to be driven toward a target frequency. Background of the computational embodiments of the present invention Some of the embodiments disclosed herein relate to a computing system for modulating voltage during plasma operation. Many types of computing systems with any computer architecture can be used as the systems disclosed for implementing the algorithms described herein. For example, the system may contain software components that execute on one or more general-purpose processors, or specially designed processors such as Application-Specific Integrated Circuits (ASICs) or programmable logic devices (such as Field-Programmable Gate Arrays (FPGAs)). Furthermore, the system may be implemented on a single device or distributed across multiple devices. The functionality of the computing elements may be combined or further divided into multiple sub-modules. In some embodiments, the software element may be embodied in the code executed during the generation or execution of the techniques described herein on a properly programmed system. The software element may be stored in a non-volatile storage medium (such as an optical disc, flash memory device, portable hard disk, etc.) and includes a plurality of instructions constituting a computer device (such as a personal computer, server, network device, etc.). In a standard system, software components execute a set of commands prepared by a programmer / developer. However, hardware-executable module software is executable code written into memory using "machine code," which is selected from a specific set of machine language instructions or "native instructions" designed into the hardware processor. It is known that machine language instructions or native instructions are essentially built into the hardware processor (multiple processors). The "language" is the "language" used by the system and application software to communicate with the hardware processor. Each native instruction is a discrete code recognized by the processing architecture, specifying a particular register for arithmetic, addressing, or control functions; a specific memory location or offset; and an addressing mode used to interpret a particular operand. More complex operations are created by combining these simple native instructions, which are executed sequentially or directed by control flow instructions. The relationship between executable software instructions and the hardware processor is structured. In other words, an instruction itself is a series of symbols or values. It does not inherently convey any information. The processor is designed to interpret these symbols / values, giving meaning to the instructions. The methods and techniques used herein can be executed on a single machine at a single location, on multiple machines at a single location, or on multiple machines at multiple locations. When multiple machines are used, individual machines can be customized for their specific tasks. For example, operations requiring large blocks of code and / or significant processing power can be performed on large and / or fixed machines. Furthermore, some embodiments relate to tangible and / or non-transient computer-readable media or computer program products containing program instructions and / or data (including data structures) for performing various computer-performed operations. Examples of computer-readable media include, but are not limited to, semiconductor memory devices, phase-change devices, magnetic media such as magnetic disks and magnetic tapes, optical media such as CDs, magneto-optical media, and hardware devices specifically used for storing and executing program instructions, such as read-only memory (ROM) and random access memory (RAM). Computer-readable media may be directly controlled by an end user or may be indirectly controlled by an end user. Examples of media subject to direct control include media located at the user's facility and / or media not shared with other entities. Examples of media subject to indirect control include media that can be indirectly accessed by the user via an external network and / or via a server that provides shared resources such as the "cloud." Examples of program instructions include machine code such as machine code generated by a compiler, and files containing high-level program code that a computer can execute using a decoder. In various embodiments, data or information used in the disclosed methods and apparatus is provided in electronic format. Such data or information may include various coefficients used in calculations, etc. Data or other information provided electronically as used herein may be stored on a machine and transferred between machines. Traditionally, data in electronic format is provided digitally, and the data may be stored in various data structures, lists, databases, etc., in the form of bits and / or bytes. Data may be represented electronically, optically, etc. System software typically intersects with computer hardware and associated memory. In some embodiments, system software includes operating system software and / or firmware, as well as middleware and drivers installed in the system. System software provides the computer with basic, non-task-specific functions. In contrast, modules and other application software are used to perform specific tasks. Each native instruction used by a module is stored in memory and represented by a numerical value. Figure 6 is a block diagram of an example of a computing device 600 suitable for use when implementing certain embodiments of the present invention. For example, device 600 is suitable for implementing some or all of the functions of the image analysis logic disclosed herein. The computing device 600 may include a bus 1002 directly or indirectly coupled to the following devices: memory 604, one or more central processing units (CPUs) 606, one or more graphics processing units (GPUs) 608, a communication interface 610, an input / output (I / O) interface 612, input / output elements 614, a power supply 616, and one or more presentation elements 618 (such as a display (multiple displays)). In addition to the CPU 606 and GPU 608, the computing device 600 may include additional logic devices not shown in FIG. 6, such as, but not limited to, an image signal processor (ISP), a digital signal processor (DSP), an ASIC, an FPGA, etc. Although the various blocks in Figure 6 are connected by bus 1002 with wires, this is not limiting but merely for clarity. For example, in some embodiments, presentation element 618, such as a display device, can be considered as I / O element 614 (e.g., if the display screen is a touch screen). As another example, CPU 606 and / or GPU 608 may include memory (e.g., memory 604 may represent storage devices other than memory in GPU 608, CPU 606, and / or other elements). In other words, the computing device in Figure 6 is merely illustrative. There is no need to distinguish between "workstation," "server," "notebook," "desktop," "tablet," "client device," "mobile device," "handheld device," "electronic control unit (ECU)," "virtual reality system," and / or other device or system types, as all of the above fall within the scope of the computing device in Figure 6. Bus 1002 may represent one or more buses such as addressing buses, data buses, control buses, or combinations thereof. Bus 1002 may include one or more bus types such as Industry Standard Architecture (ISA) buses, Extended Industry Standard Architecture (EISA) buses, Video Electronics Standards Association (VESA) buses, Peripheral Component Interconnect (PCI) buses, Peripheral Component Fast Interconnect (PCIe) buses, and / or other types of buses. Memory 604 may comprise any of a variety of computer-readable media. Computer-readable media may be any available media accessible by computing device 600. Computer-readable media may include both volatile and non-volatile media, and removable and non-removable media. For example, but not limited to, computer-readable media may include computer storage media and / or communication media. Computer storage media may include information stored using any information storage method or technology, such as volatile and non-volatile media and / or removable and non-removable media, where the information is, for example, computer-readable instructions, data structures, program modules, and / or other data types. For example, memory 604 may store computer-readable instructions (such as those representing programs (multiple programs)) and / or program elements (multiple elements) such as an operating system. Computer storage media may include, but is not limited to, RAM, ROM, EEPROM, flash memory, or other memory technologies, CD-ROM, digital versatile disc (DVD), or other optical disc storage, cassette tape, magnetic tape, magnetic disk storage, or other magnetic storage devices, or any other media that can be used to store desired information and can be accessed by computing device 600. The term "computer storage media" as used herein does not include the signal itself. Communication media can embody computer-readable instructions, data structures, program modules, and / or other data types through modulated data signals such as carrier waves or other transmission mechanisms, and can include any information transmission medium. The term "modulated data signal" can refer to a signal having one or more characteristics that are set or altered to encode information within the signal. For example, but not limited to, communication media can include connection media such as wired networks or direct-wire connections, and wireless media such as acoustic, RF, far-infrared, and other wireless media. Any combination of the foregoing should also be included within the scope of computer-readable media. CPUs (multiple CPUs) 606 can be used to execute computer-readable instructions and control one or more elements of computing device 600 to perform one or more of the methods and / or processes described herein. Each of the CPUs (multiple CPUs) 606 may include one or more cores (e.g., single-core, dual-core, quad-core, octa-core, 28-core, 72-core, etc.) capable of simultaneously processing multiple software threads. Depending on the type of computing device 600 used (e.g., a processor with fewer cores for mobile devices and a processor with more cores for servers), CPUs (multiple CPUs) 606 may include any type of processor and may include different types of processors. For example, depending on the type of computing device 600, the processor may be an ARM processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). In addition to one or more microprocessors or supplementary coprocessors such as arithmetic coprocessors, computing device 600 may include one or more CPUs 606. Computing device 600 can use GPUs (multiple GPUs) 608 to compute graphics (such as 3D graphics). GPUs (multiple GPUs) 608 may contain many (e.g., dozens, hundreds, or thousands) cores, each capable of processing multiple software programs simultaneously. GPUs (multiple GPUs) 608 can generate pixel data for output images in response to rendering instructions (e.g., rendering instructions received from CPUs (multiple GPUs) 606 via a main interface). GPUs (multiple GPUs) 608 may include graphics memory, such as display memory, for storing pixel data. Display memory may be included as part of memory 604. GPUs (multiple GPUs) 608 may include two or more GPUs operating in parallel (e.g., via linking). When combined, each GPU 608 can generate pixel data for different portions of the output image or for different output images (e.g., a first GPU for a first image and a second GPU for a second image). Each GPU may contain its own memory or share memory with other GPUs. In instances where the computing device 600 does not include a GPU (complex GPU) 608, a CPU (complex CPU) 606 may be used to compute graphics. Communication interface 610 may include one or more receivers, transmitters, and / or transceivers, enabling computing device 600 to communicate with other computing devices via electronic communication networks (including wired and / or wireless communication). Communication interface 610 may include components and functions for communication on any number of different networks, such as wireless networks (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communication over Ethernet), low-power wide area networks (e.g., LoRaWAN, SigFox, etc.), and / or the Internet. Communication interface 1207 may include any suitable components or circuits for communicating using any suitable communication network (e.g., the Internet, intranet, wide area network (WAN), local area network (LAN), wireless network, virtual private network (VPN), and / or any other suitable type of communication network). For example, communication interface 1207 may include network interface card circuitry, wireless communication circuitry, etc. I / O interface 612 enables computing device 600 to be logically coupled to other devices (including I / O elements 614, presentation elements (multiple elements) 618, and / or other elements), some of which may be established (e.g., integrated into) computing device 600. Illustrative I / O elements 614 include microphones, mice, keyboards, joysticks, trackpads, earpieces, scanners, printers, wireless devices, etc. I / O elements 614 provide a Natural User Interface (NUI) that can handle air gestures, voice, or other physiological input generated by the user. In some cases, input may be transmitted to appropriate network elements for further processing. The NUI can implement any combination of voice recognition, handwriting recognition, face recognition, biometric recognition, on-screen and adjacent gesture recognition, air gestures, head and eye tracking, and touch recognition (described in more detail below) related to the display of computing device 600. The computing device 600 for gesture detection and recognition may include depth cameras such as stereo camera systems, infrared camera systems, RGB camera systems, touch screen technology, and combinations thereof. Furthermore, the computing device 600 may include an accelerometer or gyroscope capable of detecting motion (e.g., as part of an inertial measurement unit (IMU)). In some instances, the computing device 600 may use the output of the accelerometer or gyroscope to compute immersive augmented reality or virtual reality. Power supply 616 may include hard-wired power supply, battery power supply, or a combination thereof. Power supply 616 can provide power to computing device 600, enabling the components of computing device 600 to operate. Presentation element (plural element) 618 may include a display (such as a monitor, touch screen, television screen, head-up display (HUD), other display types, or combinations thereof), a speaker, and / or other presentation elements. Presentation element (plural element) 618 may receive data from other elements (such as GPU (plural GPU) 608, CPU (plural CPU) 606, etc.) and output data (such as images, videos, sounds, etc.). This invention can be described within the general context of computer code or machine-usable instructions, which include computer-executable instructions such as program modules executed by a computer or other machine (e.g., a personal data assistant or other handheld device). Generally, program modules that include routines, programs, objects, components, data structures, etc., refer to code that performs a specific task or implements a specific abstract data type. This invention can be implemented in various system configurations, including handheld devices, consumer electronic devices, general-purpose computers, and more specific computing devices. This invention can also be implemented in distributed computing environments, where tasks are performed by remote processing devices linked together through communication networks. in conclusion Numerous specific details are set forth in the description to provide a complete understanding of embodiments of the invention. Embodiments of the invention may be practiced without some or all of these details. In other instances, well-known processing operations are not described in detail so as not to unnecessarily obscure the embodiments of the invention. Although embodiments of the invention have been described with reference to specific examples, it should be understood that these specific examples are not intended to limit the embodiments of the invention. Unless otherwise stated, the methods, operations and apparatus features disclosed herein involve techniques and equipment commonly used in the fields of measurement, semiconductor device manufacturing, software design and programming, and statistics, and all fall within the ordinary skill of the art. Unless otherwise defined herein, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Various scientific dictionaries containing the terms used herein are well known and available in the art. While any methods and materials similar to or equivalent to those used herein may be useful in the practice or testing of the embodiments disclosed herein, only certain methods and materials are described. Numerical ranges include the numbers within a defined range. Each maximum numerical limit provided in this specification is intended to include each smaller numerical limit, as if such smaller numerical limits were explicitly stated herein. Each minimum numerical limit provided in this specification includes each larger numerical limit, as if such larger numerical limits were explicitly stated herein. Each numerical range provided in this specification includes each narrower numerical range falling within such a wider numerical range, as if such narrower numerical ranges were explicitly stated herein. The titles provided in this article are not intended to limit the content disclosed. Unless the context explicitly states otherwise, the singular articles “a” and “the” used in the text have a plural meaning. Unless the context explicitly states otherwise, the word “or” used in the text refers to non-exclusivity. The word "used to" can be used to describe or claim that various computing elements, including processors, memory, instructions, operating programs, models, or other components, can perform one or more tasks. In this context, "used to" refers to a structure (such as stored instructions, circuits, etc.) that contains the components capable of performing the task or multiple tasks during operation. Thus, a unit / circuit / component can be described as being able to perform the task, even if that particular component is not currently operational (e.g., not in a startup state). The term "for" can refer to hardware—for example, circuitry, memory storing executable program instructions for operation, etc. Furthermore, "for" can refer to a general-purpose structure (such as a general-purpose circuit) controlled by software and / or firmware (such as an FPGA or a general-purpose processor executing software), which operates in a manner capable of performing the tasks (multiple tasks). Additionally, "for" can refer to one or more memories or memory elements storing computer-executable instructions for performing the tasks (multiple tasks). Such memory elements may include on-chip memory with processing logic. In some contexts, "for" can also include adapting manufacturing processes (such as semiconductor manufacturing facilities) to manufacture apparatus (such as volumetric circuits), which is adapted to perform or carry out one or more tasks. 100: Equipment; 101: Gas delivery system; 102, 102A, 102B, 102C, 102D: Processing station; 103: Evaporation point; 104: Mixing container; 105: Valve; 106: Spray head; 107: Volume; 108: Substrate support / stand; 112: Substrate; 114: RF power supply; 116: Matching network; 120, 120A: Valve; 130: Processing equipment; 132: Integrated circuit manufacturing room; 133, 134, 135, 136: Processing station; 137: Input interface; 138: Substrate handling robot; 140: System controller; 142: RF signal source; 151: Example; 160: RF signal generator; 163: Matching network; 170 Power splitters 171, 172, 173, 174; Interface 180; Reactance judgment engine 182; Sensing circuit 200; Implementation 205; Signal generator 215; Sensing circuit 220; Matched reflection optimization device C220; Variable capacitors 225A, 225B; RF power control circuit C225A; Series impedance C225B; Variable capacitors 235A, 235B; Sensing circuit 300; Processors 302, 304, 306, 308; Block 400; Processors 402, 404, 406, 408; Block 500; Processors 502, 504; Block 600; Computing device 604; Memory 606; CPU 608; GPU 610; Communication interface 612; I / O interface 614; I / O component 616; Power supply 618; Presentation element 1002; Bus Figure 1A is a schematic diagram of an exemplary device according to certain embodiments. Figure 1B is a block diagram showing various components of a system used for semiconductor manufacturing processes according to certain embodiments. Figure 1C is a block diagram showing various components of a system used for semiconductor manufacturing processes according to certain embodiments. Figure 2 shows the various circuit elements used in a feedback control system according to certain embodiments. Figure 3 is a flowchart illustrating an exemplary process of a two-feedback control system for determining the value of a variable reactance element and coordinating impedance matching according to certain embodiments. Figure 4 is a flowchart illustrating an exemplary process for determining whether to modify the variable reactance based on impedance matching in a feedback control system according to certain embodiments. Figure 5 is a flowchart illustrating an exemplary process of a two-feedback control system for impedance matching according to certain embodiments. Figure 6 shows an exemplary computer system that can be used to implement some of the embodiments described herein. 102A, 102B: Processing Stations 200: Example 205: Signal Generator 215: Sensing Circuit 220: Matching Reflection Optimization Device C220: Variable capacitor 225A, 225B: RF power control circuit C225A: Series impedance C225B: Variable Capacitor 235A, 235B: Sensing circuit

Claims

1. A computer program product for impedance matching and power distribution networks, the computer program product comprising a non-transient computer-readable medium on which a plurality of computer-executable instructions are provided, the plurality of computer-executable instructions being configured to: obtain a plurality of current values ​​of a plurality of variable reactances relating to a processing station in a processing room at a current time, wherein the plurality of variable reactances are relating to a first feedback control system for impedance matching of the processing room, wherein frequency modulation is performed on an RF generator in the processing room relating to a second feedback control system for impedance matching of the processing room; and determine, at least in part based on an error relating to the second feedback control system, a plurality of updated values ​​of the plurality of variable reactances for the processing station to be associated with the first feedback control system.

2. The computer program product for impedance matching and power distribution networks as claimed in claim 1, wherein the error associated with the second feedback control system includes a difference between a measured frequency at the processing station and a target frequency associated with the processing room.

3. As in request item 2, the computer program product for impedance matching and power distribution networks, wherein the measured frequency at the processing station is determined using one or more sensing circuits.

4. A computer program product for impedance matching and power distribution networks as described in claim 3, wherein the updated value of the complex variable reactance can be used to modify the position of one or more variable reactance elements associated with the processing room to minimize reflected power associated with the processing station.

5. The computer program product for impedance matching and power distribution networks as described in claim 4, wherein the one or more variable reactance elements include at least one of the following: a series capacitor or a parallel capacitor.

6. A computer program product for impedance matching and power distribution networks, as described in claim 4, wherein the position of one or more variable reactance elements associated with the first feedback control system is modified so that the second feedback control system drives the measured frequency toward the target frequency.

7. The computer program product for impedance matching and power distribution networks as described in claim 6, wherein the target frequency corresponds to a frequency specified for a step in a formulation performed at the present time.

8. A computer program product for impedance matching and power distribution networks, as described in any of requests 1-3, wherein the multiple computer-executable instructions are further configured to determine the position of one or more variable reactance elements using a calibration table and at least in part based on the multiple updated values ​​of the multiple variable reactances.

9. A computer program product for impedance matching and power distribution networks as described in any of requests 1-3, wherein the complex variable reactance includes a series reactance associated with the processing station in the processing room.

10. A computer program product for impedance matching and power distribution networks as described in any of claims 1-3, wherein the complex variable reactance includes a parallel reactance associated with the processing chamber.

11. A computer program product for impedance matching and power distribution networks as described in any of claims 1-3, wherein the complex variable reactance includes a variable series reactance, wherein an updated series reactance is determined based on a correction to a target series reactance, wherein the correction includes the error associated with the second feedback control system.

12. A computer program product for impedance matching and power distribution networks as described in any of claims 1-3, wherein the complex variable reactance includes a variable shunt reactance, wherein an updated shunt reactance is determined at least in part based on the error associated with the second feedback control system without needing to determine a target shunt reactance.

13. A computer program product for impedance matching and power distribution networks as described in any of requests 1-3, wherein the first feedback control system uses the updated value of the complex variable reactance to respond to compliance with one or more criteria.

14. The computer program product for impedance matching and power distribution networks as described in claim 13, wherein the one or more criteria include: a reflected power related to the processing room exceeds a reflected power threshold, a power balance ratio related to the multiple processing stations in the processing room exceeds a power balance threshold, and an error related to the second feedback control system exceeds an error threshold.

15. A computer program product for impedance matching and power distribution networks, as in request item 13, wherein the updated value of the complex variable reactance is modified before use in response to the following judgment: a difference between the current value of the complex variable reactance and the updated value of the complex variable reactance falls within a jitter threshold.

16. A computer program product for impedance matching and power distribution networks, as described in any of claims 1-3, wherein at least in part based on the error associated with the second feedback control system, determines that the complex updated value of the complex variable reactance used in the processing station is in response to the following determination: a mode has been activated in a formulation used at the present time, which is related to controlling the first feedback control system based on the error associated with the second feedback control system.

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