Plasma processing methods

Abstract

The embodiments provided herein generally include plasma processing systems and related methods for preferentially cleaning desired surfaces of a substrate support assembly by manipulating one or more characteristics of in-situ plasma. In one embodiment, the plasma processing method includes the steps of generating plasma in a processing area defined by a chamber cover and a substrate support assembly, exposing an edge ring and a substrate support surface to the plasma, and establishing a pulsed voltage (PV) waveform at an edge control electrode.

Description

[Technical Field]

[0001] The embodiments herein relate to gas or vapor electric space discharge elements for generating plasma used in the manufacture of semiconductor devices, specifically processing chambers for generating capacitively coupled or inductively coupled plasmas of gas or vapor materials supplied to the chamber volume, and processing semiconductor substrates therein. [Previous Technology]

[0002] Electrostatic chucks (ESCs) are commonly used in semiconductor device manufacturing operations where vacuum chucks are not feasible and mechanical clamping is undesirable, such as supporting and securing substrates in the low-pressure environment of a processing chamber. A typical ESC is formed of one or more layers of dielectric material, the dielectric material layers providing surfaces for supporting the substrate (e.g., substrate support surfaces), and further includes clamping electrodes embedded or disposed between one or more layers of dielectric material. The substrate is secured to the ESC by providing a voltage potential difference between the substrate and the clamping electrodes, the voltage potential difference generating an electrostatic attraction between the substrate and the clamping electrodes.

[0003] The ESC is typically part of a component used to control the state of plasma-assisted processes performed within the processing chamber, such as plasma-assisted etching, which uses ions to bombard the surface of a substrate material through openings in a shielding layer formed on the substrate surface. In a typical plasma-assisted etching process, the substrate is positioned on the ESC, plasma is formed over the substrate, and ions are accelerated from the plasma across a plasma sheath layer towards the substrate, which is the electron-depleted region formed between the plasma and the substrate surface.

[0004] The ESC assembly may include an edge ring for improving plasma processing inhomogeneity near the substrate edge by reducing electrical and thermal discontinuities between the substrate edge and the ESC assembly portion disposed outward from the substrate edge. Typically, the edge ring is positioned around the substrate, and its dimensions allow at least some tolerance for positioning the substrate on the ESC such that the inward surface of the edge ring and the peripheral edge of the substrate define a gap region between them.

[0005] Typically, processing byproducts from plasma-assisted processes accumulate on chamber surfaces, including the surface of ESC components. Conventional methods for cleaning such byproducts include exposing the chamber surfaces to an activating agent of a cleaning gas, which can be formed using a remote plasma source and flow into the processing chamber, or formed by flowing the cleaning gas into the chamber and forming in-situ plasma therein. The activating agent of the cleaning gas reacts with the processing byproducts formed on the chamber surfaces to form volatiles, which are discharged from the processing chamber through an exhaust port. Generally, repeated exposure to activating cleaning gases leads to associated downtime and surface damage to chamber components; therefore, it is best to minimize the number and / or duration of chamber cleaning processes.

[0006] Unfortunately, improper processing byproducts often accumulate in portions of the ESC assembly, such as in the gaps between the substrate periphery and the inward portion of the edge ring, long before other processing elements arranged within it require the chamber cleaning process. Processing byproducts accumulated in these gaps may migrate to the beveled edges of the substrate and / or cause plasma instability, resulting in unwanted arcing between the substrate and the edge ring. Surface defects and / or arc-related damage to the substrate edges caused by the migration of processing byproducts can lead to reliability issues or failures of components formed on the substrate, thereby inhibiting the yield of usable components formed on the substrate. Arc-induced particles also increase chamber contamination, requiring increased downtime for chamber cleaning and maintenance, thus reducing system availability and productivity. Frequent use of conventional chamber cleaning methods to clean the gap portions of the ESC also reduces system availability and productivity, and further poses the potential problem of damaging other surfaces of the ESC (such as the substrate support surface) and reducing its lifespan.

[0007] Therefore, there is a need in the art for systems and methods to solve the above problems. [Summary of the Invention]

[0008] The embodiments provided herein generally include plasma processing systems for preferentially cleaning desired surfaces of substrate support assemblies by manipulating one or more characteristics and related methods of in-situ plasma.

[0009] In one embodiment, a plasma processing method includes the following steps: (a) generating plasma in a processing area defined by a chamber cover and a substrate support assembly, the substrate support assembly including: a first portion of a dielectric material forming a substrate support surface; an edge ring surrounding the substrate support surface, the edge ring including a plasma-facing surface and one or more edge groove surfaces disposed inwardly from the plasma-facing surface; a bias electrode spaced from the substrate support surface by the first portion of the dielectric material; and an edge control electrode disposed at a distance from the center of the bias electrode, wherein the bias electrode is electrically coupled to a first bias generator for establishing a first pulsed voltage (PV) waveform at the bias electrode; the edge control electrode is electrically coupled to a second bias generator for establishing a second pulsed voltage (PV) waveform at the edge control electrode; (b) exposing the edge ring and the substrate support surface to the plasma; and simultaneously with (c) establishing a second pulsed voltage (PV) waveform at the edge control electrode.

[0010] In another embodiment, a plasma processing method includes the following steps: (a) igniting and maintaining plasma in a processing area of ​​a processing chamber, the plasma including a first portion disposed between a substrate support surface of a substrate support assembly and a chamber cover, and a second portion disposed between an edge ring and the chamber cover, the substrate support assembly including: a first portion of a dielectric material forming the substrate support surface; a bias electrode spaced from the substrate support surface by the first portion of the dielectric material, wherein the bias electrode is electrically coupled to a first pulse voltage waveform generator, the first pulse voltage waveform generator being used to bias the bias electrode. (a) establishing a first pulse voltage (PV) waveform at the edge control electrode; an edge control electrode arranged at a distance from the center of the bias electrode, wherein the edge control electrode is electrically coupled to a second pulse voltage (PV) waveform generator; and an edge ring surrounding a substrate support surface, the edge ring may include one or more edge groove surfaces defining edge groove regions, wherein at least a partially raised substrate is disposed on the substrate support surface; (b) establishing a second pulse voltage waveform at the edge control electrode using the second pulse voltage (PV) waveform generator; and (c) exposing the at least partially raised substrate to plasma.

[0011] In another embodiment, a processing method includes the steps of: (a) igniting and sustaining a plasma from a gas or vapor supplied to a processing area, the processing area being defined by a chamber cover and a substrate support assembly facing the chamber cover, the substrate support assembly including: a first portion of dielectric material forming a substrate support surface; a first electrode spaced from the substrate support surface by the first portion of dielectric material; an edge ring surrounding the substrate support surface, the edge ring having one or more edge groove surfaces defining an edge groove region having a circumferential edge of a partially raised substrate disposed on the substrate support surface; and a second electrode spaced from the edge ring by a second portion of dielectric material, wherein the substrate support assembly is electrically coupled to radio frequency (RF) (a) an RF generator, which transmits an RF signal for igniting and sustaining plasma, the RF signal establishing a first RF waveform at a first electrode and a second RF waveform at a second electrode, the second electrode being electrically coupled to an edge tuning circuit, the edge tuning circuit being used to adjust one or more characteristics of the second RF waveform relative to the first RF waveform to control plasma density uniformity in the processing area, and at least one characteristic of the second RF waveform being different from the characteristics of the first RF waveform; and (b) exposing one or more edge groove surfaces to plasma.

[0012] In another embodiment, the plasma chamber includes a chamber body and a chamber cover, the chamber body and the chamber cover defining a processing volume; and a substrate support assembly disposed in the processing volume facing the chamber cover. The substrate support assembly may include: a support base; and a substrate support member disposed on the support base, the substrate support member may include a dielectric material forming a substrate support surface, a bias electrode disposed in the dielectric material and spaced apart from the substrate support surface and the support base by a portion of the dielectric material, and an edge control electrode spaced a distance from the center of the bias electrode. The chamber also includes an edge-tuning circuit electrically coupled to an edge control electrode; and a non-transitory computer-readable medium having instructions for performing a method that may include the steps of: a) generating plasma from gas or vapor delivered to a processing volume by using a radio frequency (RF) signal transmitted to a support base, wherein the RF signal is transmitted to the support base by an RF generator and the RF signal establishes a first RF waveform at a bias electrode and a second RF waveform at an edge control electrode; and b) adjusting one or more characteristics of the second RF waveform relative to the first RF waveform by using the edge-tuning circuit.

[0013] Other embodiments may include corresponding computer systems, devices and computer programs recorded on one or more computer storage devices, each used to perform the actions of the method.

Implementation Method

[0025] The embodiments provided herein relate to processing systems and related methods used in semiconductor device manufacturing processes. Specifically, the embodiments herein provide methods for cleaning portions of a substrate support assembly using plasma (such as in-situ cleaning plasma) formed in a processing chamber. For example, in some embodiments, the systems and methods are preferably used to clean accumulated processing byproducts from portions of the substrate support assembly that define gap regions formed when a substrate is placed on the substrate support assembly. Therefore, the methods described herein can be used for beneficial in-situ plasma cleaning of the gap region surfaces of the substrate support assembly while reducing plasma damage to other surfaces, such as substrate support surfaces that may have their lifespan extended.

[0026] In some embodiments, the processing system is used for a plasma-assisted etching process, wherein ions generated by the plasma bombard the material surface of the substrate through openings formed in a patterned mask layer formed on the substrate surface. In a typical plasma-assisted etching process, the substrate is positioned on the substrate receiving surface of a substrate support assembly, a plasma is formed on the substrate using radio frequency (RF) power, and ions are accelerated from the plasma across a plasma sheath to the substrate. The plasma sheath generally exhibits nonlinear diode-like characteristics, which leads to rectification of the applied RF field, resulting in a DC voltage drop or self-bias between the substrate and the plasma.

[0027] In some embodiments, the processing system is used to control the characteristics of the plasma sheath using pulsed voltage (PV) waveforms transmitted from one or more pulsed voltage (PV) generators to bias and edge control electrodes. In some embodiments, radio frequency (RF) generated RF waveforms are provided from an RF generator to one or more power electrodes within the processing chamber to establish and maintain plasma within the processing chamber, while PV waveforms transmitted from one or more PV generators are used to establish a nearly constant sheath voltage (e.g., a constant difference between the plasma potential and the substrate potential) across the substrate surface and the surface of the substrate support assembly adjacent thereto. During one or more plasma processing operations performed within the processing chamber, the established nearly constant sheath voltage provides an ideal ion energy distribution function (IEDF) on the substrate surface.

[0028] Some embodiments disclosed herein include apparatus and methods for controlling plasma uniformity, for example, by controlling the electron density in bulk plasma on adjacent surfaces of a substrate peripheral edge region and a substrate support assembly relative to the center of the substrate. In some embodiments, an edge-tuning circuit is used to control plasma uniformity to control one or a combination of the following: the voltage amplitude ratio between a radio frequency waveform established at an edge control electrode and a radio frequency waveform established at a bias electrode (e.g., a chuck electrode), the current amplitude ratio between the radio frequency waveforms at the edge control electrode and the bias electrode, and the phase difference between the radio frequency waveforms at each electrode.

[0029] In some embodiments, ion energy and directionality are controlled by separately biasing the substrate and the edge ring surrounding the substrate using a pulsed voltage (PV) waveform. The PV waveform can be established at electrodes forming part of the substrate support assembly and is generally located within portions of the substrate support assembly, which are respectively located below the substrate (bias electrode) and the edge ring (edge ​​control electrode). As described below, the PV waveform can be used to manipulate the shape of the plasma sheath boundary to focus ions that accelerate across the sheath to a desired area on the underlying surface. In some embodiments, the chamber element cleaning method uses focused ions to target the gap region between the substrate edge and / or the substrate support surface and the surrounding edge ring to remove improper processing byproducts, such as polymers formed on the surface of the edge recess region during a reactive ion etching (RIE) plasma process.

[0030] In some embodiments, ion flux (plasma density uniformity) is controlled by using an edge tuning circuit to adjust one or more characteristics of the radio frequency waveform established at the edge control electrode relative to one or more characteristics of the radio frequency waveform established at the bias electrode. For example, the edge tuning circuit can be used to adjust the voltage amplitude ratio or current amplitude ratio between the radio frequency waveforms established at the edge control electrode and the bias electrode. The voltage and / or current amplitude ratio can be used to adjust the plasma distribution (plasma density) on the substrate support assembly, thereby increasing the plasma density on the edge ring relative to the plasma density in the central region of the substrate support assembly, and vice versa.

[0031] In some embodiments, the edge tuning circuitry is used to provide a desired phase difference between the radio frequency waveforms established at the bias electrode and the edge control electrode. The phase difference can be adjusted to amplify the electric field generated between the two electrodes. The amplification of the electric field can be manipulated to increase the concentration of ions and reactive neutral substances disposed in the gap region between the substrate edge and the circumferential inner surface of the edge. In some embodiments, the phase difference between the radio frequency waveforms is controlled to concentrate plasma between the bias electrode and the edge control electrode, thereby concentrating plasma in the gap region.

[0032] In some embodiments, the pulsed voltage (PV) waveform and / or edge-tuning circuitry are used alone or in combination with a substrate release method to preferentially clean the gap region while protecting the dielectric substrate support surface from ion-induced damage. For example, in some embodiments, the method includes focusing ions onto the gap region and / or concentrating plasma into the gap region while partially lifting the substrate from the substrate support surface.

[0033] Advantageously, the apparatus and methods can be used individually or in combination to provide separate process adjustment knobs for controlling ion energy and directional uniformity, as well as for individually controlling the ion flux and / or the uniformity of reactive neutral species across the surface of the substrate support assembly and / or the substrate disposed thereon. For example, in some embodiments, ion energy and directional uniformity can be controlled by adjusting the PV waveforms established at the edge control electrode and the bias electrode, thereby controlling the thickness distribution of the plasma sheath and the shape of the sheath boundary (between the plasma sheath and the plasma) formed in the gap region of the substrate support assembly. Ion flux and / or the uniformity of reactive neutral species concentration can be individually controlled by adjusting the radio frequency waveforms established at each electrode. Therefore, the apparatus and methods described herein promote directional cleaning of the gap region of the substrate support assembly by controlling ion energy, ion directionality, and / or the concentration of ions and reactive neutral species. Figures 1A through 1D illustrate exemplary processing systems that can be used to perform these methods.

[0034] Example of a plasma treatment system

[0035] Figures 1A and 1B are schematic cross-sectional views of respective processing systems 10A and 10B used to perform one or more plasma processing methods described herein. Figure 1C is a close-up view of a portion of the substrate support assembly 136 shown in Figure 1A. Figure 2 is a simplified schematic diagram of a processing scheme that can be used with one or both of processing systems 10A and 10B. Figures 3A to 3B are examples of edge tuning circuits 170 that can be used with one or both of processing systems 10A and 10B to control and adjust plasma uniformity.

[0036] In some embodiments, the processing systems 10A and 10B shown in Figures 1A and 1B are used for plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processing. However, it should be noted that the embodiments described herein can also be used to configure processing systems for other plasma-assisted processes, such as plasma-enhanced deposition processes, such as plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), plasma processing, or plasma-based ion implantation processes, such as plasma doping (PLAD) processes.

[0037] As shown in Figures 1A to 1B, processing systems 10A-10B are used to form capacitively coupled plasma (CCP), wherein processing chamber 100 includes an upper electrode (e.g., chamber cover 123) disposed in processing volume 129, facing a lower electrode (e.g., substrate support assembly 136) also disposed in processing volume 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., RF generator 118) is electrically coupled to one of the upper or lower electrodes, which transmits RF signals for igniting and sustaining the plasma (e.g., plasma 101). The plasma is capacitively coupled to each of the upper and lower electrodes and disposed in the processing area therebetween. Typically, one of the upper or lower electrodes opposite to the other is coupled to ground or a second RF power source. In Figures 1A to 1B, one or more elements of the substrate support assembly 136 (such as support base 107) are electrically coupled to the plasma generator assembly 163, which includes a radio frequency generator 118, and the chamber cover 123 is electrically coupled to ground.

[0038] As shown in Figures 1A to 1B, each processing system 10A and 10B includes a processing chamber 100, a substrate support assembly 136, a system controller 126, and a plasma control scheme 188. It is contemplated that any one or a combination of the characteristics, configuration, and / or structural elements of the processing system 10A, such as the structural elements of the substrate support assembly 136 and / or the electrical elements of the plasma control scheme 188, as described herein, can be used in the processing system 10B, and vice versa.

[0039] The processing chamber 100 typically includes a chamber body 113, which includes a chamber cover 123, one or more sidewalls 122, and a chamber base 124, which together define a processing volume 129. The one or more sidewalls 122 and the chamber base 124 are generally made of a material that is sized and shaped to form structural supports for the elements of the processing chamber 100 and to withstand pressures and additional energy applied thereto, while generating plasma 101 within the vacuum environment maintained in the processing volume 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed of a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0040] An air inlet 128, arranged through the chamber cover 123, is used to deliver one or more processing gases from a processing gas source 119 in fluid communication therewith to the processing volume 129. In some embodiments, the gas is supplied through a spray head (not shown). In another embodiment, the gas is supplied through a sidewall 122 (not shown). The substrate 103 is loaded into and removed from the processing volume 129 through an opening (not shown) in one or more sidewalls 122, the opening being sealed with a slit valve (not shown) during plasma processing of the substrate 103.

[0041] In some embodiments, a plurality of lifting pins 20, movably arranged through an opening formed in the substrate support assembly 136, facilitate the transfer of the substrate to and from the substrate support surface 105A. In some embodiments, the plurality of lifting pins 20 are arranged above and coupled and / or engaged with lifting pin rings (not shown) arranged in the processing volume 129. The lifting pin rings may be coupled to a shaft (not shown) that extends hermetically through the chamber base 124. The shaft may be coupled to an actuator (not shown) for raising and lowering the lifting pin rings. When the lifting pin rings are in the raised position, they engage with the plurality of lifting pins 20 to raise the upper surface of the lifting pins above the substrate support surface 105A, thereby raising the substrate 103 and enabling access to the inactive (back) surface of the substrate 103 by means of a robot handle (not shown). When the lifting pin ring is in the descending position, the plurality of lifting pins 20 are flush with or recessed below the substrate support surface 105A, and the substrate 103 is located on it.

[0042] System controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. System controller 126 controls the processing sequence for processing substrate 103, including the substrate biasing method described herein. CPU 133 is a general-purpose computer processor for use in industrial environments, used to control the processing chamber and its associated subprocessors. Memory 134, as described herein, is generally non-volatile memory and may include random access memory, read-only memory, floppy disk or hard disk drives, or other suitable forms of local or remote digital storage. Support circuitry 135 is conventionally coupled to CPU 133 and includes cache memory, clock circuitry, input / output subsystems, power supply, and combinations thereof. Software instructions (programs) and data may be encoded and stored in memory 134 for instructing the processors within CPU 133. The software program (or computer instructions) read by the CPU 133 in the system controller 126 determines which tasks can be performed by the components in the processing system 10A and / or 10B.

[0043] Typically, the program readable by the CPU 133 in the system controller 126 includes code that, when executed by the processor (CPU 133), performs tasks related to the plasma processing scheme described herein. The program may include instructions for controlling various hardware and electrical components within the processing systems 10A and / or 10B to perform various processing tasks and for implementing various processing sequences of the methods described herein. In one embodiment, the program includes instructions for performing one or more operations described below with respect to Figures 7 and 8A through 8C.

[0044] The plasma control scheme 188 shown in Figures 1A to 1B generally includes a plasma generator assembly 163, a first bias generator 196 for establishing a first PV waveform at a bias electrode 104, and a second first bias generator 197 for establishing a second PV waveform at an edge control electrode 115. In some embodiments, the plasma generator assembly 163 transmits radio frequency signals to a support base 107 (e.g., a power electrode or cathode), which can be used to generate (maintain and / or ignite) plasma 101 in a processing area disposed between a substrate support assembly 136 and a chamber cover 123. In some embodiments, the radio frequency generator 118 is used to transmit radio frequency signals with a frequency greater than 400 kHz, such as about 1 MHz or higher, or about 2 MHz or higher, such as about 13.56 MHz or higher, about 27 MHz or higher, or about 40 MHz or higher.

[0045] In some embodiments, the plasma control scheme 188 further includes an edge tuning circuit 170, which can be used to adjust one or more characteristics of the plasma 101 formed between the substrate support assembly 136 and the chamber cover 123. In some embodiments, the edge tuning circuit 170 can be used to adjust the density of the plasma 101 portion formed on the circumferential edge of the substrate 103 disposed on the substrate support assembly 136 relative to the density of the plasma 101 portion formed on the central surface of the substrate 103.

[0046] Generally, as used herein, plasma density refers to the number of free electrons per unit volume of bulk plasma (e.g., free electrons / cm³), which in some embodiments can range from about 10⁸ cm⁻³ to about 10¹¹ cm⁻³. Edge tuning circuitry 170 is capable of manipulating one or more characteristics of the radio frequency power used to maintain plasma 101 in the region above the central portion of substrate support assembly 136, relative to the radio frequency power used to maintain plasma 101 in the region above the central portion of substrate support assembly 136. For example, edge tuning circuitry 170 can be used to adjust one or more of the voltage, current, and / or phase of the radio frequency power at the edge of substrate support assembly 136 relative to the radio frequency power in the central region 103A of substrate support assembly 136.

[0047] As further discussed below, the edge tuning circuit 170 may be electrically coupled to an edge control electrode 115 disposed in the substrate support assembly 136. In some embodiments, a radio frequency (RF) signal for igniting and / or sustaining the plasma 101 is transmitted from the plasma generator assembly 163 to the support base 107, which is capacitively coupled to the edge control electrode 115 via a dielectric material layer disposed therebetween. The edge tuning circuit 170 may be used to adjust one or more characteristics of the RF power used to sustain the plasma in the region above the edge control electrode 115, for example, by adjusting the voltage, current, and / or phase of the RF power at the edge control electrode 115 relative to the RF power supplied to the support base 107.

[0048] In some embodiments, the difference between the voltage, current, and / or phase of the radio frequency power of the plasma in the region above the edge control electrode 115 and the bias electrode 104 is determined and / or monitored by measuring or determining the individual voltage, current, and / or phase of the radio frequency power at the edge control electrode 115 and / or the bias electrode 104. In some embodiments, one or more characteristics of the radio frequency power at the edge control electrode 115 and / or the bias electrode 104 are measured and / or determined using the signal detection module 187 described below.

[0049] As described above, in some embodiments, the plasma generator assembly 163, including the radio frequency generator 118 and the radio frequency generator assembly 160, is generally used to deliver a desired amount of continuous wave (CW) or pulsed RF power to the support base 107 of the substrate support assembly 136 at a desired substantially fixed sinusoidal frequency based on control signals provided from the system controller 126. During processing, the plasma generator assembly 163 is used to deliver RF power (e.g., RF signals) to the substrate support 105 and the support base 107 disposed within the substrate support assembly 136. The RF power delivered to the support base 107 is used to ignite and sustain the processing plasma 101 of the processing gas disposed within the processing volume 129.

[0050] In some embodiments, the support base 107 is an RF electrode electrically coupled to the RF generator 118 via an RF matching circuit 162 and a first filter assembly 161, both of which are disposed within the RF generator assembly 160. The first filter assembly 161 includes one or more electrical components for substantially preventing current generated by the output of the PV waveform generator 150 from flowing through the RF power transmission line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance (e.g., high Z) for the PV signal generated by the PV pulse generator P1 within the PV waveform generator 150, thereby suppressing current flowing to the RF matching circuit 162 and the RF generator 118.

[0051] In some embodiments, the RF generator assembly 160 and the RF generator 118 are used to ignite and sustain the processing plasma 101 using the field generated by the processing gas disposed in the processing volume 129 and the RF power (RF signal) delivered by the RF generator 118 to the support base 107. The processing volume 129 is fluidly coupled to one or more dedicated vacuum pumps through a vacuum outlet 120, which maintains the processing volume 129 under sub-atmospheric pressure conditions and vents the processing gas and / or other gases therefrom. In some embodiments, a substrate support assembly 136 disposed in the processing volume 129 is disposed on a support shaft 138, which is grounded and extends through the chamber base 124. However, in some embodiments, the RF generator assembly 160 is used to deliver RF power relative to the support base 107 to a bias electrode 104 disposed in a substrate support 105.

[0052] In some embodiments, the edge tuning circuit 170 is used to control and / or adjust one or more characteristics of the radio frequency waveform (e.g., the second radio frequency waveform 502 shown in Figure 5) established at the edge control electrode 115 relative to one or more characteristics of the radio frequency waveform (e.g., the first radio frequency waveform 501 shown in Figure 5) established at the bias electrode 104. In some embodiments, as shown in Figures 1A and 2, the edge tuning circuit 170 is electrically coupled between the edge control electrode 115 and ground. In other embodiments, as shown by the dashed lines in Figures 1B and 2, the edge tuning circuit 170 may be electrically coupled between the edge control electrode 115 and the plasma generator assembly 163, thereby electrically coupling the edge control electrode 115 to the support base 107.

[0053] As described above, the substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may further include an insulating plate 111 and a ground plane 112, as described below. The support base 107 is electrically isolated from the chamber base 124 by the insulating plate 111, and the ground plane 112 is inserted between the insulating plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to the support base 107 and disposed on the support base 107. In some embodiments, the support base 107 is used to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing.

[0054] In some embodiments, the support base 107 includes one or more cooling channels (not shown) disposed therein, which are fluidly coupled to and in fluid communication with a coolant source (not shown), such as a refrigerant source or a water source having relatively high resistance. In some embodiments, the substrate support 105 includes a heater (not shown), such as a resistance heating element embedded in its dielectric material. Here, the support base 107 is formed of a corrosion-resistant thermally conductive material, such as a corrosion-resistant metal, for example aluminum, aluminum alloy, or stainless steel, and is coupled to the substrate support by adhesive or mechanical means.

[0055] Typically, the substrate support 105 is formed of a dielectric material, such as a bulk sintered ceramic material, or a corrosion-resistant metal oxide or metal nitride material, such as alumina (Al₂O₃), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y₂O₃), and mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in its dielectric material. In some embodiments, one or more characteristics of the radio frequency power used to maintain the plasma 101 on the bias electrode 104 are determined and / or monitored by measuring a radio frequency waveform (e.g., the first radio frequency waveform 501 in Figure 5) established at the bias electrode 104. Typically, the first radio frequency waveform 501 is established by transmitting a radio frequency signal from the plasma generator assembly 163 to the substrate support 105, which is capacitively coupled to the bias electrode 104 through a dielectric material layer 105C (Figure 1C) disposed therein.

[0056] In one configuration, the bias electrode 104 is a clamping electrode for securing (i.e., clamping or electrostatically clamping) the substrate 103 to the substrate support surface 105A of the substrate support 105 and for biasing the substrate 103 relative to the processing plasma 101 using one or more pulse voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive parts, such as one or more metal meshes, foils, plates, or combinations thereof.

[0057] In some embodiments, the bias electrode 104 is electrically coupled to a clamping network 116, which uses an electrical conductor, such as a coaxial power transmission line 106 (e.g., a coaxial cable), to provide a clamping voltage to the electrode, such as a quiescent DC voltage between approximately -5000 V and approximately 5000 V. As will be further discussed below, the clamping network 116 includes a bias compensation circuit element 116A, a DC power supply 155, and a bias compensation module blocking capacitor, also referred to herein as the blocking capacitor C5. The blocking capacitor C5 is arranged between the output of the pulse voltage (PV) waveform generator 150 and the bias electrode 104.

[0058] Referring to Figures 1A and 1B, the substrate support assembly 136 may further include an edge control electrode 115 located below the edge ring 114 and surrounding the bias electrode 104, and / or arranged at a distance from the center of the bias electrode 104. Generally, for the processing chamber 100 for processing a circular substrate, the edge control electrode 115 is annular, made of a conductive material, and surrounds at least a portion of the bias electrode 104. In some embodiments, as shown in Figure 1A, the edge control electrode 115 is located within a region of the substrate support 105. In some embodiments, as shown in Figure 1A, the edge control electrode 115 includes a conductive mesh, foil, and / or plate, the distance between the conductive mesh, foil, and / or plate and the edge ring 114 (i.e., in the Z direction) is similar to the distance between the bias electrode 104 and the substrate support surface 105A of the substrate support 105. In some other embodiments, as shown in Figure 1B, the edge control electrode 115 includes a conductive mesh, foil, and / or plate located on or within a region of the dielectric tube 110, which surrounds at least a portion of the bias electrode and / or substrate support 105. The dielectric tube 110 may be made of various insulators, such as alumina, aluminum nitride, or quartz. In some embodiments, the dielectric tube 110 may include several portions made of the same or different materials. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is located within or coupled to an edge ring 114, which is disposed on and adjacent to the substrate support 105.

[0059] Figure 1D is a close-up view of a portion of the substrate support assembly 136 shown in Figure 1A. As shown, an edge ring 114 is located on the substrate support and surrounds the substrate 103. The edge ring 114 can be used to protect the edge of the substrate support 105 and, in some cases, minimize any electrical and / or thermal discontinuities formed at the edges of the substrate and the substrate support. The edge ring 114 includes one or more inner surfaces 114A facing a portion of the substrate support 105 and the peripheral (beveled) edge of the substrate 103 disposed thereon. The inner surfaces 114A of the edge ring 114 are spaced apart from the substrate support 105 and the substrate 103 disposed thereon to define one or more gaps 117A to 117B, and may include a boss portion 114B disposed below the beveled edge of the substrate when the substrate 103 is located on the substrate support 105.

[0060] In a typical etching process, the upper plasma-facing surface of the edge ring 114 (e.g., surface 114C) is bombarded with ions during processing, resulting in ion-induced corrosion of the dielectric material forming the edge ring 114. Unfortunately, since the surfaces of the edge ring 114 defining the gap regions 117A to 117B are less exposed to the plasma 101, they tend to accumulate processing etching byproducts, which, unless removed, can lead to improper plasma arcing and / or particle transfer between the edge ring 114 and the substrate 103 surface. Therefore, in some embodiments, bias and plasma control methods used to improve processing non-uniformity at substrate edges can also be used to preferentially clean the surfaces defining the edge recess regions 117.

[0061] As described below, the edge ring 114 can be biased using a pulsed voltage (PV) waveform to control the shape of the plasma sheath boundary 11, as it extends to the substrate edge and the edge ring 114 to span the edge groove region 117. The shape of the plasma sheath boundary 11 affects the energy and directionality of ions that accelerate across the plasma sheath. For example, as described below and shown in Figures 9A to 9C, the height difference between a portion (part 11A) of the sheath boundary 11 formed on the substrate 103 and a portion (part 11C) of the sheath boundary formed on the edge ring 114 will cause the sheath boundary to bend in a portion (bent portion 11B) of the sheath boundary spanning the edge groove region 117. Variations in sheath thickness and bending of the sheath boundary affect the ion energy and ion directionality of ions impacting the substrate 103 and the surface of the edge ring 114 disposed below it, respectively. Therefore, control of the plasma sheath boundary 11 across the edge recess region 117 allows for adjustment of ion energy and ion directionality at the surface of the substrate edge region 103B, which can be used to improve substrate processing uniformity. Improved control of the plasma sheath boundary 11 can also be used to perform the in-situ plasma cleaning method described herein, targeting surfaces 114A to 114B of the edge ring 114 for processing byproducts from improper cleaning.

[0062] When the edge control electrode 115 is positioned for use with the edge tuning circuit 170 and / or for biasing with the pulse bias scheme 140 (Figures 1A to 1B), its position relative to the substrate 103 can influence or alter the portion of the generated plasma 101 located above or outside the circumferential edge of the substrate 103. In some embodiments, bias generators 196, 197 can be used to control the shape of the sheath boundary 11 on the plasma-facing surface of the substrate support assembly 136. For example, the edge ring 114 typically undergoes plasma-based corrosion due to repeated ion bombardment, thereby reducing its thickness over its lifetime. If the thickness of the plasma sheath layer formed on the edge ring 114 remains constant, the thinning of the edge ring 114 will eventually lead to bending of the plasma sheath boundary, resulting in uneven processing at the substrate edge. Therefore, in some embodiments, one or more characteristics of the pulse voltage (PV) waveform established at the bias electrode 104 and / or the edge control electrode 115 can be adjusted to compensate for height variations of the edge ring 114 over its effective lifetime, so as to maintain a substantially uniform sheath boundary 11 on the edge of the substrate 103.

[0063] In some embodiments, the edge tuning circuit 170, electrically coupled to the edge control electrode 115, can be used to manipulate one or more characteristics of the radio frequency power used to ignite and / or sustain the plasma in the processing region 129A on the edge control electrode 115. For example, in some embodiments, the edge tuning circuit 170 can be used to adjust and / or manipulate one or more of the voltage, current, and / or phase of the radio frequency power used to ignite and / or sustain the plasma 101 in a processing region disposed between the edge control electrode 115 and the chamber cover 123.

[0064] In some embodiments, one or more differences between a second RF waveform 502 established at the edge control electrode 115 and a first RF waveform 501 established at the bias electrode 104 are measured to determine and / or monitor one or more characteristics of the RF power in the processing region for maintaining the plasma 101 on the edge control electrode 115. In some embodiments, the differences in one or more characteristics of the second RF waveform 502 and the first RF waveform 501 can be manipulated using the edge tuning circuit 170 to adjust the plasma density in the region above the circumferential edge of the substrate 103 and / or across the edge recess region 117.

[0065] In some embodiments, the characteristic difference between the second RF waveform 502 and the first RF waveform 501 can be used to preferentially form plasma between the edge ring 114 and the edge of the substrate 103, effectively concentrating the plasma in the edge recess region 117 to remove improper processing byproducts from the surface therein. Therefore, the edge tuning circuit 170 can be advantageously used to control the generation of activated species in the bulk plasma, which enables fine control of the ion and / or radical flux at the edge of the substrate 103 (edge ​​region 103B) relative to the central region 103A of the substrate 103, and / or the plasma concentration in the edge recess region 117.

[0066] The edge control electrode 115 can be biased by using a PV waveform generator 150 different from the PV waveform generator 150 used for biasing the bias electrode 104. In some embodiments, the edge control electrode 115 can be biased by using a PV waveform generator 150, which is further used to bias the bias electrode 104 by shunting a portion of the power to the edge control electrode 115. In one configuration, the first PV waveform generator 150 of the first bias generator 196 is used to bias the bias electrode 104, and the second PV waveform generator 150 of the bias generator 197 is used to bias the edge control electrode 115.

[0067] In some embodiments, a signal detection module 187 communicatively coupled to system controller 126 is used to measure and / or determine one or more characteristics of the generated radio frequency power. The signal detection module 187 is generally used to receive electrical signals from electrical signal traces (not shown) electrically coupled to various components within processing systems 10A and 10B, for example, at node N. The signal detection module 187 may include a plurality of input channels 172, each for receiving electrical signals from a corresponding electrical signal trace and data acquisition module 169. The received electrical signals may include, but are not limited to, one or more characteristics of: RF signals transmitted to support base 107, RF waveforms established at one or both of bias electrodes 104 and edge control electrodes 115, pulse voltage (PV) waveforms established at one or both of bias electrodes 104 and edge control electrodes 115, and clamping voltages transmitted to one or both of bias electrodes 104 and edge control electrodes 115.

[0068] In some embodiments, the data acquisition module 169 is used to generate control signals for automatically controlling one or more characteristics of radio frequency signals, radio frequency waveforms, PV waveforms, and / or clamping voltages during substrate processing. In some embodiments, a desired change in one or more characteristics is communicated to the signal detection module 187 by the system controller 126, and the data acquisition module 169 can be used to implement the desired change.

[0069] Referring to Figures 1A and 1B, the second bias generator 197 includes a clamping network 116 such that the bias applied to the edge control electrode 115 can be similarly used to apply the bias to the bias electrode 104 via the clamping network 116 coupled within the first bias generator 196.

[0070] In some embodiments, the processing chamber 100 further includes a dielectric tube 110 or collar, which at least partially connects to a portion of the substrate support assembly 136, serving as a dielectric barrier between the RF thermal substrate support assembly 136 and the grounding liner 108, and also preventing the substrate support 105 and / or support base 107 from contacting corrosive processing gases or plasmas, cleaning gases or plasmas, or their byproducts. Typically, the dielectric tube 110, insulating plate 111, and grounding plate 112 are external to the liner 108. In some embodiments, a plasma shield 109 is located between the cathode liner 108 and the sidewalls 122 to prevent plasma formation in the volume below the plasma shield 109 between the liner 108 and one or more sidewalls 122.

[0071] Substrate support assembly configuration

[0072] Figure 1C is a close-up view of a portion of the substrate support assembly 136 shown in Figure 1A, and includes a simplified electrical schematic diagram of the electrical characteristics of various structural elements in one or more embodiments of the substrate support assembly 136. The simplified electrical schematic diagram shown in Figure 1C is also applicable to the corresponding structural elements of the substrate support assembly 136 shown in Figure 1B. Here, the substrate support assembly 136 is used as an electrostatic chuck (ESC) and can be either a Coulomb-type ESC or a Johnsen-Rahbek-type ESC. Simplified equivalent circuit models 191 for the Coulomb ESC and the Johnsen-Rahbek ESC are shown in Figures 3D and 3E, respectively, and are described below. Generally, in any ESC configuration of the substrate support assembly 136, the substrate 103 is fixed to the substrate support 105 by providing a potential between the substrate 103 and the bias electrode 104, whereby the potential generates an electrostatic attraction. In one embodiment, the bias electrode 104 is also used to facilitate the pulse voltage (PV) waveform bias scheme described herein.

[0073] The substrate support 105 provides a substrate support surface 105A formed of dielectric material and includes a bias electrode 104 embedded in the dielectric material. The bias electrode 104 is separated from the substrate support surface 105A and the substrate 103 by a first dielectric material layer 105B, and is separated from the support base 107 by a second dielectric material layer 105C.

[0074] In some embodiments, the ESC configuration can be used to secure the substrate 103 to the substrate support 105 in a relatively low-pressure (e.g., ultra-high vacuum) processing environment. In some embodiments, it may be necessary to heat and / or cool the substrate 103 during processing to maintain the substrate at a desired processing temperature. In those embodiments, the substrate support assembly 136 can be used to maintain the substrate 103 at a desired temperature by heating or cooling the substrate support 105, and thus the substrate 103 disposed thereon. Typically, in those embodiments, the substrate support surface 105A is patterned to have protrusions (e.g., bosses) contacting the substrate 103 and recesses that, together with the substrate 103, define a back surface volume 105D. During substrate processing, an inert gas (such as helium) can be delivered to the back surface volume 105D using a gas source 173 fluidly coupled to the substrate support assembly 136 to improve heat transfer between the substrate support surface 105A and the substrate 103 disposed thereon. In some embodiments, the gas source 173 is used to deliver inert gas to the area disposed between the edge ring 114 and the surface of the substrate support assembly 136 disposed below it.

[0075] The bias electrode 104 is electrically coupled to a DC power supply 155 (as shown in Figures 1A to 1B), which provides a potential between the substrate 103 and the bias electrode 104, and thus generates an electrostatic attraction (clamping force) between them. The substrate support assembly 136 can be used as either a Coulomb ESC or a Johnsen-Rahbek ESC, wherein the Johnsen-Rahbek ESC can provide a higher clamping force and use a lower clamping voltage compared to the Coulomb ESC. In the Coulomb ESC, the dielectric material selected for the first dielectric layer 105B typically has a higher resistance than the dielectric material selected for the Johnsen-Rahbek ESC, which results in differences in the simplified functional equivalent circuit models 191 shown in Figures 3D and 3E, respectively.

[0076] In the simplest case, for example, the Coulomb ESC circuit model 191 shown in Figure 3D, the first dielectric layer 105B is formed of a dielectric material assumed to act as an insulator (e.g., having infinite resistance RJR), and the functionally equivalent circuit model 191 therefore includes a static capacitance C1 between the bias electrode 104 and the substrate 103 through the first dielectric layer 105B. In some embodiments of the Coulomb ESC, the dielectric material and thickness TDL1 of the first dielectric layer 105B are selected such that the capacitance C1 is between about 5 nF and about 100 nF, such as between about 7 and about 20 nF. For example, the dielectric layer 105B may be formed of a ceramic material (e.g., alumina (Al2O3) etc.), and the thickness TDL1 may be between about 0.1 mm and about 1 mm, such as between about 0.1 mm and about 0.5 mm, for example, about 0.3 mm.

[0077] In a more complex case, as shown in circuit model 191 of the Johnsen-Rahbek ESC in Figure 3E, circuit model 191 includes a capacitor C1 coupled in parallel with the dielectric material resistor RJR and the gap capacitor CJR. Typically, in the Johnsen-Rahbek ESC, the dielectric material layer 105B is considered "leaky" because it is not a perfect insulator and has some conductivity, for example, the dielectric material can be, for example, doped aluminum nitride (AlN) with a permittivity (ε) of about 9. As with the Coulomb ESC circuit model 191 shown in Figure 3D, there is a static capacitance C1 between the bias electrode 104 and the substrate 103 through the dielectric material layer 105B and the helium-filled back volume 105D. The volume resistivity of the dielectric layer within the Johnsen-Rahbek ESC is less than about 10¹² ohm-cm, or less than about 10¹⁰ ohm-cm, even in the range between 10⁸ ohm-cm and 10¹² ohm-cm, and therefore the dielectric layer 105B can have a dielectric resistance RJR in the range of 10⁶ to 10¹¹ ohms. In model 191 of Figure 3E, the gap capacitance CJR is used to illustrate the back volume 105D containing gas between the substrate 103 and the substrate support surface 105A. The capacitance of the gap capacitance CJR is expected to be slightly larger than that of the capacitance C1.

[0078] Returning to Figure 1C, an electrical schematic diagram of the circuit formed within the substrate support assembly 136 shows a support base dielectric layer capacitor C2, which represents the capacitance of the second dielectric material layer 105C. In some embodiments, a portion of the second dielectric material layer 105C has a thickness greater than the thickness of the first dielectric material layer 105B. In some embodiments, the dielectric material used to form the dielectric layer on either side of the bias electrode is the same material, forming the structure of the substrate support 105. In one example, the thickness of the second dielectric material layer 105C (e.g., Al2O3 or AlN), measured in the direction extending between the support base 107 and the bias electrode 104, is greater than 1 mm, such as having a thickness between about 1.5 mm and about 100 mm. The support base dielectric layer capacitor C2 typically has a capacitance between about 0.5 and about 10 nanofarads (nF).

[0079] As shown in Figure 1C, the electrical schematic diagram of the circuit formed within the substrate support assembly 136 also includes a support base resistor RP, an insulator plate capacitor C3, and a ground plane resistor RG. Since the support base 107 and the ground plane 112 are typically formed of a metallic material, the support base resistor RP and the ground plane resistor RG are quite low, such as less than a few milliohms. The insulator plate capacitor C3 represents the capacitance of the dielectric layer located between the bottom surface of the support base 107 and the top surface of the ground plane 112. In one example, the capacitance of the insulator plate capacitor C3 is between approximately 0.1 and approximately 1 nF.

[0080] Bias and Edge Control Scheme

[0081] Figure 2 is a simplified schematic diagram of the bias and edge control scheme, which can be used with one or both of the processing systems 10A to 10B shown in Figures 1A and 1B. As shown in Figure 2, the RF generator 118 and the PV waveform generator 150 are used to transmit RF waveforms and pulse voltage waveforms to one or more electrodes arranged in the processing volume 129 of the processing chamber 100, respectively. In one embodiment, the RF generator 118 and the PV waveform generator 150 are used to simultaneously transmit RF waveforms and pulse voltage waveforms to one or more electrodes arranged in the substrate support assembly 136.

[0082] As described above, the edge tuning circuit 170 is generally used to control the uniformity of the plasma formed between the chamber cover 123 and the substrate support assembly 136, for example, by controlling the plasma density (i.e., the free electron density in the bulk plasma) on the circumferential edge of the substrate 103. In some embodiments, as shown in Figures 1A and 2, the edge tuning circuit 170 is electrically coupled between the edge control electrode 115 (edge ​​bias electrode) and ground. In other embodiments, as shown by the dashed lines in Figures 1B and 2, the edge tuning circuit 170 is electrically coupled between the edge control electrode 115 and the plasma generator assembly 163, for example, between the edge control electrode 115 and the radio frequency generator 118.

[0083] In some embodiments, the edge tuning circuit 170 serves as a resonant circuit, including an inductor and a capacitor (e.g., an LC circuit), which can be used to adjust the voltage, current, and / or phase for maintaining the radio frequency power of the plasma in the region on the edge control electrode. Examples 170a, 170b, and 170c are shown in Figures 3A through 3C, which can be used as the edge tuning circuit 170 in any of the embodiments described herein. As shown, edge tuning circuits 170a and 170b are each electrically coupled between the power transmission line 158 and ground (i.e., between the edge control electrode 115 and ground). However, it is conceivable that each example edge tuning circuit 170a and 170b may also be electrically coupled between the power transmission line 158 and the plasma generator assembly 163 (i.e., between the edge control electrode 115 and the radio frequency generator 118), as shown in Figure 1B. In some other embodiments, the edge tuning circuit 170 may be electrically coupled simultaneously to the power transmission line 158, the plasma generator assembly 163, and ground, as shown in the example edge tuning circuit 170c in Figure 3C.

[0084] In one embodiment shown in Figure 3A, the edge tuning circuit 170a includes an inductor L2 and a variable capacitor C7 arranged in parallel (i.e., a parallel LC resonant circuit). In another embodiment, as shown in Figure 3B, the edge tuning circuit 170b includes an inductor L2 and a variable capacitor C7 arranged in series (i.e., a series LC resonant circuit). In yet another embodiment, as shown in Figure 3C, the edge tuning circuit 170c includes an inductor L2 and a variable capacitor C8 arranged in series between the edge control electrode 115 and the plasma generator assembly 163 (i.e., between the edge control electrode 115 and the RF generator 118) (i.e., a series LC resonant circuit), and a second variable capacitor C7 coupled to a node arranged within the power transmission line 158 between the inductor L2 and the variable capacitor C8 and ground.

[0085] In some embodiments, one or both of the variable capacitors C7 and C8 can be adjusted from at least about 50 pF to at least about 200 pF, such as from at least about 20 pF to at least about 250 pF.

[0086] The type of LC resonant circuit selected for the edge tuning circuit 170, such as parallel, series or other structures, may depend on the mechanical dimensions of the substrate support assembly 136 and the electrical coupling generated between conductive components or electrodes such as edge ring 114, edge control electrode 115, support base 107, bias electrode 104, substrate 103 and ground plane 112.

[0087] In some embodiments, the type of LC resonant circuit can be selected based on the desired ability to control the plasma density distribution. This ability can be achieved by adjusting one or more parameters of the LC resonant circuit so that one or more characteristics of the second RF waveform 502 (Figures 5A to 5B) established at the edge control electrode 115 can be adjusted relative to one or more characteristics of the first RF waveform 501 established at the bias electrode 104. Simulation results of different control characteristics that can be achieved for the exemplary edge tuning circuit 170 are described in Figures 6A to 6D below.

[0088] Returning to Figure 2, in one non-limiting example, the RF generator 118 and the PV waveform generator 150 are used to transmit the RF waveform and the pulse voltage waveform to the support base 107 and the bias electrode 104, respectively, both of which are arranged in the substrate support assembly 136. In another example, the RF generator 118, the first PV waveform generator 150, and the second PV waveform generator 150 are used to transmit the RF waveform, the first pulse voltage waveform, and the second pulse voltage waveform to the support base 107, the bias electrode 104, and the edge control electrode 115, respectively, all of which are arranged in the substrate support assembly 136.

[0089] As shown in Figure 2, the RF generator 118 is used to transmit an RF signal including a sinusoidal RF waveform (here, RF waveforms 501 and 502 (Figures 5A to 5B)) to one or more electrodes arranged in the cavity 113 via the RF (plasma) generator assembly 160 (which includes an RF matching circuit 162 and a first filter assembly 161), providing a sinusoidal RF waveform (RF signal) to one or more electrodes arranged in the cavity 113. Furthermore, each PV waveform generator 150 is used to establish a PV waveform at the bias electrode 104 via the second filter assembly 151, providing a PV waveform to one or more electrodes arranged in the cavity 113. The PV waveform typically includes a series of voltage pulses (e.g., nanosecond voltage pulses). Components within the clamping network 116 may be positioned between each PV waveform generator 150 and the second filter assembly 151 as appropriate.

[0090] During processing, PV waveforms are provided to bias electrode 104 by PV waveform generator 150 of first bias generator 196, and PV waveforms are provided to edge control electrode 115 by PV waveform generator 150 of second bias generator 197. PV waveforms are provided to a load (e.g., composite load 130 shown in Figures 3D to 3E) disposed within processing chamber 100. PV waveform generators 150 are coupled to bias electrode 104 and edge control electrode 115 via respective power transmission lines 157 and 158. Overall control of the PV waveform transmission from each PV waveform generator 150 is achieved using signals provided from system controller 126.

[0091] In one embodiment, the PV waveform generator 150 is used to output a periodic voltage function at predetermined time intervals, for example, by using a signal from a transistor-transistor logic (TTL) source (not shown). The periodic voltage function generated by the transistor-transistor logic (TTL) source can be a predetermined negative voltage or a two-state DC pulse between a positive voltage and zero. In one embodiment, the PV waveform generator 150 is used to maintain a predetermined, substantially constant negative voltage across its output (i.e., ground) during a predetermined periodic cyclic time interval by repeatedly closing and opening one or more switches at a predetermined rate. In one example, during a first phase of the pulse interval, a first switch is used to connect a high-voltage power supply to a bias electrode 104, and during a second phase of the pulse interval, a second switch is used to connect the bias electrode 104 to ground. In another embodiment, the PV waveform generator 150 is used to maintain a predetermined, substantially constant positive voltage across its output (i.e., ground) during a predetermined periodic cyclic time interval by repeatedly closing and opening its internal switches (not shown) at a predetermined rate.

[0092] In one configuration, during a first phase of the pulse interval, a first switch is used to connect the bias electrode 104 to ground, and during a second phase of the pulse interval, a second switch is used to connect the high-voltage power supply to the bias electrode 104. In an alternative configuration, during the first phase of the pulse interval, the first switch is in an open-circuit state, disconnecting the bias electrode 104 from the high-voltage power supply, and the bias electrode 104 is coupled to ground through an impedance network (e.g., an inductor and resistor connected in series). Subsequently, during the second phase of the pulse interval, the first switch is in a closed state to connect the high-voltage power supply to the bias electrode 104, while the bias electrode 104 maintains coupling to ground through the impedance network.

[0093] The PV waveform generator 150 may include a PV generator and one or more electrical components, such as, but not limited to, a high repetition frequency switch (not shown), a capacitor (not shown), an inductor (not shown), a flyback diode (not shown), a power transistor (not shown), and / or a resistor (not shown), for providing a PV waveform to the output. The actual PV waveform generator 150, which can be used as a nanosecond pulse generator, may include any number of internal components.

[0094] Power transmission line 157 electrically connects the output of the PV waveform generator 150 of the first bias generator 196 to the optional filter assembly 151 and the bias electrode 104. Although the following discussion primarily focuses on the power transmission line 157 of the first bias generator 196, the power transmission line 158 of the second bias generator 197, which couples the PV waveform generator 150 to the bias electrode 104 and the PV waveform generator 150 to the edge control electrode 115, will include the same or similar elements. The electrical conductors within the various portions of the power transmission line 157 may include: (a) a single or multiple coaxial cables, such as a flexible coaxial cable in series with a rigid coaxial cable, (b) insulated high-voltage corona-resistant connecting wires, (c) bare wires, (d) metal rods, (e) electrical connectors, or (f) any combination of the electrical elements in (a) to (e). Optional filter assembly 151 includes one or more electrical components that substantially prevent current generated by the output of RF generator 118 from flowing through power transmission line 157 and damaging PV waveform generator 150. Optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by RF generator 118, thereby suppressing current flowing to PV waveform generator 150.

[0095] In some embodiments, as shown in Figures 1A to 1B, the PV waveform generator 150 of the first bias generator 196 provides a pulse voltage (PV) waveform signal to the bias electrode 104 and ultimately to the composite load 130 (Figures 3D to 3E) via a pulse voltage (PV) waveform (Figure 1C) generated by the blocking capacitor C5, filter assembly 151, power transmission line 157, and capacitor C1. In some embodiments, the plasma control scheme 188 may further include a blocking resistor (not shown) located within an element at the point where the clamping network 116 is connected to the power transmission line 157. The primary function of the blocking capacitor C5 is to protect the PV waveform generator 150 from the DC voltage generated by the DC power supply 155, so that the DC voltage drops across the blocking capacitor C5 without interfering with the output of the PV waveform generator 150. The purpose of the blocking resistor in the clamping network 116 is to block the pulse voltage generated by the PV waveform generator 150, which is sufficient to minimize the current induced in the DC power supply 155.

[0096] Waveform Example

[0097] Figure 4 illustrates an example of a PV waveform 402 established at the substrate 103 due to a PV waveform 401 established at the bias electrode 104. Here, the PV waveform 401 is established at the bias electrode 104 and / or the edge control electrode 115 by using the PV waveform generator 150 in the corresponding bias generators 196 and 197 and the DC voltage source 155 of the corresponding clamping network 116.

[0098] In general, the output of the PV waveform generator 150 can be controlled by the settings in the plasma processing recipe stored in the memory of the controller 126 to form a PV waveform 401, which includes the inter-peak voltage VPP, also known as the pulse voltage level VPP.

[0099] The PV waveform 402 with waveform period TP is the waveform seen by the substrate 103 as the PV waveform 401 is transmitted to the bias electrode 104. It is characterized by including a sheath collapse and charging phase 450 (or, for simplicity, sheath collapse phase 450) extending between points 420 and 421, a sheath formation phase 451 extending between points 421 and 422, and an ion current phase 452 extending between point 422 and the starting point at point 420, returning to the next sequentially established pulse voltage waveform. The sheath collapse phase 450 generally includes a period of sheath capacitance discharge and the substrate potential reaching the local plasma potential level 433.

[0100] Depending on the required plasma processing conditions, it may be necessary to control and set at least the PV waveform characteristics, such as the PV waveform frequency (1 / TP), pulse voltage level VPP, pulse voltage on-time, and / or other parameters of the PV waveform 401, to achieve the desired plasma processing result on the substrate. In one example, the pulse voltage (PV) on-time (defined as the ratio of the ion current period (e.g., the time between point 422 and subsequent point 420 in Figure 4) to the waveform period TP) is greater than 50% or greater than 70%, such as between 80% and 95%. In some embodiments, the PV waveform generator 150 is used to provide a constant voltage during the ion current phase 452, as shown in Figure 4. In some embodiments, the PV waveform generator 150 is used to provide a shaped pulse voltage waveform (not shown) with a non-zero slope during the ion current phase 452 by using one or more internal switches and a DC power supply. In some embodiments, the PV waveform generator 150 is used to provide a constant positive voltage during one phase of the voltage pulse, such as only during the sheath collapse phase 450 (not shown). Generally, the DC offset ΔV found in each PV waveform at the bias electrode depends on the bias applied by the DC power supply 155 in the clamping network 116 and various properties of the configuration of the PV waveform generator 150 used to establish the PV waveform 401.

[0101] In some embodiments, as the ion current (Ii) deposits positive charges on the substrate surface during ion current phase 452, the voltage on the substrate surface will increase over time, as indicated by the positive slope of the line between points 422 and 420. Over time, the increase in substrate surface voltage will reduce the sheath voltage and lead to an expansion of the ion energy distribution. Therefore, it is desirable to at least control and arrange the PV waveform frequency (I / TPD), where TPD is the PV waveform period, to minimize the effects of the sheath voltage reduction and the expansion of the ion energy distribution.

[0102] Figures 5A to 5B illustrate a first RF waveform 501 established at the bias electrode 104 and a second RF waveform 502 established at the edge control electrode 115 due to the capacitive coupling of the RF signal supplied by the RF generator 118 within the plasma generator assembly 163 to the support base 107. The waveform characteristics of the first RF waveform 501 and the second RF waveform 502 are controlled by using an edge tuning circuit 170 configuration, such as one of the configurations shown in Figure 3A (parallel LC resonant circuit), Figure 3B (series resonant circuit), and Figure 3C (more complex resonant circuit). The example waveforms shown in Figures 5A to 5B and the simulation results shown in Figures 6A to 6D below are not intended to limit the scope of the disclosure provided herein, but are intended to simplify the discussion.

[0103] Generally, the radio frequency signal provided to the support base 107 has a relatively high frequency, such that the first radio frequency waveform 501 and the second radio frequency waveform 502 have a corresponding high frequency (1 / TRF) of about 1 MHz or higher, for example, between about 30 MHz and about 60 MHz. The edge tuning circuit 170 as described in the various embodiments disclosed herein can be used to adjust one or more characteristics of the second RF waveform 502 established at the edge control electrode 115 relative to one or more characteristics of the first RF waveform 501 established at the bias electrode 104. In some embodiments, one or more relative characteristics include the RF waveform amplitude ratio (e.g., voltage amplitude ratio VRF2 / VRF1) between the second RF waveform 502 and the first RF waveform 501, the RF current amplitude ratio (e.g., current amplitude ratio not shown) between the second RF waveform 502 and the first RF waveform 501, the phase difference (ΔΦ) between the second RF waveform 502 and the first RF waveform 501, and / or the RF transmission power ratio (e.g., transmission power ratio not shown) between the second RF waveform 502 and the first RF waveform 501.

[0104] One or more characteristics of the second RF waveform 502 relative to the first RF waveform 501 can be determined and / or monitored by measuring the corresponding voltage, current, phase, and / or power of the RF waveforms established at the edge control electrode 115 and the bias electrode 104. The measured characteristics of the second RF waveform 502 and the first RF waveform 501 correspond to the characteristics of the bulk plasma, such as plasma density, in the portions formed above the edge control electrode 115 and the bias electrode 104, respectively. The determined difference between the second RF waveform 502 and the first RF waveform 501 can be used to monitor and control the difference in electron density in the bulk plasma portion formed on the edge ring 114 and the bulk plasma portion formed on the central portion of the substrate 103. The uniformity and / or distribution of the plasma density can be controlled and / or adjusted by using the edge tuning circuit 170 (e.g., by adjusting the variable capacitor C7 using the system controller 126) to achieve the desired processing result.

[0105] Non-limiting simulation results of the edge tuning circuit 170 shown in Figures 3A and 3B are shown in Figures 6A to 6B, and simulation results of the edge tuning circuit 170 with series and parallel combination configurations shown in Figure 3C are shown in Figures 6C to 6D. In Figures 6A and 6C, the simulation results provide examples of LC circuit tuning curves illustrating the effect of changing the capacitance (e.g., by adjusting the variable capacitor C7 in each edge tuning circuit 170 configuration) across a range of approximately 20 pF to approximately 250 pF on the voltage amplitude ratio (e.g., VRF2 / VRF1) between the second RF waveform 502 and the first RF waveform 501. In Figures 6B and 6D, the simulation results provide examples of LC circuit tuning curves illustrating the effect of changing the capacitance C7 on the phase difference (e.g., ΦRF2-ΦRF1) between the second RF waveform 502 and the first RF waveform 501.

[0106] As shown in Figure 6A, the variable capacitor C7 of the edge tuning circuit 170 (configuration in Figure 3A) with a value of approximately 170 pF has a corresponding voltage amplitude ratio (VRF2 / VRF1) of approximately 1.5. As shown in Figure 6B, for the edge tuning circuit 170 with the same configuration as in Figure 6A, the phase difference corresponding to the 170 pF capacitor is relatively small, for example, less than 5 degrees, resulting in an amplification of the second RF waveform 502 relative to the first RF waveform 501 and a small phase difference (ΔΦ) between them, as shown in Figure 6A.

[0107] In Figures 6C to 6D, the variable capacitor C7 of the edge tuning circuit 170 (configuration in Figure 3C) can be set to a value of about 25 pF, and the resulting voltage amplitude ratio (VRF2 / VRF1) is equal to about 0.5 (Figure 6C), and the phase difference (ΔΦ) is about zero, as shown in Figure 6D.

[0108] As shown in Figure 6A, simulation results based on the edge tuning circuit 170 configuration (e.g., parallel LC resonant circuit) of Figure 3A show resonant peak values ​​of approximately 100 pF and 120 pF. In Figure 6D, simulation results of the edge tuning circuit 170 (configuration of Figure 3C) show resonant phase transitions at 60 pF and 250 pF. In some embodiments, it may be necessary to operate the corresponding edge tuning circuit 170 on either side of the resonance during the maintenance of the RF plasma. In some embodiments, the edge tuning circuit 170 may be configured, for example, by combining a variable capacitor with an LC circuit in parallel and in series, to allow the edge tuning circuit 170 to switch between either side of the resonant peak without crossing the resonant region. As stated above, the simulation results shown in Figures 6A through 6D are not intended to be limiting, as other edge tuning circuitry 170 configurations can be used to provide other desired operating ranges for amplifying, reducing, and / or equalizing the voltage amplitude ratio (VRF2 / VRF1) and / or current amplitude ratio and / or phase difference between the second RF waveform 502 and the first RF waveform 501.

[0109] In some embodiments, it may be necessary to select a tuning circuit configuration and / or a variable capacitor C7 that results in a phase difference between the various RF waveforms, thereby amplifying the electric field between the edge control electrode 115 and the bias electrode 104. The amplified electric field causes a corresponding increase in plasma density in the portion of plasma 101 formed on the substrate support assembly 136 at a certain distance between the two electrodes. In some embodiments, it may be necessary to select a tuning circuit configuration and / or a variable capacitor C7 that does not result in a phase difference between the RF waveforms established at the individual electrodes, so that the plasma density remains substantially uniform across the region spanning the edge of the substrate 103.

[0110] Advantageously, the edge tuning circuit 170 can be used to provide a wide range of desired plasma processing conditions to control and / or adjust the plasma density distribution at different points between the center and edge of the substrate 103. By adjusting one or more variable capacitors C7, the characteristics of the edge tuning circuit 170 can be controlled using the system controller 126, thereby controlling the system's position on the tuning curves (Figures 6A to 6D). Controlled adjustment of the edge tuning circuit characteristics by the system controller 126 will allow relatively easy changes to plasma processing conditions within a single substrate plasma process, between consecutive substrate plasma processes, and / or across different types of substrates, without requiring manual changes to hardware-related configurations. In some embodiments, one or both of the bias generators 196, 197, the edge tuning circuit 170, or combinations thereof can be used to preferentially clean the surface of the substrate support assembly 136 in the edge recess region 117 during an in-situ plasma cleaning method, as described below with respect to Figures 7A to 7C and Figures 8A to 8C.

[0111] In some embodiments, the edge tuning circuit 170 is automatically adjusted to maintain desired processing conditions, for example, to account for plasma uniformity shifts caused by changes in the geometry and / or materials of various components of the processing chamber 100 over time. For example, these methods can be used to automatically adjust the tuning circuit, such as by changing the capacitor C7 to account for changes in the thickness of the edge ring 114 due to dielectric material corrosion of the edge ring 114 caused by ion bombardment. For example, in some embodiments, by using the signal detection module 187, the system controller 126 can be used to detect signals of one or more electrical parameters at corresponding nodes N of the processing systems 10A, 10B; determine whether the processing systems 10A, 10B are operating under desired processing conditions by comparing the characteristics of the detected signals with one or more control limits; and adjust one or more components of the edge tuning circuit 170 when the electrical signal characteristics exceed the control limits. Some embodiments include automatic adjustment of edge tuning circuitry, such as adjusting capacitor C7 to maintain the desired RF voltage amplitude ratio, RF current amplitude ratio, and / or RF phase difference between different RF waveforms at edge control electrode 115 and bias electrode 104.

[0112] In some embodiments, the system controller 126 is used to automatically adjust the edge tuning circuit 170 based on the desired processing conditions and / or desired characteristics between the RF waveforms at the edge control electrode 115 and the bias electrode 104 by comparing the processing conditions and / or RF waveforms with predetermined limits, such as controlling limits, and changing one or more set points of the edge tuning circuit 170, such as capacitor C7, based on an algorithm or lookup table stored in the memory 134 of the system controller 126.

[0113] In some embodiments, the edge tuning circuit 170 can be manually adjusted and / or controlled by adjusting one or more components of the edge tuning circuit 170 to a desired setpoint and / or within a desired control limit, wherein the desired setpoint and / or control list is selected by the user and stored in instructions for controlling the processing systems 10A, 10B. For example, the capacitor C7 of the edge tuning circuit 170 can be controlled to a desired capacitance determined by the user and stored in the memory of the system controller 126.

[0114] Generally, the pulse voltage (PV) waveforms established by electrodes 104 and 115, such as negative pulse waveform 401, shaped pulse waveform 441, or positive pulse waveform 431, comprise a periodic pulse voltage (PV) waveform sequence that repeats over a voltage offset (ΔV) with a period TPD. In one example, the period TPD of the PV waveform can be between about 1 and about 5 μs, such as about 2.5 Ms, for example, between about 200 kHz and about 1 MHz, or about 400 kHz, such as about 1 MHz or less, or about 500 kHz or less.

[0115] As described above, in some embodiments, the processing chamber 100 will include at least one or more RF generators 118 and their associated first filter assemblies 161, and one or more PV generators 314 and their associated second filter assemblies 151, which together are used to transmit a desired waveform to one or more electrodes disposed within the substrate support assembly 136. Software instructions stored in the memory of the system controller 126 are used to generate RF waveforms, which are used to establish, maintain, and control one or more states of plasma formed within the processing chamber. The controlled states of plasma may include, but are not limited to, plasma density, plasma chemistry, and ion energy in the plasma formed in the processing volume 129.

[0116] Example of processing method

[0117] Figures 7A to 7C are process flow diagrams illustrating various methods that can be used to clean the surface of the substrate support assembly. Figures 8A to 8C are close-up views of the substrate support assembly 136 used to illustrate the method configurations described in Figures 7A to 7C. In Figures 8A to 8C, multiple portions of the substrate support assembly 136 are configured as shown in Figure 1B, wherein the edge control electrode 115 is disposed in or on the material of the dielectric tube 110 surrounding the substrate support 105. However, it is contemplated that the methods described below can be used with any one or combination of the substrate support assembly configurations described herein, such as the edge control electrode 115 being disposed within the dielectric material of the substrate support 105 (Figures 1A and 1D), or disposed in and / or coupled to the edge ring 114.

[0118] Figure 7A is a process flow diagram illustrating a method 700 for preferentially cleaning the surface of the edge recess region 117 defining the substrate support assembly 136, according to one embodiment. The following description refers to Figures 1A through 1D and Figure 8A to illustrate the form of method 700, but is not intended to be limiting, as it is conceivable that method 700 can be performed on other processing systems used to separately bias the substrate and the edge ring. Generally, method 700 uses in-situ plasma (plasma formed in the processing chamber 100) to remove accumulated processing byproducts from the edge ring 114 and / or portions of the substrate support surface 105A adjacent thereto. Method 700 is used to manipulate the shape of the plasma sheath boundary 11 (Figure 8A) formed on the substrate support assembly 136 by increasing or decreasing the voltage between the edge ring 114 and the plasma relative to the substrate support surface 105A and the plasma 101. The voltage difference results in corresponding differences in ion energy at surfaces 114A to 114C and 105A, and in some embodiments, causes bending in the plasma sheath boundary, which can be advantageously used to preferentially guide plasma-generated ions to desired portions of the substrate support assembly 136. For example, as shown in Figure 8A, the height difference between portion 11A of the sheath boundary 11 formed on the substrate support surface 105A and portion 11C of the sheath boundary 11 formed on the edge ring 114 causes the sheath boundary to bend in the portion crossing the edge recess region 117 (bending portion 11B).

[0119] In activity 702, method 700 includes generating a first plasma in a processing region of a processing chamber, wherein the processing chamber 100 may include any or a combination of the characteristics shown in Figures 1A to 1D. Here, the processing region 129A is defined by a chamber cover 123 and a substrate support assembly 136. Referring now to Figure 8A, when the substrate 103 is disposed on a substrate support surface 105A, the substrate support assembly 136 generally includes a first portion of a dielectric material 105B forming the substrate support surface 105A and an edge ring 114 (shown in dashed lines) surrounding the substrate 103. One or more edge recess surfaces 114A, 114B of the edge ring 114 and the peripheral edge of the first portion of the dielectric material 105B define an edge recess region 117, wherein the edge recess surfaces 114A, 114B are disposed inside the surface 114C facing the chamber cover.

[0120] In some embodiments, the substrate support assembly 136 further includes a bias electrode 104 and an edge control electrode 115. The bias electrode is separated from the substrate support surface 105A by a first portion of a dielectric material 105B, and the edge control electrode 115 is a distance from the center of the bias electrode 104. Generally, the edge control electrode 115 is separated from the bias electrode 104 by the dielectric material of the substrate support assembly 136. The substrate support assembly may include the dielectric material of the substrate support member 105, the dielectric material for forming the dielectric tube 110, the dielectric material of the edge ring 114 when the edge control electrode 115 is embedded therein, or a combination thereof. Here, the bias electrode 104 is electrically coupled to a first bias generator 196, which is used to establish a first pulse voltage (PV) waveform at the bias electrode 104. The edge control electrode 115 is electrically coupled to the second bias generator 197, which is used to establish a second pulse voltage (PV) waveform at the edge control electrode 115.

[0121] In some embodiments, the first plasma generated at activity 702 is a capacitively coupled plasma (CCP) generated by a radio frequency (RF) waveform generator 163 using a radio frequency (RF) signal electrically coupled to a substrate support assembly 136, such as electrically coupled to a support base 107, wherein the chamber cover 123 is electrically coupled to ground (as shown) or a second RF generator. In other embodiments (not shown), the first plasma may be a CCP formed using an RF generator electrically coupled to the chamber cover 123, wherein the substrate support assembly 136 is electrically coupled to ground. In other embodiments, the first plasma may be an inductively coupled plasma (ICP) formed using an RF generator electrically coupled to one or more ICP coils (not shown) disposed on the chamber cover 123.

[0122] In some embodiments, the radio frequency signal used to generate the first plasma has a frequency greater than 400 kHz, such as a frequency of about 1 MHz or higher, or a frequency of about 2 MHz or higher, such as about 13.56 MHz or higher, about 27 MHz or higher, about 40 MHz or higher, or for example between about 30 MHz and about 200 MHz, such as between about 30 MHz and about 160 MHz, between about 30 MHz and about 120 MHz, or between about 30 MHz and about 60 MHz.

[0123] In activity 704, the method includes exposing the edge ring 114 and the substrate support surface 105A to a first plasma. In some embodiments, the first plasma is formed of an oxygen-containing gas, a hydrogen-containing gas, a halogen-containing gas (such as fluorine and / or chlorine-based gases), or a combination thereof. In some embodiments, free radical species generated in the plasma react with processing byproducts accumulated on surfaces (such as surfaces 114A to 114C of the edge ring 114) within the processing volume 129. The reaction forms volatile substances, which are discharged from the processing volume 129 through a vacuum outlet 120. In some embodiments, the first time period of the radio frequency plasma may be about 1 second or longer, such as about 5 seconds or longer, or about 10 seconds or longer.

[0124] In activity 706 of method 700, the plasma sheath boundary of the first plasma in the edge groove region is adjusted by tuning the variable capacitors C7 and / or C8 in the edge tuning circuit 170, and / or by establishing a pulse voltage (PV) waveform at the edge control electrode 115 to provide a greater voltage between the bulk plasma and the edge ring 114 than between the bulk plasma and the substrate support surface 105A.

[0125] In some embodiments, the second pulse voltage (PV) waveform established at the edge control electrode during activity 706 comprises a series of repetitive cycles, wherein the voltage waveform within each cycle has a first portion occurring during a first time interval (e.g., sheath collapse phase 452) and a second portion occurring during a second time interval (e.g., sheath formation phase 451 and ion current phase 452). Generally, the voltage during the first interval differs from the voltage during the second interval, and the voltage difference determines the energy of the ions that accelerate across the sheath and reach the edge ring 114.

[0126] In some embodiments, the voltage established at the bias electrode by the first pulse voltage (PV) waveform generator 150, here the bias voltage, is effectively maintained at zero volt VPP (e.g., about 0 volts + / - 1 volt (zero volts)) during at least a plurality of repetition cycles of the second PV waveform established at the edge control electrode 115 by activity 704. For example, in some embodiments, the second PV waveform can be established at the edge control electrode 115 at a non-zero VPP, and the pulse voltage VPP established at the bias electrode using the first PV waveform generator can be effectively maintained at zero volts (e.g., about 0 volts + / - 1 volt (zero volts)) for about 1 second or longer, such as about 5 seconds or longer, or about 10 seconds or longer. In some embodiments, the bias electrode 104 is coupled to ground during the first time period by using a switch coupled between the power transmission line 157 and ground. In another embodiment, the PV waveform generator 150 or another driver (not shown) can be used to drive the bias voltage to zero voltage.

[0127] In some embodiments, as shown in Figure 8A, activities 702, 704, and 706 (shown in dashed lines) are performed without the substrate 103 so that the substrate support surface 105A is exposed to the first plasma. Advantageously, the potential difference between the plasma portion formed on the substrate support surface 105A and the plasma portion formed on the edge ring 114 causes the plasma sheath boundary 11 to bend at a portion 11B. The shape of the plasma sheath boundary shown in Figure 8A is used to preferentially guide plasma-generated ions based on the bent portions 11B formed toward the edge groove surfaces 114A to 114B. By guiding plasma-generated ions toward the edge groove surfaces 114A to 114B and simultaneously reducing the voltage in the plasma and the substrate support surface 105A, method 700 can be used to preferentially clean the surface of the edge ring 114 while significantly reducing undue plasma-based corrosion of the substrate support 105.

[0128] In some embodiments, method 700 may include, as appropriate, treating substrate 103 with a second plasma formed before or after the preferred cleaning process described in activities 702 to 706. For example, method 700 may include, as appropriate, positioning substrate 103 on substrate support surface 105A in activity 708, generating the second plasma in processing region 129A in activity 710, exposing substrate 103 to the second plasma for a second time period in activity 712, and establishing a first pulse voltage (PV) waveform at bias electrode 104 in activity 714. In some embodiments, the substrate 103 used for performing optional activities 708 to 714 of method 700 is a non-production substrate, i.e., a substrate of the type used for performing cleaning, testing, and / or maintenance operations, commonly referred to as a "blanket" or "dummy" wafer.

[0129] In some embodiments, activity 708 of method 700 further includes electrostatically clamping substrate 103 to substrate support 105 by transmitting a clamping voltage from DC power supply 155 to bias electrode 104, wherein the DC power supply is electrically coupled to bias electrode 104 via power transmission line 157. The clamping voltage is used to generate a voltage potential difference between substrate 103 and bias electrode 104, and thus generate electrostatic attraction (clamping force) through capacitance C1 (Figure 1C) of a first portion of dielectric material disposed therebetween. In some embodiments, method 700 further includes electrostatically clamping edge ring 114 to substrate support assembly 136 by transmitting a clamping voltage from DC power supply 155 to edge control electrode 115, wherein the DC power supply is electrically coupled to edge control electrode 115 via power transmission line 158. In some embodiments, method 700 includes flowing an inert gas (e.g., helium) into a back volume 105D (Figure 1D), the back volume being disposed between the substrate 103 and the substrate support surface 105A and / or between the edge ring 114 and the surface of the substrate support assembly 136, to facilitate heat transfer between them.

[0130] In some embodiments, activity 714 of method 700 further includes adjusting one or more characteristics of a second pulse voltage (PV) waveform relative to one or more characteristics of a first pulse voltage (PV) waveform to control the shape of the plasma sheath boundary 11 formed on the substrate 103 and the edge ring 114 during a second time period. Therefore, in some embodiments, activity 714 includes adjusting one or more characteristics of a first PV waveform established at the bias electrode 104 relative to one or more characteristics of a second PV waveform established at the edge control electrode 115. In some embodiments, adjusting one or more characteristics includes adjusting one or a combination of the PV waveform frequency (1 / TP), pulse voltage level VPP, and pulse voltage on-time of the first and / or second PV waveforms established at the bias electrode 104 and the edge control electrode 115, respectively. In some embodiments, one or more characteristics can be controlled to bend the plasma sheath at the edge of the substrate or the edge of the substrate support 105, increase or decrease the sheath height on the edge control electrode 115 relative to the sheath height on the bias electrode 104, so as to allow fine-tuning of the ion trajectory and ion energy in the edge region of the substrate 103 or the substrate support 105.

[0131] Figure 7B is a process flow diagram illustrating a method 720 for preferentially cleaning the surface of the edge recess region 117 defining the substrate support assembly 136, according to one embodiment. The state of method 720 is shown in Figure 8B. However, it is contemplated that method 720 can be performed using any processing system configuration described in Figures 1A through 1D. In some embodiments, substrate 103 is a non-production substrate, i.e., a substrate of the type used for performing cleaning, testing, and / or maintenance operations, commonly referred to as a "blanket" or "dummy" wafer. In other embodiments, method 720 may be performed during plasma processing of a production substrate having at least partially formed semiconductor elements thereon, for example, to remove processing byproduct residues from the bevel or back edge of the production substrate.

[0132] Here, method 720 generally includes preferentially cleaning the surface defining the edge recess region 117 by adjusting the characteristics of the respective pulse voltage (PV) waveforms established at the bias electrode 104 and the edge control electrode 115. During the cleaning process, substrate 103 remains on substrate support surface 105A, thus the substrate 103 is disposed between substrate support surface 105A and plasma. Substrate 103 provides a cap to prevent ion bombardment and corrosion of substrate support surface 105A. In some embodiments, substrate 103 is at least partially lifted from substrate support surface 105A to allow plasma and / or free radical species formed in the plasma to more easily diffuse into the edge recess region 117 and react with processing byproducts (e.g., carbon-containing polymers) formed on the surface therein. It is contemplated that at least some activities of method 720 may be the same as or substantially similar to the corresponding activities of method 700 described above.

[0133] Method 720 generally includes positioning substrate 103 on substrate support assembly 136 in activity 722, generating plasma in activity 724 so that substrate 103 and edge ring 114 (as applicable) are exposed to plasma for a first time period in activity 726, and adjusting plasma sheath boundary in activity 728 by biasing one or both of substrate 103 and edge ring 114, as applicable.

[0134] The step of positioning the substrate 103 at activity 722 generally includes transferring the substrate 103 to the substrate support surface 105A. In some embodiments, as described in activity 708 of method 700, the substrate is electrically clamped to the substrate support assembly. Plasma may be generated at activity 724 using a radio frequency signal, as described above at activities 702 and / or 710 of method 700.

[0135] In some embodiments, the substrate 103 is exposed to plasma for a first time period at activity 728 as appropriate, and the substrate 103 and edge ring 114 are biased as appropriate, for example, by using first and second pulse voltage waveform generators to establish PV waveforms at the bias and edge control electrodes, as described in activities 712 and 714 of method 700.

[0136] In activity 730, method 720 includes at least partially lifting the substrate 103 from the substrate support surface 105A, as shown in Figure 8B. Typically, a plurality of lifting pins 20 extending through the substrate support assembly 136 are used to at least partially lift the substrate 103 from the substrate support surface 105A. When the substrate is electrostatically clamped to the substrate support 105, the step of at least partially lifting the substrate 103, as described in activity 708, may include stopping or adjusting the delivery of the clamping voltage to the bias electrode 104 and / or discharging the electrostatic charge between the substrate 103 and the bias electrode 104, for example, by setting the DC voltage potential of the bias electrode 104 to be similar to the DC voltage potential of the substrate 103.

[0137] In activities 732 and 734, method 720 includes exposing the edge recess surfaces 114A to 114B to plasma while adjusting the plasma sheath boundary 11. Activities 732 and 734 can be performed using processes substantially similar to activities 704 and 706 of method 700, wherein a partially raised substrate 103 disposed on the substrate support surface 105A is added. It is conceivable that any one or more activities of method 720 can be used in conjunction with method 740, or vice versa, to improve the efficiency of in-situ plasma cleaning in the edge recess region 117 while protecting the substrate support surface 105A from improper plasma-based corrosion.

[0138] Figure 7C is a process flow diagram illustrating a method 740 for preferentially cleaning edge recess surfaces 114A to 114B of a substrate support assembly 136 according to another embodiment. It is conceivable that any of the processing systems described herein, such as any of the substrate support assemblies 136 in Figures 1A to 1D and 8A to 8C, can be used to perform method 740. As shown in Figure 8C, method 740 generally includes using tuning circuitry 170 to concentrate plasma between the peripheral edge of the substrate 103, which is at least partially raised from the substrate support surface 105A, and the edge recess surfaces 114A to 114B (e.g., edge recess region 117). The concentrated plasma increases the concentration of free radicals and ions in the edge recess region 117, which can be used to preferentially clean surfaces 114A to 114B therein. Typically, only a portion of the substrate 103 is raised to a sufficiently small distance to prevent plasma formation between the substrate 103 and the substrate support surface 105A, thereby preventing plasma-based corrosion. In some embodiments, substrate 103 is a non-production substrate commonly referred to as a "blanket" or "dummy" wafer. In other embodiments, method 740 may be performed during plasma processing of a production substrate having at least partially formed semiconductor elements thereon, for example, to remove processing byproduct residues from the bevel or back edge of the production substrate.

[0139] Activity 742 of method 740 includes positioning the substrate 103 on the substrate support surface 105A of the substrate support assembly 136, as shown in Figure 8C. Activity 742 may be the same as or substantially similar to activity 722 of method 720.

[0140] Activity 744 of method 740 includes igniting and sustaining plasma using a radio frequency (RF) signal. In some embodiments, an RF signal is transmitted to a support base 107 of the substrate support assembly 136 using a plasma generator assembly 163 electrically coupled to the substrate support assembly 136. Here, the RF signal is used to ignite and / or sustain the processing plasma 101 in a processing region 129A of the processing chamber 100, wherein the processing region 129A is disposed between the substrate support assembly 136 and the chamber cover 123. In some embodiments, the RF signal has a frequency of about 1 MHz or higher, such as about 20 MHz or higher, for example between about 30 MHz and about 60 MHz, or about 40 MHz.

[0141] Typically, the radio frequency signal transmitted to the support base 107 establishes a first radio frequency waveform 501 (Figures 6A to 6B) at the bias electrode 104, which is capacitively coupled to the support base 107 via a third portion of dielectric material (e.g., dielectric material layer 105C) disposed therebetween. The bias electrode 104 is separated from the processing plasma by a first portion of dielectric material (e.g., dielectric material layer 105B) and the substrate 103 disposed on the substrate support surface 105A. In some embodiments, method 740 further includes electrostatically clamping the substrate 103 to the substrate support 105, as described in activity 708 of method 700.

[0142] In activity 746, method 740 includes exposing the surface of substrate 103 to plasma for a first time period. Activity 748 of method 740 may include adjusting one or both of the plasma density and / or shape of the plasma sheath boundary 11. In some embodiments, the step of adjusting the plasma density includes adjusting one or more characteristics of a second RF waveform 502 established at edge control electrode 115 relative to one or more characteristics of a first RF waveform 501 established at bias electrode 104. In some embodiments, the step of adjusting one or more characteristics of the second RF waveform 502 relative to one or more characteristics of the first RF waveform 501 includes changing the voltage amplitude ratio (e.g., VRF2 / VRF1) between the second RF waveform 502 and the first RF waveform 501, as shown in Figure 5A or Figure 5B, adjusting the current amplitude ratio between the second RF waveform 502 and the first RF waveform, adjusting the phase difference between the second RF waveform 502 and the first RF waveform 501, such as ΔΦ, or a combination thereof. In some embodiments, one or more characteristics of the second RF waveform 502 relative to the first RF waveform 501 are adjusted by adjusting the electrical characteristics of one or more elements within the edge tuning circuit 170.

[0143] In some embodiments, adjusting the second RF waveform 502 relative to the first RF waveform 501 alters the plasma uniformity of at least a portion of the processing region 129A (Figures 1A to 1B). For example, in one embodiment, the processing region 129A is defined by a chamber cover 123 and a substrate support assembly 136, and the plasma 101 is a bulk plasma formed between the two. In some embodiments, a first portion of the plasma 101 is formed in a region disposed between the chamber cover 123 and a bias electrode 104, and a second portion of the plasma 101 is formed in a region between the chamber cover 123 and an edge control electrode 115. In other embodiments, adjusting the second RF waveform 502 relative to the first RF waveform 501 alters the plasma density in the second portion of the plasma 101 relative to the plasma density in the first portion of the plasma 101.

[0144] In some embodiments, adjusting one or more characteristics of a second RF waveform 502 established at the edge control electrode 115 relative to one or more characteristics of a first RF waveform 501 established at the bias electrode 104 includes using an edge tuning circuit 170. In some embodiments, the edge tuning circuit 170 includes one or more variable capacitors C7, C8, and adjusting one or more characteristics of the second RF waveform 502 relative to one or more characteristics of the first RF waveform 501 includes changing one or more capacitors C7, C8. The adjustment of the edge tuning circuit 170 can be performed automatically, such that the system controller 126 adjusts the electrical characteristics of one or more components of the edge tuning circuit 170, such as capacitors C7, C8, based on the desired characteristics of the RF waveforms 501, 502 and / or the desired difference between them.

[0145] For example, in some embodiments, by using the signal detection module 187, the system controller 126 can: determine the characteristics of each waveform by measuring one or more characteristics of electrical signals acquired at one or more nodes N; compare the determined characteristics with desired characteristics; and change the output of the components of the edge tuning circuit 170 based on the comparison. In some embodiments, the edge tuning circuit 170 can be manually adjusted, wherein the user changes the setpoint of the components of the edge tuning circuit 170, such as the capacitance of variable capacitors C7, C8 or the inductance L of the circuit. The user can change the setpoint using the system controller 126 and / or the signal detection module 187, for example, by changing the recipe parameters corresponding to the components or another arrangement in the instructions of the system controller 126 for operating the processing systems 10A, 10B.

[0146] Generally, assuming a relatively constant RF power is supplied from the plasma generator assembly 163 to the support base 107, an increase in the VRF2 / VRF1 ratio achieved by using the edge tuning circuit 170 will result in an increase in the ratio of plasma density near the substrate edge to plasma density near the substrate center. This relative increase in plasma density provides a corresponding increase in the number of plasma-generating species in the bulk plasma, thereby resulting in a relative increase in ion flux and reactive neutral molecule concentration at the edge of the underlying substrate surface. Similarly, a decrease in the VRF2 / VRF1 ratio will result in a decrease in the ratio of plasma density near the substrate edge to plasma density near the substrate center, thereby resulting in a corresponding decrease in ion flux and reactive neutral molecule concentration at the substrate edge.

[0147] By controlling the relative plasma density between the first and second portions of the plasma, the corresponding distribution of the activated material within the processing region 129A can also be controlled and utilized to improve overall processing non-uniformity, such as wafer processing non-uniformity. Advantageously, activity 748 can be implemented as adjustment of processing parameters, such as adjusting capacitors C7 and / or C8 by controlling the edge tuning circuit 170 using system controller 126. Thus, method 740 can be implemented without resorting to mechanical adjustments or hardware configuration changes, which are typically required to adjust the bulk plasma distribution in a capacitively coupled plasma (CCP) system, thereby preventing fine control over it.

[0148] Activity 750 of method 700 may include biasing substrate 103 and / or edge ring 114 by establishing a pulse voltage (PV) waveform at one or both of bias electrode 104 and edge control electrode 115. The process for biasing substrate 103 and / or edge ring 114 during a first time period may be the same as or substantially similar to the process described in activity 714 of method 700.

[0149] Activity 752 of method 740 includes at least partially lifting the substrate from the substrate support surface 105A, which can be performed using the same or substantially similar process described in activity 830 of method 720. In activity 754, method 740 includes exposing the edge recessed surfaces 114A to 114B to plasma for a period of time.

[0150] Before or during activities 752 and 754, activity 756 of method 740 includes adjusting one or more characteristics of the radio frequency (RF) waveforms established at the bias electrode 104 and the edge control electrode 115, respectively, to form plasma in the edge recess region 117 for at least a portion of the plasma duration. In some embodiments, adjusting one or more characteristics of the RF waveforms includes adjusting the phase difference, for example, ΔΦ, between the second RF waveform 502 and the first RF waveform 501 to form plasma between the peripheral edge of the substrate 103 and the edge recess surfaces 114A to 114B. Here, the substrate is at least partially raised to provide sufficient gap or space between the substrate and the edge recess surfaces 114A to 114B to allow plasma to form therebetween, while maintaining a sufficiently small gap between the substrate and the substrate support surface 105A to prevent plasma from forming therebetween. In some embodiments, the bias established at the bias electrode 104 and the edge control electrode 115, respectively, using a waveform generator 150 electrically coupled thereto, remains constant or zero for at least a portion of the duration. For example, in some embodiments, the bias voltage established at one or both of the bias electrode 104 and the edge control electrode 115 is maintained at at least a portion of an effective zero-volt VPP (e.g., about 0 volts + / - 1 volt (zero volts)) duration, such as about 1 second or longer, about 5 seconds or longer, or about 10 seconds or longer. Maintaining the bias voltage at an effective zero-volt VPP may include coupling the respective electrodes to ground, or driving the bias voltage to zero volts using a PV waveform generator 150 or another driver (not shown), as described in Figure 7A with respect to method 700.

[0151] In some embodiments, method 740 further includes preferentially adjusting the plasma density of the portion of plasma 101 formed on the edge control electrode 115 relative to the plasma density of the plasma portion formed on the bias electrode 104. Here, the step of preferentially adjusting the plasma density includes changing the voltage amplitude ratio (e.g., VRF2 / VRF1) between the second RF waveform 502 and the first RF waveform 501, as shown in Figure 6A or Figure 6B, adjusting the current amplitude ratio between the second RF waveform 502 and the first RF waveform, adjusting the phase difference between the second RF waveform 502 and the first RF waveform 501, such as ΔΦ, or a combination thereof.

[0152] The above embodiments can be used alone or in combination to provide fine control over the generation and distribution of activated material within the processing area of ​​an inductively coupled plasma (ICP) chamber or a capacitively coupled plasma (CCP) chamber. Advantageously, the embodiments can be executed using a system controller without adjusting or modifying individual chamber elements, thereby providing processing formulation parameters that can be easily adjusted during the processing of a single substrate and / or between substrates being processed continuously. The radio frequency plasma density control method can be implemented independently and / or combined with a pulsed voltage (PV) waveform biasing method to provide more precise control over ion energy, IEDF, ion orientation, ion flux, and reactive neutral molecule concentration on the substrate surface compared to conventional radio frequency biased CCP systems.

[0153] Although the foregoing content relates to embodiments of the present disclosure, other and further embodiments of the present invention may be designed without departing from the basic scope of the present invention, and their scope is determined by the following claims. [Simplified Explanation of the Diagram]

[0014] To gain a more detailed understanding of the above-described features of this disclosure, reference can be made to the embodiments for a more specific description of the disclosure briefly outlined above, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only exemplary embodiments and should not be construed as limiting their scope, as they may allow for other equally effective embodiments.

[0015] Figures 1A to 1B are schematic cross-sectional views of an example processing system according to one or more embodiments, used to implement the method described herein.

[0016] Figures 1C to 1D are close-up schematic cross-sectional views of the substrate support assembly portion shown in Figure 1A according to one embodiment.

[0017] Figure 2 is a simplified schematic diagram of a bias and edge control scheme according to one or more embodiments that can be used with one or two processing systems shown in Figures 1A to 1B.

[0018] Figures 3A to 3C schematically illustrate an example edge-tuning circuit according to one or more embodiments that can be used with one or both processing systems shown in Figures 1A to 1B.

[0019] Figures 3D and 3E are functional equivalent circuit diagrams of different electrostatic chuck (ESC) types, which can be used with one or two processing systems shown in Figures 1A to 1B.

[0020] Figure 4 illustrates an example of a pulse voltage (PV) waveform that can be established using the embodiments described herein.

[0021] Figures 5A to 5B illustrate examples of radio frequency (RF) waveforms that can be established using the embodiments described herein.

[0022] Figures 6A to 6D are simulation results using the example edge-tuning circuit configuration according to the embodiments of this article.

[0023] Figures 7A to 7C are diagrams illustrating methods that can be performed using the embodiments described herein.

[0024] Figures 8A to 8C are schematic cross-sectional views of the edge portion of the substrate support assembly according to embodiments of the present invention, illustrating the state of the method described in Figures 7A to 7C. [Biomaterial Storage]

[0155] Domestic storage information (please note in order of storage institution, date, and number) None International storage information (please note in order of storage country, institution, date, and number) None

Claims

1. A plasma processing method comprising the following steps: Step (a): generating a plasma in a processing area defined by a chamber cover and a substrate support assembly, the substrate support assembly comprising: a first portion of a dielectric material forming a substrate support surface; an edge ring surrounding the substrate support surface, the edge ring including a surface facing the plasma and one or more edge groove surfaces disposed inwardly from the surface facing the plasma; a bias electrode spaced from the substrate support surface by the first portion of the dielectric material; and an edge control electrode disposed at a distance from a center of the bias electrode, wherein: The bias electrode is electrically coupled to a first bias generator, which is used to establish a first pulse voltage (PV) waveform at the bias electrode; the edge control electrode is electrically coupled to a second bias generator, which is used to establish a second PV waveform at the edge control electrode. Step (b): Expose the edge ring and the substrate support surface exposed due to the lack of a substrate to the plasma; and Step (c): Simultaneously with Step (b), establish the second PV waveform at the edge control electrode.

2. The method of claim 1, wherein the first bias generator does not establish the first PV waveform at the bias electrode while the edge ring and the substrate support surface are exposed to at least a portion of the plasma.

3. The method as described in claim 1, wherein a frequency of the first PV waveform and the second PV waveform is about 1 MHz or lower.

4. The method as described in claim 1, wherein: The second PV waveform comprises a series of repetitive cycles, each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval, and a voltage during the second time interval being lower than a voltage during at least a portion of the first time interval.

5. The method of claim 4, wherein a voltage established at the bias electrode is maintained at about 0 + / - 1 volt (V) by electrically coupling the bias electrode to ground.

6. The method of claim 4, wherein by controlling the first bias generator, a voltage established at the bias electrode is maintained at about 0 + / - 1 volt (V).

7. The method of claim 4 further comprises the following step: Step (d): Adjusting one or more characteristics of the second PV waveform relative to one or more characteristics of the first PV waveform to control a shape of a plasma sheath boundary formed on the substrate support surface and above the edge ring.

8. The method as described in request item 7, wherein: The shape of the plasma sheath boundary is determined at least in part by a difference in the frequency, duration, and / or amplitude of the voltage pulse between the first PV waveform and the second PV waveform.

9. The method as described in request item 8, wherein: The plasma is generated using an RF signal from a radio frequency (RF) generator having a frequency of about 1 MHz or higher, and the RF generator is electrically coupled to: the chamber cover or a support base on which a substrate support is disposed, wherein the RF generator is used to transmit the RF signal to ignite and sustain the plasma; or a plasma generator assembly for generating an electromagnetic field for igniting and sustaining the plasma.

10. The method of claim 9, wherein step (d) of adjusting one or more characteristics of the second PV waveform relative to one or more characteristics of the first PV waveform causes a bend in a plasma sheath boundary to preferentially direct plasma-generated ions to an edge recess region of the substrate support assembly.

11. A plasma processing method comprising the following steps: Step (a): igniting and maintaining a plasma in a processing area of ​​a processing chamber, the plasma comprising a first portion disposed between a substrate support surface of a substrate support assembly and a chamber cover, and a second portion disposed between an edge ring and the chamber cover, the substrate support assembly comprising: a first portion of dielectric material forming the substrate support surface; a bias electrode spaced from the substrate support surface by the first portion of dielectric material, wherein the bias electrode is electrically coupled to a first pulse voltage (PV) waveform generator for establishing a first PV waveform at the bias electrode; an edge control electrode disposed at a distance from a center of the bias electrode, wherein the edge control electrode is electrically coupled to a second PV waveform generator; and an edge ring surrounding the substrate support surface, the edge ring comprising one or more edge groove surfaces defining an edge groove region, wherein a substrate at least partially raised is disposed above the substrate support surface; Step (b): Using the second PV waveform generator, a second PV waveform is established at the edge control electrode; and step (c): The at least partially raised substrate is exposed to the plasma.

12. The method as described in request item 11, wherein: The second PV waveform established at the edge control electrode comprises a series of repetitive cycles, each cycle having a first portion occurring during a first time interval and a second portion occurring during a second time interval, and a voltage during the second time interval being lower than a voltage during at least a portion of the first time interval.

13. The method of claim 12, wherein a voltage established at the bias electrode using the first PV waveform generator is maintained between about -1 volt (V) and about 1 volt for at least a portion of a time period during which the partially elevated substrate is exposed to the plasma.

14. The method of claim 12, wherein when the partially raised substrate is exposed to the plasma, the first PV waveform generator does not establish the first PV waveform at the bias electrode for at least a portion of a time period.

15. The method of claim 12, wherein the repetition periods of the second PV waveform have a frequency of about 1 MHz or less.

16. The method of claim 12 further comprises the following step: Step (d): adjusting one or more characteristics of the first PV waveform, the second PV waveform, or both, to change a shape of a plasma sheath layer formed over a substrate support.

17. The method of claim 16, wherein step (e) comprises increasing the frequency, duration and / or amplitude of the voltage pulse in the second PV waveform.

18. The method as described in request item 17, wherein: The plasma is ignited and sustained using an RF signal from a radio frequency (RF) generator, and the RF signal has a frequency of about 1 MHz or higher.

19. The method as described in request item 18, wherein: The substrate support assembly further includes a support base and a second portion of dielectric material disposed above the support base. The RF generator is electrically coupled to the support base, and the bias electrode is separated from the support base by the second portion of the dielectric material.

20. The method of claim 19, wherein changing the shape of the plasma sheath at step (d) causes a bend in a plasma sheath boundary, thereby preferentially directing plasma-generated ions to the surface of the edge recess region.

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