Method for manufacturing semiconductor structure

Abstract

A method for manufacturing a semiconductor structure is provided. The method includes the following steps: providing a substrate and a dielectric layer on the substrate; forming holes in the dielectric layer; forming an initial barrier material layer and a conductive layer on the upper surface of the dielectric layer and in the holes; removing portions of the initial barrier material layer and the conductive layer to form a barrier material layer and a via element in the holes, respectively, and exposing the upper surface of the dielectric layer, wherein the upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a three-dimensional semiconductor structure. Prior Art

[0002] Three-dimensional integrated circuits (3DICs) are a key technology in advanced semiconductor manufacturing processes, enabling smaller packages and increased functionality. 3DICs use bonding technology to stack multiple semiconductor components. This technique effectively utilizes space and increases the number of components that can be accommodated per unit area. However, the development of 3DICs still faces many challenges, among which reducing bonding failure is particularly important.

[0003] Therefore, there is a need to provide an improved method for manufacturing a semiconductor structure, which can effectively improve the bonding quality and reduce the occurrence of bonding failures. Summary of the Invention

[0004] According to one embodiment, a method for fabricating a semiconductor structure is provided. The method includes the following steps: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming a pre-barrier material layer and a conductive layer on the upper surface of the dielectric layer and in the hole; and removing portions of the pre-barrier material layer and the conductive layer to form a barrier material layer and a via element, respectively, in the hole, exposing the upper surface of the dielectric layer, wherein the upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.

[0005] According to one embodiment, a method for fabricating a semiconductor structure is provided. The method includes forming a first semiconductor element. The step of forming the first semiconductor element includes providing a first substrate, a first dielectric layer on the first substrate, a first barrier material layer on the first dielectric layer, and a first via element on the first barrier material layer, wherein the upper surface of the first barrier material layer is higher than the upper surface of the first dielectric layer. The method also includes forming a second semiconductor element. The step of forming the second semiconductor element includes providing a second substrate, a second dielectric layer on the second substrate, a second barrier material layer on the second dielectric layer, and a second via element on the second barrier material layer, wherein the upper surface of the second barrier material layer is higher than the upper surface of the second dielectric layer. The method includes bonding the upper surface of the first dielectric layer of the first semiconductor element to the upper surfaces of the two dielectric layers of the second semiconductor element.

[0006] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. Simple diagram description

[0007] Figures 1-5 are exemplary diagrams illustrating a method for manufacturing a semiconductor structure according to one embodiment of the present invention; and 6-8 exemplarily illustrate a method for manufacturing a semiconductor structure according to an embodiment of the present invention. Implementation Method

[0008] The following examples, along with accompanying figures, provide a detailed description of the method for fabricating a semiconductor structure disclosed herein. However, the present disclosure is not limited thereto. The descriptions in the examples, such as the detailed structures, fabrication method steps, and material applications, are provided for illustrative purposes only, and the scope of protection of the present disclosure is not limited to the described aspects.

[0009] At the same time, it should be noted that this disclosure does not represent all possible embodiments. Those skilled in the relevant art may, without departing from the spirit and scope of this disclosure, vary and modify the structures and manufacturing methods of the embodiments to meet the needs of actual applications. Therefore, other embodiments not set forth in this disclosure may also be applicable. Furthermore, the figures are simplified to facilitate the clear description of the embodiments, and the dimensional ratios in the figures are not drawn to scale according to the actual products. Therefore, the description and figures are intended only to describe the embodiments and are not intended to limit the scope of protection of this disclosure. Identical or similar reference numerals are used to represent identical or similar elements.

[0010] 1-5 exemplarily illustrate a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0011] Please refer to Figure 1. A substrate 101, a device layer 102, and a dielectric layer 103 are provided. The device layer 102 and the dielectric layer 103 are on the upper surface 101U of the substrate 101. The device layer 102 is interposed between the dielectric layer 103 and the substrate 101. The substrate 101 may be a semiconductor substrate, such as a silicon (Si) substrate, or a silicon-on-insulator (SOI) substrate. In one embodiment, the substrate 101 may include a multilayer structure. The device layer 102 may include at least one semiconductor device, such as a transistor, a capacitor, a resistor, other active / passive semiconductor devices, a microelectronic / micromechanical structure, or any combination thereof. The dielectric layer 103 may include a dielectric material, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon carbonitride (SiCxNy), etc.

[0012] See FIG. 2 . A hole 110 is formed in the dielectric layer 103. In one embodiment, a portion of the dielectric layer 103 can be removed by an etching process such as wet etching or dry etching to form the hole 110. See FIG. 3 . A pre-barrier material layer 104 and a conductive layer 105 are formed on the upper surface 103U of the dielectric layer 103 and in the hole 110. The conductive layer 105 can be formed on the upper surface 104U of the pre-barrier material layer 104. In one embodiment, the pre-barrier material layer 104 can be formed on the upper surface 103U of the dielectric layer 103 by a deposition process such as chemical vapor deposition, and the pre-barrier material layer 104 can be formed to line the hole 110. The conductive layer 105 can be formed by a deposition process such as chemical vapor deposition to fill the remaining space in the hole 110 and to form the conductive layer 105 on the upper surface 104U of the pre-barrier material layer 104. The primary barrier material layer 104 may include a metal barrier material, such as tantalum (Ta), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), etc. The conductive layer 105 may include a conductive material, such as copper (Cu), aluminum (Al), etc.

[0013] Refer to FIG. 4 . Portions of the pre-barrier material layer 104 and the conductive layer 105 are removed to form a barrier material layer 404 and a via element 405, respectively, exposing the upper surface 103U of the dielectric layer 103. In one embodiment, the portions of the pre-barrier material layer 104 and the conductive layer 105 above the upper surface 103U of the dielectric layer 103 can be removed by chemical-mechanical planarization (CMP) or other suitable etching methods, while retaining the portions of the pre-barrier material layer 104 and the conductive layer 105 within the hole 110. The portion of the pre-barrier material layer 104 within the hole 110 is the barrier material layer 404. The portion of the conductive layer 105 within the hole 110 is the via element 405. The via element 405 can be on the barrier material layer 404. The barrier material layer 404 can be interposed between the via element 405 and the dielectric layer 103. In this step, as shown in FIG. 4 , the upper surface 404U of the barrier material layer 404 is higher in the longitudinal direction than the upper surface 103U of the dielectric layer 103. The upper surface 404U of the barrier material layer 404 may be higher in the longitudinal direction than the upper surface 405U of the via element 405. The upper surface 103U of the dielectric layer 103 may be higher in the longitudinal direction than the upper surface 405U of the via element 405. The longitudinal direction is, for example, the normal direction to the upper surface 103U of the dielectric layer 103. The barrier material layer 404 has sidewalls 404S connected between the upper surface 404U of the barrier material layer 404 and the upper surface 405U of the via element 405.

[0014] Refer to FIG. 5 . A portion of the barrier material layer 404 is removed to form a barrier layer 504 within the hole 110. In one embodiment, the portion of the barrier material layer 404 above the upper surface 103U of the dielectric layer 103 can be removed by chemical mechanical polishing or other suitable etching methods, while retaining the portion of the barrier material layer 404 below the upper surface 103U of the dielectric layer 103. The portion of the barrier material layer 404 below the upper surface 103U of the dielectric layer 103 constitutes the barrier layer 504. In this step, the upper surface 504U of the barrier layer 504 is coplanar with the upper surface 103U of the dielectric layer 103. The upper surface 504U of the barrier layer 504 may be higher in the vertical direction than the upper surface 405U of the through-via element 405.

[0015] In one embodiment, the semiconductor device 10 can be obtained by performing the method exemplarily shown in FIG. 1-5 .

[0016] In one embodiment, the method for manufacturing a semiconductor structure provided by the present invention may further include the manufacturing steps described with reference to Figures 6-8.

[0017] Please refer to FIG. 6 . A substrate 601, a dielectric layer 603 on the substrate 601, a device layer 602 between the substrate 601 and the dielectric layer 603, a barrier material layer 604 on the dielectric layer 603, and a via element 605 on the barrier material layer 604 are provided. In one embodiment, the structure shown in FIG. 6 can be formed using the manufacturing steps described with reference to FIG. 1-4 . In this step, the upper surface 604U of the barrier material layer 604 is higher in the longitudinal direction than the upper surface 603U of the dielectric layer 603. The upper surface 604U of the barrier material layer 604 can be higher in the longitudinal direction than the upper surface 605U of the via element 605. The upper surface 603U of the dielectric layer 603 can be higher in the longitudinal direction than the upper surface 605U of the via element 605. The longitudinal direction is, for example, the normal direction to the upper surface 603U of the dielectric layer 603. Barrier material layer 604 has sidewalls 604S connected between upper surface 604U of barrier material layer 604 and upper surface 605U of via element 605. Substrate 601 may be similar to substrate 101 of Figures 1-4. Device layer 602 may be similar to device layer 102 of Figures 1-4. Device layer 602 may be similar to device layer 102 of Figures 1-4. Dielectric layer 603 may be similar to dielectric layer 103 of Figures 1-4. Barrier material layer 604 may be similar to barrier material layer 404 of Figures 1-4. Via element 605 may be similar to via element 405 of Figures 1-4.

[0018] Refer to FIG. 7 . A portion of the barrier material layer 604 is removed to form a barrier layer 704. In one embodiment, the portion of the barrier material layer 604 above the upper surface 603U of the dielectric layer 603 can be removed by chemical mechanical polishing or other suitable etching methods, while retaining the portion of the barrier material layer 604 below the upper surface 603U of the dielectric layer 603. The portion of the barrier material layer 604 below the upper surface 603U of the dielectric layer 603 constitutes the barrier layer 704. In this step, the upper surface 704U of the barrier layer 704 is coplanar with the upper surface 603U of the dielectric layer 603. The upper surface 704U of the barrier layer 704 can be higher in the longitudinal direction than the upper surface 605U of the via element 605. In one embodiment, the semiconductor device 20 can be obtained by performing the method exemplarily illustrated in FIG. 6-7 . The manufacturing steps of the semiconductor device 10 and the semiconductor device 20 can be performed simultaneously or sequentially.

[0019] Please refer to FIG. 8 . After forming semiconductor device 10 and semiconductor device 20, semiconductor device 10 and semiconductor device 20 are bonded to form semiconductor structure 80. In one embodiment, the method for bonding semiconductor device 10 and semiconductor device 20 includes aligning upper surface 103U of dielectric layer 103 of semiconductor device 10 and upper surface 603U of dielectric layer 603 of semiconductor device 20 face to face; applying a force perpendicular to upper surface 103U of dielectric layer 103 and upper surface 603U of dielectric layer 603 to semiconductor device 10 and semiconductor device 20 so that upper surface 103U of dielectric layer 103 of semiconductor device 10 and upper surface 603U of dielectric layer 603 of semiconductor device 20 contact and bond together; and bonding upper surface 704U of barrier layer 704 of semiconductor device 10 and upper surface 504U of barrier layer 504 of semiconductor device 20. In one embodiment, the method for fabricating a semiconductor structure of the present invention may further include an annealing process to cause the via element 405 of the semiconductor device 10 and the via element 605 of the semiconductor device 20 to re-grow and bond to each other, forming a via element 805. In this embodiment, the bonding between the semiconductor device 10 and the semiconductor device 20 includes hybrid bonding, which involves at least two types of bonding, such as metal-to-metal bonding and nonmetal-to-nonmetal bonding.

[0020] In a comparative example, a method for fabricating a semiconductor structure does not include a step of raising the upper surface of the barrier material layer above the upper surface of the dielectric layer. Instead, a portion of the initial barrier material layer and a portion of the conductive layer are removed to directly form the barrier layer and the via element. This step may result in rounded corners or bevels at the junction between the dielectric layer and the barrier layer, and / or a tilted upper surface of the barrier layer, resulting in a reduced bonding surface area and affecting bonding quality.

[0021] According to the aforementioned embodiments, the method for manufacturing a semiconductor structure provided by the present invention avoids the formation of rounded corners or bevels at the junction between the dielectric layer and the barrier layer and / or avoids the upper surface of the barrier layer from tilting by making the upper surface of the barrier material layer higher than the upper surface of the dielectric layer. This ensures a sufficient bonding area, effectively improves bonding quality, and reduces the occurrence of bonding failures.

[0022] It should be noted that the diagrams, structures, and steps described above are intended to describe some embodiments or application examples of the present disclosure, and the present disclosure is not limited to the scope and application of the aforementioned structures and steps. Other embodiments with different structural aspects, such as known components of different internal components, can be applied, and the illustrative structures and steps can be adjusted according to the needs of actual applications. Therefore, the structures in the diagrams are merely illustrative and are not intended to limit the present invention. A person skilled in the art should understand that the relevant structures and step processes of the present disclosure, such as the arrangement or configuration of relevant elements and layers in a semiconductor structure, or the details of the manufacturing steps, may be adjusted and varied accordingly depending on the needs of the actual application.

[0023] In summary, although the present invention has been disclosed above through the use of embodiments, this is not intended to limit the present invention. Persons skilled in the art will readily appreciate that various modifications and alterations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0024] 10,20:Semiconductor components 80:Semiconductor structure 101,601:Substrate 101U, 103U, 104U, 404U, 405U, 504U: Top surface 102,602: Device layer 103,603: Dielectric layer 104: Primary barrier material layer 105: conductive layer 110: Holes 404,604: Barrier material layer 404S, 604S: sidewall 405,605,805:Through-hole components 504,704: Barrier layer 603U, 604U, 605U, 704U: Top surface

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; and removing a portion of the initial barrier material layer and a portion of the conductive layer to form a U-shaped barrier material layer and a via element in the hole, respectively, and exposing the upper surface of the dielectric layer, wherein an upper surface of the U-shaped barrier material layer is higher than the upper surface of the dielectric layer.

2. The method as described in claim 1, wherein the upper surface of the U-shaped barrier material layer is higher than an upper surface of the through-hole element.

3. The method as described in claim 2, wherein the upper surface of the dielectric layer is higher than the upper surface of the via element.

4. The method as described in claim 2, wherein the U-shaped barrier material layer has a sidewall connected between the upper surface of the U-shaped barrier material layer and the upper surface of the through-hole element.

5. The method as described in claim 1 further comprises: removing a portion of the U-shaped barrier material layer to form a barrier layer in the hole, wherein an upper surface of the barrier layer and the upper surface of the dielectric layer are coplanar.

6. The method as described in claim 5, wherein the upper surface of the barrier layer is higher than an upper surface of the via element.

7. A method for manufacturing a semiconductor structure, comprising: forming a first semiconductor element, comprising: providing a first substrate, a first dielectric layer on the first substrate, a first U-shaped barrier material layer on the first dielectric layer, and a first via element on the U-shaped first barrier material layer, wherein an upper surface of the first U-shaped barrier material layer is higher than an upper surface of the first dielectric layer; forming a second semiconductor element, comprising: providing a second substrate, a second dielectric layer on the second substrate, a second U-shaped barrier material layer on the second dielectric layer, and a second via element on the U-shaped second barrier material layer, wherein an upper surface of the U-shaped second barrier material layer is higher than an upper surface of the second dielectric layer; and bonding the upper surface of the first dielectric layer of the first semiconductor element to the upper surface of the second dielectric layer of the second semiconductor element.

8. The method as described in claim 7 further comprises: removing a portion of the first U-shaped barrier material layer to form a first barrier layer, wherein an upper surface of the first barrier layer and the upper surface of the first dielectric layer are coplanar; and removing a portion of the second U-shaped barrier material layer to form a second barrier layer, wherein an upper surface of the second barrier layer and the upper surface of the second dielectric layer are coplanar.

9. The method as described in claim 8 further comprises: bonding the upper surface of the first barrier layer and the upper surface of the second barrier layer.

10. The method of claim 7, wherein the upper surface of the first barrier material layer is higher than an upper surface of the first through-hole element, and the first U-shaped barrier material layer has a sidewall connected between the upper surface of the first U-shaped barrier material layer and the upper surface of the first through-hole element.

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