Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options

Abstract

Systems and methods for chip operation using Serial Peripheral Interface (SPI) with pin reduction options consider eliminating chip select, interrupt, and / or reset pins for the master-to-device (also known as slave) communication link, while retaining backward compatibility with legacy devices if needed. The communication link may include clock lines, master-to-device lines, and device-to-master lines. The master can use specific signal sequences on the clock and master-to-device lines to provide start and stop sequence commands, interrupt, or reset commands. By consolidating these commands into clock and master-to-device lines, pin counts can be reduced for portions of both master and slave circuitry. Similarly, fewer (or at least potentially shorter) conductive traces may be needed to interconnect the master to the device. This change can save costs, simplify circuit design, and / or save space within computing devices.

Description

Technical Field

[0001] The technology in this case relates to communication between integrated circuits (ICs) operating using the Serial Peripheral Interface (SPI) specification. Prior Technology

[0002] Computing devices are ubiquitous in modern society, and more specifically, mobile communication devices have become increasingly prevalent. The popularity of these mobile communication devices is driven in part by the many functions now available on them. The increased processing power in these devices means that mobile communication devices have evolved from mere communication tools into sophisticated mobile entertainment centers, thereby enabling enhanced user experiences.

[0003] In many cases, functionality can be achieved via circuitry on different chips or wafers that communicate with each other. For example, a processor chip can communicate with a memory chip or a sensor chip. Various standards and protocols have been developed to describe this communication. A popular standard for low-speed communication is the Serial Peripheral Interface (SPI) specification. SPI is widely adopted. Therefore, improvements to SPI can have a significant impact on computing devices. Summary of the Invention

[0004] The embodiments disclosed include systems and methods for chip operation using a Serial Peripheral Interface (SPI) with reduced pin options. Specifically, exemplary embodiments envision eliminating chip select pins, interrupt pins, and / or reset pins for host-to-device (also known as master) communication links, while retaining backward compatibility with legacy devices when needed. Communication links may include clock lines, host-to-device lines, and device-to-host lines. The host can use specific signal sequences on the clock line and host-to-device lines to provide start and stop sequence commands, interrupt or reset commands. By consolidating these commands into the clock line and host-to-device line, the pin count can be reduced for portions of both host and slave circuitry. Similarly, fewer (or at least potentially shorter) conductive traces may be required to interconnect the host to the device. This change can save costs, simplify circuit design, and / or save space within computing devices.

[0005] In one embodiment, an integrated circuit (IC) is disclosed. The IC includes a bus interface. The bus interface includes a clock pin configured to couple to a clock line on an associated bus. The bus interface also includes a host-to-subordinate pin configured to couple to an associated bus. The bus interface also includes a subordinate-to-host pin configured to couple to an associated bus. The IC also includes control circuitry. The control circuitry is configured to: change the logic state of the host-to-subordinate pin, subsequently activate the clock line, and subsequently send an address and command to the subordinate pin via the host.

[0006] In another embodiment, an IC is disclosed. The IC includes a bus interface. The bus interface includes a clock pin configured to be coupled to a clock line on an associated bus. The bus interface also includes a master-to-slave pin configured to be coupled to an associated bus. The bus interface also includes a slave-to-master pin configured to be coupled to an associated bus. The IC also includes control circuitry. The control circuitry is configured to change the state of the master-to-slave pin from a logic idle state to an asserted state. While keeping the master-to-slave pin in the asserted state, the control circuitry is also configured to toggle the clock pin a predetermined number of times to send a reset signal.

[0007] In another embodiment, an IC is disclosed. The IC includes a bus interface. The bus interface includes a clock pin configured to couple to a clock line on an associated bus. The bus interface also includes a master-to-slave pin configured to couple to an associated bus. The bus interface also includes a slave-to-master pin configured to couple to an associated bus. The IC also includes control circuitry. When in a logic idle state, the control circuitry is configured to detect a state change on the slave-to-master pin caused by a slave chip. In response to a state change on the slave-to-master pin, the control circuitry is configured to start a clock signal on the clock pin.

[0008] In another embodiment, a system is disclosed. The system includes a slave chip. The system also includes a bus coupled to the slave chip. The system also includes a master chip. The master chip includes a bus interface. The bus interface includes a clock pin configured to be coupled to a clock line on the bus. The bus interface also includes a master-to-slave pin configured to be coupled to the bus. The bus interface also includes a slave-to-master pin configured to be coupled to the bus. The master chip also includes control circuitry. The control circuitry is configured to: change the logic state of the master-to-slave pin, subsequently activate the clock line, and subsequently send an address and command via the master-to-slave pin to instruct the slave chip to select a chip. The control circuitry is also configured to change the state on the master-to-slave pin from a logic idle state to an asserted state. While keeping the master-to-slave pin in the asserted state, the control circuitry is configured to toggle the clock pin a predetermined number of times to send a reset signal to the slave chip. When in the logic idle state, the control circuitry is configured to detect state changes on the slave-to-master pin caused by the slave chip. In response to a state change on the slave-to-master pin, the control circuitry is configured to start a clock signal on the clock pin. Simple Explanation of the Diagram

[0009] Figure 1 is a block diagram of a traditional chip-to-chip multichip system using Serial Peripheral Interface (SPI) for communication;

[0010] Figure 2 is a diagram illustrating how to use the wires within an SPI link in a traditional SPI link;

[0011] Figure 3 illustrates how to use the interrupt and reset lines within an SPI link in a conventional SPI link;

[0012] Figure 4 is a block diagram of a chip-to-multichip system that uses a Serial Peripheral Interface (SPI) to communicate with traditional devices and devices with merged pin options according to the present invention.

[0013] Figure 5A shows the signal transmission diagram for the start and stop sequence of the system in Figure 4;

[0014] Figure 5B is a flowchart showing the procedure corresponding to the signal transmission diagram in Figure 5A;

[0015] Figure 6A is a signal transmission diagram showing possible soft repositioning sequences for the system in Figure 4;

[0016] Figure 6B is a flowchart showing the procedure corresponding to the signal transmission diagram in Figure 6A;

[0017] Figure 7A is a signal transmission diagram showing a possible hard reset sequence for the system in Figure 4;

[0018] Figure 7B is a flowchart showing the procedure corresponding to the signal transmission diagram in Figure 7A;

[0019] Figure 8A is a signal transmission diagram illustrating possible interrupt sequences of the system in Figure 4;

[0020] Figure 8B is a flowchart showing the procedure corresponding to the signal transmission diagram in Figure 8A;

[0021] Figure 9 is a block diagram of an exemplary mobile computing device that can include the system of Figure 4. Implementation

[0022] Referring now to the accompanying drawings, several exemplary embodiments of the content of this case are described. The word "exemplary" is used herein to mean "serving as an example, illustration, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior to or having an advantage over other embodiments.

[0023] The embodiments disclosed include systems and methods for chip operation using a Serial Peripheral Interface (SPI) with reduced pin options. Exemplary embodiments envision eliminating chip select pins, interrupt pins, and / or reset pins for host (also known as master device) to device (also known as slave device) communication links, while retaining backward compatibility with legacy devices when needed. Communication links may include clock lines, master-to-device lines, and device-to-master lines. The host can use specific signal sequences on the clock line and master-to-device line to provide start and stop sequence commands, interrupt or reset commands. By consolidating these commands into the clock and master-to-device lines, the pin count can be reduced for each part of the host and slave circuitry. Similarly, fewer (or at least potentially shorter) conductive traces may be needed to interconnect the host to the device. This change can save costs, simplify circuit design, and / or save space within computing devices.

[0024] Figures 1-3 provide a brief overview of a chip-to-chip multichip system using an SPI link, and the following discussion of exemplary forms of the subject matter begins with reference to Figure 4.

[0025] Figure 1 is a block diagram of an exemplary chip-to-chip system 100 that uses an SPI link 102 to communicate between chips. As used herein, a chip is an integrated circuit (IC) or monolithic IC that has a set of electronic circuits on a small piece of semiconductor material (e.g., silicon). It should be understood that multiple chips can be stacked to form a system in a package (SiP), which can be several ICs packaged in one or more chip carrier packages that can be stacked using stacked packages. SiPs perform all or most of the functions of an electronic system and are commonly used inside mobile phones, digital music players, etc. The dies containing the ICs can be stacked vertically on a substrate. The dies are internally connected via fine wires soldered to the package. Alternatively, flip-chip technology is used, where stacked chips are held together using solder bumps. SiPs are similar to system-on-a-chip (SoC) but have lower integration and are not on a single semiconductor die.

[0026] Referring again to Figure 1, the first chip 104 may be the master IC. Historically, the master IC may have been referred to as the master IC, and these terms are used interchangeably in this document. The first chip 104 is coupled to a plurality of second chips 106(1)-106(N) via an SPI link 102. The second chips 106(1)-106(N) may be referred to as device chips, subordinate chips, or slave chips. Slave chip is a historically used term, and although it can still be found in the current document, it is becoming inappropriate given the alternative terms, although there is no clear consensus at the time of writing on which term is the most appropriate alternative. The SPI link 102 includes a clock line (SCLK) 108, a master output, slave input (MOSI) line 110, a master input, slave output (MISO) line 112, and a slave select (SS) line 114(1)-114(N). The slave select lines 114(1)-114(N) are also commonly referred to as chip select (CS) lines. In addition, the SPI link 102 may include reset lines 116(1)-116(N) and interrupt lines 118(1)-118(N). According to the SPI protocol, each second chip 106(1)-106(N) has dedicated SS lines 114(1)-114(N), reset lines 116(1)-116(N) and interrupt lines 118(1)-118(N).

[0027] The presence of dedicated lines 114(1)-114(N), 116(1)-116(N), and 118(1)-118(N) increases the number of pins required in the first wafer 104 and the second wafer 106(1)-106(N). Specifically, the first wafer 104 may have an additional number of 3*(N-1) pins (i.e., three additional pins for each additional second wafer beyond the second wafer 106(1)). Pins are generally considered expensive, both in terms of material / manufacturing costs and space requirements. Furthermore, the additional pins must be connected to each other via wires, which requires additional space and materials, increasing the cost of the equipment.

[0028] Figures 2 and 3 illustrate signal transmission diagrams reflecting signals via a typical SPI link 102. Figure 2 illustrates the activity 200 on clock line 108, MOSI line 110, MISO line 112, and SS line 114(X). It should be understood that the first chip 104 controls clock line 108, MOSI line 110, and SS line 114(X), while the second chip 106(X) controls MISO line 112. SS lines 114(1)-114(N) are used to indicate which of the second chips 106(1)-106(N) are active and should be read from MOSI line 100 and authorized to send signals on MISO line 110. Specifically, the first chip 104 indicates a valid transaction phase by asserting logic low on SS line 114(X) during an active transaction. A falling edge 202 indicates the start of a transaction, and a rising edge 204 indicates the end of a transaction. During the active transaction window 206, clock line 108 provides clock signal 208. The first chip 104 can send command 210 on MOSI line 110 during the active transaction window 206, causing the second chip 106(X) to send response data 212 on MISO line 112. The first chip 108 can also send data 214 to the second chip 104(X) during the transaction window 206.

[0029] Figure 3 illustrates a typical activity 300 of the SPI link 102. During the past active communication period 302, clock signal 208 may be present on clock line 108, but during the idle communication period 304, clock line 108 may remain at logic low 306. Similarly, during the past active communication period 302, data 214 and 212 may be present on MOSI line 110 and MISO line 112 (as discussed above with reference to Figure 2), but during the idle communication period 304, they are at logic low 308 and 310, respectively. As implied in Figure 2, SS line 114(X) is at logic low 312 during the past active communication period 302 and at logic high 314 during the idle communication period 304. In contrast, interrupt line 116(X) may be held at logic high 316 during the past active communication period 302, but may be brought to logic low 318 during the idle communication period 304 when the second chip 106(X) asserts an interrupt. Similarly, the reset line 118(X) can be held at logic high 320 during the past active communication period 302 and brought to logic low 322 during the assertion retiming of the first chip 104.

[0030] It should be understood that SPI is a low-speed (typically below 50 MHz, more typically below 10 MHz, with throughput ranging from approximately 10 megabits per second (Mbps) to 50 Mbps) synchronous serial communication interface specification for short-range communication, primarily used in embedded systems. Therefore, although the exemplary embodiments of this application focus on SPI as an exemplary embodiment, the application is not limited thereto. Other synchronous serial communication systems employing full-duplex communication and including slave device select or chip select lines, reset lines, and / or interrupt lines can also benefit from the application.

[0031] Since its introduction in the mid-1980s, the SPI specification has proven useful. However, more modern computing devices may have a central application processor or modem with multiple associated auxiliary chips. Each of these auxiliary chips on the SPI link 102 has six pins to handle SPI signal transmissions. The host chip also has several pins to accommodate all these lines. Routing the various lines between the host and the multiple auxiliary chips can be challenging. Each of these facts aims to simplify the SPI link.

[0032] The exemplary configurations of this application allow for the elimination of chip select lines or slave select lines, reset lines, and / or interrupt lines, as well as the elimination of corresponding pins at both ends of the SPI link. The exemplary configurations of this application not only eliminate these lines and pins but also preserve their functionality by introducing a signal transmission sequence between the host and device using the remaining lines. Furthermore, the host chip can have pin capabilities to operate legacy lines used by subsidiary chips that have not yet been upgraded to the configurations included in this application.

[0033] Figure 4 illustrates an exemplary system 400 with merged pins and lines according to an exemplary configuration of the present invention. System 400 includes a master (or main) chip 402 coupled to conventional slave (or slave device) chips 404(1)-404(4) and merged slave chips 406(1)-406(M) via an SPI link 408. The SPI link 418 has a shared clock (SCLK) line 410, a shared MOSI line 412 (more generally referred to as a master-to-slave line), and a shared MISO line 414 (more generally referred to as a slave-to-master line) extending to all chips 404(1)-404(4) and 406(1)-406(M). However, the SPI link 408 only includes SS lines 416(1)-416(4), reset lines 418(1)-418(4), and interrupt lines 420(1)-420(4) for conventional slave chips 404(1)-404(4). According to the exemplary state of the present invention, the functions of slave select line, reset line, and interrupt line are provided on clock line 410, MOSI line 412, and MISO line 414.

[0034] The host chip 402 may include a clock 422 and control circuitry 424, as well as a bus interface 426 (sometimes referred to as the host bus interface). The bus interface 426 may include one or more pins (not explicitly shown) configured to couple to clock line 410, MOSI line 412 and MISO line 414, SS lines 416(1)-416(4), reset lines 418(1)-418(4), and interrupt lines 420(1)-420(4). In addition, the host chip 402 may include a normally open circuit (AOC) 428 that can detect changes in voltage levels on the SPI link 408, even when the SPI link 408 is idle or in a low-power state.

[0035] The conventional slave chips 404(1)-404(4) are conventional devices and are well known. However, the slave chips 406(1)-406(M) have been modified to eliminate the SS pin, reset pin, and interrupt pin. Therefore, the slave chips 406(1)-406(M) may include bus interfaces 430(1)-430(M) including clock pins 432(1)-432(M), MOSI pins 434(1)-434(M) (more generally, master to slave pins), and MISO pins 436(1)-436(M) (more generally, slave to master pins). The slave chips 406(1)-406(M) may also include AOC 438(1)-438(M) and control circuitry 440(1)-440(M). Optionally, slave chips 406(1)-406(M) may include internal clocks 442(1)-442(M). Slave chips 406(1)-406(M) may have addresses assigned to them at system startup or manufacturing time, which are known to the host chip 402 and stored in memory associated with the AOC 438(1)-438(M) or control circuitry 440(1)-440(M).

[0036] The exemplary configuration of this case allows the host chip 402 to send chip select signals, communication start signals, and reset signals via clock line 410 and MOSI line 412, while slave chips 406(1)-406(M) can send interrupt signals on MISO line 414. Figures 5A-8B provide an explanation of how this signal transmission is implemented via signal transmission diagrams and related flowcharts.

[0037] In this regard, FIG5A illustrates an exemplary configuration of the present invention via signal transmission FIG500, showing how a chip select signal can be provided without using the SS line. The host chip 402 can initiate a communication period at a communication period start time 502. The host chip 402 asserts a signal 504 on the MOSI line 412 (e.g., if the idle state is logic low, the host chip 402 raises signal 504 to logic high), while keeping the clock line 410 in an idle state 506 (e.g., logic low). Following this initial signal, the host chip 402 provides an address sequence signal 508 on the MOSI line 412, followed by a command sequence signal 510. The address sequence signal 508 includes the addresses of the target slave chips 406(1)-406(M). The AOC 438(1)-438(M) of the slave chips 406(1)-406(M) reads the address sequence signal 508 to determine whether the address corresponds to an address in the local storage area. If a match is found, the control circuit 440(1)-440(M) processes the command sequence signal 510 and responds with a data signal 512 on the MISO line 414. If needed or desired, the host chip 402 can also send a data signal 514 on the MOSI line 412.

[0038] At the end of the sequence, the host chip 402 can send a stop command on the MOSI line 412 and keep the clock line 410 idle for a predetermined amount of time as measured by the internal clocks 442(1)-442(M), etc.

[0039] Figure 5B shows a procedure 520 corresponding to the signal transmission diagram 500 in Figure 5A. Procedure 520 begins when the communication period starts (block 522). The host chip 402 keeps the clock line 410 idle while asserting the MOSI line 412 (block 524). The host chip 402 sends an address sequence signal 508 on the MOSI line 412, followed by a command sequence signal 510 (block 526). The slave chips 406(1)-406(M) read the address sequence signal 508 (block 528) and determine whether the addresses match (block 530). If the addresses do not match, procedure 520 ends for the slave chip 406 (block 532). However, if the address matches, the slave chip 406(X) reads the command sequence signal 510 (block 534) and executes the command (block 536), for example via sending data signal 512 (block 538) or receiving data signal 514.

[0040] Note that the conventional slave chips 404(1)-404(4) ignore the signals on clock line 410 and MOSI line 412 because the corresponding SS lines 416(1)-416(4) have not yet been activated. Therefore, the signal transmission procedure can easily work with the conventional slave chips 404(1)-404(4).

[0041] Figures 6A and 6B illustrate the signal transmission diagram 600 and flowchart 620 for the soft reset sequence. In this process, the host chip 402 determines that one or more slave chips 406(1)-406(M) require a soft reset. The host chip 402 initially asserts the MOSI line 412 (typically indicated at 602). When the MOSI line 412 is asserted, the host chip 402 also switches the clock line 410 once (typically at 604(1)) for a directed soft reset, or twice (typically at 604(2)) for a global soft reset. If a global soft reset has already been indicated, no further signaling is required, and all slave chips 406(1)-406(M) initiate a soft reset. However, if a directed soft reset has already been indicated, the host chip 402 deasserts the MOSI line 412 (typically at 606). Subsequently, the host chip 402 asserts the MOSI line 412 again (typically at 608), and then sends the address sequence signal 508 on the clock line 410. The slave chips 406(1)-406(M) evaluate the address, and if the address matches, the slave chip 407(X) initiates a soft reset.

[0042] Figure 6B illustrates procedure 620, which begins when the host chip 402 determines that a soft reset is required (block 622). The host chip 402 asserts the MOSI line 412 (block 624). When the MOSI line 412 is asserted, the host chip 402 sends a signal on clock line 410 for either a targeted soft reset or a global soft reset (block 626). If the soft reset is targeted, the host chip 402 deasserts and reasserts the MOSI line 412 (block 628). Subsequently, the host chip 402 sends an address sequence signal 508 on clock line 410 for the target of the soft reset (block 630). Slave chips 406(1)-406(M) evaluate the address (block 632), and if the address is correct, slave chip 406(X) performs a soft reset (block 634). If the address is incorrect, the slave chip 406(1)-406(M) will terminate the program (block 636).

[0043] If the signal at block 626 is a global reset, then the host chip 402 de-asserts the MOSI line 412 (block 638), and the slave chips 406(1)-406(M) perform a global soft reset (block 640).

[0044] Note that the legacy slave chips 404(1)-404(4) ignore the signals on clock line 410 and MOSI line 412 because the reset lines 418(1)-418(4) have not yet been activated. Therefore, in order to send a directed soft reset to a specific legacy slave chip 404(1)-404(4), the host chip 402 does not execute program 620, but only provides the appropriate signal on the appropriate reset line 418(1)-418(4). If a global soft reset is required, program 620 is executed simultaneously with the signal transmission on all reset lines 418(1)-418(4).

[0045] Similarly, Figures 7A and 7B illustrate the signal delivery diagram 700 and flowchart 720 for the hard reset sequence. In this process, the host chip 402 determines that one or more slave chips 406(1)-406(M) require a hard reset. The host chip 402 initially asserts the MOSI line 412 (typically indicated at 702). When the MOSI line 412 is asserted, the host chip 402 also switches the clock line 410 three times (typically at 704) for a directional hard reset, or four times (typically at 706) for a global hard reset. If a global hard reset has been indicated, no further signaling is required, and all slave chips 406(1)-406(M) initiate a hard reset. However, if a directional hard reset has been indicated, the host chip 402 deasserts the MOSI line 412 (typically at 708). Subsequently, the host chip 402 asserts the MOSI line 412 again (typically at 710), and then sends the address sequence signal 508 on the clock line 410. The slave chips 406(1)-406(M) evaluate the address, and if the address is correct, the slave chip 406(X) initiates a hard reset.

[0046] The procedure 720 is illustrated in Figure 7B, where the host chip 402 begins when it determines that a hard retiming is required (block 722). The host chip 402 asserts the MOSI line 412 (block 724). When the MOSI line 412 is asserted, the host chip 402 sends a signal on clock line 410 for either a targeted hard retiming or a global hard reset (block 726). If the hard retiming is targeted, the host chip de-asserts and re-asserts the MOSI line 412 (block 728). Subsequently, the host chip 402 sends an address sequence signal 508 on clock line 410 for the target of the hard retiming (block 730). Slave chips 406(1)-406(M) evaluate the address (block 732), and if the address is correct, slave chip 406(X) performs a hard reset (block 734). If the address is incorrect, the slave chip 406(1)-406(M) will terminate the program (block 736).

[0047] If the signal at block 626 is a global reset, then the master chip 402 de-asserts the MOSI line 412 (block 738), and the slave chips 406(1)-406(M) perform a global hard reset (block 740).

[0048] Note that the legacy slave chips 404(1)-404(4) ignore the signals on clock line 410 and MOSI line 412 because the corresponding reset lines 418(1)-418(4) have not yet been activated. Therefore, in order to send a directed hard reset to a specific legacy slave chip 404(1)-404(4), the host chip 402 does not execute program 720, but only provides the appropriate signal on the appropriate reset line 418(1)-418(4). If a global hard reset is required, program 720 is executed simultaneously with the signal transmission on all reset lines 418(1)-418(M).

[0049] Note that while the foregoing discussion assigns a specific number of switches to clock line 410 to distinguish between directional soft reset and global soft reset and hard reset (e.g., one to four switches), it should be understood that the specific number of switches can be changed to assign a specific command without departing from the scope of this case. Similarly, more switches can be used if necessary. Furthermore, different numbers of switches can be used to signal resets for specific subsets of slave chips 406(1)-406(M).

[0050] Figures 8A and 8B illustrate signal transfer diagram 800 and procedure 840 related to how a given slave chip 406(1)-406(M) can send an interrupt status signal to the master chip 402. Signal transfer diagram 800 begins with a past communication period 802, where a clock signal 804 is present on clock line 410, and the master chip 402 and slave chip 406(X) exchange signals 806 and 808 on MOSI line 412 and MISO line 414, respectively. When the past communication period 802 ends, an idle communication period 810 may exist on the SPI link 408, and lines 410, 412, and 414 may be idle (e.g., at logic low). At some point during the idle communication period 810, slave chip 406(X) may determine that it requires interrupt functionality. Slave chip 406(X) drives MISO line 414 to logic high 812, which is detected by AOC 428 of master chip 402. In response to the logic high on MISO line 414, master chip 402 starts clock signal 814 on clock line 410. After slave chip 406(X) detects a full clock cycle 816 on clock line 410, slave chip 406(X) deasserts MISO line 414 at 818. Master chip 402 sends interrupt fetch code signal 820 on MOSI line 412. Interrupt fetch code signal 820 is a command broadcast to all slave chips 407(1)-406(M) requesting that any slave chip 406(1)-406(M) that generated logic high 812 provide an identifier and optional details about the nature of the interrupt. The slave chip 406(X) that generated logic high 812 will respond with a device interrupt response 822, which includes the address of the slave chip 407(X) and optionally a code indicating the interrupt. Alternatively, the master chip 402 can then query the slave chip 406(X) for interrupt details.

[0051] Note that another option is to modulate logic high 812 into an interrupt flag signal (not shown), which includes information indicating the address of slave chip 406(X) and / or details about the interrupt.

[0052] When the slave chip 406(X) implements an interrupt, program 840, illustrated in Figure 8B, begins (block 842). The slave chip 406(X) drives logic high 812 on MISO line 414 (block 844). The master chip 402 starts clock signal 814 (block 846), and the slave chip 406(X) de-asserts MISO line 414 (block 848). The master chip 402 sends interrupt fetch code 820 (block 850), and the slave chip 406(X) sends interrupt response (block 852).

[0053] Because the traditional slave chips 404(1)-404(N) do not activate the corresponding SS lines, these signals on the MOSI line 412 are ignored by the traditional devices 404(1)-404(4).

[0054] Systems and methods for chip operation using the Serial Peripheral Interface (SPI) without reducing pin options, as disclosed herein, can be provided in or integrated into any processor-based device. Non-limiting examples include set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, SIP phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-wing drones.

[0055] Figure 9 is a system-level block diagram of an exemplary mobile terminal 900, such as a smartphone, a mobile computing device, a tablet, etc. Although the mobile terminal is specifically conceived as an exemplary form that can benefit from the content of this application, it should be understood that the content of this application is not limited thereto and can be used in any system with an SPI bus.

[0056] Referring again to Figure 9, the mobile terminal 900 includes an application processor 904 (sometimes referred to as a host) that communicates with a large storage device 906 via a Universal Flash Memory (UFS) bus 908. The application processor 902 can also be connected to a display 910 via a Display Serial Interface (DSI) bus 912 and to a camera 914 via a Camera Serial Interface (CSI) bus 906. Various audio components, such as a microphone 918, a speaker 920, and an audio transcoder 922, can be coupled to the application processor 904 via a Serial Low Power Inter-Chip Multimedia Bus (SLIMbus) 924. Additionally, audio components can communicate with each other via a Soundwire bus 926. A modem 928 can also be coupled to the SLIMbus 924 and / or the Soundwire bus 926. The modem 928 can also be connected to the application processor 904 via the peripheral component connection (PCI) or PCI express (PCIe) bus 930 and / or the system power management interface (SPMI) bus 932.

[0057] Referring again to Figure 9, the SPMI bus 932 can also be coupled to a local area network (LAN or WLAN) IC 934, a power management integrated circuit (PMIC) 936, a companion IC (sometimes called a bridge chip) 938, and a radio frequency IC (RFIC) 940. It should be understood that separate PCI buses 942 and 944 can also couple the application processor 904 to the companion IC 938 and the WLAN IC 934. The application processor 904 can also be connected to the sensor 946 via the sensor bus 948, which can be an SPI bus. The modem 928 and the RFIC 940 can communicate using bus 950.

[0058] Referring again to Figure 9, RFIC 940 can be coupled to one or more RFFE components, such as antenna tuner 952, switch 954, and power amplifier 956, via RFFE bus 958. Furthermore, RFIC 940 can be coupled to envelope tracking power supply (ETPS) 960 via bus 962, and ETPS 960 can communicate with power amplifier 956. Overall, the RFFE components (including RFIC 940) can be considered as RFFE system 964. It should be understood that RFFE bus 958 can be formed by clock lines and data lines (not shown).

[0059] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described herein, in conjunction with the various forms disclosed herein, can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As examples, the master and slave devices described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information as required. To clearly illustrate this interchangeability, the various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as deviating from the scope of this invention.

[0060] The various illustrative logic blocks, modules, and circuits described in conjunction with the various states disclosed herein can be implemented or executed via a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, individual gate or transistor logic, or other programmable logic device, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any known processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0061] The various forms disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, and any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor, allowing the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as separate components in a remote station, base station, or server.

[0062] It should also be noted that the operational steps described in any of the exemplary samples herein are described to provide examples and discussion. The described operations can be performed in many different sequences other than those shown. Furthermore, the operation described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary samples can be combined. It should be understood that the operational steps shown in the flowcharts can be modified in many different ways, which will be apparent to those skilled in the art to which this invention pertains. Those skilled in the art to which this invention pertains will also understand that information and signals can be represented using any of a variety of different techniques and methods. For example, the data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0063] The preceding description of the contents of this application is provided to enable those skilled in the art to practice or use the contents. Various modifications to the contents of this application will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, the contents of this application are not intended to limit them to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0064] The following numbered variants / clauses describe implementation examples: 1. An integrated circuit (IC) comprising: Bus interface, which includes: A clock pin, configured to be coupled to a clock line on an associated bus; The master-to-slave pin is configured to be coupled to the associated bus; and The slave-to-master pin is configured to be coupled to the associated bus; and The control circuit is configured as follows: Change the logic state of the master-slave pin; Then the clock line is activated; and The host then sends the address and command to the slave pin. 2. ICs according to Clause 1 also include conventional slave device select pins. 3. According to Clause 2 of the IC, the control circuit is also configured to keep the conventional slave select pin in a logically idle state while changing the logic state of the master-to-slave pin. 4. The IC according to any of the preceding clauses, wherein the control circuit is also configured to receive data from the slave chip via the slave-to-master pin after the address and command are sent. 5. The IC according to any of the preceding clauses, wherein the bus interface includes a Serial Peripheral Interface (SPI) bus interface. 6. The IC according to any of the preceding clauses, wherein the control circuitry is configured to send commands to a plurality of slave chips via the master-to-slave pin. 7. The IC according to any of the preceding clauses, wherein the control circuitry is configured to send a reset command to the slave chip using the master-to-slave pin and the clock pin. 8. An integrated circuit (IC) comprising: Bus interface, which includes: A clock pin, configured to be coupled to a clock line on an associated bus; The master-to-slave pin is configured to be coupled to the associated bus; and The slave-to-master pin is configured to be coupled to the associated bus; and The control circuit is configured as follows: Change the state of the master-to-slave pin from logical idle to asserted; and While keeping the master-to-slave pin in the asserted state, the clock pin is switched a predetermined number of times to send a reset signal. 9. ICs according to Clause 8 also include conventional reset pins. 10. According to Clause 9 of the IC, the control circuit is also configured to: activate the conventional reset pin and simultaneously send the reset signal on the clock pin. 11. The IC according to any one of Clauses 8 to 10, wherein the control circuit is configured to send a soft reset to a single slave chip using a signal on the clock pin using a first command. 12. According to Clause 11, the IC, wherein the control circuit is configured to send a global soft reset to a plurality of slave chips using a second command on the clock pin. 13. According to Clause 11, the IC, wherein the control circuit is configured to send a hard reset to a single slave chip using a third command on the clock pin. 14. According to Clause 13, the control circuit is configured to send a global hard reset to a plurality of slave chips using a fourth command on the clock pin. 15. The IC according to any one of Clauses 8 to 14, wherein the bus interface includes a Serial Peripheral Interface (SPI) bus interface. 16. An integrated circuit (IC) comprising: Bus interface, which includes: A clock pin, configured to be coupled to a clock line on an associated bus; The master-to-slave pin is configured to be coupled to the associated bus; and The slave-to-master pin is configured to be coupled to the associated bus; and The control circuit is configured as follows: When in a logically idle state, detect state changes on the slave-to-master pin caused by the slave chip; and In response to this state change on the slave-to-master pin, a clock signal is started on the clock pin. 17. According to Clause 16, the control circuit is also configured to drive the slave-to-master pin to a logically opposite state after detecting the state change. 18. IC according to Clause 16 or 17, wherein the control circuit is also configured to send an extraction code on the host-to-slave pin. 19. IC pursuant to Clause 18, wherein the extraction code includes an identifier request. 20. The IC according to Clause 19, wherein the control circuit is also configured to receive a slave identifier from the slave chip in response to the extraction code. 21. IC pursuant to Clause 18, wherein the extraction code includes an identifier with an interruption clarification request. 22. The IC according to Clause 21, wherein the control circuit is also configured to receive a slave identifier and an interrupt identifier in response to the extraction code. 23. IC according to Clause 18, wherein the extraction code includes an identifier and an interrupt command request. 24. According to Clause 23, the IC, wherein the control circuit is also configured to receive a slave identifier, interrupt identifier, and remedial command in response to the extraction code. 25. A system comprising: Subordinate chips; Buses coupled to the slave chip; and The host chip includes: Bus interface coupled to the bus, the bus interface including: A clock pin, configured to be coupled to a clock line on the bus; The master-to-slave pin is configured to be coupled to the bus; and The slave-to-master pin is configured to be coupled to the bus; and The control circuit is configured to perform each of the following three items at different times: 1) Change the logic state of the master-slave pin; Then the clock line is activated; and The host then sends an address and command to the slave pin to instruct the slave chip to select a chip. 2) Change the state of the master-to-slave pin from logical idle to asserted state; While keeping the master-to-slave pin in the asserted state, the clock pin is switched a predetermined number of times to send a reset signal to the slave chip; and 3) When in this logic idle state, detect state changes on the slave-to-master pin caused by the slave chip; and In response to this state change on the slave-to-master pin, a clock signal is started on the clock pin.

[0065] 100: Multichip System 102: SPI Link 104: First Chip 106(1): Second chip 106(2): Second chip 106(3): Second chip 106(N): Second wafer 106(X): Second chip 108: Clock line 110: MOSI line 112: From Device Output (MISO) Cable 114(1): SS line 114(N): SS line 114(X): SS line 116(1): Reset line 116(N): Reset line 116(X): Reset line 118(1): Interrupted line 118(N): Interruption line 118(X): Interruption line 200: Activities 202: Falling edge 204: Rising edge 206: Effective Transaction Window 208: Clock signal 210: Command 212: Response Materials 214: Data 300: Typical Activities 302: Activity Communication Period 304: Idle Communication Period 306: Low logic 308: Low logic 310: Low logic 312: Low logic 314: High Logic 316: High Logic 318: Low logic 320: High logic 322: Low logic 402: Main unit (or main chip) 404: Traditional slave (or secondary device) chip 404(1): Traditional slave (or slave device) chip 404(2): Traditional slave (or slave device) chip 404(3): Traditional slave (or slave device) chip 404(4): Traditional slave (or slave device) chip 406(1): Subordinate chip 406(2): Subordinate chip 406(M): Slave chip 406(X): Slave chip 408: SPI Link 410: Clock line 412: Shared MOSI line 414: Shared Clock (SCLK) Line 416(1): SS line 416(2): SS line 416(3): SS line 416(4): SS line 418(1): Reset line 418(2): Reset line 418(3): Reset line 418(4): Reset line 420(1): Interrupted line 420(3): Interrupted line 420(4): Interrupted line 422: Clock 424: Control Circuit 426: Bus Interface 428: Normally Open Circuit (AOC) 430(1): Bus Interface 430(2): Bus Interface 430(M): Bus Interface 432(1): Clock pin 432(M): Clock pin 434(1): MOSI pin 434(M): MOSI pin 436(1): MISO pin 436(M): MISO pin 438(1):AOC 438(M):AOC 440(1): Control circuit 440(2): Control Circuit 440(M): Control circuit 442(1): Internal clock 442(2): Internal clock 442(M): Internal clock 500: Signal Transmission Diagram 502: Start time of communication period 504: Signal 506: Idle status 508: Address Sequence Signal 510: Command sequence signal 512: Data Signal 514: Data Signal 520: Program 522: Square 524: Square 526: Square 528: Square 530: Square 532: Square 534: Square 536: Square 538: Square 600: Signal Transmission Diagram 602: Program 604(1): Program 604(2): Program 606: Program 608: Program 620: Flowchart 622: Square 624: Square 626: Square 628: Square 630: Square 632: Square 634: Square 636: Square 638: Square 640: Square 700: Signal Transmission Diagram 702: Program 704: Program 706: Program 708: Program 710: Program 720: Flowchart 722: Square 724: Square 726: Square 728: Square 730: Square 732: Square 734: Square 736: Square 738: Square 740: Square 800: Signal Transmission Diagram 802: Communication period 804: Clock signal 806: Signal 808: Signal 810: Idle Communication 812: High Logic 814: High Logic 816: Complete clock cycle 818: Program 820: Interruption of code extraction message 822: Equipment Interruption Response 840: Program 842: Square 844: Square 846: Square 848: Square 850: Square 852: Square 900: Mobile Terminal 904: Application Processor 906: Components for large storage areas 908: Universal Flash Memory (UFS) Bus 910: Monitor 912: Display Sequence Interface (DSI) Bus 914: Camera 916: Camera Sequence Interface (CSI) Bus 918: Such as microphones 920: Speaker 922: Audio transcoder 924: Serial Low Power Inter-Chip Multimedia Bus (SLIMbus) 926: SOUNDWIRE bus 928: Modem 930: Peripheral Component Connection (PCI) 932: SPMI Bus 934: Local Area Network (LAN or WLAN) IC 936: Power Management Integrated Circuit (PMIC) 938: Supporting IC 940: Radio Frequency IC (RFIC) 942: PCI Bus 944: PCI bus 946: Sensor 948: Sensor Bus 950: Busbar 952: Antenna Tuner 954: Switch 956: Power Amplifier 958:RFFE bus 960: Envelope Tracking Power Supply (ETPS) 962: Busbar 964: RFFE System IDLE: Idle MISO: Output from device MOSI: Input from device SCLK: Shared Clock SS: Select from device

[0066] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An integrated circuit (IC) comprising: A bus interface includes: a clock pin configured to be coupled to a clock line on an associated bus; a master-to-slave pin configured to be coupled to the associated bus; and a slave-to-master pin configured to be coupled to the associated bus; a legacy slave select pin; and a control circuit configured to: change a logic state of the master-to-slave pin; subsequently enable the clock line; and subsequently send an address to a slave chip and send a command via the master-to-slave pin without enabling the slave select pin.

2. According to the IC of request item 1, wherein the control circuit is also configured to: while changing the logic state of the master-to-slave pin, keep the conventional slave device select pin in a logic idle state.

3. According to the IC in request item 1, the control circuit is also configured to receive data from the slave chip via the slave-to-master pin after sending the address and the command.

4. The IC according to request item 1, wherein the bus interface includes a serial peripheral interface (SPI) bus interface.

5. The IC according to request item 1, wherein the control circuit is configured to send commands to a plurality of slave chips via the master-to-slave pin.

6. The IC according to request item 1, wherein the control circuit is configured to send a reset command to the slave chip using the master-to-slave pin and the clock pin.

7. An integrated circuit (IC) comprising: A bus interface includes: a conventional reset pin; a clock pin configured to be coupled to a clock line on an associated bus; a master-to-slave pin configured to be coupled to the associated bus; and a slave-to-master pin configured to be coupled to the associated bus; and a control circuit configured to: change a state on the master-to-slave pin from a logical idle state to an asserted state; and while keeping the master-to-slave pin in the asserted state, switch the clock pin a predetermined number of times to send a reset signal; wherein the control circuit is configured to: send a soft reset signal to a single slave chip using a first command on the clock pin.

8. According to the IC in request item 7, the control circuit is also configured to: activate the conventional reset pin and simultaneously send the reset signal on the clock pin.

9. The IC according to request item 7, wherein the control circuit is configured to send a global soft reset to a plurality of slave chips by means of a signal using a second command on the clock pin.

10. An integrated circuit (IC) comprising: A bus interface includes: a conventional reset pin; a clock pin configured to be coupled to a clock line on an associated bus; a master-to-slave pin configured to be coupled to the associated bus; and a slave-to-master pin configured to be coupled to the associated bus; and a control circuit configured to: change a state on the master-to-slave pin from a logical idle state to an asserted state; and while keeping the master-to-slave pin in the asserted state, switch the clock pin a predetermined number of times to send a reset signal; wherein the control circuit is configured to: send a hard reset signal to a single slave chip using a third command on the clock pin.

11. The IC according to request item 10, wherein the control circuit is configured to send a global hard reset to a plurality of slave chips by means of a signal using a fourth command on the clock pin.

12. The IC according to request item 7, wherein the bus interface includes a serial peripheral interface (SPI) bus interface.

13. An integrated circuit (IC) comprising: A bus interface includes: a clock pin configured to be coupled to a clock line on an associated bus; a master-to-slave pin configured to be coupled to the associated bus; and a slave-to-master pin configured to be coupled to the associated bus; and a control circuit configured to: when in a logically idle state, detect a state change on the slave-to-master pin caused by a slave chip; and in response to the state change on the slave-to-master pin, start a clock signal on the clock pin without activating a slave select pin, and drive the slave-to-master pin to a logically opposite state.

14. According to the IC of request item 13, the control circuit is also configured to send an extraction code on the host-to-slave pin.

15. According to the IC of request item 14, wherein the extraction code includes an identifier request.

16. The IC according to request item 15, wherein the control circuit is also configured to receive a slave identifier from the slave chip in response to the extraction code.

17. The IC according to request item 14, wherein the extraction code includes an identifier having an interruption clarification request.

18. The IC according to request item 17, wherein the control circuit is also configured to receive a slave identifier and an interrupt identifier in response to the extraction code.

19. IC according to request item 14, wherein the extraction code includes an identifier and an interrupt command request.

20. The IC according to request item 19, wherein the control circuit is also configured to receive a slave identifier and an interrupt identifier in response to the extraction code.

21. A system for wafer manipulation, comprising: A subordinate chip; A bus coupled to the slave chip; And a host chip, comprising: a bus interface coupled to the bus, the bus interface including: a clock pin configured to be coupled to a clock line on the bus; a host-to-slave pin configured to be coupled to the bus; and a slave-to-host pin configured to be coupled to the bus; a conventional slave select pin; and a control circuit configured to perform each of the following three at different times: 1) changing a logic state of the host-to-slave pin; subsequently activating the clock line without activating the slave select pin; and subsequently sending an address and command via the host-to-slave pin to indicate a chip select to the slave chip; 2) changing the state on the host-to-slave pin from a logic idle state to an asserted state; while keeping the host-to-slave pin in the asserted state, switching the clock pin a predetermined number of times to send a reset signal to the slave chip; and 3) When in the logic idle state, a state change on the slave-to-master pin caused by the slave chip is detected; and in response to the state change on the slave-to-master pin, a clock signal is started on the clock pin.

Images