Semiconductor packages

Abstract

A semiconductor package may include a first semiconductor wafer and a second semiconductor wafer on its top surface. The first semiconductor wafer may include: a first bonding pad on the top surface of a first semiconductor substrate; and a first through-via on the bottom surface of the first bonding pad and through the first semiconductor substrate. The second semiconductor wafer may include: a second interconnect pattern on the bottom surface of the second semiconductor substrate; and a second bonding pad on the bottom surface of the second interconnect pattern and coupled to the second interconnect pattern. The second bonding pad may be directly bonded to the first bonding pad. The width of the first through-via may be less than the width of the first bonding pad, and the width of the second interconnect pattern may be greater than the width of the second bonding pad.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including bonding pads that are directly bonded to each other. Cross - Reference to Related Applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2021 - 0164691, filed on November 25, 2021, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Prior Art

[0003] Semiconductor packages are configured to use semiconductor wafers as part of electronic products. Generally, a semiconductor package may include a printed circuit board (PCB) and a semiconductor wafer, the semiconductor wafer being mounted on the PCB and electrically connected to the PCB using bonding wires or bumps. With the development of the electronics industry, many studies are being conducted to improve the reliability and durability of semiconductor packages. Summary of the Invention

[0004] Embodiments of the inventive concept provide a semiconductor package having improved reliability, durability, and electrical characteristics.

[0005] According to an embodiment of the inventive concept, a semiconductor package may include: a first semiconductor wafer; and a second semiconductor wafer on a top surface of the first semiconductor wafer. The first semiconductor wafer may include: a first semiconductor substrate; a first bonding pad on a top surface of the first semiconductor substrate; and a first through - via on a bottom surface of the first bonding pad and passing through the first semiconductor substrate. The second semiconductor wafer may include: a second semiconductor substrate; a second interconnect pattern on a bottom surface of the second semiconductor substrate; and a second bonding pad on a bottom surface of the second interconnect pattern and coupled to the second interconnect pattern. The second bonding pad may be directly bonded to the first bonding pad. The width of the first through - via may be less than the width of the first bonding pad, and the width of the second interconnect pattern may be greater than the width of the second bonding pad.

[0006] According to an embodiment of the inventive concept, a semiconductor package may include: a first substrate; a first pad on a top surface of the first substrate; a first conductive pattern in contact with a bottom surface of the first pad; and a semiconductor chip on the top surface of the first substrate. The semiconductor chip may include: a semiconductor substrate; an interconnect layer on a bottom surface of the semiconductor substrate, the interconnect layer including an interconnect pattern; and a bonding pad coupled to a bottom surface of the interconnect pattern. The bonding pad may be directly bonded to the first pad. A width of the interconnect pattern may be greater than a width of the bonding pad, and a width of the first conductive pattern may be less than a width of the first pad.

[0007] According to an embodiment of the inventive concept, a semiconductor package may include: a first semiconductor chip; and a second semiconductor chip on a top surface of the first semiconductor chip. The first semiconductor chip may include: a first semiconductor substrate; a first integrated circuit on a bottom surface of the first semiconductor substrate; a first interconnect layer on the bottom surface of the first semiconductor substrate, the first interconnect layer including a first insulating layer and a first interconnect structure; a first backside insulating layer on the top surface of the first semiconductor substrate; a first through via in the first semiconductor substrate and electrically connected to the first interconnect structure; and a first bonding pad on a top surface of the first through via and in the first backside insulating layer and coupled to the first through via. The second semiconductor chip may include: a second semiconductor substrate; a second integrated circuit on a bottom surface of the second semiconductor substrate; a second interconnect layer on the bottom surface of the second semiconductor substrate, the second interconnect layer including a second insulating layer, a second interconnect structure, and a second interconnect pattern; and a second bonding pad in contact with a bottom surface of the second interconnect pattern. The second bonding pad may be directly bonded to the first bonding pad, and the second insulating layer may be directly bonded to the first backside insulating layer. A width of a bottom surface of the second interconnect pattern may be greater than a width of a bottom surface of the second bonding pad, and a width of a top surface of the first bonding pad may be greater than a width of the first through via. Brief Description of the Drawings

[0008] FIG. 1A is a diagram showing a semiconductor package according to an embodiment of the inventive concept. FIG. 1B is a diagram showing a first semiconductor chip according to an embodiment of the inventive concept. FIG. 1C is a diagram showing a second semiconductor chip according to an embodiment of the inventive concept. FIG. 1D is an enlarged cross-sectional view showing part I of FIG. 1A. FIG. 1E is an enlarged cross-sectional view showing part II of FIG. 1A. FIG. 1F is an enlarged cross-sectional view showing part III of FIG. 1A. FIG. 1G is an enlarged cross-sectional view showing part IV of FIG. 1A. FIG. 2A is a diagram showing a direct bonding structure between a first semiconductor wafer and a second semiconductor wafer according to an embodiment of the concept of the present invention. FIG. 2B is a diagram showing a direct bonding structure between a first semiconductor wafer and a second semiconductor wafer according to an embodiment of the concept of the present invention. FIG. 2C is a diagram showing a direct bonding structure between second semiconductor wafers according to an embodiment of the concept of the present invention. FIG. 2D is a diagram showing a direct bonding structure between a second semiconductor wafer and a third semiconductor wafer according to an embodiment of the concept of the present invention. FIG. 3A is a diagram showing a direct bonding structure between a first semiconductor wafer and a second semiconductor wafer according to an embodiment of the concept of the present invention. FIG. 3B is a diagram showing a direct bonding structure between second semiconductor wafers according to an embodiment of the concept of the present invention. FIG. 3C is a diagram showing a direct bonding structure between a second semiconductor wafer and a third semiconductor wafer according to an embodiment of the concept of the present invention. FIG. 4A is a diagram showing a direct bonding structure between a first semiconductor wafer and a second semiconductor wafer according to an embodiment of the concept of the present invention. FIG. 4B is a diagram showing a direct bonding structure between second semiconductor wafers according to an embodiment of the concept of the present invention. FIG. 5A is a diagram showing a semiconductor package according to an embodiment of the concept of the present invention. FIG. 5B is an enlarged cross-sectional view of part V of FIG. 5A. FIG. 6A is a diagram showing a semiconductor package according to an embodiment of the concept of the present invention. FIG. 6B is an enlarged cross-sectional view of part V' of FIG. 6A. FIG. 6C is a diagram showing a direct bonding structure between a first semiconductor wafer and an interposer substrate according to an embodiment of the concept of the present invention. FIG. 7 is a diagram showing a semiconductor package according to an embodiment of the concept of the present invention. Embodiments

[0009] Exemplary embodiments of the concept of the present invention will now be described more fully with reference to the accompanying drawings that illustrate example embodiments. Like reference numerals in the drawings denote like elements and thus their repeated description may be omitted for simplicity.

[0010] FIG. 1A is a diagram showing a semiconductor package according to an embodiment of the concept of the present invention.

[0011] Referring to FIG. 1A, the semiconductor package may be the chip stack 10. The chip stack 10 may include a first semiconductor chip 100 and a second semiconductor chip 200.

[0012] The first semiconductor chip 100 may be, for example, a logic chip or a buffer chip. The first semiconductor chip 100 may be configured to control the second semiconductor chip 200. The first semiconductor chip 100 may include a first substrate, a first interconnect layer 120, a first conductive pad 150, a first through via 170, a first backside insulating layer 130, and a first bonding pad 155. The first substrate may be the first semiconductor substrate 110. The first interconnect layer 120 may include a first insulating layer 121, a first interconnect structure 123, and a first interconnect pattern 125. The first through via 170 may be a first conductive pattern.

[0013] The second semiconductor chip 200 may be disposed on the first semiconductor chip 100. The second semiconductor chip 200 may have a different size from the first semiconductor chip 100. For example, the width of the second semiconductor chip 200 may be smaller than the width of the first semiconductor chip 100. The second semiconductor chip 200 may have a different type from the first semiconductor chip 100. For example, the second semiconductor chip 200 may be a memory chip. The memory chip may be a high bandwidth memory (HBM) chip. The second semiconductor chip 200 may include a plurality of stacked second semiconductor chips 200. For example, the second semiconductor chip 200 may include a stacked second lower semiconductor chip 200A, a second intermediate semiconductor chip 200B, and a second upper semiconductor chip 200C. The second semiconductor chips 200 may have the same size. The second semiconductor chips 200 may have the same type. Each of the second semiconductor chips 200 may include a second semiconductor substrate 210, a second interconnect layer 220, a second bonding pad 250, a second through via 270, a second backside insulating layer 230, and a second upper bonding pad 255. The second interconnect layer 220 may include a second insulating layer 221 and a second interconnect pattern 225. The number of the second semiconductor chips 200 may be modified differently according to the number in the illustrated example. As an example, the chip stack 10 may be configured to include one second semiconductor chip 200. For ease of description, the following description will refer to an example in which only one second semiconductor chip 200 is disposed.

[0014] The chip stack 10 may further include a third semiconductor chip 300. The third semiconductor chip 300 may be disposed on the second semiconductor chip 200. For example, the third semiconductor chip 300 may be disposed on the second upper semiconductor chip 200C. The third semiconductor chip 300 may be the uppermost semiconductor chip. The third semiconductor chip 300 may have the same or substantially the same width as the second semiconductor chip 200. The height or thickness of the third semiconductor chip 300 may be greater than the height or thickness of the second semiconductor chip 200. In one embodiment, the third semiconductor chip 300 may be of the same type as the second semiconductor chip 200. For example, the third semiconductor chip 300 may be a high bandwidth memory (HBM) chip. The third semiconductor chip 300 may include a third semiconductor substrate 310, a third interconnect layer 320, and a third bonding pad 350. The third semiconductor chip 300 may not include third vias, a third backside insulating layer, and a third upper bonding pad. The third interconnect layer 320 may include a third insulating layer 321 and a third interconnect pattern 325.

[0015] The chip stack 10 may further include a first molding layer 400. The first molding layer 400 may be disposed on the top surface of the first semiconductor chip 100. The first molding layer 400 may cover or surround the top surface of the first semiconductor chip 100, the side surfaces of the second semiconductor chip 200, and the side surfaces of the third semiconductor chip 300. The first molding layer 400 may expose the top surface of the third semiconductor chip 300. The first molding layer 400 may include an insulating polymer (e.g., an epoxy molding compound).

[0016] Hereinafter, the first semiconductor chip will be described in more detail.

[0017] FIG. 1B is a diagram showing a first semiconductor chip according to an embodiment of the inventive concept.

[0018] Referring to FIGS. 1A and 1B, in addition to the first semiconductor substrate 110, the first interconnect layer 120, the first conductive pad 150, the first vias 170, the first backside insulating layer 130, and the first bonding pad 155, the first semiconductor chip 100 may further include a first integrated circuit 115.

[0019] The first semiconductor substrate 110 may be formed of or include a semiconductor material (e.g., silicon, germanium, or silicon germanium). The bottom surface of the first semiconductor substrate 110 may be the front surface, and the top surface of the first semiconductor substrate 110 may be the back surface. The first integrated circuit 115 may be disposed on the bottom surface of the first semiconductor substrate 110. The first integrated circuit 115 may include, for example, transistors. The first interconnect layer 120 may be disposed on the bottom surface of the first semiconductor substrate 110. The first interconnect layer 120 may include a front-end-of-line (FEOL) layer and a back-end-of-line (BEOL) layer. The FEOL layer of the first interconnect layer 120 may be disposed between the first semiconductor substrate 110 and the BEOL layer of the first interconnect layer 120. The first insulating layer 121 may be disposed on the bottom surface of the first semiconductor substrate 110 to cover the first integrated circuit 115. The first insulating layer 121 may include multiple layers. The first insulating layer 121 may include a silicon-containing insulating material. For example, the silicon-containing insulating material may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and / or tetraethyl orthosilicate. The first interconnect structure 123 may be disposed in the first insulating layer 121. The first interconnect structure 123 may be electrically connected to the first integrated circuit 115. The expression "an element is electrically connected to a semiconductor wafer" may mean that the element is electrically connected to an integrated circuit of the semiconductor wafer. In this specification, the expression "two elements are electrically connected to each other" may mean that the elements are directly connected to each other or indirectly connected to each other via other conductive elements. The first interconnect structure 123 may include a first interconnect line and a first via hole connected to the first interconnect line. The first via hole may be disposed between the first interconnect lines. The first interconnect line and the first via hole may be formed of or include at least one metal material.

[0020] The first conductive pad 150 may be disposed on the bottom surface of the first interconnect layer 120. For example, the first conductive pad 150 may be disposed in the first interconnect layer 120, but the bottom surface of the first conductive pad 150 may be exposed to the outside of the first insulating layer 121. The bottom surface of the first semiconductor wafer 100 may include the bottom surface of the first interconnect layer 120 and the bottom surface of the first conductive pad 150. The first conductive pads 150 may be respectively disposed on the bottom surfaces of the first interconnect patterns 125.

[0021] Each of the first conductive pads 150 may have an inclined side surface. The angle θ10 between the bottom surface and the side surface of the first conductive pad 150 may be an acute angle. The angle between the side surface and the top surface of the first conductive pad 150 may be an obtuse angle. The width W10 of the bottom surface of each of the first conductive pads 150 may be greater than the width of its top surface. The width W10 of the bottom surface of each of the first conductive pads 150 may be in the range of 1 micrometer to 6 micrometers. The width of each of the first conductive pads 150 may increase in the direction from its top surface to its bottom surface.

[0022] Each of the first conductive pads 150 may include a lower metal pad or a lower metal pad portion 150M and a lower barrier pad or a lower barrier pad portion 150B. The lower barrier pad 150B may be disposed on the top surface and the side surface of the lower metal pad 150M. The lower barrier pad 150B may be formed of or include at least one of titanium, tantalum, and / or their alloys. The lower metal pad 150M may be formed of or include copper, for example. The coefficient of thermal expansion of the lower metal pad 150M may be in the range of 5 ppm / K to 18 ppm / K.

[0023] The first interconnect pattern 125 may be disposed on the top surface of the first conductive pad 150. For example, the first interconnect pattern 125 may be in direct contact with the top surface of the first conductive pad 150. The first interconnect pattern 125 may be disposed between the first conductive pad 150 and the first interconnect structure 123 and may be electrically connected to the first conductive pad 150 and the first interconnect structure 123. The first interconnect pattern 125 may correspond to the lowermost interconnect line of the first insulating layer 121. As an example, the first interconnect pattern 125 may correspond to the lowermost interconnect line of the BEOL layer. The first interconnect patterns 125 may be laterally spaced apart from each other. The expression "components are laterally spaced apart from each other" means that the components are horizontally spaced apart from each other. Here, the term "horizontal" refers to a direction parallel to the top surface of the first semiconductor substrate 110. Each of the first interconnect patterns 125 may have an inclined side surface. For example, the angle θ1 between the bottom surface and the side surface of each of the first interconnect patterns 125 may be an obtuse angle. The angle between the side surface and the top surface of each of the first interconnect patterns 125 may be an acute angle. The bottom surface of each of the first interconnect patterns 125 may have a first width W1. The width of the top surface of each of the first interconnect patterns 125 may be greater than the first width W1. As an example, the width of each of the first interconnect patterns 125 may increase in a direction from its bottom surface toward its top surface. The width of the first interconnect pattern 125 may be greater than the width of the bottom surface of the first conductive pad 150. For example, the first width W1 may be greater than a corresponding one of the widths W10 of the bottom surface of the first conductive pad 150. Accordingly, the bottom surface of the first conductive pad 150 may be vertically overlapped or aligned with the first interconnect pattern 125. Here, the term "vertical" refers to a direction perpendicular to the top surface of the first semiconductor substrate 110.

[0024] Each of the first interconnect patterns 125 may have a first thickness T1. The first thickness T1 may be 0.5 times to 1.5 times the thickness T10 of the first conductive pad 150. The first thickness T1 may be greater than the thickness of the first interconnect line of the first interconnect structure 123. In one embodiment, the first thickness T1 may be in the range of 1 micron to 5 microns.

[0025] Each of the first interconnect patterns 125 may include a first barrier layer 125B and a first metal line 125M. The first barrier layer 125B may be disposed on the top surface of the first metal line 125M. The first barrier layer 125B may be formed of or include at least one of titanium, tantalum, and / or their alloys. The thickness of the first barrier layer 125B may be less than the thickness of the first metal line 125M. The first metal line 125M may include a metal material (metal element) different from that of the lower metal pad 150M. The first metal line 125M may be formed of or include aluminum, tin, and / or zinc.

[0026] The first interconnect pattern 125 may have a coefficient of thermal expansion greater than that of the first conductive pad 150. For example, the coefficient of thermal expansion of the first metal line 125M may be greater than that of the lower metal pad 150M. The coefficient of thermal expansion of the first metal line 125M may be greater than 18 ppm / K and may be less than or equal to 50 ppm / K.

[0027] The conductive pattern may be disposed in the first semiconductor substrate 110. The conductive pattern may be the first through-via 170. In one embodiment, the first through-via 170 may be disposed to completely penetrate the first semiconductor substrate 110 in the vertical direction. The first through-via 170 may further penetrate an upper portion of the first insulating layer 121. For example, the first insulating layer 121 may include multiple layers, and the first through-via 170 may further penetrate at least one of the multiple layers. The first through-via 170 may be coupled to the first interconnect structure 123. The first through-via 170 may be electrically connected to the first integrated circuit 115 via the first interconnect structure 123. The first through-via 170 may be electrically connected to the first interconnect pattern 125 and the first conductive pad 150.

[0028] Each of the first through-vias 170 may include a first via barrier layer 170B and a first conductive via 170M. The first conductive via 170M may be disposed on an inner surface of the first via barrier layer 170B. The first conductive via 170M may be formed of or include at least one metal material (e.g., copper or tungsten). The first via barrier layer 170B may be disposed along a side surface of the first conductive via 170M. For example, the first via barrier layer 170B may be disposed between the first conductive via 170M and the first semiconductor substrate 110, between the first conductive via 170M and the first backside insulating layer 130, and between the first conductive via 170M and the first insulating layer 121. The first via barrier layer 170B may not cover a top surface and a bottom surface of the first conductive via 170M. The first via barrier layer 170B may be formed of or include at least one of titanium, tantalum, and / or an alloy thereof. The first via barrier layer 170B may prevent the material contained in the first conductive via 170M from diffusing. The first via barrier layer 170B may be used as a seed layer during the process of forming the first conductive via 170M.

[0029] The first semiconductor wafer 100 may further include a first liner layer 117. The first liner layer 117 may be disposed between the first via barrier layer 170B and the first semiconductor substrate 110. In one embodiment, the first liner layer 117 may further extend into the regions between the first via barrier layer 170B and the first backside insulating layer 130 and between the first via barrier layer 170B and the first insulating layer 121.

[0030] The first backside insulating layer 130 may be disposed on the top surface of the first semiconductor substrate 110. The first backside insulating layer 130 may be a single layer or may include multiple layers. The first backside insulating layer 130 may be formed of or include at least one of silicon-based insulating materials. In one embodiment, the first through via 170 may be partially inserted into the lower portion of the first backside insulating layer 130.

[0031] The first bonding pad 155 may be disposed on the top surface of the first semiconductor wafer 100. The top surface of the first semiconductor wafer 100 may include the top surface of the first bonding pad 155 and the top surface of the first backside insulating layer 130. The first bonding pad 155 may be disposed on the first through via 170 and in the first backside insulating layer 130. The first bonding pad 155 may be electrically connected to the first through via 170. The first bonding pad 155 may be in direct contact with the first through via 170. Therefore, it is possible to simplify the manufacturing process of the first semiconductor wafer 100 and reduce the size of the first semiconductor wafer 100. The width of the first bonding pad 155 may be greater than the width of the first through via 170. For example, the width W11 of the top surface of each of the first bonding pads 155 may be greater than the width W12 of the top surface of the first through via 170 electrically connected thereto. Each of the first bonding pads 155 may have an inclined side surface. For example, the angle θ15 between the bottom surface and the side surface of each of the first bonding pads 155 may be an obtuse angle. The angle between the side surface and the top surface of each of the first bonding pads 155 may be an acute angle. The width W11 of the top surface of each of the first bonding pads 155 may be greater than the width of its bottom surface. For example, the width W11 of the top surface of each of the first bonding pads 155 may be in the range of 5 micrometers to 20 micrometers.

[0032] Each of the first bonding pads 155 may include a first metal pad or a first metal pad portion 155M and a first barrier pad or a first barrier pad portion 155B. The first barrier pad 155B may cover the bottom surface and the side surfaces of the first metal pad 155M. The first barrier pad 155B may be formed of or include at least one of titanium, tantalum, and / or an alloy thereof. The first metal pad 155M may be formed of or include copper, for example. As an example, the first metal pad 155M may be formed of or include the same metal material as the first conductive via 170M, but the inventive concept is not limited to this example. The thermal expansion coefficient of the first metal pad 155M may be in the range of 5 ppm / K to 18 ppm / K.

[0033] Hereinafter, the second semiconductor wafer will be described in more detail. For convenience of description, the following description will refer to an example in which one second semiconductor wafer is provided.

[0034] FIG. 1C is a diagram showing a second semiconductor wafer according to an embodiment of the inventive concept.

[0035] Referring to FIG. 1C, in addition to the second semiconductor substrate 210, the second interconnect layer 220, the second bonding pads 250, the second through vias 270, the second backside insulating layer 230, and the second upper bonding pads 255, the second semiconductor wafer 200 may further include a second integrated circuit 215. The second semiconductor wafer 200 may be the second lower semiconductor wafer 200A, the second intermediate semiconductor wafer 200B, or the second upper semiconductor wafer 200C previously described with reference to FIG. 1A. The second semiconductor substrate 210 may be formed of or include a semiconductor material (e.g., silicon, germanium, or silicon germanium). The bottom surface of the second semiconductor substrate 210 may be the front surface, and the top surface of the second semiconductor substrate 210 may be the back surface. The second integrated circuit 215 may be disposed on the bottom surface of the second semiconductor substrate 210. The second integrated circuit 215 may include, for example, transistors.

[0036] The second interconnect layer 220 may be disposed on the bottom surface of the second semiconductor substrate 210. The second interconnect layer 220 may include a FEOL layer and a BEOL layer. The FEOL layer of the second interconnect layer 220 may be disposed between the second semiconductor substrate 210 and the BEOL layer of the second interconnect layer 220. The second interconnect layer 220 may include a second insulating layer 221, second interconnect patterns 225, and a second interconnect structure 223. The second insulating layer 221 may be disposed on the bottom surface of the second semiconductor substrate 210 to cover the second integrated circuit 215. The second insulating layer 221 may include multiple layers. The second insulating layer 221 may include a silicon-containing insulating material. The second interconnect structure 223 may be disposed in the second insulating layer 221. The second interconnect structure 223 may be electrically connected to the second integrated circuit 215. The second interconnect structure 223 may include second interconnect lines and second vias. The second vias may be disposed between the second interconnect lines and may be coupled to the second interconnect lines. The second interconnect lines and the second vias may be formed of or include at least one metal material.

[0037] The second interconnect patterns 225 may correspond to the lowermost interconnect lines of the second insulating layer 221. As an example, the second interconnect patterns 225 may correspond to the lowermost interconnect lines of the BEOL layer. The second interconnect patterns 225 may be laterally spaced apart from each other. Each of the second interconnect patterns 225 may have an inclined side surface. For example, the angle θ2 between the bottom surface and the side surface of each of the second interconnect patterns 225 may be an obtuse angle. The angle between the side surface and the top surface of each of the second interconnect patterns 225 may be an acute angle. The bottom surface of each of the second interconnect patterns 225 may have a second width W2. The width of the top surface of each of the second interconnect patterns 225 may be greater than the second width W2. As an example, the width of each of the second interconnect patterns 225 may increase in a direction from its bottom surface toward its top surface. The second thickness T2 of the second interconnect patterns 225 may be relatively large. For example, the second thickness T2 may be greater than the thickness of the second interconnect lines of the second interconnect structure 223. In one embodiment, the second thickness T2 may be in the range of 1 micrometer to 5 micrometers.

[0038] Each of the second interconnect patterns 225 may include a second barrier layer 225B and a second metal line 225M. The second barrier layer 225B may be disposed on the top surface of the second metal line 225M. The second barrier layer 225B may be formed of or include at least one of titanium, tantalum, and / or their alloys. The thickness of the second barrier layer 225B may be less than the thickness of the second metal line 225M. The second metal line 225M may be formed of or include at least one of aluminum, tin, and / or zinc. The coefficient of thermal expansion of the second metal line 225M may be greater than 18 ppm / K and may be less than or equal to 50 ppm / K.

[0039] The second bonding pad 250 may be disposed near the bottom surface of the second interconnect layer 220. For example, the second bonding pad 250 may be disposed in the second interconnect layer 220. Here, the second insulating layer 221 may be disposed to expose the bottom surface of the second bonding pad 250. The bottom surface of the second semiconductor wafer 200 may include the bottom surface of the second interconnect layer 220 and the bottom surface of the second bonding pad 250. The bottom surface of the second interconnect layer 220 may include the bottom surface of the second insulating layer 221. The second interconnect pattern 225 may be disposed on the top surface of the second bonding pad 250. For example, the second interconnect pattern 225 may be in direct contact with the top surface of the second bonding pad 250. The second bonding pad 250 may be electrically connected to the second integrated circuit 215 via the second interconnect pattern 225 and the second interconnect structure 223.

[0040] The angle θ20 between the bottom surface and the side surface of the second bonding pad 250 may be an acute angle. The angle between the side surface and the top surface of the second bonding pad 250 may be an obtuse angle. The width W20 of the bottom surface of each of the second bonding pads 250 may be greater than the width of its top surface. As an example, the width of each of the second bonding pads 250 may increase in the direction from its top surface toward its bottom surface. The width of the second bonding pad 250 may be less than the second width W2. For example, the width W20 of the bottom surface of each of the second bonding pads 250 may be less than the second width W2. The width W20 of the bottom surface of each of the second bonding pads 250 may be in the range of 1 μm to 6 μm. Accordingly, the bottom surface of each of the second bonding pads 250 may be vertically overlapped or aligned with the second interconnect pattern 225 connected thereto.

[0041] Each of the second bonding pads 250 may include a second metal pad or second metal pad portion 250M and a second barrier pad or second barrier pad portion 250B. The second barrier pad 250B may be disposed on the top surface and the side surface of the second metal pad 250M. The second barrier pad 250B may be formed of or include at least one of titanium, tantalum, and / or an alloy thereof. The second metal pad 250M may include a metal material (metal element) different from the metal material of the second metal wire 225M. The second metal pad 250M may be formed of or include, for example, copper.

[0042] The thermal expansion coefficient of the second interconnect pattern 225 may be greater than the thermal expansion coefficient of the second bonding pad 250. The thermal expansion coefficient of the second metal wire 225M may be greater than the thermal expansion coefficient of the second metal pad 250M. For example, the thermal expansion coefficient of the second metal pad 250M may be in the range of 5 ppm / K to 18 ppm / K.

[0043] The second thickness T2 may be 0.5 times to 1.5 times the thickness T20 of the second bonding pad 250.

[0044] The second through-via 270 may be disposed in the second semiconductor substrate 210. For example, the second through-via 270 may be disposed to completely penetrate the second semiconductor substrate 210 in the vertical direction. The second through-via 270 may be partially inserted into the upper portion of the second insulating layer 221. For example, the second insulating layer 221 may include multiple layers, and the second through-via 270 may further penetrate at least one of the multiple layers. The second through-via 270 may be coupled to the second interconnect pattern 225 via the second interconnect structure 223. Thus, each of the second through-vias 270 may be electrically connected to at least one of the second integrated circuit 215 and the second bonding pad 250.

[0045] Each of the second through-vias 270 may include a second via barrier layer 270B and a second conductive via 270M. The second conductive via 270M may be disposed on the inner surface of the second via barrier layer 270B. The second conductive via 270M may be formed of or include at least one metal material (e.g., copper or tungsten). The second via barrier layer 270B may be disposed along the side surface of the second conductive via 270M. For example, the second via barrier layer 270B may be disposed between the second conductive via 270M and the second semiconductor substrate 210, between the second conductive via 270M and the second backside insulating layer 230, and between the second conductive via 270M and the second insulating layer 221. The second via barrier layer 270B may not cover the top and bottom surfaces of the second conductive via 270M. The second via barrier layer 270B may be formed of or include at least one of titanium, tantalum, or an alloy thereof. The second via barrier layer 270B may be used as a seed layer during the formation of the second conductive via 270M.

[0046] The second semiconductor wafer 200 may further include a second liner layer 217. The second liner layer 217 may be disposed between the second via barrier layer 270B and the second semiconductor substrate 210. The second liner layer 217 may extend into the regions between the second via barrier layer 270B and the second backside insulating layer 230 and between the second via barrier layer 270B and the second insulating layer 221. However, in one embodiment, the second liner layer 217 may not be disposed between the second via barrier layer 270B and the second backside insulating layer 230 or between the second via barrier layer 270B and the second insulating layer 221.

[0047] The second backside insulating layer 230 may be disposed on the top surface of the second semiconductor substrate 210. The second backside insulating layer 230 may be a single layer or may include multiple layers. The second backside insulating layer 230 may be formed of or include a silicon-based insulating material. In one embodiment, the second vias 270 may further extend into the second backside insulating layer 230.

[0048] The second upper bonding pad 255 may be disposed on the second vias 270 and within the second backside insulating layer 230. The second upper bonding pad 255 may be electrically connected to the second vias 270. In the case where additional conductive elements (e.g., additional interconnect lines) are inserted between the second upper bonding pad 255 and the second vias 270, the process of manufacturing the second semiconductor wafer 200 may be complex. In one embodiment, the second upper bonding pad 255 may be in direct contact with the second vias 270. Thus, it is possible to simplify the manufacturing process of the second semiconductor wafer 200 and reduce the size of the second semiconductor wafer 200. The width of the second upper bonding pad 255 may be greater than the width of the second vias 270. For example, the width W21 of the top surface of each of the second bonding pads 250 may be greater than the width W22 of the top surface of the second vias 270 connected thereto. For example, the width W21 of the top surface of each of the second bonding pads 250 may be in the range of 5 micrometers to 20 micrometers.

[0049] The shape and material of the second upper bonding pad 255 may be the same as or similar to those of the first bonding pad 155 in the previous embodiment of FIG. 1B. For example, each of the second bonding pads 250 may have an inclined side surface. As an example, the angle θ25 between the bottom surface and the side surface of each of the second bonding pads 250 may be an obtuse angle. The angle between the side surface and the top surface of each of the second bonding pads 250 may be an acute angle. The width W21 of the top surface of each of the second bonding pads 250 may be greater than the width of its bottom surface.

[0050] Each of the second upper bonding pads 255 may include a second upper metal pad 255M and a second upper barrier pad 255B. The second upper barrier pad 255B may cover the bottom surface and the side surface of the second upper metal pad 255M. The second upper barrier pad 255B may include at least one of titanium, tantalum, and / or an alloy thereof. The second upper metal pad 255M may be formed of or include copper, for example. As an example, the second upper metal pad 255M may include the same metal material as the second conductive via 270M, but the inventive concept is not limited to this example. The thermal expansion coefficient of the second upper metal pad 255M may be in the range of 5 ppm / K to 18 ppm / K.

[0051] Hereinafter, the bonding structure between the first semiconductor wafer and the second semiconductor wafer will be described in more detail. For convenience of description, the following description will refer to an example in which a single first bonding pad, a single second bonding pad, and a single second interconnect pattern are provided.

[0052] FIG. 1D is an enlarged cross-sectional view showing part I of FIG. 1A. FIG. 1E is an enlarged cross-sectional view showing part II of FIG. 1A.

[0053] Referring to FIGS. 1A and 1D, the second semiconductor wafer 200 may be disposed on the top surface of the first semiconductor wafer 100. The second semiconductor wafer 200 may be connected to the first semiconductor wafer 100 in a direct bonding manner. For example, the second lower semiconductor wafer 200A may be directly bonded to the first semiconductor wafer 100. The expression "two wafers are directly bonded to each other or connected to each other in a direct bonding manner" or "direct bonding between wafers" means that the opposing conductive elements of the two wafers are directly bonded to each other and the opposing insulating elements of the two wafers are directly bonded to each other. The expression "insulating elements are directly bonded to each other" may mean that chemical bonds are formed between the insulating elements. The direct bonding of wafers may include hybrid bonding of wafers. For example, the second bonding pad 250 of the second lower semiconductor wafer 200A may be directly bonded to the first bonding pad 155 of the first semiconductor wafer 100. During such a direct bonding process, metal atoms may diffuse from the first bonding pad 155 into the second bonding pad 250 or from the second bonding pad 250 into the first bonding pad 155. In this case, there may be no observable interface between the first bonding pad 155 and the second bonding pad 250.

[0054] The second insulating layer 221 of the second lower semiconductor wafer 200A may be in direct contact with the first backside insulating layer 130 of the first semiconductor wafer 100 and may be connected to the first backside insulating layer 130 in a direct bonding manner. For example, chemical bonds may be provided between the second insulating layer 221 and the first backside insulating layer 130. The chemical bonds may be covalent bonds. There may be no observable interface between the first backside insulating layer 130 and the second insulating layer 221.

[0055] The direct bonding process of the first semiconductor wafer 100 and the second lower semiconductor wafer 200A may include providing heat and pressure to the first semiconductor wafer 100 and the second lower semiconductor wafer 200A. The second interconnect pattern 225 may have a coefficient of thermal expansion greater than that of the first bonding pad 155 and the second bonding pad 250. For example, the coefficient of thermal expansion of the second metal line 225M may be greater than the coefficient of thermal expansion of the second metal pad 250M and the first metal pad 155M. Due to the difference in the coefficients of thermal expansion, the second interconnect pattern 225 may apply a force to the second bonding pad 250 during the direct bonding process. The force may be applied in the form of pressure. Since the coefficient of thermal expansion of the second metal line 225M is greater than 18 ppm / K, the second interconnect pattern 225 may apply a sufficiently strong force to the first bonding pad 155 and the second bonding pad 250 during direct bonding. Therefore, the second bonding pad 250 may be easily and firmly coupled to the first bonding pad 155.

[0056] The second interconnect pattern 225 may overlap with the bottom surface of the second bonding pad 250. The bottom surface of the second bonding pad 250 may be the surface bonded to the first bonding pad 155. This enables a stable direct bonding structure between the first bonding pad 155 and the second bonding pad 250.

[0057] According to an embodiment of the inventive concept, since the second thickness T2 of the second interconnect pattern 225 is 0.5 times greater than the thickness T20 of the second bonding pad 250, the second interconnect pattern 225 may apply a sufficiently strong force to the second bonding pad 250 during the direct bonding process. Therefore, the first bonding pad 155 and the second bonding pad 250 may be more firmly bonded to each other.

[0058] If the second thickness T2 is 1.5 times greater than the thickness T20 of the second bonding pad 250, due to the difference in the coefficients of thermal expansion between the second interconnect pattern 225 and the second insulating layer 221, the second insulating layer 221 may peel off from the second interconnect pattern 225. In this case, defects (e.g., voids) may occur between the second insulating layer 221 and the second interconnect pattern 225. According to an embodiment of the present invention concept, since the thickness of the second interconnect pattern 225 is greater than or equal to 1.5 times the thickness of the first bonding pad 155, the second interconnect pattern 225 can be more effectively covered by the second insulating layer 221. Therefore, peeling of the second insulating layer 221 from the second interconnect pattern 225 can be prevented. The width of the first bonding pad 155 may be greater than the width of the second bonding pad 250. For example, the width W11 of the top surface of the first bonding pad 155 may be greater than the width W20 of the bottom surface of the second bonding pad 250. Thus, even when there are process errors during the placement of the second semiconductor wafer 200, the bottom surface of the second bonding pad 250 can still be in good contact with the first bonding pad 155. As an example, the bottom surface of the second bonding pad 250 may completely overlap the first bonding pad 155. The first bonding pad 155 may have a first top surface or a first top surface portion and a second top surface or a second top surface portion. The first top surface of the first bonding pad 155 may contact the second bonding pad 250 and may be directly bonded to the second bonding pad 250. The second top surface of the first bonding pad 155 may be spaced apart from the second bonding pad 250 and may contact the first insulating layer 121.

[0059] The thickness T11 of the first bonding pad 155 may be less than the thickness T20 of the second bonding pad 250.

[0060] Referring to FIGS. 1A and 1E, the second interconnect patterns 225 may be horizontally spaced apart from each other. The second insulating layer 221 may have: a first bottom surface or a first bottom surface portion 221u1, which is vertically overlapped or aligned with the second interconnect pattern 225; and a second bottom surface or a second bottom surface portion 221u2, which is not vertically overlapped or aligned with the second interconnect pattern 225. During the direct bonding process between the first semiconductor wafer 100 and the second lower semiconductor wafer 200A, a force may be applied to the boundary between the first bottom surface 221u1 of the second insulating layer 221 and the first backside insulating layer 130 by the second interconnect pattern 225. The force may be applied in the form of pressure. Therefore, chemical bonds can be easily formed between the first bottom surface 221u1 of the second insulating layer 221 and the top surface of the first backside insulating layer 130. The first bottom surface 221u1 of the second insulating layer 221 can be well bonded to the first backside insulating layer 130 in a direct bonding manner.

[0061] Meanwhile, during the direct bonding process, it may be difficult to apply a force from the second interconnect pattern 225 to the second bottom surface 221u2 of the second insulating layer 221. In this case, a direct bonding structure may not be formed between the second bottom surface 221u2 of the second insulating layer 221 and the first backside insulating layer 130. As an example, the second bottom surface 221u2 of the second insulating layer 221 may be spaced apart from the top surface of the first backside insulating layer 130. A gap or air gap may be provided between the second bottom surface 221u2 of the second insulating layer 221 and the first backside insulating layer 130. As another example, the second bottom surface 221u2 of the second insulating layer 221 may contact the top surface of the first backside insulating layer 130, but may not be chemically bonded to the top surface of the first backside insulating layer 130.

[0062] Hereinafter, the bonding structure between the second semiconductor wafers will be described in more detail.

[0063] FIG. 1F is an enlarged cross-sectional view showing part III of FIG. 1A.

[0064] Referring to FIGS. 1A and 1F, a plurality of second semiconductor wafers 200 may be vertically stacked on the first semiconductor wafer 100. The second semiconductor wafers 200 may be connected to each other in a direct bonding manner. For example, the second lower semiconductor wafer 200A and the second intermediate semiconductor wafer 200B may be connected to each other in a direct bonding manner. Each of the second lower semiconductor wafer 200A and the second intermediate semiconductor wafer 200B may be substantially the same as the second semiconductor wafer 200 previously described with reference to FIG. 1B. The second upper bonding pad 255 of the second lower semiconductor wafer 200A and the second bonding pad 250 of the second intermediate semiconductor wafer 200B may be in direct contact with each other and may be connected to each other in a direct bonding manner. There may be no observable interface between the second upper bonding pad 255 of the second lower semiconductor wafer 200A and the second bonding pad 250 of the second intermediate semiconductor wafer 200B.

[0065] According to an embodiment of the inventive concept, since the second thickness T2 of the second interconnect pattern 225 of the second intermediate semiconductor wafer 200B is 0.5 times greater than the thickness T21 of the second upper bonding pad 255 of the second intermediate semiconductor wafer 200B, the second upper bonding pad 255 of the second lower semiconductor wafer 200A and the second bonding pad 250 of the second intermediate semiconductor wafer 200B can be well bonded to each other in a direct bonding manner.

[0066] The thickness T21 of the second upper bonding pad 255 of the second lower semiconductor wafer 200A may be less than the thickness T20 of the second bonding pad 250 of the second intermediate semiconductor wafer 200B. The width of the second upper bonding pad 255 of the second lower semiconductor wafer 200A may be greater than the width of the second bonding pad 250 of the second intermediate semiconductor wafer 200B. For example, the width W21 of the top surface of the second upper bonding pad 255 of the second lower semiconductor wafer 200A may be greater than the width W20 of the bottom surface of the second bonding pad 250 of the second intermediate semiconductor wafer 200B. Even when there are process errors during the placement of the second intermediate semiconductor wafer 200B, the second bonding pad 250 of the second intermediate semiconductor wafer 200B can still make good contact with the second upper bonding pad 255 of the second lower semiconductor wafer 200A. In one embodiment, the width W21 of the top surface of the second upper bonding pad 255 of the second lower semiconductor wafer 200A may be greater than the width W20 of the bottom surface of the second bonding pad 250 of the second intermediate semiconductor wafer 200B, and may be less than or equal to twice the width W20.

[0067] The second backside insulating layer 230 of the second lower semiconductor wafer 200A and the second insulating layer 221 of the second intermediate semiconductor wafer 200B can be connected to each other in a direct bonding manner. There may be chemical bonds between the second backside insulating layer 230 of the second lower semiconductor wafer 200A and the second insulating layer 221 of the second intermediate semiconductor wafer 200B. There may be no observable interface between the second backside insulating layer 230 of the second lower semiconductor wafer 200A and the second insulating layer 221 of the second intermediate semiconductor wafer 200B.

[0068] Referring to FIG. 1A, the second interconnect patterns 225 may be horizontally spaced apart from each other. The second insulating layer 221 of the second intermediate semiconductor wafer 200B may have a first bottom surface or a first bottom surface portion and a second bottom surface or a second bottom surface portion. The first bottom surface and the second bottom surface of the second insulating layer 221 of the second intermediate semiconductor wafer 200B may be substantially the same as the first bottom surface 221u1 and the second bottom surface 221u2 of the second insulating layer 221 of the second lower semiconductor wafer 200A described previously with reference to FIG. 1E. For example, the first bottom surface of the second insulating layer 221 of the second intermediate semiconductor wafer 200B may be vertically overlapped or aligned with the second interconnect pattern 225 of the second intermediate semiconductor wafer 200B, and may be directly bonded to the top surface of the second backside insulating layer 230 of the second lower semiconductor wafer 200A by a good bonding profile. The second bottom surface of the second insulating layer 221 of the second intermediate semiconductor wafer 200B may not be vertically overlapped or aligned with the second interconnect pattern 225 of the second intermediate semiconductor wafer 200B. The second bottom surface of the second insulating layer 221 of the second intermediate semiconductor wafer 200B may be spaced apart from the second backside insulating layer 230 of the second lower semiconductor wafer 200A. As another example, the second bottom surface of the second insulating layer 221 of the second intermediate semiconductor wafer 200B may be in contact with the second backside insulating layer 230 of the second lower semiconductor wafer 200A, but may not be chemically coupled to the second backside insulating layer 230.

[0069] The second upper semiconductor wafer 200C may be connected to the second intermediate semiconductor wafer 200B in a direct bonding manner. The direct bonding structure between the second upper semiconductor wafer 200C and the second intermediate semiconductor wafer 200B may be substantially the same as the direct bonding structure between the second intermediate semiconductor wafer 200B and the second lower semiconductor wafer 200A described with reference to FIG. 1F. For example, the second upper bonding pad 255 of the second intermediate semiconductor wafer 200B and the second bonding pad 250 of the second upper semiconductor wafer 200C may be in direct contact with each other and may be connected to each other in a direct bonding manner. There may be no observable interface between the second upper bonding pad 255 of the second intermediate semiconductor wafer 200B and the second bonding pad 250 of the second upper semiconductor wafer 200C. The second backside insulating layer 230 of the second intermediate semiconductor wafer 200B and the second insulating layer 221 of the second upper semiconductor wafer 200C may be connected to each other in a direct bonding manner. There may be a chemical bond provided between the second backside insulating layer 230 of the second intermediate semiconductor wafer 200B and the second insulating layer 221 of the second upper semiconductor wafer 200C. There may be no observable interface between the second backside insulating layer 230 of the second intermediate semiconductor wafer 200B and the second insulating layer 221 of the second upper semiconductor wafer 200C.

[0070] Hereinafter, the third semiconductor wafer 300 and the bonding structure between the second semiconductor wafer 200 and the third semiconductor wafer 300 will be described in more detail.

[0071] FIG. 1G is an enlarged cross-sectional view showing part IV of FIG. 1A. For convenience of description, the following description will refer to an example in which only one second semiconductor wafer is provided.

[0072] Referring to FIGS. 1A and 1G, the third semiconductor wafer 300 may be disposed on the second semiconductor wafer 200. The third semiconductor wafer 300 may include a third semiconductor substrate 310, a third interconnect layer 320, third bonding pads 350, and a third integrated circuit 315. The top surface of the third semiconductor substrate 310 may be the top surface of the third semiconductor wafer 300. In one embodiment, the third semiconductor substrate 310 may be formed of or include at least one of silicon, germanium, or silicon germanium. The third integrated circuit 315 may be disposed on the bottom surface of the third semiconductor substrate 310. The third integrated circuit 315 may include transistors. The third interconnect layer 320 may be disposed on the bottom surface of the third semiconductor substrate 310. The third interconnect layer 320 may include a FEOL layer and a BEOL layer. The third interconnect layer 320 may include a third insulating layer 321, third interconnect patterns 325, and a third interconnect structure 323. The third insulating layer 321 may be disposed on the bottom surface of the third semiconductor substrate 310 to cover the third integrated circuit 315. The third insulating layer 321 may include multiple layers. The third insulating layer 321 may include a silicon-containing insulating material. The third interconnect structure 323 may be disposed in the third insulating layer 321. The third interconnect structure 323 may be electrically connected to the third integrated circuit 315. The third interconnect structure 323 may include third interconnect lines and third vias that connect to the third interconnect lines. The third interconnect lines and the third vias may be formed of or include at least one metal material.

[0073] The third interconnect pattern 325 may correspond to the bottommost interconnect line of the third insulating layer 321. As an example, the third interconnect pattern 325 may correspond to the bottommost interconnect line of the BEOL layer. Each of the third interconnect patterns 325 may have an inclined side surface. For example, the angle between the bottom surface and the side surface of each of the third interconnect patterns 325 may be an obtuse angle. The angle between the side surface and the top surface of each of the third interconnect patterns 325 may be an acute angle. The bottom surface of each of the third interconnect patterns 325 may have a third width W3. The width of the top surface of each of the third interconnect patterns 325 may be greater than the third width W3. As an example, the width of the third interconnect pattern 325 may increase in the direction from its bottom surface toward its top surface. The third thickness T3 of the third interconnect pattern 325 may be greater than the thickness of the third interconnect line of the third interconnect structure 323. For example, the third thickness T3 may be in the range of 1 micrometer to 5 micrometers.

[0074] Each of the third interconnect patterns 325 may include a third barrier layer 325B and a third metal line 325M. The third barrier layer 325B may be disposed on the top surface of the third metal line 325M. The third barrier layer 325B may be formed of or include at least one of titanium, tantalum, and / or their alloys. The thickness of the third barrier layer 325B may be less than the thickness of the third metal line 325M. The third metal line 325M may be formed of or include at least one of aluminum, tin, and / or zinc.

[0075] The third bonding pad 350 may be disposed on the bottom surface of the third interconnect layer 320. For example, the third bonding pad 350 may be disposed in the third interconnect layer 320, and in this case, the third insulating layer 321 may be disposed to expose the bottom surface of the third bonding pad 350. The bottom surface of the third semiconductor wafer 300 may include the bottom surface of the third interconnect layer 320 and the bottom surface of the third bonding pad 350. The top surface of the third bonding pad 350 may be in direct contact with the third interconnect pattern 325. The third bonding pad 350 may be electrically connected to the third integrated circuit 315 via the third interconnect structure 323. The angle between the bottom surface and the side surface of the third bonding pad 350 may be an acute angle. The angle between the side surface and the top surface of the first bonding pad 155 may be an obtuse angle. The width W30 of the bottom surface of each of the third bonding pads 350 may be greater than the width of its top surface. The width W30 of the bottom surface of each of the third bonding pads 350 may be in the range of 1 micrometer to 6 micrometers.

[0076] Each of the third bonding pads 350 may include a third metal pad or a third metal pad portion 350M and a third barrier pad or a third barrier pad portion 350B. The third barrier pad 350B may be disposed on the top surface and the side surface of the third metal pad 350M. The third barrier pad 350B may be formed of or include at least one of titanium, tantalum, and / or an alloy thereof. The third metal pad 350M may be formed of or include a metal material different from that of the third metal line 325M. For example, the third metal pad 350M may be formed of or include copper.

[0077] The third interconnect pattern 325 may have a coefficient of thermal expansion greater than that of the third bonding pad 350. The third metal line 325M may have a coefficient of thermal expansion greater than that of the third metal pad 350M. For example, the coefficient of thermal expansion of the third metal line 325M may be greater than 18 ppm / K and may be less than or equal to 50 ppm / K. The coefficient of thermal expansion of the third metal pad 350M may be in the range of 5 ppm / K to 18 ppm / K. For ease of description, the following description will refer to an example in which a single second upper bonding pad 255, a single third bonding pad 350, and a single third interconnect pattern 325 are provided.

[0078] The third semiconductor wafer 300 may be connected to the second upper semiconductor wafer 200C in a direct bonding manner. For example, the second upper bonding pad 255 of the second upper semiconductor wafer 200C and the third bonding pad 350 of the third semiconductor wafer 300 may be connected to each other in a direct bonding manner. There may be no observable interface between the second upper bonding pad 255 of the second upper semiconductor wafer 200C and the third bonding pad 350 of the third semiconductor wafer 300.

[0079] The third thickness T3 may be 0.5 times to 1.5 times the thickness T30 of the third bonding pad 350. According to an embodiment of the inventive concept, since the third thickness T3 is 0.5 times greater than the thickness T30 of the third bonding pad 350 of the third semiconductor wafer 300, the third interconnect pattern 325 may apply a sufficiently strong force to the third bonding pad 350 and the second bonding pad 250 of the second upper semiconductor wafer 200C during the direct bonding process. Since the third thickness T3 is 1.5 times smaller than the thickness of the third bonding pad 350 of the third semiconductor wafer 300, the third insulating layer 321 may not peel off from the third interconnect pattern 325.

[0080] The third width W3 may be greater than the width W30 of the bottom surface of the third bonding pad 350. Accordingly, the bottom surface of the third bonding pad 350 may be vertically overlapped or aligned with a corresponding one of the third interconnect patterns 325.

[0081] The width of the second upper bonding pad 255 of the second upper semiconductor wafer 200C may be equal to or greater than the width of the third bonding pad 350. For example, the width W21 of the top surface of the second upper bonding pad 255 of the second upper semiconductor wafer 200C may be greater than the width W30 of the bottom surface of the third bonding pad 350. Accordingly, during the placement of the third semiconductor wafer 300, the third bonding pad 350 may be well coupled to the second upper bonding pad 255 of the second upper semiconductor wafer 200C.

[0082] The width W21 of the top surface of the second upper bonding pad 255 of the second upper semiconductor wafer 200C may be greater than the width W30 of the bottom surface of the third bonding pad 350, and may be less than or equal to twice the width W30.

[0083] The thickness T21 of the second upper bonding pad 255 of the second upper semiconductor wafer 200C may be less than the thickness T30 of the third bonding pad 350.

[0084] The second backside insulating layer 230 of the second upper semiconductor wafer 200C and the third insulating layer 321 of the third semiconductor wafer 300 may be connected to each other in a direct bonding manner. A chemical bond may be provided between the second backside insulating layer 230 of the second upper semiconductor wafer 200C and the third insulating layer 321 of the third semiconductor wafer 300.

[0085] As depicted in FIG. 1A, multiple third interconnect patterns 325 may be horizontally spaced apart from each other. The third insulating layer 321 may have a first bottom surface (portion) and a second bottom surface (portion). The first bottom surface and the second bottom surface of the third insulating layer 321 may be similar to the first bottom surface 221u1 and the second bottom surface 221u2 of the second insulating layer 221 described with reference to FIG. 1E. For example, the first bottom surface of the third insulating layer 321 may be vertically overlapped or aligned with the third interconnect pattern 325, and may be well bonded to the second backside insulating layer 230 of the second upper semiconductor wafer 200C in a direct bonding manner. The second bottom surface of the third insulating layer 321 may not be vertically overlapped and aligned with the third interconnect pattern 325. A portion of the bottom surface of the third semiconductor wafer 300 may be vertically spaced apart from the second backside insulating layer 230 of the second upper semiconductor wafer 200C. As another example, the bottom surface of the third semiconductor wafer 300 may contact the second backside insulating layer 230 of the second upper semiconductor wafer 200C, but may not be chemically bonded to the second backside insulating layer 230.

[0086] FIG. 2A is a diagram showing a direct bonding structure between a first semiconductor wafer and a second semiconductor wafer according to an embodiment of the inventive concept, and is an enlarged cross-sectional view showing a portion I of FIG. 1A. FIG. 2B is a diagram showing a direct bonding structure between a first semiconductor wafer and a second semiconductor wafer according to an embodiment of the inventive concept, and is an enlarged cross-sectional view showing a portion I of FIG. 1A. In the following description of FIGS. 2A and 2B, a first through via will be described in more detail with further reference to FIG. 1A.

[0087] Referring to FIGS. 2A and 2B, the second semiconductor wafer 200 may be connected to the first semiconductor wafer 100 in a direct bonding manner. For example, the second bonding pad 250 of the second lower semiconductor wafer 200A may be directly bonded to the first bonding pad 155 of the first semiconductor wafer 100. However, the second bonding pad 250 may have a protruding portion partially inserted into the second interconnect pattern 225. For example, the top surface of the second bonding pad 250 may be disposed at a level higher than the bottom surface of the second interconnect pattern 225. Here, the bottom surface of the second interconnect pattern 225 may be the surface covered by the second insulating layer 221.

[0088] The first through via 170 may include a protruding portion partially inserted into the first bonding pad 155. For example, the top surface of the first through via 170 may be disposed at a level higher than the bottom surface of the first bonding pad 155. The bottom surface of the first bonding pad 155 may be disposed on the first backside insulating layer 130.

[0089] Referring to FIG. 2B, in addition to the second metal line 225M and the second barrier layer 225B, the second interconnect pattern 225 may further include a second lower barrier layer 225BB. The second lower barrier layer 225BB may be disposed on the bottom surface of the second metal line 225M. The thickness of the second lower barrier layer 225BB may be less than the thickness of the second metal line 225M. The second lower barrier layer 225BB may be formed of or include at least one of titanium, tantalum, and / or an alloy thereof.

[0090] FIG. 2C is a diagram showing a direct bonding structure between second semiconductor wafers according to an embodiment of the inventive concept and is an enlarged cross-sectional view showing part III of FIG. 1A. In the following description of FIG. 2C, one second through-via will be described in more detail with further reference to FIG. 1A.

[0091] Referring to FIG. 2C, the second bonding pad 250 of the second intermediate semiconductor wafer 200B may be directly bonded to the second upper bonding pad 255 of the second lower semiconductor wafer 200A. However, the second bonding pad 250 of the second intermediate semiconductor wafer 200B may include a protruding portion that is partially inserted into the second interconnect pattern 225 of the second intermediate semiconductor wafer 200B. For example, the top surface of the second bonding pad 250 may be at a level higher than the bottom surface of the second interconnect pattern 225.

[0092] The second through-via 270 of the second lower semiconductor wafer 200A may include a protruding portion that is partially inserted into the second upper bonding pad 255 of the second lower semiconductor wafer 200A. For example, the top surface of the second through-via 270 may be at a level higher than the bottom surface of the second upper bonding pad 255.

[0093] Although not shown in the figures, in addition to the second metal line 225M and the second barrier layer 225B, the second interconnect pattern 225 of the second intermediate semiconductor wafer 200B may further include the second lower barrier layer 225BB of FIG. 2B.

[0094] FIG. 2D is a diagram showing a direct bonding structure between a second semiconductor wafer and a third semiconductor wafer according to an embodiment of the inventive concept and is an enlarged cross-sectional view showing part IV of FIG. 1A.

[0095] Referring to FIG. 2D, the third bonding pad 350 of the third semiconductor wafer 300 can be directly bonded to the second upper bonding pad 255 of the second upper semiconductor wafer 200C. The third bonding pad 350 of the third semiconductor wafer 300 may include a protruding portion partially inserted into the third interconnect pattern 325. For example, the top surface of the third bonding pad 350 may be disposed at a level higher than the bottom surface of the third interconnect pattern 325. Here, the bottom surface of the third interconnect pattern 325 may be the surface covered by the third insulating layer 321.

[0096] The second vias 270 of the second upper semiconductor wafer 200C may include a protruding portion partially inserted into the second upper bonding pad 255 of the second upper semiconductor wafer 200C. For example, the top surface of the second vias 270 may be disposed at a level higher than the bottom surface of the second upper bonding pad 255.

[0097] Although not shown in the figures, in addition to the third metal line 325M and the third barrier layer 325B, the third interconnect pattern 325 may further include a third lower barrier layer. The third lower barrier layer may be disposed on the bottom surface of the third interconnect pattern 325. The third lower barrier layer may be substantially the same as the second lower barrier layer 225BB in FIG. 2B.

[0098] FIG. 3A is a diagram showing a direct bonding structure between a first semiconductor wafer and a second semiconductor wafer according to an embodiment of the inventive concept, and is an enlarged cross-sectional view showing a portion I of FIG. 1A. Hereinafter, embodiments of the present invention will be described with reference to FIG. 3A in conjunction with FIG. 1A.

[0099] Referring to FIG. 3A, the second semiconductor wafer 200 can be connected to the first semiconductor wafer 100 in a direct bonding manner. For example, the second lower semiconductor wafer 200A can be directly bonded to the first semiconductor wafer 100. The direct bonding structure between the second lower semiconductor wafer 200A and the first semiconductor wafer 100 may be substantially the same as the direct bonding structure between the semiconductor wafers in the embodiments of FIGS. 1D and 1E. For example, the second bonding pad 250 of the second lower semiconductor wafer 200A can be directly bonded to the first bonding pad 155 of the first semiconductor wafer 100. However, the width W20 of the bottom surface of the second bonding pad 250 may be substantially the same as the width W11 of the top surface of the first bonding pad 155. The thickness T20 of the second bonding pad 250 may be equal to the thickness T11 of the first bonding pad 155 or different from the thickness T11.

[0100] FIG. 3B is a diagram showing a direct bonding structure between second semiconductor wafers according to an embodiment of the concept of the present invention, and is an enlarged cross-sectional view showing part III of FIG. 1A. Hereinafter, embodiments of the present invention will be described with reference to FIG. 3B in combination with FIG. 1A.

[0101] Referring to FIG. 3B, the second intermediate semiconductor wafer 200B can be connected to the second lower semiconductor wafer 200A in a direct bonding manner. The direct bonding structure between the second lower semiconductor wafer 200A and the second intermediate semiconductor wafer 200B can be the same as or similar to the direct bonding structure between the semiconductor wafers in the previous embodiment of FIG. 1F. For example, the second bonding pad 250 of the second intermediate semiconductor wafer 200B can be directly bonded to the second upper bonding pad 255 of the second lower semiconductor wafer 200A. However, the width W20 of the bottom surface of the second bonding pad 250 of the second intermediate semiconductor wafer 200B can be substantially the same as the width W21 of the top surface of the second upper bonding pad 255 of the second lower semiconductor wafer 200A.

[0102] Returning to FIG. 1A, the direct bonding structure between the second upper semiconductor wafer 200C and the second intermediate semiconductor wafer 200B can be similar to the direct bonding structure between the second intermediate semiconductor wafer 200B and the second lower semiconductor wafer 200A described in the embodiment with reference to FIG. 3B. For example, different from the structure shown in FIG. 3A, the bottom surface of the second bonding pad 250 of the second upper semiconductor wafer 200C can have a width substantially the same as the width of the top surface of the second upper bonding pad 255 of the second intermediate semiconductor wafer 200B.

[0103] FIG. 3C is a diagram showing a direct bonding structure between a second semiconductor wafer and a third semiconductor wafer according to an embodiment of the concept of the present invention, and is an enlarged cross-sectional view showing part IV of FIG. 1A. Hereinafter, embodiments of the present invention will be described with reference to FIG. 3C in combination with FIG. 1A.

[0104] Referring to FIG. 3C, the third semiconductor wafer 300 can be connected to the second upper semiconductor wafer 200C in a direct bonding manner. The direct bonding structure between the second upper semiconductor wafer 200C and the third semiconductor wafer 300 can be the same as or similar to the direct bonding structure between the semiconductor wafers in the previous embodiment of FIG. 1G. For example, the third bonding pad 350 of the third semiconductor wafer 300 can be directly bonded to the second upper bonding pad 255 of the second upper semiconductor wafer 200C. However, the width W30 of the bottom surface of the third bonding pad 350 of the third semiconductor wafer 300 can be substantially the same as the width W21 of the top surface of the second upper bonding pad 255 of the second upper semiconductor wafer 200C.

[0105] FIG. 4A is a diagram showing a direct bonding structure between a first semiconductor wafer and a second semiconductor wafer according to an embodiment of the inventive concept, and is an enlarged cross-sectional view showing part I of FIG. 1A. Hereinafter, embodiments of the present invention will be described with reference to FIG. 4A in combination with FIG. 1A.

[0106] Referring to FIG. 4A, the second semiconductor wafer 200 can be connected to the first semiconductor wafer 100 in a direct bonding manner. For example, the second lower semiconductor wafer 200A can be directly bonded to the first semiconductor wafer 100. The direct bonding structure between the second lower semiconductor wafer 200A and the first semiconductor wafer 100 can be substantially the same as the direct bonding structure between the semiconductor wafers in the embodiment described with reference to FIG. 3A. For example, the bottom surface of the second bonding pad 250 of the second lower semiconductor wafer 200A can be directly bonded to the top surface of the first bonding pad 155 of the first semiconductor wafer 100. The width W20 of the bottom surface of the second bonding pad 250 can be substantially the same as the width W11 of the top surface of the first bonding pad 155. However, the central axis of the second bonding pad 250 may not be vertically aligned with the central axis of the first bonding pad 155 (for example, the second bonding pad 250 and the first bonding pad 155 can be horizontally offset). In this case, a part of the bottom surface of the second bonding pad 250 can contact the first backside insulating layer 130. In addition, a part of the top surface of the first bonding pad 155 can contact the second insulating layer 221.

[0107] FIG. 4B is a diagram showing a direct bonding structure between second semiconductor wafers according to an embodiment of the inventive concept, and is an enlarged cross-sectional view showing part III of FIG. 1A. Hereinafter, embodiments of the present invention will be described with reference to FIG. 4B in combination with FIG. 1A.

[0108] Referring to FIG. 4B, the second intermediate semiconductor wafer 200B can be connected to the second lower semiconductor wafer 200A in a direct bonding manner. The direct bonding structure between the second lower semiconductor wafer 200A and the second intermediate semiconductor wafer 200B can be the same as or similar to the direct bonding structure between the semiconductor wafers in the previous embodiment of FIG. 3B. For example, the second bonding pad 250 of the second intermediate semiconductor wafer 200B can be directly bonded to the second upper bonding pad 255 of the second lower semiconductor wafer 200A. The width W20 of the bottom surface of the second bonding pad 250 of the second intermediate semiconductor wafer 200B can be substantially the same as the width W21 of the top surface of the second upper bonding pad 255 of the second lower semiconductor wafer 200A. However, the central axis of the second bonding pad 250 of the second intermediate semiconductor wafer 200B may not be vertically aligned with the central axis of the second upper bonding pad 255 of the second lower semiconductor wafer 200A (for example, the second bonding pad 250 and the second upper bonding pad 255 can be horizontally offset). In this case, a part of the bottom surface of the second bonding pad 250 of the second intermediate semiconductor wafer 200B can be in contact with the second backside insulating layer 230 of the second lower semiconductor wafer 200A. In addition, a part of the top surface of the second upper bonding pad 255 of the second lower semiconductor wafer 200A can be in contact with the second insulating layer 221.

[0109] The direct bonding structure between the second intermediate semiconductor wafer 200B and the second upper semiconductor wafer 200C shown in FIG. 1A can be modified in the same manner as the direct bonding structure between the second lower semiconductor wafer 200A and the second intermediate semiconductor wafer 200B described with reference to FIG. 4B.

[0110] The direct bonding structure between the second upper semiconductor wafer 200C and the third semiconductor wafer 300 shown in FIG. 1A can be modified in the same manner as the direct bonding structure between the second lower semiconductor wafer 200A and the second intermediate semiconductor wafer 200B described with reference to FIG. 4B.

[0111] FIG. 5A is a diagram showing a semiconductor package according to an embodiment of the inventive concept. FIG. 5B is an enlarged cross-sectional view showing part V of FIG. 5A.

[0112] Referring to FIGS. 5A and 5B, the semiconductor package may be the chip stack 10A. The chip stack 10A may include a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, and a first molding layer 400. The first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and the first molding layer 400 may be substantially the same as the embodiments described with reference to FIGS. 1A to 1G. For example, the first semiconductor chip 100 may include a first semiconductor substrate 110, a first interconnect layer 120, a first conductive pad 150, a first integrated circuit 115, a first through via 170, a first backside insulating layer 130, and a first bonding pad 155. The first interconnect layer 120 may include a first insulating layer 121 and a first interconnect structure 123.

[0113] However, the first interconnect layer 120 may not include the first interconnect pattern 125 described in the embodiments of FIGS. 1A and 1B. The first conductive pad 150 may be directly coupled to the first interconnect structure 123.

[0114] FIG. 6A is a diagram showing a semiconductor package according to an embodiment of the inventive concept. FIG. 6B is an enlarged cross-sectional view showing a portion V' of FIG. 6A.

[0115] Referring to FIGS. 6A and 6B, the semiconductor package 1 may include a substrate, solder balls 500, a chip stack 10, and a fourth semiconductor chip 600. The substrate may be an interposer substrate 900. The interposer substrate 900 may include an interposer die 910, metal vias 970, an interposer interconnect layer 920, and bonding pads. The bonding pads may be interposer bonding pads 950. The interposer substrate 900 may not include an integrated circuit, such as a transistor. For example, the integrated circuit may not be disposed on the interposer die 910. The interposer die 910 may be a first substrate. The interposer die 910 may include a semiconductor die (e.g., a silicon die, a germanium die, or a silicon germanium die).

[0116] The metal vias 970 may be disposed in the interposer die 910. The metal vias 970 may be laterally spaced apart from each other. In one embodiment, the metal vias 970 may be disposed to completely penetrate the interposer die 910 in the vertical direction.

[0117] The interposer interconnect layer 920 may be disposed on the top surface of the interposer die 910. The interposer interconnect layer 920 may include a dielectric layer 921 and a conductive structure 923. The dielectric layer 921 may include multiple layers. The dielectric layer 921 may be formed of or include a silicon-based insulating material. The conductive structure 923 may be disposed in the dielectric layer 921. The conductive structure 923 may include a wire portion and a via portion. The via portion may be connected to the wire portion. The conductive structure 923 may be formed of or include at least one metal material (e.g., copper, tungsten, titanium, and / or their alloys).

[0118] The interposer bonding pads 950 may be disposed on the top surface of the interposer substrate 900. For example, the interposer bonding pads 950 may be disposed on the conductive structure 923 and coupled to the conductive structure 923. The conductive structure 923 may include a first conductive structure and a second conductive structure. The second conductive structure may be electrically separated from the first conductive structure. Two of the interposer bonding pads 950 may be electrically connected to each other via the first conductive structure. Another one of the interposer bonding pads 950 may be electrically connected to one of the metal vias 970 via the second conductive structure. The electrical connection to the interposer substrate 900 may mean the electrical connection to at least one of the conductive structures 923.

[0119] The chip stack 10 may be disposed on the top surface of the interposer substrate 900. The chip stack 10 may be substantially the same as the chip stack 10 described in the embodiment of FIG. 1A. In one embodiment, multiple chip stacks 10 may be provided, and in this case, the chip stacks 10 may be laterally spaced apart from each other. The number of chip stacks 10 may vary differently. For example, the semiconductor package 1 may include one chip stack 10. The chip stack 10 may include a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, and a first molding layer 400.

[0120] The chip stack 10 may be connected to the interposer substrate 900 in a direct bonding manner. For example, the first semiconductor chip 100 may be connected to the interposer substrate 900 in a direct bonding manner. The first conductive pad 150 and the interposer bonding pad 950 may be connected to each other in a direct bonding manner. There may be no observable interface between the first conductive pad 150 and the interposer bonding pad 950. The thermal expansion coefficient of the first interconnect pattern 125 may be greater than the thermal expansion coefficients of the first conductive pad 150 and the interposer bonding pad 950. Since the first interconnect pattern 125 is disposed on the first conductive pad 150, a direct bonding structure between the first conductive pad 150 and the interposer bonding pad 950 may be well formed. For the convenience of description, the following description will refer to an example in which a single first conductive pad 150, a single interposer bonding pad 950, and a single first interconnect pattern 125 are provided.

[0121] Since, as described with reference to FIG. 1B, the first thickness T1 is 0.5 times greater than the thickness T10 of the first conductive pad 150, the first interconnect pattern 125 can apply a sufficiently strong force on the first conductive pad 150 during the direct bonding process. Since the first thickness T1 is 1.5 times smaller than the thickness T10 of the first conductive pad 150, the first insulating layer 121 may not peel off from the first interconnect pattern 125. The first width W1 (FIG. 1) can be greater than the width W10 of the bottom surface of the first conductive pad 150. Accordingly, the bottom surface of the first conductive pad 150 can be vertically overlapped with the first interconnect pattern 125.

[0122] The width of the interposer bonding pad 950 can be greater than the width of the first conductive pad 150. For example, the width of the top surface of the interposer bonding pad 950 can be greater than the width W10 of the bottom surface of the first conductive pad 150. Accordingly, during the process of placing the chip stack 10, the first conductive pad 150 can be well coupled to the interposer bonding pad 950. The thickness T10 of the first conductive pad 150 can be smaller than the thickness T40 of the interposer bonding pad 950.

[0123] The dielectric layer 921 and the first insulating layer 121 can be connected to each other by direct bonding. There may be chemical bonds provided between the dielectric layer 921 and the first insulating layer 121.

[0124] The interposer bonding pad 950 can include a fourth barrier pad or a fourth barrier pad portion 950B and a fourth metal pad or a fourth metal pad portion 950M. The fourth barrier pad 950B can cover the bottom surface and the side surfaces of the fourth metal pad 950M. The fourth barrier pad 950B can be formed of or include at least one of tantalum and / or its alloys. For example, the fourth metal pad 950M can be formed of or include copper. The coefficient of thermal expansion of the fourth metal pad 950M can be in the range of 5 ppm / K to 18 ppm / K.

[0125] Each of the conductive structures 923 can further include a conductive pattern 922. The conductive pattern 922 can be in contact with the bottom surface of the interposer bonding pad 950 electrically connected thereto. The width of the conductive pattern 922 can be smaller than the width of the interposer bonding pad 950 electrically connected thereto.

[0126] As shown in FIG. 6A, solder balls 500 can be disposed on the bottom surface of the interposer substrate 900 and can be electrically connected to the metal vias 970. The solder balls 500 can be laterally spaced apart from each other and can be electrically isolated from each other. The solder balls 500 can be formed of or include at least one of a solder material (e.g., tin, silver, zinc, and / or an alloy thereof). The semiconductor package 1 can further include bonding pads 905. The bonding pads 905 can be inserted between the solder balls 500 and the metal vias 970. In one embodiment, the bonding pads 905 can be formed of or include a material different from that of the solder balls 500. The bonding pads 905 can be formed of or include at least one metal material (e.g., copper, gold, or nickel).

[0127] The wafer stack 10 can be electrically connected to the solder balls 500 and the fourth semiconductor wafer 600 via the interposer substrate 900.

[0128] The fourth semiconductor wafer 600 can be mounted on the interposer substrate 900. The fourth semiconductor wafer 600 can be laterally spaced apart from the wafer stack 10. For example, the fourth semiconductor wafer 600 can be disposed between the wafer stacks 10. The fourth semiconductor wafer 600 can have a different type from the first to third semiconductor wafers 100, semiconductor wafer 200, and semiconductor wafer 300. For example, the fourth semiconductor wafer 600 can be a logic wafer or a system-on-chip (SOC). As an example, the fourth semiconductor wafer 600 can be a logic wafer having a different function from the first semiconductor wafer 100. The fourth semiconductor wafer 600 can be an ASIC wafer or an application processor (AP) wafer. The fourth semiconductor wafer 600 can include a central processing unit (CPU) or a graphics processing unit (GPU).

[0129] The fourth semiconductor wafer 600 may include a fourth insulating layer 621, a fourth interconnect pattern 615, and a fourth bonding pad 650. The fourth insulating layer 621, the fourth interconnect pattern 615, and the fourth bonding pad 650 may be similar to the first insulating layer 121, the first interconnect pattern 125, and the first bonding pad 155 described with reference to FIGS. 1B and 6B, respectively. For example, the bottom surface of the fourth semiconductor wafer 600 may include the bottom surface of the fourth insulating layer 621 and the bottom surface of the fourth bonding pad 650. The fourth insulating layer 621 may be disposed in the lower portion of the fourth semiconductor wafer 600. The fourth insulating layer 621 may be formed of or include a silicon-based insulating material. The fourth bonding pad 650 may be disposed on the bottom surface of the fourth semiconductor wafer 600. The fourth bonding pad 650 may be a wafer pad. The fourth bonding pad 650 may be formed of or include, for example, copper.

[0130] The fourth interconnect pattern 615 may be disposed in the fourth insulating layer 621. The fourth interconnect pattern 615 may be disposed on and in contact with the fourth bonding pad 650. The fourth bonding pad 650 may be electrically connected to the integrated circuit of the fourth semiconductor wafer 600 via the fourth interconnect pattern 615. The thickness of the fourth interconnect pattern 615 may be 0.5 times to 1.5 times the thickness of the fourth bonding pad 650. The width of the fourth interconnect pattern 615 may be greater than the width of the fourth bonding pad 650. The coefficient of thermal expansion of the fourth interconnect pattern 615 may be greater than the coefficient of thermal expansion of the fourth bonding pad 650. For example, the coefficient of thermal expansion of the fourth interconnect pattern 615 may be greater than 18 ppm / K and may be less than or equal to 50 ppm / K. The coefficient of thermal expansion of the fourth bonding pad 650 may be in the range of 5 ppm / K to 18 ppm / K.

[0131] The fourth semiconductor wafer 600 may be connected to the interposer substrate 900 in a direct bonding manner. For example, the fourth bonding pad 650 and the corresponding interposer bonding pad 950 may be connected to each other in a direct bonding manner. There may be no observable interface between the fourth bonding pad 650 and the interposer bonding pad 950. Since the fourth interconnect pattern 615 is disposed on the fourth bonding pad 650, a direct bonding structure between the fourth bonding pad 650 and the interposer bonding pad 950 may be well formed. The dielectric layer 921 and the fourth insulating layer 621 may be connected to each other in a direct bonding manner. A chemical bond may be provided between the dielectric layer 921 and the fourth insulating layer 621.

[0132] The fourth semiconductor wafer 600 may be electrically connected to the solder ball 500 via the interposer substrate 900.

[0133] The semiconductor package 1 may further include a second molding layer 420. The second molding layer 420 may be disposed on the interposer substrate 900 to cover or surround the side surfaces of the chip stack 10 and the side surfaces of the fourth semiconductor chip 600. The second molding layer 420 may be disposed to expose the top surfaces of the chip stack 10 and the fourth semiconductor chip 600. The second molding layer 420 may be formed of or include an insulating polymer (e.g., an epoxy molding compound).

[0134] FIG. 6C is a diagram showing a direct bonding structure between a first semiconductor chip and an interposer substrate according to an embodiment of the inventive concept, and is an enlarged cross-sectional view showing a portion V' of FIG. 6A. Hereinafter, embodiments of the present invention will be described with reference to FIG. 6C in combination with FIG. 6A.

[0135] Referring to FIG. 6C, the first conductive pad 150 and the interposer bonding pad 950 may be connected to each other in a direct bonding manner. However, the first conductive pad 150 may include a protruding portion that is partially inserted into the first interconnect pattern 125. The top surface of the first conductive pad 150 may be disposed at a level higher than the bottom surface of the first interconnect pattern 125. Here, the bottom surface of the first interconnect pattern 125 may be covered by the first insulating layer 121.

[0136] FIG. 7 is a diagram showing a semiconductor package according to an embodiment of the inventive concept. For simplicity of description, the previously described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0137] Referring to FIG. 7, the semiconductor package 1A may include an interposer substrate 900, solder balls 500, a chip stack 10A, and a fourth semiconductor chip 600. The chip stack 10A may be substantially the same as the chip stack in the embodiments of FIGS. 5A and 5B. For example, the first semiconductor chip 100 may not include the first interconnect pattern 125.

[0138] The semiconductor package 1A may further include a first bump 810, a second bump 820, and an underfill layer 430. The first bump 810 may be inserted between the interposer substrate 900 and the first semiconductor chip 100. The first bump 810 may be coupled to the interposer bonding pad 950 and the first bonding pad 155. The first bump 810 may include at least one of a solder ball and a metal pillar.

[0139] The second bump 820 can be inserted between the interposer substrate 900 and the fourth semiconductor chip 600. The fourth semiconductor chip 600 may include a plurality of fourth bonding pads 650. The second bump 820 can be coupled to the fourth bonding pad 650 and the interposer bonding pad 950. The second bump 820 may include at least one of a solder ball and a metal pillar.

[0140] The underfill layer 430 can be inserted between the interposer substrate 900 and the first semiconductor chip 100 to hermetically seal the first bump 810. The underfill layer 430 can further extend into the gap region between the interposer substrate 900 and the fourth semiconductor chip 600 to hermetically seal the second bump 820. The underfill layer 430 can be formed of or include an insulating polymer.

[0141] According to an embodiment of the inventive concept, the first semiconductor chip may include first bonding pads disposed on its top surface. The second semiconductor chip may be disposed on the first semiconductor chip. The second semiconductor chip may include a second interconnect pattern and second bonding pads. The second bonding pads can be directly bonded to the first bonding pads. The second interconnect pattern can be disposed on the top surface of the second bonding pads. The second interconnect pattern can be configured to apply a force to the first bonding pads and the second bonding pads during the process of directly bonding the first bonding pads to the second bonding pads. Accordingly, it is possible to form a good direct bonding structure between the first bonding pads and the second bonding pads. Accordingly, it is possible to improve the electrical characteristics between the first semiconductor chip and the second semiconductor chip and the reliability characteristics of the semiconductor package.

[0142] Although the exemplary embodiments of the inventive concept have been specifically illustrated and described, those of ordinary skill in the art will understand that changes in form and detail may be made herein without departing from the scope of the appended claims.

[0143] 1: Semiconductor package 10, 10A: Chip stack 100: First semiconductor chip 110: First semiconductor substrate 115: First integrated circuit 117: First liner layer 120: First interconnect layer 121: First insulating layer 123: First interconnect structure 125: First interconnect pattern 125B: First barrier layer 125M: First metal wire 130: First backside insulating layer 150: First conductive pad 150B: Lower barrier pad 150M: Lower metal pad 155: First bonding pad 155B: First barrier pad 155M: First metal pad 170: First through via 170B: First via barrier layer 170M: First conductive via 200: Second semiconductor wafer 200A: Second lower semiconductor wafer 200B: Second intermediate semiconductor wafer 200C: Second upper semiconductor wafer 210: Second semiconductor substrate 215: Second integrated circuit 217: Second liner layer 220: Second interconnect layer 221: Second insulating layer 221u1: First bottom surface 221u2: Second bottom surface 223: Second interconnect structure 225: Second interconnect pattern 225B: Second barrier layer 225BB: Second lower barrier layer 225M: Second metal line 230: Second backside insulating layer 250: Second bonding pad 250B: Second barrier pad 250M: Second metal pad 255: Second upper bonding pad 255B: Second upper barrier pad 255M: Second upper metal pad 270: Second through via 270B: Second via barrier layer 270M: Second conductive via 300: Third semiconductor wafer 310: Third semiconductor substrate 315: Third integrated circuit 320: Third interconnect layer 321: Third insulating layer 323: Third interconnect structure 325: Third interconnect pattern 325B: Third barrier layer 325M: Third metal line 350: Third bonding pad 350B: Third barrier pad 350M: Third metal pad 400: First molding layer 420: Second molding layer 430: Underfill layer 500: Solder ball 600: Fourth semiconductor chip 615: Fourth interconnect pattern 621: Fourth insulating layer 650: Fourth bonding pad 810: First bump 820: Second bump 900: Interposer substrate 905: Bonding pad 910: Interposer die 920: Interposer interconnect layer 921: Dielectric layer 922: Conductive pattern 923: Conductive structure 950: Interposer bonding pad 950B: Fourth barrier pad 950M: Fourth metal pad 970: Metal via I, II, III, IV, V, V': Portions T1: First thickness T2: Second thickness T3: Third thickness T10, T11, T20, T21, T30, T40: Thicknesses W1: First width W2: Second width W3: Third width W10, W11, W12, W20, W21, W22, W30: Widths θ1, θ2, θ10, θ15, θ20, θ25: Angles

Claims

1. A semiconductor package, comprising: First semiconductor chip; The first semiconductor wafer comprises a first semiconductor substrate, a first bonding pad on the top surface of the first semiconductor substrate, and a first through-hole on the bottom surface of the first bonding pad and through the first semiconductor substrate. The second semiconductor wafer comprises a second semiconductor substrate, a second interconnect pattern on the bottom surface of the second semiconductor substrate, and a second bonding pad on the bottom surface of the second interconnect pattern and coupled to the second interconnect pattern. The second bonding pad is directly bonded to the first bonding pad. The width of the first through-hole is less than the width of the first bonding pad. The width of the second interconnect pattern is greater than the width of the second bonding pad. The angle between the bottom surface and the side surface of the second bonding pad is an acute angle, and the angle between the bottom surface and the side surface of the second interconnect pattern is an obtuse angle.

2. The semiconductor package of claim 1, wherein the second interconnect pattern contacts the top surface of the second bonding pad, and the first through-hole contacts the bottom surface of the first bonding pad.

3. The semiconductor package as claimed in claim 1, wherein the first bonding pad comprises: The first top surface portion contacts the second bonding pad; And the second top surface portion, which does not contact the second bonding pad.

4. The semiconductor package of claim 1, wherein the width of the first bonding pad is greater than the width of the second bonding pad, and the thickness of the first bonding pad is less than the thickness of the second bonding pad.

5. The semiconductor package as claimed in claim 1, wherein the thickness of the second interconnect pattern is 0.5 to 1.5 times the thickness of the second bonding pad.

6. The semiconductor package of claim 1, wherein the coefficient of thermal expansion of the second interconnect pattern is greater than the coefficient of thermal expansion of the second bonding pad.

7. The semiconductor package as claimed in claim 1, wherein the second interconnect pattern comprises: Metal wire; and a barrier pattern on the top surface of the metal wire, wherein the second bonding pad comprises: a metal pad; And a barrier pad, covering the bottom and side surfaces of the metal pad, wherein the metal wire comprises a metal element different from the metal element of the metal pad.

8. The semiconductor package as claimed in claim 7, wherein the metal pad comprises copper and the metal wire comprises aluminum, tin and / or zinc.

9. The semiconductor package of claim 1, further comprising a third semiconductor wafer on the top surface of the second semiconductor wafer, wherein the second semiconductor wafer comprises: The second through-hole passes through the second semiconductor substrate; The third semiconductor wafer includes: a third semiconductor substrate; a third interconnect pattern on the bottom surface of the third semiconductor substrate; and a third bonding pad on the bottom surface of the third interconnect pattern and coupled to the third interconnect pattern, wherein the third bonding pad is directly bonded to the second upper bonding pad, and the width of the third interconnect pattern is greater than the width of the third bonding pad.

10. The semiconductor package of claim 9, wherein the width of the second through-hole is less than the width of the second upper bonding pad.

11. A semiconductor package, comprising: First base; The first pad is on the top surface of the first substrate; The first conductive pattern is in contact with the bottom surface of the first pad; and a semiconductor wafer on the top surface of the first substrate, wherein the semiconductor wafer comprises: a semiconductor substrate; an interconnect layer on the bottom surface of the semiconductor substrate, the interconnect layer comprising an interconnect pattern; and a bonding pad coupled to the bottom surface of the interconnect pattern, the bonding pad being directly bonded to the first pad, the width of the interconnect pattern being greater than the width of the bonding pad, and the width of the first conductive pattern being less than the width of the first pad, wherein the angle between the bottom surface and the side surface of the bonding pad is an acute angle, and the angle between the bottom surface and the side surface of the interconnect pattern is an obtuse angle.

12. The semiconductor package of claim 11, wherein the interconnect layer further includes an insulating layer, and the top surface of the first pad includes: The first top surface portion is in contact with the bonding pad; And the second top surface portion, which is in contact with the insulating layer.

13. The semiconductor package of claim 11, wherein the first substrate includes an interposer die and the first pad includes an interposer pad.

14. The semiconductor package of claim 11, further comprising an integrated circuit on the bottom surface of the first substrate, wherein the first conductive pattern includes a first through-hole through the first substrate.

15. A semiconductor package, comprising: First semiconductor chip; The first semiconductor wafer comprises: a first semiconductor substrate; a first integrated circuit on a bottom surface of the first semiconductor substrate; a first interconnect layer on the bottom surface of the first semiconductor substrate, the first interconnect layer including a first insulating layer and a first interconnect structure; a first back-side insulating layer on the top surface of the first semiconductor substrate; a first through-hole in the first semiconductor substrate and electrically connected to the first interconnect structure; and a first bonding pad on the top surface of the first through-hole and in the first back-side insulating layer and coupled to the first through-hole. The second semiconductor wafer comprises: a second semiconductor substrate; a second integrated circuit on a bottom surface of the second semiconductor substrate; a second interconnect layer on the bottom surface of the second semiconductor substrate, the second interconnect layer including a second insulating layer, a second interconnect structure, and a second interconnect pattern; and a second bonding pad in contact with the bottom surface of the second interconnect pattern, the second bonding pad being directly bonded to the first bonding pad, and the second insulating layer being directly bonded to the first back-side insulating layer. The width of the bottom surface of the second interconnect pattern is greater than the width of the bottom surface of the second bonding pad, and the width of the top surface of the first bonding pad is greater than the width of the first through-hole.

16. The semiconductor package of claim 15, wherein the width of the top surface of the first bonding pad is greater than the width of the bottom surface of the second bonding pad, and the thickness of the first bonding pad is less than the thickness of the second bonding pad.

17. The semiconductor package of claim 15, wherein the width of the bottom surface of the second bonding pad is greater than the width of the top surface of the second bonding pad, and the width of the bottom surface of the second interconnect pattern is less than the width of the top surface of the second interconnect pattern.

18. The semiconductor package of claim 15, wherein the second interconnect pattern has a coefficient of thermal expansion greater than that of the second bonding pad, and the thickness of the second interconnect pattern is 0.5 to 1.5 times the thickness of the second bonding pad.

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