Semiconductor package, semiconductor bonding structure, and method of fabricating the same

Abstract

This invention relates to a semiconductor package, a semiconductor bonding structure, and a method for forming the same. The semiconductor package includes a first wafer, a second wafer, and conductive structures. The conductive structures are disposed on one side of the second wafer and located on the second upper surface of a first interconnect structure to electrically connect to the first interconnect structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnect structures, a plurality of wafers, and a plurality of conductive structures. The conductive structures are respectively disposed on one side of each wafer and located on the second upper surface of each first interconnect structure to electrically connect to each first interconnect structure.

Description

Semiconductor package, semiconductor bonding structure and its formation method This invention relates to the field of semiconductor technology, and in particular to semiconductor packages, semiconductor bonding structures, and methods for forming semiconductors. In the advanced semiconductor industry, by gradually reducing the size of components, the density of various electronic components can be continuously increased, allowing more electronic components to be integrated and placed in a specific area at the same time, occupying a relatively small package volume. Three-dimensional integrated circuits (3DIC) refer to the transformation of traditional two-dimensional chips into three-dimensional stacked chips using wafer-level bonding and through-silicon via (TSV) technologies. Because 3DICs can effectively utilize space and shorten circuit transmission distances, providing extremely low-resistance connections, they have gradually become the mainstream technology for components such as power converters, low-noise amplifiers, and radio frequency (RF) or millimeter-wave (MMW) devices. Furthermore, 3DICs can also be implemented by placing chips on wafer-level wafers and forming bonding interfaces between chips through a hybrid bonding process. This hybrid bonding process (also known as "metal / dielectric hybrid bonding") is a technique that directly forms bonds on the surface of interconnect structures without the use of solder bonds or adhesives, allowing metal-to-metal bonding and dielectric-to-dielectric bonding to occur simultaneously. Thus, this hybrid bonding process overcomes the process limitations of microbump technology. However, current three-dimensional integrated circuits still have many problems that need to be improved and require further refinement. The present invention aims to provide a semiconductor package, a semiconductor bonding structure, and a method for forming the same. The semiconductor package is formed using a copper-to-copper wafer bonding method, with the wafer and conductive structure respectively bonded to the two upper surfaces of the wafer's interconnect structure. This not only replaces through-silicon via (TSV) structures, eliminating the process complexity and cost savings of TSVs, but also improves upon potential structural defects arising from TSVs. Therefore, the present invention can form a more structurally reliable semiconductor package while simplifying the manufacturing process. Furthermore, the conductive structure is positioned above the wafer within the semiconductor package to facilitate the installation of input / output terminals in subsequent processes. An embodiment of the present invention provides a semiconductor package including a first wafer, a second wafer, and a conductive structure. The first wafer includes a first substrate and a first interconnect structure disposed on the first substrate, wherein an upper surface of the first interconnect structure includes a first upper surface and a second upper surface. The second wafer is stacked on the first wafer and includes a second substrate and a second interconnect structure disposed on the second substrate, wherein the second interconnect structure directly contacts and is electrically connected to the first upper surface of the first interconnect structure, and the conductive structure is disposed on one side of the second wafer and located on the second upper surface of the first interconnect structure to electrically connect to the first interconnect structure. Another embodiment of the present invention provides a semiconductor bonding structure, including a first substrate, a plurality of first interconnect structures, a plurality of wafers, and a plurality of conductive structures. The first interconnect structures are disposed on the first substrate, wherein an upper surface of each first interconnect structure includes a first upper surface and a second upper surface. The wafers are disposed on and electrically connected to the first interconnect structures. Each wafer includes a second substrate and a second interconnect structure disposed on the second substrate, wherein the second interconnect structure directly contacts and electrically connects to the first upper surface of each first interconnect structure. The conductive structures are respectively disposed on one side of each wafer and located on the second upper surface of each first interconnect structure to electrically connect to the first interconnect structures respectively. An embodiment of the present invention provides a method for forming a semiconductor bonding structure, comprising the following steps: First, a first semiconductor structure is formed, the first semiconductor structure including a first substrate and a first interconnect structure disposed on the first substrate, the upper surface of the first interconnect structure including a first upper surface and a second upper surface. Next, a second semiconductor structure is formed, the second semiconductor structure including at least one wafer. Then, the second semiconductor structure is bonded to the first upper surface of the first interconnect structure of the first semiconductor structure. Furthermore, at least one conductive structure is formed on one side of the second semiconductor structure, the conductive structure being located on the second upper surface of the first interconnect structure to electrically connect the first interconnect structure. To enable those skilled in the art to further understand this invention, several preferred embodiments are provided below, along with accompanying drawings, to explain in detail the structure and desired effects of the invention. Furthermore, without departing from the spirit of the invention, the technical features in the different embodiments described below can be substituted, rearranged, or combined to form other embodiments. Please refer to Figures 1 to 6, which illustrate schematic diagrams of the semiconductor bonding structure and the method for forming a semiconductor package according to the first embodiment of the present invention. First, as shown in Figure 1, a semiconductor structure is provided, such as a wafer-level semiconductor structure, which includes an initial substrate 100 and at least one interconnect structure 106. The initial substrate 100 is, for example, a silicon substrate, an epitaxial silicon substrate, a silicon-containing substrate (SiC or SiGe), a group III-V semiconductor substrate, or a substrate containing other suitable materials, and has two opposing surfaces 102 and 104. In this embodiment, a plurality of interconnect structures 106 are formed and disposed adjacent to each other on the surface 104 of the initial substrate 100, and are respectively located in a plurality of die regions (not shown) on the initial substrate 100. Each die region may include different types of chips or is expected to provide different functions, such as display driver integrated circuit (DDIC), radio frequency (RF), dynamic random access memory (DRAM), static random access memory (SRAM) or driver chip, but is not limited thereto. The interconnect structure 106 includes, for example, a plurality of dielectric layers (not shown) stacked in sequence and a plurality of conductive layers (not shown) disposed within each dielectric layer. The dielectric layer includes, for example, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, and the conductive layer includes, for example, a low-resistivity metal such as copper (Cu), aluminum (Al), tungsten (W), or titanium (Ti), preferably copper, but not limited thereto. It should be noted that each interconnect structure 106 also includes at least one bonding pad 108, 109, which is embedded within the interconnect structure 106, such that the surfaces of bonding pads 108 and 109 can be exposed from an upper surface 106a, 106b of the interconnect structure 106, respectively. The upper surfaces 106a and 106b may be coplanar and located on a top surface of the interconnect structure 106, but are not limited thereto. In another embodiment, depending on the actual device requirements, the surfaces of bonding pads 108 and 109 may be exposed from two non-coplanar upper surfaces (not shown). Furthermore, although this embodiment uses the example of one bonding pad 108 on each opposite side of the bonding pad 109 for subsequent description, those skilled in the art should readily understand that the specific number or position of bonding pads 108 and / or bonding pads 109 is not limited to those shown in Figure 1 and can be further adjusted according to the needs of the actual device. Next, another semiconductor structure is provided, such as a wafer-level semiconductor structure. This other semiconductor structure includes, for example, an initial substrate 200 (e.g., a silicon substrate, epitaxial silicon substrate, silicon-containing substrate, group III-V semiconductor substrate, etc.) having two opposing surfaces 202 and 204, and at least one interconnect structure 206. In this embodiment, a plurality of interconnect structures 206 are formed, disposed adjacent to each other on the surface 204 of the initial substrate 200, respectively located in a plurality of wafer regions (not shown) on the initial substrate 200. Each interconnect structure 206 also includes a plurality of dielectric layers (not shown) stacked sequentially and a plurality of conductive layers (not shown) disposed within each dielectric layer. The materials of the dielectric layer and the conductive layer are generally the same as those of the interconnect structure 106, and will not be described again here. Furthermore, those skilled in the art will readily understand that the specific number of interconnect structures 106 and / or 206 is not limited to that shown in Figure 1, and can be further adjusted according to the number of chip areas required in the actual device. In this embodiment, the other semiconductor structure also includes a plurality of dicing channels 208 formed at the junctions of each wafer region. Thus, during the subsequent wafer sawing process, the dicing channels 208 can cut the initial substrate 200 and the plurality of interconnect structures 206 of the other semiconductor structure into a plurality of wafers (die) 210 as shown in Figure 2. Each wafer 210 includes a cut substrate 200a and an interconnect structure 206 located on the surface 204 of the substrate 200a. As shown in Figure 2, the semiconductor structure and wafer 210 are placed on a die bond machine (not shown) to bond the wafer 210 to the semiconductor structure. In this embodiment, die bonding is performed by attaching the interconnect structure 206 of the wafer 210 to the upper surface 106b of the interconnect structure 106 located in the semiconductor structure, exposing the upper surfaces 106a on both sides (i.e., the surfaces of the bonding pads 108). In this configuration, at least one of the conductive layers in the interconnect structure 206 can directly contact the bonding pads 109 in the interconnect structure 106, allowing the wafer 210 to be electrically connected to the semiconductor structure. Furthermore, in this embodiment, a wafer thinning process can be selectively performed before the wafer dicing process, for example, by performing a chemical mechanical polishing (CMP) process or an etching process on the surface 202 of the initial substrate 200 to reduce the overall thickness of the initial substrate 200 and form surface 202a. Those skilled in the art will readily understand that the substrate thickness reduced by this wafer thinning process can be adjusted according to actual process requirements to avoid excessively increasing the overall thickness and causing structural defects after the subsequent molding layer is formed. Furthermore, reducing the substrate thickness can also increase heat dissipation performance. As shown in Figure 3, a capping layer 110 is formed on the upper surface 106a of the interconnect structure 106, covering the surface of the bonding pads 108. Specifically, the capping layer 110 is formed on the bonding pads 108 on both sides of the wafer 210 through a deposition process (such as a redox deposition process) or an electroplating process (such as electroless plating or chemical plating) to prevent metal oxidation of the bonding pads 108. In this embodiment, the capping layer 110 may include a protective conductive material, such as a metal that is not easily oxidized, such as tin (Sn), gold (Au), palladium (Pd), nickel (Ni), and silver (Ag), preferably a solder bond, but not limited thereto. In another embodiment, the capping layer may also include a protective non-conductive material. As shown in Figure 4, a molding layer 112 is formed on the semiconductor structure and the wafer 210 to cover the wafer 210 and the first interconnect structure 106, so as to present an overall semiconductor structure similar to a wafer-level structure. Specifically, the molding layer 112 includes a plurality of openings 114, each opening 114 corresponding to a bonding pad 108 below it, thereby exposing the cover layer 110 above the bonding pad 108 through each opening 114. In one embodiment, the openings 114 are fabricated, for example, through a photolithography and etching process, a dry etching process, or a laser ablation process. Preferably, the laser ablation process is used, with the cover layer 110 serving as a stop layer to save on manufacturing costs, but this is not a limitation. As shown in Figure 5, at least one conductive structure is formed on the semiconductor structure. In this embodiment, the conductive structure includes, for example, at least one solder pillar 116 that fills at least the opening 114 shown in Figure 4. The solder pillar 116 may be made of materials such as tin, gold, or palladium, but is not limited thereto. In a preferred embodiment, the solder pillar 116 may include the same material as the cover layer 110, such as both being solder balls. In this way, the solder pillar 116 can be formed using a reflow process, so that the solder pillar 116 and the underlying cover layer 110 can form an integrally formed structure, but is not limited thereto. It should be noted that the solder post 116 is partially disposed within the encapsulation layer 112 and partially protrudes from the top surface of the encapsulation layer 112, so that the bottom of the solder post 116 can directly contact or contact the bonding pad 108 through the cover layer 110, thereby electrically connecting with the interconnect structure 106, while the top of the solder post 116 protrudes from the encapsulation layer 112 to facilitate the setting of input / output terminals (I / O) in subsequent processes. Subsequently, in the subsequent wafer dicing process, the semiconductor structure can be diced into a plurality of wafers 120 as shown in Figure 6 by forming a plurality of dicing paths 118 at the junctions of each wafer region, thereby cutting the initial substrate 100 and a plurality of interconnect structures 106. Each wafer 120 includes, for example, the diced substrate 100a and the interconnect structure 106 located on the surface 104 of the substrate 100a, and simultaneously forming a plurality of semiconductor packages 300 as shown in Figure 6. Thus, the semiconductor bonding structure and the semiconductor package formation method in the first embodiment of the present invention are completed. The semiconductor package 300 can continue to undergo subsequent packaging processes, and the bonding pillars 116 provided on the semiconductor package 300 are correspondingly packaged to a circuit board (not shown) or other secondary packaging substrate to produce the required integrated circuit; or, the semiconductor package 300 can also be directly used as a chip scale package (CSP) for wafer-level packaging to facilitate thin and small packaging applications. As shown in Figure 6, the semiconductor package 300 formed by the method of this embodiment includes a wafer 120, a wafer 210 stacked on the wafer 120, and a conductive structure (such as a bonding pillar 116). The wafer 210 is electrically connected to the wafer 120 by directly contacting the upper surface 106b of the interconnect structure 106 provided thereon, thus eliminating the need for additional through-silicon vias. It should be noted that a bonding pillar 116 is further provided on the upper surface 106a of the interconnect structure 106 of the wafer 120 as the conductive structure. The bonding pillar 116 is located on one side of the wafer 210 and electrically connected to the bonding pad 108 embedded within the interconnect structure 106. Furthermore, a portion of the bonding pillar 116 protrudes beyond the top surface of the packaging layer 112 and is higher than the surface 202a of the wafer 210. This facilitates the placement of the input / output terminals around the perimeter of the semiconductor package 300 in subsequent processes. Those skilled in the art will readily understand that, to meet actual product requirements, the method for forming the semiconductor package and / or semiconductor bonding structure of the present invention may have other forms, and is not limited to those described in the foregoing embodiments. The following will further describe other embodiments or variations of the method for forming the semiconductor package and / or semiconductor bonding structure of the present invention. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical elements in the embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments. Please refer to Figures 7 and 8, which illustrate schematic diagrams of the semiconductor bonding structure and the method for forming a semiconductor package in the second embodiment of the present invention. The formation method of this embodiment is generally the same as that of the previous embodiments, as shown in Figures 1 to 4, and the similarities will not be repeated here. The main difference between this embodiment and the previous embodiments is that the conductive structure of this embodiment includes at least one redistribution layer (RDL) 122 and at least one solder ball 126. In detail, as shown in Figure 7, a redistribution layer 122 is formed on the package layer 112. The fabrication of the redistribution layer 122 includes, but is not limited to, the following steps: First, a redistribution material layer (not shown) is formed using an electroplating process, conformally covering the surfaces of the package layer 112 and each opening 114 as shown in Figure 4, and positioned on the upper surface 106a. Next, through a patterning process, the redistribution material layer is partially removed, forming a plurality of recesses 124 to expose the underlying package layer 112, while simultaneously forming the redistribution layer 122. Thus, the redistribution layer 122 can electrically connect to the bonding pads 108 within the interconnect structure 106 and export their signals to the surface 202a of each chip 210, serving as a path for the bonding pads 108 to electrically connect with other signals. Then, solder balls 126 are correspondingly formed on each redistribution layer 122, such that each solder ball 126 can be positioned on the surface 202a of each chip 210. It should be noted that although this embodiment only shows the solder balls 126 arranged sequentially on each chip 210, those skilled in the art will easily understand that the specific positions and quantities of the solder balls 126 and the redistribution layer 122 can be adjusted according to the input / output terminal configuration requirements in the actual device. For example, in one embodiment, from a top view (not shown), the solder balls 126 can be arranged in an array arrangement (not shown) or a matrix arrangement (not shown) to facilitate the configuration of a relatively large number of input / output terminals, but this is not a limitation. Subsequently, in the subsequent wafer dicing process, the semiconductor structure can be diced into a plurality of wafers 130 as shown in Figure 8 by forming a plurality of dicing paths 128 at the junctions of each wafer region, thereby cutting the initial substrate 100 and a plurality of interconnect structures 106. Each wafer 130 includes, for example, the diced substrate 100a and the interconnect structure 106 located on the surface 104 of the substrate 100a, and simultaneously forming a plurality of semiconductor packages 302 as shown in Figure 8. Thus, the semiconductor bonding structure and semiconductor package formation method of the second embodiment of the present invention are completed. The semiconductor package 302 can also be further packaged onto a circuit board or other secondary packaging substrate to produce the required integrated circuit, or directly used as a wafer-level packaged crystal-scale package. As shown in Figure 8, the semiconductor package 302 formed by the method of this embodiment includes a wafer 130, a wafer 210 stacked on the wafer 130, and a conductive structure (including a redistribution layer 122 and solder balls 126). The connection method between the wafer 130 and the wafer 210 is generally the same as that of the semiconductor package 300 in the first embodiment, and will not be described again here. It should be noted that a redistribution layer 122 and solder balls 126 are further provided on the upper surface 106a of the interconnect structure 106 of the wafer 130 as the conductive structure. The redistribution layer 122 directly covers the surface of each opening 114 as shown in Figure 4, so as to directly contact the cover layer 110 at the bottom of each opening 114 and further extend to the top surface of the package layer 112. In this way, the solder balls 126 can be placed on the surface 202a of the wafer 210 and above the top surface of the package layer 112, thereby significantly increasing the placement position of the input / output terminal. Please refer to Figures 9 to 11, which illustrate schematic diagrams of the semiconductor bonding structure and the method for forming a semiconductor package in the third embodiment of the present invention. The formation method of this embodiment is generally the same as that of the formation method in the second embodiment described above, and the similarities will not be repeated here. The main difference between this embodiment and the previous embodiment is that a protective layer 134 is additionally provided on the redistribution layer 122 to protect the redistribution layer 122. In detail, as shown in Figure 9, a protective material layer 132 is formed, conformally covering the redistribution layer 122 and the encapsulation layer 112, and partially filling the opening 114 shown in Figure 4. The protective material layer 132 may include, for example, polyimide (PI), polyethylene (PVO), or other materials suitable as a passivation layer, but is not limited thereto. As shown in Figure 10, a patterning process is performed, partially removing the protective material layer 132 and exposing the underlying redistribution layer 122 to form a protective layer 134. Then, solder balls 136 are formed on the exposed redistribution layers 122. Thus, each solder ball 136 can also be located on the surface 202a of each wafer 210, and a portion of the protective layer 134a can be further sandwiched between each solder ball 136 and the underlying redistribution layer 122. Subsequently, in a subsequent wafer dicing process, the semiconductor structure can be diced from the initial substrate 100 and the plurality of interconnect structures 106 into a plurality of wafers 140 as shown in Figure 11 by forming a plurality of dicing paths 138 at the junctions of each wafer region. Each wafer 140 includes, for example, the diced substrate 100a and the interconnect structure 106 located on the surface 104 of the substrate 100a, and simultaneously forms a plurality of semiconductor packages 304 as shown in Figure 11. Thus, the semiconductor bonding structure and semiconductor package formation method in the third embodiment of the present invention are completed. The semiconductor package 304 can also continue to undergo subsequent packaging processes and be correspondingly packaged to a circuit board or other secondary packaging substrate by solder balls 136 to produce the required integrated circuit, or directly as a wafer-level packaged crystal-scale package. As shown in Figure 11, the semiconductor package 304 formed by the method of this embodiment includes a wafer 140, a wafer 210 stacked on the wafer 140, and the conductive structure (including a redistribution layer 122 and solder balls 136). The connection method between the wafer 140 and the wafer 210 is generally the same as that of the semiconductor packages 300 and 302 in the previous embodiments, and will not be described again here. It should be noted that a protective layer 134 is additionally provided between the redistribution layer 122 and the solder balls 136 to protect the underlying redistribution layer 122. Please refer to Figure 12, which illustrates a schematic diagram of the semiconductor bonding structure and the method for forming a semiconductor package in the fourth embodiment of the present invention. The formation method of this embodiment is generally the same as that of the previous embodiments, and the similarities will not be repeated here. The main difference between this embodiment and the previous embodiments is that the cover layer 110 in this embodiment includes a non-conductive material with protective capabilities, such as a dielectric material. Thus, when forming the opening 144 through the photolithography process, the dry etching process, or the laser ablation process, it is necessary to further penetrate the cover layer 110 to expose the underlying bonding pad 108. In one embodiment, the cover layer 110 may be completely removed or partially removed until the bonding pad 108 is exposed, leaving a portion of the cover layer 110a at the bottom of the opening, as shown in FIG12. Therefore, the subsequently formed conductive structure, such as the solder pillar 116 in the first embodiment or the redistribution layer 122 in the second embodiment, can directly contact the underlying bonding pad 108 and be electrically connected to the interconnect structure 106. Under this configuration, the semiconductor package (not shown) formed by the method of this embodiment can also have the conductive structure disposed on the upper surface 106a of the interconnect structure 106, so that the conductive structure is located on one side of the wafer 210 and partially protrudes from the top surface of the package layer 112, facilitating the subsequent placement of input / output terminals. Overall, the method of this invention forms a package by bonding a wafer to a copper-copper interface. This eliminates the complexity and cost of conventional through-silicon via (TSV) fabrication, avoids the stress effects of TSVs on the substrate, and saves the fabrication space required for TSVs. This simplifies the process and allows for the formation of a more structurally reliable semiconductor package. Furthermore, the semiconductor package formed by this method involves placing a wafer on one upper surface of an interconnect structure within a wafer-level semiconductor structure. A conductive structure, such as a redistribution layer, solder balls, and / or solder pillars, is disposed on the other upper surface of the interconnect structure. This conductive structure can be positioned above the upper surface of the wafer to facilitate the placement of input / output terminals in subsequent processes. Thus, the package of this invention can be directly used as a wafer-level package for crystal-scale applications, enabling thin and compact packaging, or it can be further packaged onto a circuit board or other secondary packaging substrate to fabricate the required integrated circuit. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention. 100, 200: Initial substrate; 100a, 200a: Substrate; 102, 104: Surface; 202a: Surface; 106, 206: Interconnect structure; 106a, 106b: Top surface; 108, 109: Bonding pads; 110: Cover layer; 110a: Partial cover layer; 112: Encapsulation layer; 114, 144: Opening; 116: Solder pillars; 118, 128, 138, 208: Cutter tracks; 120, 130, 140, 210: Wafer; 122: Redistribution layer; 124: Groove; 126, 136: Solder balls; 132: Protective material layer; 134: Protective layer; 134a: Partial protective layer; 300, 302, 304: Semiconductor package. Figures 1 to 6 illustrate schematic diagrams of the semiconductor bonding structure and the method for forming a semiconductor package according to the first embodiment of the present invention, wherein: Figure 1 is a cross-sectional schematic diagram of the semiconductor bonding structure after forming an interconnect structure; Figure 2 is a cross-sectional schematic diagram of the semiconductor bonding structure after forming and bonding a wafer; Figure 3 is a cross-sectional schematic diagram of the semiconductor bonding structure after forming a capping layer; Figure 4 is a cross-sectional schematic diagram of the semiconductor bonding structure after forming a package layer and an opening; Figure 5 is a cross-sectional schematic diagram of the semiconductor bonding structure after forming a conductive structure; and Figure 6 is a cross-sectional schematic diagram of the semiconductor bonding structure after forming a semiconductor package. Figures 7 and 8 illustrate schematic diagrams of the semiconductor bonding structure and the method for forming a semiconductor package according to the second embodiment of the present invention, wherein: Figure 7 is a cross-sectional schematic diagram of the semiconductor bonding structure after forming a conductive structure; and Figure 8 is a cross-sectional schematic diagram of the semiconductor bonding structure after forming a semiconductor package. Figures 9 to 11 illustrate schematic diagrams of the semiconductor bonding structure and the method for forming a semiconductor package according to the third embodiment of the present invention, wherein: Figure 9 is a cross-sectional schematic diagram of the semiconductor bonding structure after the formation of the protective layer; Figure 10 is a cross-sectional schematic diagram of the semiconductor bonding structure after the formation of the conductive structure; and Figure 11 is a cross-sectional schematic diagram of the semiconductor bonding structure after the formation of the semiconductor package. Figure 12 illustrates a schematic diagram of the method for forming a semiconductor bonding structure according to the fourth embodiment of the present invention. 100a: Substrate 102: Surface 104: Surface 106: Internal Wiring Structure 108: Joint Pad 109: Joint Pad 110: Overlay 112: Encapsulation layer 116: Welded column 120: Chip 200a: Substrate 202a: Surface 204: Surface 206: Internal Wiring Structure 210: Chip 300: Semiconductor package

Claims

1. A semiconductor package, comprising: A first wafer includes: a first substrate; and a first interconnect structure disposed on the first substrate, wherein a top surface of the first interconnect structure includes a first upper surface and a second upper surface; a second wafer is stacked on the first wafer, the second wafer including: a second substrate; and a second interconnect structure disposed on the second substrate, wherein the second interconnect structure directly contacts and is electrically connected to the first upper surface of the first interconnect structure; and a conductive structure disposed on one side of the second wafer and located on the second upper surface of the first interconnect structure, the conductive structure being electrically connected to the first interconnect structure, wherein the first upper surface directly contacts and is electrically connected to the second interconnect structure is separated from the second upper surface electrically connected to the conductive structure.

2. The semiconductor package as described in claim 1, wherein, The conductive structure includes at least one welding post, a portion of which protrudes from a surface of the second wafer.

3. The semiconductor package as described in claim 1, wherein, The conductive structure further includes: at least one wiring layer directly disposed on the second upper surface of the first interconnect structure; and at least one solder ball disposed on the at least one wiring layer and located on a surface of the second wafer.

4. The semiconductor package as described in claim 3, wherein, The conductive structure further includes: a protective layer covering the at least one wiring layer, a portion of which is sandwiched between the at least one wiring layer and the at least one solder ball.

5. The semiconductor package as described in claim 1, wherein, The first interconnect structure of the first wafer further includes: a bonding pad embedded in the first interconnect structure, the bonding pad being electrically connected to the conductive structure.

6. The semiconductor package as described in claim 1 further includes: An encapsulation layer covers the second wafer and the first interconnect structure, wherein the conductive structure is partially disposed within the encapsulation layer.

7. A semiconductor bonding structure, comprising: An initial base; A plurality of first interconnect structures are disposed on the initial substrate, wherein a top surface of each first interconnect structure includes a first upper surface and a second upper surface; a plurality of wafers are disposed on and electrically connected to the first interconnect structures, each wafer including: a substrate; and a second interconnect structure disposed on the substrate, wherein the second interconnect structure directly contacts and electrically connects to the first upper surface of each first interconnect structure; and a plurality of conductive structures are respectively disposed on one side of each wafer and located on the second upper surface of each first interconnect structure, the conductive structures being electrically connected to the first interconnect structures, wherein the first upper surface directly contacts and electrically connects to the second interconnect structure is separated from the second upper surface electrically connected to the conductive structure.

8. The semiconductor bonding structure as described in claim 7, wherein, Each conductive structure includes at least one welding post, a portion of which protrudes from a surface of each wafer.

9. The semiconductor bonding structure as described in claim 7, wherein, Each conductive structure further includes: at least one wiring layer directly disposed on the second upper surface of each of the first interconnect structures; and at least one solder ball disposed on the at least one wiring layer and located on a surface of each of the wafers.

10. The semiconductor bonding structure as described in claim 9, wherein, The conductive structure further includes: a protective layer covering the at least one wiring layer, a portion of which is sandwiched between the at least one wiring layer and the at least one solder ball.

11. The semiconductor bonding structure as described in claim 7 further includes: A plurality of bonding pads are embedded in each of the first interconnect structures and electrically connected to the conductive structures.

12. The semiconductor bonding structure as described in claim 7 further includes: An encapsulation layer covers the wafers and the first interconnect structures, wherein each of the conductive structures is disposed within the encapsulation layer.

13. A method for forming a semiconductor junction structure, comprising: A first semiconductor structure is formed, wherein the first semiconductor structure includes a first substrate and a first interconnect structure disposed on the first substrate, and a top surface of the first interconnect structure includes a first upper surface and a second upper surface; a second semiconductor structure is formed, wherein the second semiconductor structure includes at least one wafer; the second semiconductor structure is bonded to the first upper surface of the first interconnect structure of the first semiconductor structure; and at least one conductive structure is formed on one side of the second semiconductor structure and located on the second upper surface of the first interconnect structure to electrically connect the first interconnect structure, wherein the first upper surface bonded to the second semiconductor structure and the second upper surface electrically connected to the conductive structure are separated from each other.

14. The method for forming a semiconductor bonding structure as described in claim 13, wherein the at least one wafer further comprises: A second basement; And a second interconnect structure formed on the second substrate, wherein the second interconnect structure directly contacts and electrically connects to the first upper surface of the first interconnect structure.

15. The method for forming a semiconductor bonding structure as described in claim 13, further comprising: Provide an initial base; A plurality of second interconnect structures are formed on the initial substrate; And to cut the initial substrate and the second interconnect structures into a plurality of the second semiconductor structures.

16. The method for forming a semiconductor bonding structure as described in claim 13 further includes: At least one bonding pad is formed within the first interconnect structure, wherein the at least one bonding pad is exposed from the second upper surface of the first interconnect structure; a capping layer is formed on the at least one bonding pad; an encapsulation layer is formed to cover the second semiconductor structure and the first interconnect structure; at least one opening is formed within the encapsulation layer to expose the capping layer; and at least one conductive structure is formed within the at least one opening, the at least one conductive structure being in direct contact with the capping layer.

17. The method for forming a semiconductor bonding structure as described in claim 16, wherein, The overlay includes a conductive material.

18. The method for forming a semiconductor bonding structure as described in claim 16, wherein, The at least one conductive structure includes at least one welded post filled within the at least one opening.

19. The method for forming a semiconductor bonding structure as described in claim 16 further includes: At least one wiring layer is formed, covering a surface of the at least one opening and positioned on the second semiconductor structure; And at least one solder ball is formed on the at least one wiring layer, located on the second semiconductor structure.

20. The method for forming a semiconductor bonding structure as described in claim 19 further includes: A protective layer is formed on the at least one wiring layer, wherein a portion of the protective layer is sandwiched between the at least one wiring layer and the at least one solder ball.

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