Computing system

Abstract

Systems, devices, and methods can provide a technology for including: a voltage regulator, a board assembly including a die and a circuit board electrically coupled to a first side of the die, and a heat dissipation assembly thermally and electrically coupled to a second side of the die, wherein the heat dissipation assembly is further electrically coupled to the voltage regulator. In one embodiment, the heat dissipation assembly includes a thermally conductive plate, and the technology further includes a plurality of copper plates electrically coupled to the voltage regulator and a package substrate containing a die, wherein the plurality of copper plates are further thermally coupled to the thermally conductive plate.

Description

Integrated top-side electric delivery thermal technology Invention Field The embodiments generally relate to power delivery in computing systems. More specifically, the embodiments relate to integrated top-side power delivery thermal technology. Background of the Invention A conventional computing system may include a processing unit die (e.g., a graphics processing unit / GPU die) that receives an operating voltage from a voltage regulator mounted on a motherboard. In this case, the power delivery path may include the motherboard, power contacts on the motherboard, and a package substrate containing the processing unit die. As the TDP (thermal design point) of the computing system increases to meet performance requirements, the losses (e.g., power losses) in the power delivery path from the voltage regulator to the die (e.g., the load) also increase with the square of the current (the square of the current (I) multiplied by the resistance (R)). 2 R). According to one embodiment of the present invention, a computing system is specifically proposed, comprising a voltage regulator; a board assembly including a die and a circuit board electrically coupled to a first side of the die; and a heat dissipation assembly thermally and electrically coupled to a second side of the die, wherein the heat dissipation assembly is further electrically coupled to the voltage regulator. Detailed Description of Preferred Embodiments This embodiment provides a three-dimensional (3D) power architecture integrated into a thermal solution, delivering power from the top side of a semiconductor package to a processing unit die. The techniques described herein can substantially reduce total power loss (e.g., 50-80%, from 60 watts (W) to 30W-12W) and reduce the overall package size by vertically dividing power and I / O (input / output) – primary power enters from the top of the package while I / O enters from the bottom of the vertical stack. This approach helps enhance desired performance while maintaining a relatively small form factor for the package and PCB (printed circuit board) layers. Referring now to Figure 1, a computing system 20 is shown, wherein region 22 contains a fan, region 24 contains a semiconductor package (e.g., containing one or more processing unit chips), and region 26 contains a critical core component. The increase in the width of region 24 28 and the increase in the width of region 26 typically reduces the amount of space available for the fan. Therefore, a negative impact on performance may occur. Figure 2A illustrates a conventional computing system 30, in which a voltage regulator (VR) 32 supplies power to a die 34. In the illustrated example, the power path includes one or more layers of a circuit board 36, a power contact 38, a package substrate 40, and one or more power bumps (e.g., C4 solder bumps) on the bottom side of one of the die 34. Similarly, a ground connection between the die 34 and the voltage regulator 32 includes ground bumps on the bottom surface of the die, the package substrate 40, a ground pin 42, and one or more layers of the circuit board 36. I / O signals are transmitted to the I / O bumps on the bottom side of the die 34 via one or more signal pins 48 and the package substrate 40. The conventional computing system 30 also includes an integrated heat sink (IHS) 44 thermally coupled to the die 34 via a thermally conductive material (e.g., adhesive). In the conventional computing system 30, power loss may be significant due to the voltage drop across the electrical path (e.g., for an operating voltage of 1V and a load of 1A, the worst-case DC resistance is 1.17 mOhm and the power loss is 755 µW). An enhanced computing system 50 includes a voltage regulator 52 supplying power to a die 56. In the illustrated example, the power path includes a heat dissipation assembly, such as, for example, an integrated heat sink 54 (54a, 54b). More specifically, a first heat sink 54a is electrically coupled to the voltage regulator 52 and supplies an operating voltage (e.g., V). CC The voltage regulator 52 carries one or more power bumps on the top side of one of the die 56. Additionally, a second heatsink 54b is electrically coupled to the voltage regulator 52 and provides a ground connection from one or more ground bumps on the top side of the die 56 to a ground connection of the voltage regulator 52. The first heatsink 54a and the second heatsink 54b are electrically isolated from each other. In one embodiment, I / O signals are transmitted via one or more signal pins 58 and the package substrate 60 to I / O through-silicon vias (TSVs) on the bottom side of the die 56. The integrated heatsink 54 is also thermally coupled to the top side of the die 56 to remove heat from the die 56 during operation. The enhanced computing system 50 substantially reduces power consumption (e.g., for an operating voltage of -1V and a load of -1A, the worst-case DC resistance is 0.38 mOhm and the power consumption is 670 µW). Power savings also allow for an increase in the operating frequency of the die 56 (e.g., an increase of 200 MHz, improving performance) while remaining within the same TDP. Furthermore, power and I / O separation helps reduce package size. For example, in a 37.5 x 37.5 mm package with a total of 1200 pins / bumps, including 500 signal pins, 380 ground (GND) pins, and approximately 320 power pins, pin separation reduces the package size to approximately 30 x 30 mm. Figure 2B shows another enhanced computing system 62, in which a circuit board 64 provides a ground connection from the bottom side of a die 66 to a voltage regulator 68. In the illustrated example, an integrated heatsink 70 is thermally and electrically coupled to the top side of the die 66. The integrated heatsink 70 is also electrically coupled to the voltage regulator 68. Therefore, the integrated heatsink 70 provides a power delivery path from the voltage regulator 68 to the top side of the die 66. In the illustrated example, power loss is further reduced (e.g., for an operating voltage of 1 V and a load of 1 A, the worst-case DC resistance is 0.239 mOhm and the power loss is 391 µW). Power savings also make it possible to increase the operating frequency of the die 56 (e.g., by 250 MHz, improving performance) while remaining within the same TDP. Figure 2C shows another enhanced computing system 72, in which a voltage regulator 74 is mounted to a package substrate 76 and supplies power to a die 78, which is also mounted to the package substrate 76. In one embodiment, an integrated heat sink 80 provides a power delivery path from the regulator 74 to the top side of the die 78. In the illustrated example, power loss is further reduced (e.g., for a 1V operating voltage and a 1A load, the worst-case DC resistance is 22 µOhm). Power savings also enable an increase in the operating frequency of the die 78 (e.g., an increase of 350 MHz, improving performance) while remaining within the same TDP. Referring now to Figure 3, a first conventional computing system 82 is shown, in which a VR 84 is mounted to a motherboard 86 and the power delivery path passes through the motherboard 86. A second conventional computing system 88 shows a VR 90 mounted to one of the same package substrates 92 as a processing unit die 94, wherein the power delivery path passes through the package substrate 92. In an enhanced computing system 96, a plurality of VR modules (VRMs) 98 are mounted to a heatsink 100. In one example, the main power pin and ground pin are moved to the top side / surface of a package substrate 104 (e.g., containing multiple chips) to reduce the package size. In one embodiment, the plurality of VRMs 98 resolve power imbalances among multiple chips on the package substrate 104. Therefore, the power path 102 is much shorter than the power paths of conventional computing systems 82 and 88. The power pins from the VRMs 98 to the package substrate 104 are more flexible. Furthermore, the input voltage from the power supply unit (PSU) to the VRM 98 is more flexible. In one example, more high-speed I / O (HSIO) pins can be added to the bottom side of the package base 104. Figure 4A shows a conventional computing system 110, which includes a thermally conductive plate (e.g., a two-dimensional (2D) heat dissipation assembly) thermally coupled to the top side of a silicon (Si) die 114. In the illustrated example, a power path 116 and a ground connection 118 between the bottom side of the die 114 and a VR component 122 (e.g., a field-effect transistor (FET) and a charge storage device, such as an inductor (I), a capacitor (C), etc.) are routed to a substrate 120 of the die 114 via a path on a PCB motherboard 121. In the enhanced computing system 124, a thermally conductive plate 126 is also thermally coupled to the top side of a silicon die 128. In the example example, copper plate 130 provides a power path and ground connection between the bottom side of die 128 and VR component 132, wherein the power path and ground connection are routed to a substrate 134 of die 128 without passing through a path on a PCB motherboard 135. Figure 4B shows a top side view of a computing system 140, wherein a plurality of copper plates 142 (142a-142d) are electrically coupled to a first set 144 (e.g., inductors) of VR components, a second set 147 (e.g., inductors) of VR components, a third set 146 (e.g., inductors) of VR components, and a fourth set 148 (e.g., inductors) of VR components. The plurality of copper plates 142 are also electrically coupled to a package substrate 150 containing a die and thermally coupled to a thermally conductive plate. In one embodiment, each copper plate 142 provides a dedicated power delivery rail from a voltage regulator to the package substrate 150. For example, a first copper plate 142a provides a dedicated power delivery rail from a first set 144 of VR components, a second copper plate 142b provides a dedicated power delivery rail from a second set 147 of VR components, a third copper plate 142c provides a dedicated power delivery rail from a third set 146 of VR components, and a fourth copper plate 142d provides a dedicated power delivery rail from a fourth set 148 of VR components. Figures 4C and 4D show that a first end of each copper plate 142 may include a spring pin 152 electrically coupled to the package substrate, and a second end of each copper plate 142 includes a spring clip 154 ​​mating with a terminal of a charge storage device associated with VR. Figure 4E shows a development view of the copper plates 142 relative to one of the thermally conductive adhesives 156 positioned between the thermally conductive plate 158 and the plurality of copper plates 142. Additionally, a copper pedestal 160 may be positioned between the thermally conductive plate and the top side of the grain. Turning now to Figures 4F through 4H, a cross-sectional view of a computing system 162 is shown. In the illustrated example, a CPU package 164 is mounted to a circuit board 166. A first end of a copper plate 168 includes a spring pin 170 that contacts a pad on the CPU package 164, and a second end of the copper plate 168 includes a spring clip 172 that mates with a terminal 174 of a charge storage device 176 (e.g., an inductor) associated with a VR. Thus, the spring clip 172 provides a locking feature for interlocking with a pad of the charge storage device 176. The copper plate 168 is thermally coupled to a thermally conductive plate 178. Figure 4I is a bottom side view showing that the thin and wide cross-sectional area of ​​each of the plurality of copper plates 180 (180a-180d) provides significant current carrying capacity (e.g., 15A for a 5 mm x 0.25 mm cross-section). As previously mentioned, a thermally conductive adhesive 182 may be positioned between the thermally conductive plate 184 and the copper plates 180. In one example, the thermally conductive adhesive 182 is electrically insulating. Additionally, the copper plates 180 may be made of a copper alloy with elasticity, which facilitates the use of spring clips at the contact edges. The relatively high thermal conductivity of one of the copper plates 180 improves the cooling capacity of the thermally conductive plate 184. Accordingly, the solution shown offers advantages in cost and current carrying capacity compared to conventional solutions. Figure 4J illustrates a conventional computing system 190 containing a processing unit package 192. Because all power pins (e.g., host processor power pins and graphics processor power pins) are located at the bottom of the package 192, this processing unit package is relatively large (e.g., 50 x 25 mm). In contrast, a first enhanced computing system 194 moves 15% of the power pins to the top of a processing unit package 196. This results in a 2 mm size reduction in the x-axis. Furthermore, a second enhanced computing system 198 moves 50% of the power pins to the top of a processing unit package 200. This results in a 5.5 mm size reduction in the x-axis. Turning to Figure 5, a computing system 210 is shown, in which a main circuit board 212 includes a power supply unit (PSU) 214. The PSU uses a first power delivery path 220 (e.g., cable and / or busbar) to directly power a plurality of virtual power units (VRMs) 222 mounted on a heatsink 214, which acts as a heat dissipation assembly for a CPU 226. Alternatively, the PSU 214 can use a second power delivery path 216 to supply power to a power board 218, which in turn uses a third power delivery path 228 to supply power to the VRMs 222 on the heatsink 214. In one embodiment, high-speed channels 230 and 232 support I / O communication in the computing system 210. Placing the VRMs 222 on the heatsink 214 shortens the power delivery path from the VRMs 222 to the CPU 226. Furthermore, dividing the VRMs into individual VRMs 222 allows the VRMs to be easily designed with flexible PCB thicknesses and layers to meet design and cost requirements. Furthermore, the illustrated solution allows voltage input pins (e.g., VCC IN pins) to be used for other purposes, such as, for example, high-speed I / O (HSIO). Additionally, form factor optimization can involve a substantial reduction in package size. The illustrated solution also provides more routing space on the main board 212 (e.g., HSIO fan-out). Figure 6 illustrates a computing system 240, in which a regulator board 242 is electrically coupled to a heatsink 244 and a voltage regulator 246 is mounted to the regulator board 242. Thus, the illustrated example provides a purely high-current power delivery path depending on requirements. In one embodiment, the heatsink 244 serves as both a power delivery path and a ground connection. In another embodiment, the heatsink 244 serves as a ground connection and a separate path for power delivery. While load line optimization in computing system 240 may not be as effective as in computing system 210 (Figure 5), the impact on cooling performance may be smaller. Furthermore, a unified cooling solution can be used to cool both the CPU and the voltage regulator 246. Figure 7 illustrates a computing system 250, in which a voltage regulator 252 and a plurality of CPU chips 256 share a package substrate 254. An integrated heatsink (IHS) 258 may be positioned between the CPU chips 256 and a heatsink 260. The illustrated solution allows the bottom of the package to remain small, having an staggered form factor. Additionally, a unified cooling solution can be used to cool both the CPU chips 256 and the voltage regulator 252. Figure 8 shows that the first zones 262 and 264 can be used for CPU power delivery, and the second zones 266 and 268 can be used for high-speed signals to the storage channel. Figure 9 illustrates a CPU package 270, where connection points 272, 274, and 276 are provided to multiple VRM outputs via an IHS 278. More specifically, a first connection point 272 is electrically coupled to a first VRM output and a power pin at the center of a first CPU die 280, and delivers power via an upper (but not top) layer of the first CPU die 280. In this configuration, high-speed signals can be routed to a lower layer of the first CPU die 280, and subsequently to the bottom layer of the first CPU die 280. A second connection point 274 may be electrically coupled to a second VRM output and a power pin at the center of a second CPU die 282. In one embodiment, the second connection point 274 delivers power via an upper layer of the second CPU die 282, wherein high-speed signals are routed to a lower layer of the second CPU die 282 and then to the bottom layer of the second CPU die 282. Similarly, a third connection point 276 may be electrically coupled to a third VRM output and a power pin at the center of a third CPU die 284. In one embodiment, the third connection point 276 delivers power via an upper layer of the third CPU die 284, wherein high-speed signals are routed to a lower layer of the third CPU die 284 and then to the bottom layer of the third CPU die 284. Figure 10 illustrates a portion of a CPU package 290 (e.g., with the IHS removed). In the illustrated example, connection points 292, 294, and 296 are provided to a single VRM output 298. More specifically, a first connection point 292 is electrically coupled to a power pin at the center of the single VRM output 298 and the first CPU die 300, and delivers power via an upper layer (but not the top layer) of the first CPU die 300. In this configuration, high-speed signals can be routed to a lower layer of the first CPU die 300, and subsequently to the bottom layer of the first CPU die 300. The second connection point 294 may be electrically coupled to a single VRM output 298 and a power pin at the center of the second CPU die 302. In one embodiment, the second connection point 294 delivers power via an upper layer of the second CPU die 302, wherein high-speed signals are routed to a lower layer of the second CPU die 302 and then to the bottom layer of the second CPU die 302. Similarly, a third connection point 296 may be electrically coupled to a power pin at the center of a single VRM output 298 and a third CPU die 304. In one embodiment, the third connection point 296 delivers power via an upper layer of the third CPU die 304, wherein high-speed signals are routed to a lower layer of the third CPU die 304 and then to the bottom layer of the third CPU die 304. Figure 11 shows a CPU package 310 having a first connector 312, a second connector 314, and a third connector 316 integrated onto a CPU package 310. In one embodiment, a VRM (not shown) is mounted within connectors 312, 314, and 316. The processing unit described herein may include a set of logic instructions that can be implemented in one or more modules and stored in a machine- or computer-readable storage medium, such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc.; implemented in configurable hardware, such as, for example, programmable logic array (PLA), field-programmable gate array (FPGA), complex programmable logic device (CPLD); or implemented in fixed-function hardware using circuit technology, such as, for example, using ASIC, complementary metal-oxide-semiconductor (CMOS) or transistor logic (TTL) technology, or any combination thereof. A semiconductor device (e.g., a wafer and / or package) may include one or more substrates (e.g., silicon, sapphire, gallium arsenide) and logic (e.g., transistor arrays and other integrated circuit / IC components) coupled to the substrates. The logic may be at least partially implemented in configurable or fixed functional hardware. In one example, the logic includes transistor channel regions located (e.g., embedded) within the substrate. Therefore, the interface between the logic and the substrate may not be a steep junction. The logic may also be considered as including an epitaxial layer grown on an initial wafer of the substrate. Additionally, a computing system can generally be part of an electronic device / platform that has computing functionality (e.g., personal digital assistant / PDA, laptop, tablet, convertible tablet, server), communication functionality (e.g., smartphone), imaging functionality (e.g., camera, camcorder), media playback functionality (e.g., smart TV), wearable functionality (e.g., watch, glasses, headwear, shoes, jewelry), vehicle functionality (e.g., car, truck, motorcycle), robotic functionality (e.g., autonomous robot), Internet of Things (IoT) functionality, or any combination thereof. The technology described herein offers performance and form factor benefits by avoiding the increase in package size due to the addition of power and ground pins. This technology also reduces package thickness (e.g., "System Z") by avoiding the addition of PCB layers. Furthermore, the technology improves power delivery by reducing power loss. For example, eliminating the power delivery (PD) path through conventional BGA (Ball Grid Array) packages and the power plane that introduces more IR voltage drop shortens the overall path and inductor loop. Accordingly, the load line is improved for greater performance. Additional advantages are achieved through a Cu board integrated with a thermally conductive plate, delivering power via the onboard VR. For example, flexibility regarding VR placement and location in the platform / computing system is enhanced. Moreover, the inductor's position on the board is defined by the power ball diagram / package quadrant. Furthermore, this technology offers a simpler board layout and shorter I / O channel range. For example, with most VR components removed from the board, I / O channel interruption and routing are simpler and more direct (e.g., no need to wrap around VR components). In fact, shorter I / O channel routing lengths can potentially reduce board costs. The technology described in this paper also provides better heat dissipation for power – the power-carrying Cu board is attached to a thermally conductive plate to dissipate heat directly from the VR and SOC (System-on-a-Chip). Better performance is achieved due to these thermal improvements. Additional notes and examples Example 1 includes a performance-enhanced computing system comprising a voltage regulator, a board assembly including a die and a circuit board electrically coupled to a first side of the die, and a heat dissipation assembly thermally coupled and electrically coupled to a second side of the die, wherein the heat dissipation assembly is further electrically coupled to the voltage regulator. Example 2 includes the computing system of Example 1, wherein the heat dissipation assembly provides a power delivery path from the voltage regulator to the second side of the die. Example 3 includes the computing system of Example 2, wherein the heat dissipation assembly further provides a ground connection from the second side of the die to the voltage regulator. Example 4 includes the computing system of Example 1, wherein the circuit board provides a ground connection from the first side of the die to the voltage regulator. Example 5 includes the computing system of Example 1, wherein the voltage regulator is installed in the heat dissipation assembly. Example 6 includes the computing system of Example 5, wherein the voltage regulator includes a plurality of voltage regulator modules. Example 7 includes the computing system of Example 1, wherein the voltage regulator is mounted on the circuit board. Example 8 includes the computing system of Example 1, and further includes a regulator board electrically coupled to the heat dissipation assembly, wherein the voltage regulator is mounted on the regulator board. Example 9 includes the computing system of Example 1, and further includes a plurality of signal contacts electrically coupled to the circuit board, and a package substrate electrically coupled to the plurality of signal contacts and the first side of the die. Example 10 includes the computing system of Example 9, wherein the voltage regulator is mounted to the package substrate. Example 11 includes the computing system of Example 1, wherein the second side includes a plurality of power contacts. Example 12 includes a computing system of any of Examples 1 to 11, wherein the heat dissipation assembly includes a heat sink. Example 13 includes a computing system of any of Examples 1 to 11, wherein the heat dissipation assembly includes a heat sink. Example 14 includes the computing system of Example 1, wherein the heat dissipation assembly includes a heat-conducting plate. Example 15 includes the computing system of Example 14, further including a plurality of copper plates electrically coupled to the voltage regulator and a package substrate containing the die, wherein the plurality of copper plates are further thermally coupled to the heat-conducting plate. Example 16 includes the computing system of Example 15, wherein each copper plate provides a dedicated power delivery rail from the voltage regulator to the package substrate. Example 17 includes the computing system of Example 15, wherein a first end of each copper plate includes a spring pin electrically coupled to the package substrate. Example 18 includes the computing system of Example 15, wherein a second end of one of the copper plates includes a spring clip that engages with a terminal of a charge storage device associated with the VR. Example 19 includes the computing system of Example 15, and further includes a thermally conductive adhesive located between the heat dissipation assembly and the plurality of copper plates. Example 20 includes the computing system of Example 15, and further includes a copper pedestal positioned between the thermally conductive plate and the second side of the die. Example 21 includes the computing system of Example 15, wherein the circuit board provides a ground connection from the first side of the die to the voltage regulator. Example 22 includes a computing system comprising a board assembly including a die and a circuit board electrically coupled to a first side of one of the dies, wherein the circuit board includes a voltage regulator; a heat dissipation assembly; and a plurality of copper plates electrically coupled to the voltage regulator and a package substrate containing one of the dies, wherein the plurality of copper plates are further thermally coupled to the heat dissipation assembly. Example 23 includes the computing system of Example 22, wherein each copper plate provides a dedicated power delivery rail from the voltage regulator to the package substrate. Example 24 includes the computing system of Example 22, wherein one of the copper plates has a first end including a spring pin electrically coupled to the package substrate. Example 25 includes the computing system of Example 22, wherein a second end of one of the copper plates includes a spring clip that engages with a terminal of a charge storage device associated with the VR. Example 26 includes the computing system of Example 22, and further includes a thermally conductive adhesive located between the heat dissipation assembly and the plurality of copper plates. Example 27 includes the computing system of Example 22, and further includes a copper pedestal positioned between the heat dissipation assembly and a second side of the grain. Example 28 includes the computing system of Example 22, wherein the circuit board provides a ground connection from the first side of the die to the voltage regulator. Example 29 includes the computing system of any of Examples 22 to 28, wherein the heat dissipation assembly includes a heat-conducting plate. The embodiments are suitable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of such IC chips include, but are not limited to, processors, controllers, chipset assemblies, programmable logic arrays (PLAs), memory chips, network chips, system-on-a-chip (SoC), SSD / NAND controller ASICs, and the like. Furthermore, in some diagrams, signal conductor lines are represented by lines. Some may differ to indicate more constituting signal paths, have a numerical label to indicate multiple constituting signal paths, and / or have arrows at one or more ends to indicate the main information flow direction. However, this should not be interpreted in a limiting manner. Rather, these added details may be used with one or more exemplary embodiments to facilitate a clearer understanding of a circuit. Any represented signal line, whether or not it contains additional information, may actually include one or more signals that can travel in multiple directions and can be implemented using any suitable type of signaling scheme, such as digital or analog lines implemented using differential pairs, fiber optic lines, and / or single-ended lines. Exemplary dimensions / models / values / ranges may be given, although the embodiments are not limited thereto. As manufacturing technologies (e.g., photolithography) mature over time, smaller devices are expected to be produced. Additionally, known power / ground connections to IC chips and other components may or may not be shown in the drawings for the sake of simplicity of description and discussion, and to avoid obscuring certain aspects of these embodiments. Furthermore, configurations may be shown in block diagram form to avoid obscuring the embodiments, and also because the details of how such block diagram configurations are implemented are highly dependent on the computing system on which the embodiment is to be implemented; that is, such details should be within the scope of knowledge of those skilled in the art. While specific details (e.g., circuitry) are set forth to illustrate exemplary embodiments of the invention, it will be apparent to those skilled in the art that the invention may be practiced without such specific details or with variations thereof. This detailed description should therefore be considered illustrative rather than restrictive. The term "coupled" may be used herein to refer to any type of direct or indirect relationship between the components under discussion, and may be applied to electrical, mechanical, fluid, optical, electromagnetic or other connections. Furthermore, terms such as "first," "second," etc., are used herein for convenience only and, unless otherwise indicated, do not carry any specific temporal or chronological meaning. As used in this application and in the scope of the claims, the list of items connected by the term "one or more of them" can refer to any combination of the listed terms. For example, the phrase "one or more of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. From the foregoing description, those skilled in the art will recognize that the broad techniques of these embodiments can be implemented in various forms. Therefore, although these embodiments have been described in conjunction with specific examples, their true scope should not be so limited, as other modifications will become apparent to those skilled in the art upon reading the drawings, the specification, and the subsequent claims of the patent application. 20: Computing System 22: Zone 24: Zone 26: Zone 28: Added 30: Known Computing System 32: Voltage Regulator (VR) 34: Die 36: Circuit Board 38: Power Contact 40: Package Substrate 42: Ground Pin 44: Integrated Heatsink (IHS) 48: Signal Pin 50: Enhanced Computing System 52: Voltage Regulator 54, 54a, 54b: Heatsink 56: Die 58: Signal Pin 60: Package Substrate 62: Enhanced Computing System 64: Circuit Board 66: Die 68: Voltage Regulator 70: Integrated Heatsink 72: Enhanced Computing System 74: Voltage Regulator, Regulator 76: Package Substrate 78: Die 80: Integrated Heatsink 82: Known Computing System 84: VR 86: Motherboard 88: Known Computing System 90: VR 92: Package substrate 94: Processing unit die 96: Enhanced computing system 98: VR module (VRM) 100: Heat sink 102: Power path 104: Package substrate 110: Computing system 114: Silicon (Si) die 116: Power path 118: Ground connection 120: Substrate 121: PCB motherboard 124: Enhanced computing system 126: Thermal conductive plate 128: Silicon die 130: Copper plate 134: Substrate 135: PCB motherboard 140: Computing system 142, 142a, 142b, 142c, 142d: Copper plate 144: First set 146: Third set 147: Second set 148: Fourth set 150: Package substrate 152: Spring pin 154: Spring clip 156: Thermally conductive adhesive 158: Thermally conductive plate 160: Copper base 62: Computing System 164: CPU Package 166: Circuit Board 168: Copper Plate 170: Spring Pin 172: Spring Clip 174: Terminal 176: Charge Storage Device 178: Thermal Conductive Plate 180, 180a, 180b, 180c, 180d: Copper Plate 182: Thermally Conductive Adhesive 184: Thermal Conductive Plate 192: Processing Unit Package, Package 190: Pre-existing Computing System 194: Enhanced Computing System 196: Processing Unit Package 198: Enhanced Computing System 200: Processing Unit Package 210: Computing System 212: Main Circuit Board 214: PSU, Heatsink 216: Second Power Delivery Path 218: Power Board 220: First Power Delivery Path 222: VRM 226: CPU 228: Third Power Delivery Path 230,232: High-speed channel; 240: Computing system; 242: Regulator board; 244: Heatsink; 246: Voltage regulator; 250: Computing system; 252: Voltage regulator; 254: Package substrate; 256: CPU die; 258: Integrated heatsink (IHS); 260: Heatsink; 262, 264: First zone; 266, 268: Second zone; 270: CPU package; 278: IHS; 272, 274, 276: Connector point; 280: First CPU die; 282: Second CPU die; 284: Third CPU die; 290: CPU package; 292, 294, 296: Connector point; 298: VRM output; 300: First CPU die; 302: Second CPU die; 304: Third CPU die; 310: CPU package; 312: First connector; 314: Second connector; 316: Third connector. By reading the following specification and the accompanying claims, and by referring to the following drawings, the various advantages of the embodiments will become apparent to those skilled in the art, wherein: Figure 1 is a plan view of an example of the width and fan diameter of a key core in a computing system; Figure 2A is a comparative side view of a conventional power delivery path and grounding connection and an example of a power delivery path and grounding connection according to one embodiment; Figure 2B is a side view of one example of a power delivery path and grounding connection according to another embodiment; Figure 2C is a side view of an example of a voltage regulator mounted on a package substrate according to an embodiment; Figure 3 is a comparative perspective view of a conventional voltage regulator mounted on a heat dissipation assembly according to one embodiment; Figure 4A is a comparative side view of a conventional power delivery path in a computing system containing a thermally conductive plate and an example of an enhanced power delivery path in a computing system containing a thermally conductive plate according to an embodiment. Figure 4B is a plan view of an example of a computing system including a plurality of copper plates according to an embodiment; Figure 4C is an enlarged perspective bottom view of an example of a spring clip according to one embodiment; Figure 4D is a perspective bottom view of one example of a plurality of copper plates according to an embodiment; Figure 4E is an exploded perspective view of one embodiment of a copper base, a plurality of copper plates, a thermally conductive adhesive and a thermally conductive plate. Figure 4F is a plan view of an example of a computing system including a heat-conducting plate according to an embodiment; Figure 4G is a cross-sectional view taken along line AA in Figure 4F; Figure 4H is an enlarged view of an example of a spring clip that engages with a terminal of a charge storage device according to an embodiment; Figure 4I is an enlarged bottom view of one example of a plurality of copper plates according to an embodiment; Figure 4J is a comparative plan view of a conventional semiconductor package and an example of a semiconductor package according to an embodiment; Figure 5 is a perspective view of one example of a plurality of voltage regulator modules mounted to a heat sink according to an embodiment; Figure 6 is a perspective view of an example of a regulator board according to one embodiment and a voltage regulator mounted to the regulator board; Figure 7 is a perspective view of an example of a voltage regulator mounted on a package substrate according to one embodiment; Figure 8 is a plan view of an example of a high-speed channel according to one embodiment; Figure 9 is a perspective view of an example of a processing unit design for a plurality of voltage regulator modules according to an embodiment; Figure 10 is a perspective view of an example design for a processing unit of a single voltage regulator according to an embodiment; and Figure 11 is a perspective view of an example of a processing unit design with an integrated connector according to an embodiment. 30: Knowledge-based computational system 32: Voltage Regulator (VR) 34: Grain 36: Circuit board 38: Power contacts 40: Package substrate 42: Grounding pin 44: Integrated Radiator (IHS) 46:TIM 48: Signal pin 50: Enhanced computing system 52: Voltage regulator 54, 54a, 54b: Radiators 56: Grains 58: Signal pin 60: Package substrate

Claims

1. A computing system, comprising: A voltage regulator; A board assembly includes a die and a circuit board electrically coupled to a first side of one of the dies; And a heat dissipation assembly thermally and electrically coupled to a second side of one of the chips, wherein the heat dissipation assembly is further electrically coupled to the voltage regulator.

2. The computing system of claim 1, wherein the heat dissipation assembly provides a power delivery path from the voltage regulator to the second side of the die.

3. The computing system of claim 2, wherein the heat dissipation assembly further provides a ground connection from the second side of the die to the voltage regulator.

4. The computing system of claim 1, wherein the circuit board provides a ground connection from the first side of the die to the voltage regulator.

5. The operating system of claim 1, wherein the voltage regulator is mounted on the heat dissipation assembly.

6. The operating system of claim 5, wherein the voltage regulator comprises a plurality of voltage regulator modules.

7. The operating system of claim 1, wherein the voltage regulator is mounted on the circuit board.

8. The computing system of claim 1 further includes a regulator board electrically coupled to the heat dissipation assembly, wherein the voltage regulator is mounted on the regulator board.

9. The computing system of claim 1, further comprising: Electrically coupled to a plurality of signal contacts on the circuit board; and a package substrate electrically coupled to the plurality of signal contacts and the first side of the die.

10. The computing system of claim 9, wherein the voltage regulator is mounted to the package substrate.

11. The computing system of claim 1, wherein the second side includes a plurality of power contacts.

12. The computing system of any one of claims 1 to 11, wherein the heat dissipation assembly includes a heat sink.

13. The computing system of any one of claims 1 to 11, wherein the heat dissipation assembly includes a heat sink.

14. The computing system of claim 1, wherein the heat dissipation assembly includes a heat-conducting plate.

15. The computing system of claim 14 further includes a plurality of copper plates electrically coupled to the voltage regulator and a package substrate containing the die, wherein the plurality of copper plates are further thermally coupled to the thermally conductive plate.

16. The computing system of claim 15, wherein each copper plate provides a dedicated power delivery rail from the voltage regulator to the package substrate.

17. The computing system of claim 15, wherein a first end of each copper plate includes a spring pin electrically coupled to the package substrate, and wherein a second end of each copper plate includes a spring clip mating with a terminal of a charge storage device associated with VR.

18. The computing system of claim 15 further includes: A thermally conductive adhesive is positioned between the heat dissipation assembly and the plurality of copper plates.

19. The computing system of claim 15, wherein the circuit board provides a ground connection from the first side of the die to the voltage regulator.

20. A computing system comprising: a board assembly including a die and a circuit board electrically coupled to a first side of one of the dies, wherein the circuit board includes a voltage regulator; a heat dissipation assembly; and a plurality of copper plates electrically coupled to the voltage regulator and a package substrate containing one of the dies, wherein the plurality of copper plates are further thermally coupled to the heat dissipation assembly.

21. The computing system of claim 20, wherein each copper plate provides a dedicated power delivery rail from the voltage regulator to the package substrate.

22. The computing system of claim 20, wherein a first end of each copper plate includes a spring pin electrically coupled to the package substrate, and wherein a second end of each copper plate includes a spring clip mating with a terminal of a charge storage device associated with VR.

23. The computing system of claim 20 further includes a thermally conductive adhesive positioned between the heat dissipation assembly and the plurality of copper plates.

24. The computing system of claim 20, wherein the circuit board provides a ground connection from the first side of the die to the voltage regulator.

25. The computing system of any one of claims 20 to 24, wherein the heat dissipation assembly includes a heat-conducting plate.

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