Transmitter, receiver and system for pulse amplitude modulation signaling

Abstract

This invention provides a transmitter including an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generating a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group in different ways based on the value of the first bit group, and generating a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group. Each of the first symbol group and the second symbol group includes multiple symbols, and each of the multiple symbols has three different voltage levels. The transmitter includes a driver configured to generate an output data signal by serially connecting the first symbol group and the second symbol group.

Description

Transmitter and Receiver for 3-Level Pulse Amplitude Modulation Signal and System Comprising the Same Some example embodiments generally relate to semiconductor integrated circuits including a transmitter and a receiver for 3-level pulse amplitude modulation signaling and / or a system including the same. Cross-reference to related applications This application claims priority to Korean Patent Application No. 10-2022-0050576, filed on Apr. 25, 2022, Korean Patent Application No. 10-2022-0070511, filed on Jun. 10, 2022, and Korean Patent Application No. 10-2022-0079545, filed on Jun. 29, 2022, in the Korean Intellectual Property Office (KIPO), the disclosures of each of the applications of which are incorporated herein by reference in their entireties. Recently, for high performance computing (HPC), such as artificial intelligence (AI) and graphic processing unit (GPU), there are intensive requirements or demands for memory bandwidth. The amplification of bandwidth may rely on the innovation of process technology. The development of process technology has resulted in higher density in integrated circuit (IC). To increase bandwidth, pulse amplitude modulation-2 (PAM-2) signaling having two data modulation levels may be used for data communication. Conventional PAM-2 signaling may enable simplifying the structure of a transceiver. However, only one bit may be transmitted during a unit interval (UI), and an increase in clock frequency is required or needed to increase bandwidth. For this reason, this may lead to channel attenuation and clock quality degradation. Pulse amplitude modulation-4 (PAM-4) signaling may transmit two bits during one UI. However, in terms of single-ended signaling, the sensing tolerance of PAM-4 signaling is extremely small, and PAM-4 signaling is extremely sensitive to supply voltage noise and has extremely low linearity of the signal. Therefore, the feasibility of PAM-4 signaling may be relatively low. Pulse amplitude modulation-3 (PAM-3) signaling refers to signaling that transmits three voltage levels at a time and can theoretically transmit 1.5849 bits (log 23 ≒ 1.5849). However, PAM-3 signaling has structural inefficiencies. The PAM-3 interface may not encode two bits in a single UI, and the output driver has difficulty maintaining impedance matching for all inputs. Some example embodiments provide a transmitter capable of reducing footprint and power consumption when using PAM-3 signaling. Some example embodiments provide a receiver capable of reducing footprint and power consumption when using PAM-3 signaling. Some example embodiments provide a system including a transmitter and a receiver that may be capable of reducing footprint and power consumption when using PAM-3 signaling. According to some example embodiments, a transmitter includes an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group in different ways based on the value of the first bit group, and generate a first symbol group by encoding the first intermediate bit group and generate a second symbol group by encoding the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver configured to generate an output data signal by concatenating the first symbol group and the second symbol group, the driver configured to transmit the output data signal via a channel. According to some example embodiments, a receiver includes a decoder configured to generate a first intermediate bit group by decoding a first symbol group of an input data signal, and generate a second intermediate bit group by decoding a second symbol group of the input data signal, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels, and generate a first bit group and a second bit group by manipulating the first intermediate bit group and the second intermediate bit group in different ways based on a specific bit value of the second intermediate bit group. The receiver includes a buffer configured to generate an output data signal including the first number of binary output bits by buffering the first bit group and the second bit group. According to some example embodiments, a system includes: a transmitter including an encoder and a driver, the transmitter configured to output write data to be stored in a semiconductor memory device; a channel configured to transmit the write data; and a receiver including a decoder and a buffer, the receiver configured to receive the write data. The encoder is configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group in different ways based on the value of the first bit group, and generate a first symbol group by encoding the first intermediate bit group and a second symbol group by encoding the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The driver is configured to generate an output data signal by concatenating the first symbol group and the second symbol group and is configured to transmit the output data signal via the channel. The decoder is configured to receive the output data signal including the first symbol group and the second symbol group, generate the first intermediate bit group by decoding the first symbol group and the second intermediate bit group by decoding the second symbol group, and generate the first bit group and the second bit group by manipulating the first intermediate bit group and the second intermediate bit group in different ways based on the value of a specific bit of the second intermediate bit group. The buffer is configured to generate an output data signal including the first number of binary output bits by buffering the first bit group and the second bit group. Thus, instead of encoding the first number of binary input bits into symbols all at once, the transmitter according to the example embodiments divides the first number of binary inputs into a first bit group including a second number of binary input bits and a second bit group including a third number of binary input bits, generates a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group in different ways according to the value of the first bit group, and generates a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group in parallel. Accordingly, the transmitter can reduce the occupied area and power consumption. The various example embodiments will be described more fully with reference to the accompanying drawings, in which some example embodiments are shown. However, the inventive concept may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. In this application, like reference numerals refer to like elements. A multilevel signaling scheme can be used as a means to compress the bandwidth required to transmit data at a given bit rate. In a simple binary scheme, two single symbols (usually two voltage levels) can be used to represent '1' and '0', and thus the symbol rate can be equal to the bit rate. In contrast, the principle of a multilevel signaling scheme can be to use a larger alphabet of m symbols to represent data, such that each symbol can represent more than one bit of data. Therefore, the number of symbols that need to be transmitted can be less than the number of bits (e.g., the symbol rate can be less than the bit rate), and thus the bandwidth can be compressed. In other words, a multilevel signaling scheme can be used to increase the data transmission (or transfer) rate without increasing the data transmission frequency and / or the transmission power of the data being conveyed. An example of one type of multilevel signaling scheme can be a pulse amplitude modulation (PAM) scheme, where the unique symbols of the multilevel signaling can represent multiple bits of data. FIG. 1 is a block diagram showing a transmitter and a receiver according to some example embodiments. Referring to FIG. 1, a transmitter (TX) 100 and a receiver (RX) 200 can be connected to each other via a channel 50. The transmitter 100 can generate an output data signal TX_OUT based on an input data signal TX_IN that includes a plurality of binary input bits. The output data signal TX_OUT can include a plurality of PAM-3 symbols, and each of the plurality of PAM-3 symbols can have a first voltage level VL1, a second voltage level VL2, and a third voltage level VL3. The output data signal TX_OUT can be transmitted to the receiver 200 via the channel 50. The receiver 200 can generate an output data signal RX_OUT that includes a plurality of binary output bits based on an input data signal RX_IN that includes a plurality of PAM-3 symbols. For example, the three voltage levels of the output data signal TX_OUT can include a first voltage level VL1, a second voltage level VL2 that is higher than the first voltage level VL1, and a third voltage level VL3 that is higher than the second voltage level VL2. The first voltage level VL1, the second voltage level VL2, and the third voltage level VL3 can be referred to as a low level, a middle (or mid) level, and a high level, respectively. For example, the output data signal RX_OUT can have two voltage levels that are different from each other, and one value (or data) included in the output data signal RX_OUT as a binary signal can represent one value (or bit) included in the input data signal TX_IN. For example, two voltage levels of the output data signal RX_OUT may include a first voltage level VL1 and a fourth voltage level VL4 higher than the first voltage level VL1. The first voltage level VL1 and the fourth voltage level VL4 may be referred to as a low level and a high level, respectively. For example, the fourth voltage level VL4 may be higher than the third voltage level VL3 and may be about 1.2 volts. In other words, the swing width of the output data signal RX_OUT (e.g., the voltage difference between the low level and the high level) may be greater than the swing width of the output data signal TX_OUT. For example, the input data signal TX_IN as a binary signal may also have two voltage levels different from each other. For example, although not shown in FIG. 1, the low level of the input data signal TX_IN may be substantially equal to the first voltage level VL1, and the high level of the input data signal TX_IN may be substantially equal to the third voltage level VL3. The transmitter 100 and the receiver 200 according to some example embodiments may have a structure for reducing the occupied area and power consumption. The detailed configuration and operation of the transmitter 100 will be described with reference to FIGS. 2 to 12. The detailed configuration and operation of the receiver 200 will be described with reference to FIGS. 13 to 17. FIG. 2 is a block diagram showing an example of the transmitter in FIG. 1 according to some example embodiments. Referring to FIG. 2, the transmitter 100 may include an encoder 110 and a driver 190. The encoder 110 may divide a first number of binary input bits of the input data signal TX_IN into a first bit group BTG1 and a second bit group BTG2, may generate a first intermediate bit group IBTG1 and a second intermediate bit group IBTG2 by manipulating the first bit group BTG1 and the second bit group BTG2 in different ways, and may generate a first symbol group SG1 and a second symbol group SG1 by encoding the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2, respectively. Each of the first symbol group SG1 and the second symbol group SG2 may include a plurality of symbols, and each of the plurality of symbols may have three different voltage levels. The driver 190 may generate an output data signal TX_OUT by concatenating the first symbol group SG1 and the second symbol group SG2, and may transmit the output data signal TX_OUT to the receiver 200 via the channel 50. For example, when the input data signal TX_IN includes a first number of binary input bits b0, binary input bit b1, binary input bit b2, binary input bit b3, binary input bit b4, binary input bit b5, binary input bit b6, binary input bit b7, binary input bit b8, binary input bit b9, and binary input bit b10, the first bit group BTG1 may include a second number of binary input bits b0, binary input bit b1, binary input bit b2, binary input bit b3, and binary input bit b4, the second bit group BTG2 may include a third number of binary input bits b5, binary input bit b6, binary input bit b7, binary input bit b8, binary input bit b9, and binary input bit b10, and the third number may be greater than the second number. The first number may correspond to eleven, the second number may correspond to five, and the third number may correspond to six. In addition, the first symbol group SG1 may include a plurality of first symbols S0, first symbol S1, and first symbol S2, and the second symbol group SG2 may include a plurality of second symbols S3, second symbol S4, second symbol S5, and second symbol S6. That is, the first symbol group SG1 may include a fifth number of first symbols S0, first symbol S1, and first symbol S2, and the second symbol group SG2 may include a sixth number of second symbols S3, second symbol S4, second symbol S5, and second symbol S6. The encoder 110 may include an intermediate data generator 120, a first sub-encoder 170, and a second sub-encoder 180. The intermediate data generator 120 may generate a first intermediate bit group IBTG1 and a second intermediate bit group IBTG2 by manipulating the first bit group BTG1 including binary input bits b0, binary input bit b1, binary input bit b2, binary input bit b3, and binary input bit b4 and the second bit group BTG2 including binary input bits b5, binary input bit b6, binary input bit b7, binary input bit b8, binary input bit b9, and binary input bit b10. The first sub-encoder 170 may generate a first symbol group SG1 including first symbols S0, first symbol S1, and first symbol S2 by encoding the first intermediate bit group IBTG1. The second sub-encoder 180 may generate a second symbol group SG2 including second symbols S3, second symbol S4, second symbol S5, and second symbol S6 by encoding the second intermediate bit group IBTG2. FIG. 3 is a block diagram showing an example of the intermediate data generator in the transmitter of FIG. 2 according to some example embodiments. Referring to FIG. 3, the intermediate data generator 120 may include a check value generator 121, a first demultiplexer 123, a second demultiplexer 125, a first data conditioner 130, a second data conditioner 140, a first multiplexer 160, and a second multiplexer 165. The check value generator 121 may receive the first bit group BTG1 and may generate a check value CHK indicating whether the value of the first bit group BTG1 is equal to or greater than a first threshold value. The check value generator 121 may generate a check value CHK having a first logic level (e.g., logic low level) in response to the value of the first bit group BTG1 being less than the first threshold value, and may generate a check value CHK having a second logic level (e.g., logic high level) in response to the value of the first bit group BTG1 being equal to or greater than the first threshold value. For example, the first threshold value may be 26. The first demultiplexer 123 may receive the first bit group BTG1 and the second bit group BTG2, and may provide the first bit group BTG1 and the second bit group BTG2 to the first data conditioner 130 in response to the check value CHK indicating that the value of the first bit group BTG1 is less than the first threshold value, and may provide the first bit group BTG1 and the second bit group BTG2 to the second data conditioner 140 in response to the check value CHK indicating that the value of the first bit group BTG1 is equal to or greater than the first threshold value. The second demultiplexer 125 may receive the check value CHK, and may provide the check value CHK to the first data conditioner 130 in response to the check value CHK indicating that the value of the first bit group BTG1 is less than the first threshold value, and may provide the check value CHK to the second data conditioner 140 in response to the check value CHK indicating that the value of the first bit group BTG1 is equal to or greater than the first threshold value. The first data conditioner 130 may generate a first sub-intermediate bit group IBTG11 and a second sub-intermediate bit group IBTG12 by respectively manipulating the first bit group BTG1 and the second bit group BTG2 according to a first scheme in response to the value of the first bit group BTG1 being less than the first threshold value and based on the check value CHK. In response to the value of the first bit group BTG1 being less than the first threshold value, the first data conditioner 130 may generate the first sub-intermediate bit group IBTG11 based on the first bit group BTG1, and may generate the second sub-intermediate bit group IBTG12 based on the second bit group BTG2 and the check value CHK. The second data conditioner 140 can respond that the value of the first bit group BTG1 is equal to or greater than the first threshold value and, based on the check value CHK, generate a third sub-intermediate bit group IBTG21 and a fourth sub-intermediate bit group IBTG22 by respectively manipulating the first bit group BTG1 and the second bit group BTG2 according to a second scheme different from the first scheme. In response to the value of the first bit group BTG1 being equal to or greater than the first threshold value, the second data conditioner 140 can generate the third sub-intermediate bit group IBTG21 based on the first bit group BTG1 and the second bit group BTG2, and can generate the fourth sub-intermediate bit group IBTG22 based on the check value CHK and the second bit group BTG2. Here, the first scheme and the second scheme can include circuitry configured to perform certain mathematical operations. For example, the first bit group BTG1 and the second bit group BTG2 can be used by the first data conditioner 130 to generate a first sub-intermediate bit group IBTG11 and a second sub-intermediate bit group IBTG12 based on the circuitry configured to perform the first scheme. For example, the first bit group BTG1 and the second bit group BTG2 can be used by the second data conditioner 140 to generate a third sub-intermediate bit group IBTG21 and a fourth sub-intermediate bit group IBTG22 based on the circuitry configured to perform the second scheme. The first multiplexer 160 can receive the first sub-intermediate bit group IBTG11 and the third sub-intermediate bit group IBTG21, and can output one of the first sub-intermediate bit group IBTG11 and the third sub-intermediate bit group IBTG21 as the first intermediate bit group IBTG1 based on the check value CHK. The second multiplexer 160 can receive the second sub-intermediate bit group IBTG12 and the fourth sub-intermediate bit group IBTG22, and can output one of the second sub-intermediate bit group IBTG12 and the fourth sub-intermediate bit group IBTG22 as the second intermediate bit group IBTG2 based on the check value CHK. The first multiplexer 160 can provide the first sub-intermediate bit group IBTG11 as the first intermediate bit group IBTG1 in response to the check value CHK having a first logic level (for example, in response to the value of the first bit group BTG1 being less than the first threshold value), and can provide the third sub-intermediate bit group IBTG21 as the first intermediate bit group IBTG1 in response to the check value CHK having a second logic level (for example, in response to the value of the first bit group BTG1 being equal to or greater than the first threshold value). The second multiplexer 165 may provide the second sub-intermediate bit group IBTG12 as the second intermediate bit group IBTG2 in response to the check value CHK having a first logic level, and may provide the fourth sub-intermediate bit group IBTG22 as the second intermediate bit group IBTG2 in response to the check value CHK having a second logic level. When the check value CHK has a first logic level and indicates that the value of the first bit group BTG1 is less than the first threshold value, the first data conditioner 130 generates a first sub-intermediate bit group IBTG11 and a second sub-intermediate bit group IBTG12 by respectively manipulating the first bit group BTG1 and the second bit group BTG2 according to the first scheme, and the first multiplexer 160 and the second multiplexer 165 respectively provide the first sub-intermediate bit group IBTG11 and the second sub-intermediate bit group IBTG12 as the first intermediate bit group IBTG1 and the second intermediate bit group IBTC2. When the check value CHK has a second logic level and indicates that the value of the first bit group BTG1 is equal to or greater than the first threshold value, the first data conditioner 130 generates a third sub-intermediate bit group IBTG21 and a fourth sub-intermediate bit group IBTG22 by using the check value CHK and respectively manipulating the first bit group BTG1 and the second bit group BTG2 according to the second scheme, and the first multiplexer 160 and the second multiplexer 165 respectively provide the third sub-intermediate bit group IBTG21 and the fourth sub-intermediate bit group IBTG22 as the first intermediate bit group IBTG1 and the second intermediate bit group IBTC2. FIG. 4 shows the operation of the first data conditioner in the intermediate data generator of FIG. 3 according to some example embodiments. Referring to FIGS. 3 and 4, in response to the value of the first bit group BTG1 being less than the first threshold value, the first data conditioner 130 provides the first bit group BTG1 including the first binary input bit b0, the first binary input bit b1, the first binary input bit b2, the first binary input bit b3, and the first binary input bit b4 as the first sub-intermediate bit group IBTG11 (operation S111), provides the check value CHK and the second bit group BTG2 including the second binary input bit b5, the second binary input bit b6, the second binary input bit b7, the second binary input bit b8, the second binary input bit b9, and the second binary input bit b10 as the second sub-intermediate bit group IBTG12 (operation S112), and the first multiplexer 160 and the second multiplexer 165 respectively output the first sub-intermediate bit group IBTG11 and the second sub-intermediate bit group IBTG12 as the first intermediate bit group IBTG1 (operation S113) and the second intermediate bit group IBTC2 (operation S114). Therefore, when the value of the first bit group BTG1 is less than the first threshold value, each of the first intermediate bits Ib0, Ib1, Ib2, Ib3, and Ib4 of the first intermediate bit group IBTG1 is the same as the corresponding one of the first binary input bits b0, b1, b2, b3, and b4, and each of the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 of the second intermediate bit group IBTG2 is the same as the corresponding one of the check value CHK and the second binary input bits b5, b6, b7, b8, b9, and b10. FIG. 5 shows the operation of the second data conditioner in the intermediate data generator of FIG. 3 according to some example embodiments. Referring to FIGS. 3 and 5, in response to the value of the first bit group BTG1 being equal to or greater than the first threshold value, the second data conditioner 140 provides the manipulation parts b2xb3, b3', and b4 of the first binary input bits b0, b1, b2, b3, and b4 of the first bit group BTG1 and the parts b5 and b6 of the second binary input bits b5, b6, b7, b8, b9, and b10 of the second bit group BTG2 as the third sub-intermediate bit group IBTG21 (operation S211), provides the check value CHK, the specific constant 0, and the constant 0, and the remaining parts b7, b8, b9, and b10 of the second binary input bits b5, b6, b7, b8, b9, and b10 of the second bit group as the fourth sub-intermediate bit group IBTG22 (operation S212), and the first multiplexer 160 and the second multiplexer 165 respectively output the third sub-intermediate bit group IBTG21 and the fourth sub-intermediate bit group IBTG22 as the first intermediate bit group IBTG1 (operation S213) and the second intermediate bit group IBTC2 (operation S214). Here, "x" indicates logical multiplication, and "'" indicates logical NOT. Thus, when the value of the first bit group BTG1 is equal to or greater than the first threshold value, each of the first intermediate bits Ib0, Ib1, Ib2, Ib3, and Ib4 of the first intermediate bit group IBTG1 corresponds to the corresponding one of b2xb3, b3', b4, b5, and b6, and each of the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 of the second intermediate bit group IBTG2 corresponds to the corresponding one of CHK, 0, 0, b7, b8, b9, and b10. The first intermediate bit group IBTG1 may include a second number of the first intermediate bits Ib0, Ib1, Ib2, Ib3, and Ib4, and the second intermediate bit group may include a fourth number of the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11, and the fourth number is one greater than the third number. The fourth number may be 7. FIG. 6 shows an example of a second data conditioner in the intermediate data generator of FIG. 3 according to some example embodiments. Referring to FIG. 6, the second data conditioner 140 may include an AND gate 141 and an inverter 142. The AND gate 141 may perform an AND operation on the binary input bit b2 and the binary input bit b3, and provide the result of the AND operation as the intermediate bit Ib0. The inverter 142 may provide the intermediate bit Ib1 by inverting the binary input bit B3, and a specific constant "0" may be assigned to each of the intermediate bits Ib6 and Ib7. In some example embodiments, a specific constant "1" may be assigned to each of the intermediate bits Ib6 and Ib7. In addition, the second data conditioner 140 may provide the binary input bit b4 as the intermediate bit Ib2, may provide the binary input bit b5 as the intermediate bit Ib3, may provide the check value CHK as the intermediate bit Ib4, and may provide each of the binary input bits b7, b8, b9, and b10 as the corresponding one of the intermediate bits Ib8, Ib9, Ib10, and Ib11. FIG. 7 shows the operations of the first sub-encoder and the second sub-encoder in the encoder of FIG. 2 according to some example embodiments. Referring to FIG. 7, the first sub-encoder 170 can generate a first symbol group SG1 including the first three symbols S0, symbol S1, and symbol S2 by performing a first encoding of 5-bit to 3-symbol (5b3S) on a first intermediate bit group IBTG1 including a first intermediate bit Ib0, a first intermediate bit Ib1, a first intermediate bit Ib2, a first intermediate bit Ib3, and a first intermediate bit Ib4. The second sub-encoder 180 can generate a second symbol group SG2 including the second four symbols S3, symbol S4, symbol S5, and symbol S6 by performing a second encoding of 7-bit to 4-symbol (7b4S) on a second intermediate bit group IBTG2 including a second intermediate bit Ib5, a second intermediate bit Ib6, a second intermediate bit Ib7, a second intermediate bit Ib8, a second intermediate bit Ib9, and a second intermediate bit Ib10. The first sub-encoder 170 can perform the first encoding in parallel with the second sub-encoder 180 that performs the second encoding. Instead of encoding the 11-bit binary input bits b0, binary input bit b1, binary input bit b2, binary input bit b3, binary input bit b4, binary input bit b5, binary input bit b6, binary input bit b7, binary input bit b8, binary input bit b9, and binary input bit b10 into seven symbols at once, the encoder 110 in the transmitter 100 of FIG. 2 can divide the 11-bit binary input bits b0, binary input bit b1, binary input bit b2, binary input bit b3, binary input bit b4, binary input bit b5, binary input bit b6, binary input bit b7, binary input bit b8, binary input bit b9, and binary input bit b10 into a first bit group BTG1 including a second number of binary input bits b0, binary input bit b1, binary input bit b2, binary input bit b3, and binary input bit b4 and a second bit group BTG2 including a third number of binary input bits b5, binary input bit b6, binary input bit b7, binary input bit b8, binary input bit b9, and binary input bit b10, can generate a first intermediate bit group IBTG1 and a second intermediate bit group IBTG2 by manipulating the first bit group BTG1 and the second bit group BTG2 in different ways according to the value of the first bit group BTG1, and can generate a first symbol group SG1 including the first three symbols S0, symbol S1, and symbol S2 and a second symbol group SG2 including the second four symbols S3, symbol S4, symbol S5, and symbol S6 by encoding the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 in parallel. Therefore, when compared with the case where the encoder 110 encodes eleven binary input bits b0, binary input bit b1, binary input bit b2, binary input bit b3, binary input bit b4, binary input bit b5, binary input bit b6, binary input bit b7, binary input bit b8, binary input bit b9, and binary input bit b10 into seven symbols at once, the encoder 110 reduces the occupied area and power consumption. FIG. 8 shows an example of a first look-up table used by the first sub-encoder in FIG. 7 according to some example embodiments. Referring to FIG. 8, the first sub-encoder 170 in FIG. 7 can perform a first encoding of 5 bits to 3 symbols (5b3S) by using a first look-up table LUT1 indicating the mapping relationship between the first intermediate bits Ib0, first intermediate bit Ib1, first intermediate bit Ib2, first intermediate bit Ib3, and first intermediate bit Ib4 and the first symbols S0, first symbol S1, and first symbol S2. In FIG. 8, Ib[0:4] represents the first intermediate bits Ib0, first intermediate bit Ib1, first intermediate bit Ib2, first intermediate bit Ib3, and first intermediate bit Ib4, and when the value of the first bit group BTG1 is less than the first threshold value (e.g., 26), each of the first intermediate bits Ib0, first intermediate bit Ib1, first intermediate bit Ib2, first intermediate bit Ib3, and first intermediate bit Ib4 in the first intermediate bit group IBTG1 is the same as the corresponding one of the first binary input bits b0, first binary input bit b1, first binary input bit b2, first binary input bit b3, and first binary input bit b4 as mentioned above. Therefore, Ib[0:4] in FIG. 8 corresponds to the first binary input bits b0, first binary input bit b1, first binary input bit b2, first binary input bit b3, and first binary input bit b4. When the first binary input bits b0, first binary input bit b1, first binary input bit b2, first binary input bit b3, and first binary input bit b4 are mapped to the first symbols S0, first symbol S1, and first symbol S2, 2 5 (i.e., 32) combinations are possible. When the value of the first bit group BTG1 is equal to or greater than the first threshold value (e.g., 26), the first binary input bits b0, b1, b2, b3, and b4 are not assigned to the first symbols S0, S1, and S2. When the values of the first binary input bits b0, b1, b2, b3, and b4 correspond to one of '0' to '25', the first binary input bits b0, b1, b2, b3, and b4 are mapped to the first symbols S0, S1, and S2. Symbol S0 can represent 2 bits t[0:1] of the output data signal TX_OUT, symbol S1 can represent 2 bits t[2:3] of the output data signal TX_OUT, and symbol S2 can represent 2 bits t[4:5] of the output data signal TX_OUT. Figure 9 is an example table of implementing the first lookup table of Figure 8 by gate-level logic. Referring to Figure 9, the check value CHK in the first lookup table LUT1 and the bits t0, t1, t2, t3, t4, and t5 of the output data signal TX_OUT are expressed as the following Expression 1. [Expression 1] CHK = Ib0xIb1xIb3+Ib0xIb1xIb2 t0 = Ib0'+Ib1 t1 = Ib0xIb1xIb4+Ib0'xIb1' t2 = Ib0'xIb2'+Ib1'xIb2'+Ib2xIb4 t3 = Ib2'xIb3+Ib3xIb4 t4 = Ib0'xIb4+Ib1'xIb4+Ib2 t5 = bI2xIb4+Ib2xIb3 The bits t0, t1, t2, t3, t4, and t5 of the output data signal TX_OUT can be obtained based on the combination of the first intermediate bits Ib0, Ib1, Ib2, Ib3, and Ib4. Figures 10A, 10B, and 10C show examples of the second lookup table used by the second sub-encoder in Figure 7 according to some example embodiments. Referring to FIGS. 10A, 10B, and 10C, the first sub-encoder 180 in FIG. 7 can perform a second encoding of 7 bits to 4 symbols (7b4S) by using a second look-up table LUT2 indicating the mapping relationship between the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, and Ib10 and the second symbols S3, S4, S5, and S6. In FIGS. 10A, 10B, and 10C, Ib[5:11] represents the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11, and when the values of the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 are equal to or greater than 80 (e.g., the second threshold value), the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 are not mapped to the second symbols S3, S4, S5, and S6. When the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 are mapped to the second symbols S3, S4, S5, and S6, 2 7 (i.e., 128) combinations are possible. However, when the values of the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 correspond to one of '0' to '79', the second sub-encoder 180 can use 80 combinations, and the second sub-encoder 180 does not use the combinations in which the values of the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 are equal to or greater than 80. Symbol S3 can represent 2 bits t[6:7] of the output data signal TX_OUT, symbol S4 can represent 2 bits t[8:9] of the output data signal TX_OUT, symbol S5 can represent 2 bits t[10:11] of the output data signal TX_OUT, and symbol S6 can represent 2 bits t[12:13] of the output data signal TX_OUT. Referring to the first lookup table LUT1 in FIG. 8 and the second lookup table LUT2 in FIGS. 10A, 10B, and 10C, when the value of the first bit group BTG1 is less than the first threshold value, the first sub-encoder 170 in FIG. 7 can generate 26 combinations of the first symbol S0, the first symbol S1, and the first symbol S2 based on the first binary input bit b0, the first binary input bit b1, the first binary input bit b2, the first binary input bit b3, and the first binary input bit b4, and the second first sub-encoder 180 in FIG. 7 can generate 64 combinations of the second symbol S3, the second symbol S4, the second symbol S5, and the second symbol S6 based on the second binary input bit b5, the second binary input bit b6, the second binary input bit b7, the second binary input bit b8, the second binary input bit b9, and the second binary input bit b10. Therefore, when the value of the first bit group BTG1 is less than the first threshold value, the first sub-encoder 170 and the second sub-encoder 180 in FIG. 7 can generate 1664 (i.e., 26x64) combinations of the symbol S0, the symbol S1, the symbol S2, the symbol S3, the symbol S4, the symbol S5, and the symbol S6. In addition, when the value of the first bit group BTG1 is equal to or greater than the first threshold value, the first sub-encoder 170 can generate 24 combinations of the first symbol S0, the first symbol S1, and the first symbol S2 based on the first binary input bit b0, the first binary input bit b1, the first binary input bit b2, the first binary input bit b3, the first binary input bit b4, and parts b5 and b6 of the second binary input bit b5, the second binary input bit b6, the second binary input bit b7, the second binary input bit b8, the second binary input bit b9, and the second binary input bit b10, and the second first sub-encoder 180 can generate 16 combinations of the second symbol S3, the second symbol S4, the second symbol S5, and the second symbol S6 based on the remaining parts b7, b8, b9, and b10 of the second binary input bit b5, the second binary input bit b6, the second binary input bit b7, the second binary input bit b8, the second binary input bit b9, and the second binary input bit b10. Therefore, when the value of the first bit group BTG1 is equal to or greater than the first threshold value, the first sub-encoder 170 and the second sub-encoder 180 in FIG. 7 can generate 384 (i.e., 24x16) combinations of the symbol S0, the symbol S1, the symbol S2, the symbol S3, the symbol S4, the symbol S5, and the symbol S6. Therefore, the encoder 110 can generate 2048 combinations of symbols S0, S1, S2, S3, S4, S5, and S6 based on the first number of binary input bits b0, binary input bit b1, binary input bit b2, binary input bit b3, binary input bit b4, binary input bit b5, binary input bit b6, binary input bit b7, binary input bit b8, binary input bit b9, and binary input bit b10. FIG. 11 is an example table of implementing the second look-up table of FIGS. 10A, 10B, and 10C by gate-level logic. Referring to FIG. 11, bits t6, t7, t8, t9, t10, t11, t12, and t13 of the output data signal TX_OUT in the second look-up table LUT2 are expressed as the following Expression 2. [Expression 2] t6 = Ib5'xIb6'+Ib8xIb9'+Ib8xIb11+Ib6xIb8 t7 = Ib5xIb8xIb9'xIb10+Ib5xIb8xIb10xIb11+Ib6'xIb7+Ib7xIb8 t8 = Ib5'xIb8+Ib8xIb11+Ib8xIb9+Ib6 t9 = Ib5xIb8xIb9xIb11+ Ib5xIb8xIb9xIb10+Ib6xIb8+ Ib6xIb7 t10 = Ib5'xIb9'+ Ib8'xIb9'+ Ib5'xIb11+ Ib8'xIb11 t11 = Ib5'xIb9'xIb10+ Ib8'xIb9'xIb10+ Ib5'xIb10xIb11+ Ib8'xIb10xIb11 t12 = Ib5'xIb11+Ib8'xIb11+Ib5'xIb9+Ib8'xIb9 t13 = Ib5'xIb9xIb11+ Ib8'xIb9xIb11+Ib5'xIb9xIb10+ Ib8'xIb9xIb10 Bits t6, t7, t8, t9, t10, t11, t12, and t13 of the output data signal TX_OUT can be obtained based on the combinations of the second intermediate bits Ib5, second intermediate bit Ib6, second intermediate bit Ib7, second intermediate bit Ib8, second intermediate bit Ib9, second intermediate bit Ib10, and second intermediate bit Ib11. FIG. 12 is a block diagram showing an example of the receiver in FIG. 1 according to some example embodiments. Referring to FIG. 12, the receiver 200 can include a decoder 210 and a buffer 290. The decoder 210 can generate a first intermediate bit group IBTG1 and a second intermediate bit group IBTG2 by separately decoding a first symbol group SG1 and a second symbol group SG2 of an input data signal (RX_IN in FIG. 1). Each of the symbol groups includes a plurality of symbols having three different voltage levels, and can generate a first bit group BTG1 and a second bit group BTG2 by manipulating the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 in different ways based on the values of specific bits of the second intermediate bit group IBTG2. The buffer 290 can generate an output data signal RX_OUT including a first number of binary output bits by buffering the first bit group BTG1 and the second bit group BTG2. The output data signal RX_OUT can be referred to as a recovered data signal RDT. The decoder 210 can include a first sub-decoder 220, a second sub-decoder 230, and a data recovery circuit 240. The first sub-decoder 220 can generate a first intermediate bit group IBTG1 including a first intermediate bit Ib0, a first intermediate bit Ib1, a first intermediate bit Ib2, a first intermediate bit Ib3, and a first intermediate bit Ib4 by decoding a first symbol group SG1 including a first symbol S0, a first symbol S1, and a first symbol S2. The second sub-decoder 230 can generate a second intermediate bit group IBTG2 including a second intermediate bit Ib5, a second intermediate bit Ib6, a second intermediate bit Ib7, a second intermediate bit Ib8, a second intermediate bit Ib9, a second intermediate bit Ib10, and a second intermediate bit Ib11 by decoding a second symbol group SG2 including a second symbol S3, a second symbol S4, a second symbol S5, and a second symbol S6. The first sub-decoder 220 can generate a first intermediate bit group IBTG1 including five bits, namely a first intermediate bit Ib0, a first intermediate bit Ib1, a first intermediate bit Ib2, a first intermediate bit Ib3, and a first intermediate bit Ib4, by performing a first decoding of 3 symbols to 5 bits (3S5b) on a first symbol group SG1 including the first three symbols S0, symbol S1, and symbol S2. The second sub-decoder 220 can generate a second intermediate bit group IBTG2 including seven bits, namely a second intermediate bit Ib5, a second intermediate bit Ib6, a second intermediate bit Ib7, a second intermediate bit Ib8, a second intermediate bit Ib9, a second intermediate bit Ib10, and a second intermediate bit Ib11, by performing a second decoding of 4 symbols to 7 bits (4S7b) on a second symbol group SG2 including the second four symbols S3, symbol S4, symbol S5, and symbol S6. The first decoder 220 can perform the first decoding in parallel with the second decoder 230 that performs the second decoding. The data recovery circuit 240 can recover the first bit group BTG1 and the second bit group BTG2 by manipulating the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 in different ways based on the values of specific bits of the second intermediate bit group IBTG2. FIG. 13 is a block diagram showing an example of the data recovery circuit in the receiver of FIG. 12 according to some example embodiments. Referring to FIG. 13, the data recovery circuit 240 may include a check value extractor 241, a demultiplexer 243, a first data recovery logic 250, a second data recovery logic 260, a first multiplexer 270, and a second multiplexer 275. The check value extractor 241 can output a check value CHK by extracting specific bits from the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 of the second intermediate bit group IBTG2. The check value extractor 241 can extract the first bit Ib5 as the check value CHK from the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11, and can provide the check value CHK to the demultiplexer 243, the first multiplexer 270, and the second multiplexer 275. The demultiplexer 243 can provide the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 to the first data recovery logic 250 in response to the check value CHK having a first logic level (e.g., a logic low level), and can provide the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 to the second data recovery logic 260 in response to the check value CHK having a second logic level (e.g., a logic high level). The first data recovery logic 250 can generate a first sub-bit group BTG11 and a second sub-bit group BTG12 by respectively manipulating the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 according to a first scheme in response to the check value having a first logic level. The second data recovery logic 260 can generate a third sub-bit group BTG21 and a fourth sub-bit group BTG22 by respectively manipulating the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 according to a second scheme different from the first scheme in response to the check value having a second logic level. The first multiplexer 270 can receive the first sub-bit group BTG11 and the third sub-bit group BTG21, and can output one of the first sub-bit group BTG11 and the third sub-bit group BTG21 as the first bit group BTG1 based on the check value CHK. The second multiplexer 275 can receive the second sub-bit group BTG12 and the fourth sub-bit group BTG22, and can output one of the second sub-bit group BTG12 and the fourth sub-bit group BTG22 as the second bit group BTG2 based on the check value CHK. The first multiplexer 270 and the second multiplexer 275 can output the first sub-bit group BTG11 and the second sub-bit group BTG12 as the first bit group BTG1 and the second bit group BTG2 respectively in response to the check value having a first logic level, and can output the third sub-bit group BTG21 and the fourth sub-bit group BTG22 as the first bit group BTG1 and the second bit group BTG respectively in response to the check value having a second logic level. FIG. 14 shows the operation of the first data recovery logic in FIG. 13 according to some example embodiments. Referring to FIGS. 13 and 14, in response to the check value having a first logic level, the first data recovery logic 250 provides a first intermediate bit group IBTG1 including the first intermediate bits Ib0, Ib1, the first intermediate bit Ib2, the first intermediate bit Ib3, and the first intermediate bit Ib4 as the first sub-bit group BTG11 (operation S611), and provides the second intermediate bits Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 as the second sub-bit group BTG12 by eliminating the first bit Ib5 from the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 (operation S613). In addition, since the first multiplexer 270 and the second multiplexer 275 can respectively output the first sub-bit group BTG11 and the second sub-bit group BTG12 as the first bit group BTG1 and the second bit group BTG2, the output data bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, and b10 of the restored data signal RDT can include the first intermediate bits Ib0, Ib1, Ib2, Ib3, and Ib4 and the second intermediate bits Ib6, Ib7, Ib8, Ib9, Ib10 (operation S615). As described with reference to FIG. 4, each of the first intermediate bits Ib0, Ib1, Ib2, Ib3, and Ib4 corresponds to the corresponding one of the bits b0, b1, b2, b3, and b4, and each of the second intermediate bits Ib6, Ib7, Ib8, Ib9, Ib10 corresponds to the corresponding one of the bits b5, b6, b7, b8, b9, and b10. FIG. 15 shows the operation of the second data recovery logic in FIG. 13 according to some example embodiments. Referring to FIGS. 13 and 15, in response to the check value having a second logic level, the second data recovery logic 260 provides a third sub-bit group BTG21 including bits 1, 1, Ib1 + Ib0, Ib', Ib2 by filling specific bits with a specific constant and by manipulating a part of the first intermediate bits Ib0, Ib1, Ib2, Ib3, and Ib4 of the first intermediate bit group IBTG1 (operation S621), and provides the remaining part Ib3 and part Ib4 of the first intermediate bits Ib0, Ib1, Ib2, Ib3, and Ib4 and parts Ib8, Ib9, Ib10, and Ib11 of the second intermediate bit group IBTG2 as a fourth sub-bit group BTG22 (operation S623). In addition, since the first multiplexer 270 and the second multiplexer 275 can respectively output the third sub-bit group BTG21 and the fourth sub-bit group BTG22 as the first bit group BTG1 and the second bit group BTG2, the output data bits b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, and b10 of the restored data signal RDT can include bit 1, bit 1, bit Ib1 + Ib0, bit Ib', bit Ib2 and bit Ib3, bit Ib4, bit Ib8, bit Ib9, bit Ib10, and bit Ib11 (operation S625). FIG. 16 shows an example table representing the relationship between the bits of the first symbol and the first intermediate bits in the receiver of FIG. 12 according to some example embodiments. Referring to FIG. 16, the relationship between the bits t0, t1, t2, t3, t4, and t5 of the first symbol S0, the first symbol S1, and the first symbol S2 and the first intermediate bits Ib0, Ib1, Ib2, Ib3, and Ib4 is expressed as the following Expression 3. [Expression 3] Ib0 = t2'xt4'+t0' Ib1 = t0xt1'+ t2xt4' Ib2 = t2'xt4'+t5 Ib3 = t2'xt5+t3 Ib4 = t1xt2'xt4'+ t2xt4 When the first decoder 220 performs the first decoding by using the first look-up table LUT of FIG. 8, the first decoder 220 can use Expression 3. FIG. 17 shows an example table representing the relationship between the bits of the second symbol and the second intermediate bits in the receiver of FIG. 12 according to some example embodiments. Referring to FIG. 17, the relationship between the bits t6, t7, t8, t9, t10, t11, t12, and t13 of the second symbol S3, the second symbol S4, the second symbol S5, and the second symbol S6 and the second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11 is expressed as the following Expression 4. [Expression 4] Ib5 = t6'xt8'+t10'xt12' Ib6 = t6'xt8xt10+ t6'xt8xt12+t9xt10+t9xt12 Ib7 = t6'xt9xt10+ t6'xt9xt12+t7xt10+t7xt12 Ib8 = t6xt8+t10xt12 Ib9 = t10'xt12+ t6'xt10'+t9xt10'+t9xt13 Ib10 = t6'xt9xt10'xt12'+ t7xt10'xt12'+t10'xt13xt11 Ib11 = t6xt8xt10'xt12'+ t10xt12 When the second decoder 230 performs the second decoding, the second decoder 230 may use Expression 4. FIG. 18 is a flowchart illustrating a method of operating a transmitter according to some example embodiments. Referring to FIGS. 2 to 11 and FIG. 18, an encoder 110 of a transmitter 100 divides a first number of binary input bits of an input data signal TX_IN into a first bit group BTG1 and a second bit group BTG2 (operation S100). When the input data signal TX_IN includes the first number of binary input bits b0, binary input bit b1, binary input bit b2, binary input bit b3, binary input bit b4, binary input bit b5, binary input bit b6, binary input bit b7, binary input bit b8, binary input bit b9, and binary input bit b10, the first bit group BTG1 includes the second number of binary input bits b0, binary input bit b1, binary input bit b2, binary input bit b3, and binary input bit b4, the second bit group BTG2 includes the third number of binary input bits b5, binary input bit b6, binary input bit b7, binary input bit b8, binary input bit b9, and binary input bit b10, and the third number may be greater than the second number. The intermediate data generator 120 of the encoder 110 generates a first intermediate bit group IBTG1 and a second intermediate bit group IBTG2 by manipulating the first bit group BTG1 and the second bit group BTG2 in different ways based on the value of the first group BTG1 (operation S200). The first intermediate bit group IBTG1 may include a second number of first intermediate bits Ib0, Ib1, Ib2, Ib3, and Ib4, and the second intermediate bit group IBTG2 may include a fourth number of second intermediate bits Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, and Ib11. The fourth number may be greater than the third number. The first sub-encoder 170 and the second sub-encoder 180 of the encoder 170 generate a first symbol group SG1 including a first symbol S0, a first symbol S1, and a first symbol S2 and a second symbol group SG2 including a second symbol S3, a second symbol S4, a second symbol S5, and a second symbol S6 by encoding the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2, respectively (operation S300). The driver 190 may generate an output data signal TX_OUT by concatenating the first symbol group SG1 and the second symbol group SG2 (operation S400), and may transmit the output data signal TX_OUT to the receiver 200 via the channel 50. FIG. 19 is a flowchart showing the operations of generating the first intermediate bit group and the second intermediate bit group. Referring to FIGS. 3 and 19, to generate the first intermediate bit group IBTG1 and the second intermediate bit group IBTG2 (operation S200), the check value generator 121 determines whether the value of the first bit group BTG1 (e.g., the decimal value of the first bit group BTG1) is equal to or greater than a first threshold value (operation S210). The check value generator 121 receives the first bit group BTG1 and may generate a check value CHK indicating whether the value of the first bit group BTG1 is equal to or greater than the first threshold value. In response to the value of the check value CHK being less than the first threshold value (No in S210), the first data conditioner 130 and the first multiplexer 160 generate the second intermediate bit group IBTG2 based on the check value CHK and the second bit group BTG2, while generating the first intermediate bit group IBTG1 based on the first bit group BTG1 (operation S230). In response to the value of the check value CHK being equal to or greater than the first threshold value (Yes in S210), the second data conditioner 140 and the second multiplexer 165 generate a second intermediate bit group IBTG2 based on the check value CHK and the second bit group BTG2, and at the same time generate a first intermediate bit group IBTG1 based on the first bit group BTG1 and the second bit group BTG2 (operation S250). Therefore, according to the transmitter and the method of operating the transmitter, instead of encoding the first number of binary input bits into symbols at once, the encoder 110 divides the first number of binary inputs into a first bit group including the second number of binary input bits and a second bit group including the third number of binary input bits, generates a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group in different ways according to the value of the first bit group, and generates a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group in parallel. Therefore, the encoder 110 can reduce the occupied area and power consumption. FIG. 20 is a block diagram showing a memory system according to some example embodiments. Referring to FIG. 20, the memory system 300 may include a memory controller 305 and a semiconductor memory device 400. The memory system 300 may further include a plurality of signal lines 330 that electrically connect the memory controller 305 and the semiconductor memory device 400. The semiconductor memory device 400 may be controlled by the memory controller 305. For example, based on a request from a host (not shown), the memory controller 305 may store (e.g., write or program) data into the semiconductor memory device 400, or may retrieve (e.g., read or sense) data from the semiconductor memory device 400. The plurality of signal lines 330 may include control lines, command lines, address lines, data input / output (I / O) lines, and power lines. The memory controller 305 may transmit a command CMD, an address ADDR, and a control signal CTRL to the semiconductor memory device 400 via the command lines, address lines, and control lines, may exchange data signals MLDAT with the semiconductor memory device 400 via the data I / O lines, and may transmit a power supply voltage PWR to the semiconductor memory device 400 via the power lines. For example, the data signal MLDAT may be a PAM-3 multi-level signal generated and transmitted according to some example embodiments. Although not shown in FIG. 20, the plurality of signal lines 330 may further include DQS lines for transmitting data strobe signal (DQS) signals. In some example embodiments, at least a portion or all of the signal line 330 may be referred to as a channel. The term "channel" as used herein may refer to a signal line including data I / O lines for transmitting data signals MLDAT. However, example embodiments are not limited thereto, and a channel may further include command lines for transmitting commands CMD and / or address lines for transmitting addresses ADDR. FIGS. 21 and 22 are block diagrams illustrating example embodiments of the memory system of FIG. 20. Referring to FIGS. 21 and 22, the memory system 301 may include a graphics processing unit (GPU) 310, a semiconductor memory device 400a, and a plurality of channels 31a, 31b, and 31c. The GPU 310 may include a plurality of transmitters 25a, 25b, and 25c, a plurality of receivers 27a, 27b, and 27c, and a plurality of data I / O pads 29a, 29b, and 29c. The semiconductor memory device 400a may include a plurality of transmitters 45a, 45b, and 45c, a plurality of receivers 47a, 47b, and 47c, and a plurality of data I / O pads 49a, 49b, and 49c. Each of the plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c may generate a PAM-3 multilevel signal and may perform a method of generating a multilevel signal. Each of the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c may receive a PAM-3 multilevel signal. The plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c and the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c may transmit and receive PAM-3 multilevel signals via the plurality of channels 31a, 31b, and 31c. Each of the plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c may employ the transmitter 100 of FIG. 2, and each of the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c may employ the receiver 200 of FIG. 12. Each of a plurality of data I / O pads 29a, data I / O pad 29b, data I / O pad 29c, data I / O pad 49a, data I / O pad 49b, and data I / O pad 49c can be connected to a corresponding one of a plurality of transmitters 25a, transmitter 25b, transmitter 25c, transmitter 45a, transmitter 45b, and transmitter 45c and a corresponding one of a plurality of receivers 27a, receiver 27b, receiver 27c, receiver 47a, receiver 47b, and receiver 47c. A plurality of channels 31a, channel 31b, and channel 31c can connect the GPU 310 and the semiconductor memory device 400a. Each of the plurality of channels 31a, channel 31b, and channel 31c can be connected to a corresponding one of a plurality of transmitters 25a, transmitter 25b, and transmitter 25c and a corresponding one of a plurality of receivers 27a, receiver 27b, and receiver 27c via a plurality of data I / O pads 29a, data I / O pad 29b, and data I / O pad 29c. Additionally, each of the plurality of channels 31a, channel 31b, and channel 31c can be connected to a corresponding one of a plurality of transmitters 45a, transmitter 45b, and transmitter 45c and a corresponding one of a plurality of receivers 47a, receiver 47b, and receiver 47c via a corresponding one of the plurality of data I / O pads 49a, data I / O pad 49b, and data I / O pad 49c. A PAM-3 multi-level signal can be transmitted via each of the plurality of channels 31a, channel 31b, and channel 31c. FIG. 21 shows an operation of transmitting data from the GPU 310 to the semiconductor memory device 400a. For example, the transmitter 25a can generate an output data signal DS11 as a PAM-3 multi-level signal based on the input data DAT11, the output data signal DS11 can be transmitted from the GPU 310 to the semiconductor memory device 400a via the channel 31a, and the receiver 47a can receive the output data signal DS11 to obtain the data ODAT11 corresponding to the input data DAT11. Similarly, the transmitter 25b can generate an output data signal DS21 as a PAM-3 multi-level signal based on the input data DAT21. The output data signal DS21 can be transmitted via the channel 31b to the semiconductor memory device 400a, and the receiver 47b can receive the output data signal DS21 to obtain the data ODAT21 corresponding to the input data DAT21. The transmitter 25c can generate an output data signal DSN1 as a PAM-3 multi-level signal based on the input data DATN1. The output data signal DSN1 can be transmitted via the channel 31c to the semiconductor memory device 400a, and the receiver 47c can receive the output data signal DSN1 to obtain the data ODATN1 corresponding to the input data DATN1. For example, the input data DAT11, the input data DAT21, and the input data DATN1 can be write data to be written into the semiconductor memory device 400a. FIG. 22 shows an operation of transmitting data from the semiconductor memory device 400a to the GPU 310. For example, the transmitter 45a can generate an output data signal DS12 as a PAM-3 multi-level signal based on the input data DAT12. The output data signal DS12 can be transmitted from the semiconductor memory device 400a to the GPU 310 via the channel 31a, and the receiver 27a can receive the output data signal DS12 to obtain the data ODAT12 corresponding to the input data DAT12. Similarly, the transmitter 45b can generate an output data signal DS22 as a PAM-3 multi-level signal based on the input data DAT22. The output data signal DS22 can be transmitted to the GPU 310 via the channel 31b, and the receiver 27b can receive the output data signal DS22 to obtain the data ODAT22 corresponding to the input data DAT22. The transmitter 45c can generate an output data signal DSN2 as a PAM-3 multi-level signal based on the input data DATN2. The output data signal DSN2 can be transmitted to the GPU 310 via the channel 31c, and the receiver 27c can receive the output data signal DSN2 to obtain the data ODATN2 corresponding to the input data DATN2. For example, the input data DAT12, the input data DAT22, and the input data DATN2 can be read data fetched from the semiconductor memory device 400a. FIG. 23 is a block diagram showing an example of a semiconductor memory device included in the memory system of FIGS. 21 and 22 according to some example embodiments. Referring to FIG. 23, the semiconductor memory device 400a may include a control logic circuit 410, an address register 420, a memory bank control logic 430, a refresh counter 445, a column address multiplexer 440, a row address latch 450, a column decoder 460, a row decoder 470, a memory cell array 510, a sense amplifier unit 485, an I / O gating circuit 490, an error correction code (ECC) engine 590, an on-die termination (ODT) circuit 497, and a data I / O buffer 495. For example, the semiconductor memory device 400a may be a volatile memory device and may include a Graphics Double Data Rate 7 (GDDR7) synchronous dynamic random access memory (SDRAM) device. The memory cell array 510 includes a first memory bank array 510a to an eighth memory bank array 510h. The column decoder 460 includes a first memory bank column decoder 460a to an eighth memory bank column decoder 460h respectively coupled to the first memory bank array 510a to the eighth memory bank array 510h. The row decoder 470 includes a first memory bank row decoder 470a to an eighth memory bank row decoder 470h respectively coupled to the first memory bank array 510a to the eighth memory bank array 510h. And the sense amplifier unit 485 includes a first memory bank sense amplifier 485a to an eighth memory bank sense amplifier 485h respectively coupled to the first memory bank array 510a to the eighth memory bank array 510h. The first memory bank array 510a to the eighth memory bank array 510h, the first memory bank column decoder 460a to the eighth memory bank column decoder 460h, the first memory bank row decoder 470a to the eighth memory bank row decoder 470h, and the first memory bank sense amplifier 485a to the eighth memory bank sense amplifier 485h may form the first memory bank to the eighth memory bank. Each of the first memory bank array 510a to the eighth memory bank array 510h may include a plurality of memory cells MC formed at the intersections of a plurality of word lines WL and a plurality of bit lines BTL. The address register 420 can receive an address ADDR including a memory bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller in the GPU 310. The address register 420 can provide the received memory bank address BANK_ADDR to the memory bank control logic 430, can provide the received row address ROW_ADDR to the row address multiplexer 440, and can provide the received column address COL_ADDR to the column address latch 450. The memory bank control logic 430 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, one of the first memory bank column decoders 510a to the eighth memory bank column decoders 510h corresponding to the memory bank address BANK_ADDR can be activated, and in response to the memory bank control signal, one of the first memory bank row decoders 470a to the eighth memory bank row decoders 470h corresponding to the memory bank address BANK_ADDR can be activated. The row address multiplexer 440 can receive the row address ROW_ADDR from the address register 420 and can receive the refresh row address REF_ADDR from the refresh counter 445. The row address multiplexer 440 can selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 440 is applied to the first memory bank column decoders 460a to the eighth memory bank column decoders 460h. The refresh counter 445 can sequentially output the refresh row address REF_ADDR under the control of the control logic circuit 410. One of the first memory bank column decoders 460a to the eighth memory bank column decoders 460h activated by the memory bank control logic 430 can decode the row address RA output from the row address multiplexer 440 and can activate the word line corresponding to the row address RA. For example, the activated memory bank column decoder applies a word line drive voltage to the word line corresponding to the row address. The column address latch 450 can receive the column address COL_ADDR from the address register 420 and can temporarily store the received column address COL_ADDR. In some example embodiments, in burst mode, the column address latch 450 generates a column address COL_ADDR' incremented from the received column address COL_ADDR. The column address latch 450 can apply the temporarily stored column address COL_ADDR or the generated column address COL_ADDR' to the first memory bank row decoders 470a to the eighth memory bank row decoders 470h. One of the activated first to eighth memory bank row decoders 470a - 470h can activate a sense amplifier corresponding to a memory bank address BANK_ADDR and a column address COL_ADDR via the I / O gating circuit 490. The I / O gating circuit 490 may include circuitry for gating input / output data, and further includes input data masking logic, a read data latch for storing data output from the first to eighth memory bank arrays 510a - 510h, and a write driver for writing data to the first to eighth memory bank arrays 510a - 510h. A codeword CW read from one of the first to eighth memory bank arrays 510a - 510h can be sensed by a sense amplifier of a memory bank array from which the data is read, and stored in the read data latch. After performing ECC decoding on the codeword CW by the ECC engine 590, the codeword CW stored in the read data latch can be provided to the memory controller via the data I / O buffer 495. Multi - level data MLDAT to be written into one of the first to eighth memory bank arrays 510a - 510h can be provided from the memory controller to the data I / O buffer 495, provided from the data I / O buffer 495 to the ECC engine 590. The ECC engine 590 can perform ECC encoding on the multi - level data MLDAT to generate parity bits. The ECC engine 590 can provide the multi - level data MLDAT and the parity bits to the I / O gating circuit 490, and the I / O gating circuit 490 can write the multi - level data MLDAT and the parity bits into a sub - page in a memory bank array via the write driver. The data I / O buffer 495 can provide multi - level data MLDAT to the ECC engine 590 during a write operation of the semiconductor memory device 400a, and provide multi - level data MLDAT from the ECC engine 590 to the memory controller during a read operation of the semiconductor memory device 400a. The ECC engine 590 can perform ECC encoding and ECC decoding on the multi - level data MLDAT according to the control of the control logic circuit 410. The control logic circuit 410 can control the operation of the semiconductor memory device 400a. For example, the control logic circuit 410 can generate control signals for the semiconductor memory device 400a to perform a write operation or a read operation. The control logic circuit 410 may include a command decoder 411 for decoding a command CMD received from the memory controller and a mode register 412 for setting the operation mode of the semiconductor memory device 400a. For example, the command decoder 411 may generate control signals corresponding to the command CMD by decoding a write enable signal, a column address select signal, a row address select signal, a chip select signal, etc. The ODT circuit 497 may be connected to the data I / O pads 499 and the data I / O buffers 495. When the ODT circuit 497 is enabled, the ODT circuit 497 may perform an ODT operation. When performing the ODT operation, the signal integrity of the transmitted / received signal may be enhanced by preventing signal reflections due to impedance matching. Although the semiconductor memory device included in the memory system according to some example embodiments is described based on DRAM, the semiconductor memory device according to other example embodiments may be any volatile memory device and / or any non-volatile memory device, such as flash memory, phase random access memory (PRAM), resistive random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), thyristor random access memory (TRAM), etc., but the example embodiments are not limited thereto. FIG. 24 shows an example embodiment of the first memory bank array in the semiconductor memory device of FIG. 23. Referring to FIG. 24, the first memory bank array 510a may include a plurality of word lines WL0 to WLm-1 (where m is an even number equal to or greater than two), a plurality of bit lines BTL0 to BTLn-1 (where n is an even number equal to or greater than two), and a plurality of memory cells MC disposed at the intersection points between the word lines WL0 to WLm-1 and the bit lines BTL0 to BTLn-1. The bit lines BTL0 to BTLn-1 may extend in a first direction D1, and the word lines WL to WLm-1 may extend in a second direction D2 that intersects the first direction D1. Each of the memory cells MC includes an access (cell) transistor coupled to one of word lines WL0 to WLm-1 and one of bit lines BTL0 to BTLn-1, and a storage (cell) capacitor coupled to the cell transistor. That is, each of the memory cells MC has a DRAM cell structure. In addition, the memory cell MC may have different configurations depending on whether the memory cell MC is coupled to an even word line (e.g., WL0) or an odd word line (e.g., WL1). That is, the bit lines coupled to adjacent memory cells may be different depending on whether the word line selected by the access address is an even word line or an odd word line. However, the example embodiments are not limited thereto. The memory cells MC coupled to the even word line (e.g., WL0) and the odd word line (e.g., WL1) may have the same or substantially the same configuration. FIG. 25 is a block diagram showing a semiconductor memory device according to some example embodiments. Referring to FIG. 25, the semiconductor memory device 700 may include at least one buffer die 710 that provides a soft error analysis and correction function in a stacked die structure and a plurality of memory dies 720-1 to memory dies 720-p (p is a natural number equal to or greater than three). The plurality of memory dies 720-1 to memory dies 720-p are stacked on the buffer die 710 and transfer data via a plurality of through silicon via (TSV) lines. Each of the memory dies 720-1 to memory dies 720-p may include a memory core that stores data and a unit core ECC engine 722 that generates a transmission parity bit (e.g., transmission parity data) based on the transmission data to be sent to at least one buffer die 710. The unit core 721 may include a plurality of memory cells having a DRAM cell structure. The buffer die 710 may include a via ECC engine 712 that uses the transmission parity bit to correct a transmission error when the transmission error is detected from the transmission data received via the TSV line and error correction data is generated. The buffer die 710 may further include a receiver 713 and a transmitter 714. The transmitter 714 may adopt the transmitter 100 of FIG. 2, and the receiver 713 may adopt the receiver 200 of FIG. 12. Therefore, instead of encoding the first number of binary input bits provided by the through-hole ECC engine 712 into symbols at once, the transmitter 714 divides the first number of binary inputs into a first bit group including a second number of binary input bits and a second bit group including a third number of binary input bits, generates a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group in different ways according to the value of the first bit group, and generates a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group in parallel. Therefore, the transmitter 714 can reduce the occupied area and power consumption of the encoder included in the transmitter 714. In addition, the receiver 713 may perform operations on the input data signal from the memory controller, and the operations are opposite to those of the transmitter 714. The semiconductor memory device 700 may be a stacked die type memory device or a stacked memory device that transmits data and control signals via TSV lines. The TSV lines may also be referred to as 'through electrodes'. The unit core ECC engine 722 may perform error correction on the data output from the memory die 720-p before transmitting the transmission data. The transmission errors occurring at the transmission data may be attributed to the noise occurring at the TSV lines. The data failures caused by the noise occurring at the TSV lines can be distinguished from the data failures attributed to the incorrect operation of the memory die, so they can be regarded as soft data failures (or soft errors). The soft data failures may be generated due to transmission failures on the transmission path and can be detected and corrected by ECC operations. By the above description, the data TSV line group 732 formed at one memory die 720-p may include the TSV line L1 and the TSV lines L2 to Lp, and the parity TSV line group 734 may include the TSV lines L10 to Lq. The TSV line L1 and the TSV lines L2 to Lp of the data TSV line group 732 and the parity TSV lines L10 to the parity TSV lines Lq of the parity TSV line group 734 may be connected to the microbumps MCB formed correspondingly in the memory dies 720-1 to 720-p. At least one of the memory dies 720-1 to 720-p may include DRAM cells each including at least one access transistor and one storage capacitor. The semiconductor memory device 700 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a host via a data bus B10. The buffer die 710 may be connected to a memory controller via the data bus B10. The unit core ECC engine 723 may output and transmit parity bits and transmit data via a parity TSV line group 734 and a data TSV line group 732, respectively. The output transmitted data may be data that has been error-corrected by the unit core ECC engine 723. Based on the transmitted parity bits received via the parity TSV line group 734, the via ECC engine 712 may determine whether a transmission error has occurred in the transmitted data received via the data TSV line group 732. When a transmission error is detected, the via ECC engine 712 may use the transmitted parity bits to correct the transmission error on the transmitted data. When the transmission error cannot be corrected, the via ECC engine 712 may output information indicating that an uncorrectable data error has occurred. FIG. 26 is a diagram showing a semiconductor package including a stacked memory device according to some example embodiments. Referring to FIG. 26, the semiconductor package 900 may include one or more stacked memory devices 910 and a GPU 920, and the GPU 920 includes a memory controller (CONT) 925. The stacked memory devices 910 and the GPU 920 may be mounted on an insert 930, and the insert 930 on which the stacked memory devices 910 and the GPU 920 are mounted may be mounted on a package substrate 940. The package substrate 940 may be mounted on solder balls 950. The memory controller 925 may employ the memory controller in FIG. 1. Each of the stacked memory devices 910 may be implemented in various forms and may be a memory device in the form of a high bandwidth memory (HBM) in which multiple layers are stacked. Thus, each of the stacked memory devices 910 may include a buffer die and multiple memory dies, and each of the multiple memory dies may include a unit core. The unit core ECC engine and the buffer die may include a via ECC engine, a transmitter, and a receiver. Multiple stacked memory devices 910 may be mounted on the insert 930, and the GPU 920 may communicate with the multiple stacked memory devices 910. For example, each of the stacked memory devices 910 and the GPU 920 may include a physical area, and communication may be performed between the stacked memory devices 910 and the GPU 920 via the physical area. The inventive concept can be applied to various electronic devices and systems including memory devices and memory systems. For example, the inventive concept can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, internet of things (IoT) devices, internet of everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc., but the example embodiments are not limited thereto. It will be understood that elements and / or their attributes described herein as "substantially" the same and / or consistent encompass elements and / or their attributes having a relative difference equal to or less than 10% in magnitude. In addition, whether or not the elements and / or their attributes are modified as "substantially", it will be understood that such elements and / or their attributes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) with respect to the stated elements and / or their attributes. One or more of the elements disclosed above may include one or more processing circuitry systems or be implemented in one or more processing circuitry systems, such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof. For example, the processing circuitry system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FGPA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The foregoing shows some example embodiments and is not to be construed as limiting thereof. Although several example embodiments have been described, those of ordinary skill in the art will readily appreciate that many modifications may be made to the example embodiments without materially departing from the novel teachings and advantages of the present invention concept. Accordingly, all such modifications are intended to be included within the scope of the present invention concept. 31a, 31b, 31c, 50: Channels 25a, 25b, 25c, 45a, 45b, 45c, 100, 714: Transmitters 27a, 27b, 27c, 47a, 47b, 47c, 200, 713: Receivers 29a, 29b, 29c, 49a, 49b, 49c, 499: Data I / O Pads 110: Encoder 120: Intermediate Data Generator 121: Check Value Generator 123: First Demultiplexer 125: Second Demultiplexer 130: First Data Adjuster 140: Second Data Adjuster 141: AND Gate 142: Inverter 160: First Multiplexer 165: Second Multiplexer 170: First Sub-encoder 180: Second Sub-encoder 190: Driver 210: Decoder 220: First Sub-decoder 230: Second Sub-decoder 240: Data Recovery Circuit 241: Check Value Extractor 243: Demultiplexer 250: First Data Recovery Logic 260: Second Data Recovery Logic 270: First Multiplexer 275: Second Multiplexer 290: Buffer 300, 301: Memory System 305, 925: Memory Controller 310, 920: Graphics Processing Unit 330: Signal Line 400, 400a, 700: Semiconductor Memory Device 410: Control Logic Circuit 411: Command Decoder 412: Mode Register 420: Address Register 430: Memory Bank Control Logic 440: Column Address Multiplexer 445: Refresh Counter 450: Row Address Latch 460: Column Decoder 460a: First Memory Bank Column Decoder 460h: Eighth Memory Bank Column Decoder 470: Row Decoder 470a: First Memory Bank Row Decoder 470h: Eighth Memory Bank Row Decoder 485: Sense Amplifier Unit 485a: First Memory Bank Sense Amplifier 485h: Eighth Memory Bank Sense Amplifier 490: I / O Gate Control Circuit 495: Data I / O Buffer 497: Die-Level Termination Circuit 510: Memory Cell Array 510a: First Memory Bank Array 510h: Eighth Memory Bank Array 590: Error Correction Code Engine 710: Buffer Die 712: Through-Silicon Via ECC Engine 720-1, 720-2, 720-p-1, 720-p: Memory Dies 721: Cell Core 723: Cell Core ECC Engine 732: Data TSV Line Group 734: Parity TSV Line Group 900: Semiconductor Package 910: Stacked Memory Device 930: Insert 940: Package Substrate 950: Solder Balls ADDR: Address b0, b1, b2, b3, b4: First Binary Input Bits b5, b6, b7, b8, b9, b10: Second Binary Input Bits B10: Data BusBANK_ADDR: Memory bank address BTG1: First bit group BTG2: Second bit group BTL, BTL0, BTL1, BTL2, BTLn-2, BTLn-1: Bit lines CHK: Check value CMD: Command COL_ADDR, COL_ADDR': Column address CTRL: Control signal CW: Codeword D1: First direction D2: Second direction DAT11, DAT12, DAT21, DAT22, DATN1, DATN2: Input data DS11, DS12, DS21, DS22, DSN1, DSN2: Output data signal Ib0, Ib1, Ib2, Ib3, Ib4: First intermediate bit Ib5, Ib6, Ib7, Ib8, Ib9, Ib10, Ib11: Second intermediate bit IBTG1: First intermediate bit group IBTG2: Second intermediate bit group IBTG11: First sub-intermediate bit group IBTG12: Second sub-intermediate bit group IBTG21: Third sub-intermediate bit group IBTG22: Fourth sub-intermediate bit group L1, L2, L10, Lp, Lq: TSV lines LUT1: First look-up table LUT2: Second look-up table MC: Memory cell MCB: Micro bump MLDAT: Data signal / multi-level data ODAT11, ODAT12, ODAT21, ODAT22, ODATN1, ODATN2: Data PWR: Power supply voltage RA, ROW_ADDR: Row address RDT: Recovery data signal REF_ADDR: Refresh row address RX_IN, TX_IN: Input data signal RX_OUT, TX_OUT: Output data signal S0, S1, S2: First symbol S3, S4, S5, S6: Second symbol S100, S111, S112, S113, S114, S200, S210, S211, S212, S213, S214, S230, S250, S300, S400, S611, S613, S615, S621, S623, S625: Operations SG1: First symbol group SG2: Second symbol group t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13: Bits VL1: First voltage level VL2: Second voltage level VL3: Third voltage level VL4: Fourth voltage level WL, WL0, WL1, WLm-2, WLm-1: Word lines The following detailed description, taken in conjunction with the accompanying drawings, will more clearly understand the illustrative, non-limiting example embodiments. FIG. 1 is a block diagram showing a transmitter and a receiver according to some example embodiments. FIG. 2 is a block diagram showing an example of the transmitter in FIG. 1 according to some example embodiments. FIG. 3 is a block diagram showing an example of an intermediate data generator in the transmitter of FIG. 2 according to some example embodiments. FIG. 4 shows the operation of a first data conditioner in the intermediate data generator of FIG. 3 according to some example embodiments. FIG. 5 shows the operation of a second data conditioner in the intermediate data generator of FIG. 3 according to some example embodiments. FIG. 6 shows an example of the second data conditioner in the intermediate data generator of FIG. 3 according to some example embodiments. FIG. 7 shows the operation of a first sub-encoder and a second sub-encoder in the encoder of FIG. 2 according to some example embodiments. FIG. 8 shows an example of a first look-up table used by the first sub-encoder in FIG. 7 according to some example embodiments. FIG. 9 is an example table implementing the first look-up table of FIG. 8 by gate-level logic. FIGS. 10A, 10B, and 10C show examples of a second look-up table used by the second sub-encoder in FIG. 7 according to some example embodiments. FIG. 11 is an example table implementing the second look-up table of FIGS. 10A, 10B, and 10C by gate-level logic. FIG. 12 is a block diagram showing an example of the receiver in FIG. 1 according to some example embodiments. FIG. 13 is a block diagram showing an example of a data recovery circuit in the receiver of FIG. 12 according to some example embodiments. FIG. 14 shows the operation of a first data recovery logic in FIG. 13 according to some example embodiments. FIG. 15 shows the operation of a second data recovery logic in FIG. 13 according to some example embodiments. FIG. 16 shows an example table representing the relationship between the bits of a first symbol and a first intermediate bit in the receiver of FIG. 12 according to some example embodiments. FIG. 17 shows an example table representing the relationship between the bits of a second symbol and a second intermediate bit in the receiver of FIG. 12 according to some example embodiments. FIG. 18 is a flowchart showing a method of operating a transmitter according to some example embodiments. FIG. 19 is a flowchart showing an operation of generating a first intermediate bit group and a second intermediate bit group. FIG. 20 is a block diagram showing a memory system according to some example embodiments. FIGS. 21 and 22 are block diagrams showing examples of the memory system of FIG. 20. FIG. 23 is a block diagram showing an example of a semiconductor memory device included in the memory systems of FIGS. 21 and 22 according to some example embodiments. FIG. 24 shows an example of a first memory bank array in the semiconductor memory device of FIG. 23. FIG. 25 is a block diagram showing a semiconductor memory device according to some example embodiments. FIG. 26 is a diagram showing a semiconductor package including a stacked memory device according to some example embodiments. 50: Channel 100: Transmitter 200: Receiver RX_IN, TX_IN: Input data signals RX_OUT, TX_OUT: Output data signals VL1: First voltage level VL2: Second voltage level VL3: Third voltage level

Claims

1. A transmitter, comprising: An encoder is configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group in different ways based on the value of the first bit group, generate a first symbol group by encoding the first intermediate bit group, and generate a second symbol group by encoding the second intermediate bit group, each of the first symbol group and the second symbol group comprising a plurality of symbols, each of the plurality of symbols having three different voltage levels; and a driver is configured to generate an output data signal by concatenating the first symbol group and the second symbol group, the driver being configured to transmit the output data signal via a channel.

2. The transmitter as described in claim 1, wherein: The first bit group includes a second number of binary input bits from the first number of binary input bits; the second bit group includes a third number of binary input bits from the first number of binary input bits, and the third number is greater than the second number; the first intermediate bit group includes a second number of first intermediate bits; the second intermediate bit group includes a fourth number of second intermediate bits, and the fourth number is one greater than the third number; the first symbol group includes a fifth number of first symbols, and the fifth number is less than the first number. The second symbol group contains a sixth number of second symbols, the sixth number being less than the fourth number and greater than the fifth number.

3. The transmitter as claimed in claim 2, wherein the encoder comprises: an intermediate data generator configured to generate the first intermediate bit group and the second intermediate bit group by manipulating the first bit group and the second bit group; a first sub-encoder configured to generate the first symbol group by encoding the first intermediate bit group; and a second sub-encoder configured to generate the second symbol group by encoding the second intermediate bit group.

4. The transmitter as claimed in claim 3, wherein the intermediate data generator comprises: a check value generator configured to receive the first bit group, the check value generator being configured to generate a check value indicating whether the value of the first bit group is equal to or greater than a first threshold value; a first data processor configured to, in response to the value of the first bit group being less than the first threshold value, generate a first sub-intermediate bit group by manipulating the first bit group according to a first scheme, and generate a second sub-intermediate bit group by manipulating the second bit group according to the first scheme; and a second data processor configured to, in response to the value of the first bit group... The value is based on the check value being equal to or greater than the first threshold value. A third sub-intermediate bit group is generated by manipulating the first bit group according to a second scheme, and a fourth sub-intermediate bit group is generated by manipulating the second bit group according to the second scheme, wherein the second scheme is different from the first scheme; a first multiplexer is configured to output one of the first sub-intermediate bit group and the third sub-intermediate bit group as the first intermediate bit group based on the check value; and a second multiplexer is configured to output one of the second sub-intermediate bit group and the fourth sub-intermediate bit group as the second intermediate bit group based on the check value.

5. The transmitter as claimed in claim 4, wherein the second data processor is configured to manipulate the first bit group such that the value of the third sub-intermediate bit group is less than the first threshold value, and the second data processor is configured to manipulate the second bit group such that the value of the fourth sub-intermediate bit group is less than the second threshold value.

6. The transmitter as claimed in claim 4, wherein the intermediate data generator further comprises: a first demultiplexer configured to provide the first bit group and the second bit group to the first data processor in response to a check value indicating that the value of the first bit group is less than the first threshold value, and the first demultiplexer configured to provide the first bit group and the second bit group to the second data processor in response to a check value indicating that the value of the first bit group is equal to or greater than the first threshold value; and a second demultiplexer configured to provide the check value to the first data processor in response to a check value indicating that the value of the first bit group is less than the first threshold value, and the second demultiplexer configured to provide the check value to the second data processor in response to a check value indicating that the value of the first bit group is equal to or greater than the first threshold value.

7. The transmitter as claimed in claim 4, wherein in response to the value of the first bit group being less than the first threshold value, the first data processor is configured to provide the first bit group as the first sub-intermediate bit group, and the first data processor is configured to provide the check value and the second bit group as the second sub-intermediate bit group.

8. The transmitter of claim 4, wherein in response to the value of the first bit group being equal to or greater than the first threshold value, the second data processor is configured to provide a manipulated portion of the first binary input bits of the first bit group and a portion of the second binary input bits of the second bit group as the third sub-intermediate bit group, and the second data processor is configured to provide the check value, a specific constant, and the remainder of the second binary input bits of the second bit group as the fourth sub-intermediate bit group.

9. The transmitter as described in claim 3, wherein: The first sub-encoder is configured to generate a first symbol group containing three first symbols by performing a first encoding on a first intermediate bit group containing a first intermediate bit corresponding to five bits; and the second sub-encoder is configured to generate a second symbol group containing five second symbols by performing a second encoding on a second intermediate bit group containing a second intermediate bit corresponding to seven bits.

10. The transmitter as claimed in claim 9, wherein the first sub-encoder is configured to perform the first encoding in parallel with the second sub-encoder performing the first encoding.

11. The transmitter as claimed in claim 9, wherein: The first sub-encoder is configured to perform the first encoding using a first lookup table indicating the mapping relationship between the first intermediate bit and the three first symbols; and the second sub-encoder is configured to perform the second encoding using a second lookup table indicating the mapping relationship between the second intermediate bit and the five second symbols.

12. A receiver, comprising: A decoder is configured to generate a first intermediate bit group by decoding a first symbol group of the input data signal, and a second intermediate bit group by decoding a second symbol group of the input data signal, each of the first and second symbol groups comprising a plurality of symbols, each of the plurality of symbols having three different voltage levels, and to generate a first bit group and a second bit group by manipulating the first and second intermediate bit groups in different ways based on the values ​​of specific bits of the second intermediate bit group; and a buffer is configured to generate an output data signal comprising a first number of binary output bits by buffering the first and second bit groups.

13. The receiver as described in claim 12, wherein: The first bit group includes a second number of binary output bits from the first number of binary output bits; the second bit group includes a third number of binary output bits from the first number of binary output bits, and the third number is greater than the second number; the first intermediate bit group includes a second number of first intermediate bits; the second intermediate bit group includes a fourth number of second intermediate bits, and the fourth number is one greater than the third number; the first symbol group includes a fifth number of first symbols, and the fifth number is less than the first number. The second symbol group contains a sixth number of second symbols, the sixth number being less than the fourth number and greater than the fifth number.

14. The receiver of claim 13, wherein the decoder comprises: a first sub-decoder configured to generate the first intermediate bit group by decoding the first symbol group; a second sub-decoder configured to generate the second intermediate bit group by decoding the second symbol group; and data recovery circuitry configured to recover the first bit group and the second bit group by manipulating the first intermediate bit group and the second intermediate bit group in different ways based on the values ​​of specific bits of the second intermediate bit group.

15. The receiver of claim 14, wherein the data recovery circuitry comprises: a check value extractor configured to output a check value by extracting a specific bit from a second intermediate bit group; a first data recovery logic configured to generate a first sub-bit group by manipulating the first intermediate bit group according to a first scheme, and to generate a second sub-bit group by manipulating the second intermediate bit group according to the first scheme, in response to the check value having a first logic level; a second data recovery logic configured to generate a third sub-bit group by manipulating the first intermediate bit group according to a second scheme, and to generate a fourth sub-bit group by manipulating the second intermediate bit group according to the second scheme, wherein the second scheme is different from the first scheme; a first multiplexer configured to output one of the first sub-bit group and the third sub-bit group as the first bit group based on the check value; and a second multiplexer configured to output one of the second sub-bit group and the fourth sub-bit group as the second bit group based on the check value.

16. The receiver as claimed in claim 15, wherein the data recovery circuit further includes a multiplexer configured to: provide a first intermediate bit group and a second intermediate bit group to the first data recovery logic in response to the check value having the first logic level; and provide the first intermediate bit group and the second intermediate bit group to the second data recovery logic in response to the check value having the second logic level.

17. The receiver as claimed in claim 15, wherein in response to the check value having the first logic level, the first data recovery logic is configured to: provide the first intermediate bit group as the first sub-bit group; and provide the second sub-bit group by eliminating the specific bit from the second intermediate bit group.

18. The receiver as claimed in claim 15, wherein the response to the check value has the second logic level, and the second data recovery logic is configured to: provide the third sub-bit group by filling the specific bit with a specific constant and manipulating a portion of the first intermediate bit of the first intermediate bit group; and provide the remaining portion of the first intermediate bit of the first intermediate bit group and a portion of the second intermediate bit of the second intermediate bit group as the fourth sub-bit group.

19. A system for pulse amplitude modulation signal transmission, comprising: A transmitter, including an encoder and a driver, is configured to output write data to be stored in a semiconductor memory device; The channel is configured to transmit the written data; The encoder is configured to divide a first number of binary input bits of the input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group in different ways based on the value of the first bit group, generate a first symbol group by encoding the first intermediate bit group, and generate a second symbol group by encoding the second intermediate bit group, each of the first symbol group and the second symbol group contains a plurality of symbols, each of the plurality of symbols having three different voltage levels, and the driver is configured to receive the written data by serially connecting the first symbol group and the second intermediate bit group. The output data signal is generated by the second symbol group and configured to be transmitted via the channel; and the decoder is configured to receive the output data signal containing the first symbol group and the second symbol group, generate the first intermediate bit group by decoding the first symbol group, generate the second intermediate bit group by decoding the second symbol group, generate the first bit group and the second bit group by manipulating the first intermediate bit group and the second intermediate bit group in different ways based on the value of a specific bit of the second intermediate bit group, and the buffer is configured to generate an output data signal containing the first number of binary output bits by buffering the first bit group and the second bit group.

20. The system as described in claim 19, wherein: The input data signal, the output data signal, and the output data correspond to the written data; the transmitter is included in a graphics processing unit (GPU) configured to generate the written data; and the semiconductor memory device includes a graphics double data rate 7 (GDDR7) synchronous dynamic random access memory (SDRAM) device.

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