Memory system and operating method thereof

Abstract

This invention relates to a memory system comprising: a main memory device configured to include a plurality of column lines; a cache memory device configured to include a plurality of cache columns, column knock status values, and access selection bits, wherein the plurality of cache columns are used to store data in the cache column lines, each cache column includes cached data, the column knock status values ​​are used to store the number of accesses for the corresponding column line, and the access selection bits are set according to the column knock status values; and a memory controller configured to respond to a request from a host to control an access operation to be performed on one of the main memory device and the cache memory device, wherein one of the main memory device and the cache memory device is selected according to the access selection bits of the cache column hit by the cache.

Description

Technical Field

[0001] Various embodiments of the present invention relate to a semiconductor design technique, and more specifically, to a memory system including a semiconductor memory device and a method of operating the same. Prior Technology

[0002] Recently, the computing paradigm has shifted to ubiquitous computing environments where computer systems can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use data storage devices with memory. This data storage device is used to store data for the portable electronic device. Because data storage devices using memory do not have mechanical drives, they offer excellent stability and durability, high data access speeds, and low power consumption.

[0003] However, when memory cells are accessed consecutively, adjacent memory cells may be continuously exposed to the electromagnetic fields generated by this access, and the likelihood of data distortion in the memory cells may increase. This phenomenon is called row hammering.

[0004] Cross-referencing of related applications: This application claims priority to Korean Patent Application No. 10-2022-0084986, filed on July 11, 2022, the entire contents of which are incorporated herein by reference. Summary of the Invention

[0005] The embodiments of the present invention relate to a memory system that can store the number of accesses to each column line of the main memory device as column knock status values ​​in the cache column of the cache memory device, and manage access to the main memory device based on the stored column knock status values.

[0006] According to an embodiment of the present invention, a memory system includes: a main memory device configured to include a plurality of column lines; a cache memory device configured to include a plurality of cache columns, column knock state values, and access selection bits, wherein the plurality of cache columns are used to store data in the cache column lines, each cache column includes cached data, the column knock state values ​​are used to store the number of accesses for the corresponding column line, and the access selection bits are set according to the column knock state values; and a memory controller configured to control an access operation to be performed on one of the main memory device and the cache memory device in response to a request from a host, wherein one of the main memory device and the cache memory device is selected according to the access selection bits of the cache column hit by the cache.

[0007] According to an embodiment of the present invention, an operation method of a memory system includes: when a host requests an access operation on a column line of a main memory device, searching for a cache column that has been hit from a plurality of cache columns of a cache memory device; performing an access operation on one of the main memory device and the cache memory according to the access selection bit of the cache column that has been hit; and incrementing the column knock state value of the cache column that has been hit when performing an access operation on the column line, and setting the access selection bit when the column knock state value reaches a threshold.

[0008] According to an embodiment of the present invention, the memory system can prevent data corruption and distortion caused by column knocking by allowing access to the column lines of the main memory device before the number of accesses to the column lines reaches a threshold, and allowing access to the cache columns of the cache memory device when the number of accesses to the column lines reaches the threshold.

[0009] Furthermore, according to embodiments of the present invention, in a memory system that communicates with the host via a Compute Xpress Link (CXL) interface, limited memory resources can be used efficiently by managing the number of accesses per column line using existing cache memory devices. Simple Explanation of the Diagram

[0010] Figure 1 is a block diagram illustrating a data storage device according to an embodiment of the present invention. Figure 2 is a configuration diagram of a memory system according to an embodiment of the present invention. Figure 3 is a detailed configuration diagram of the cache memory device shown in Figure 2 according to an embodiment of the present invention. Figures 4 to 6 are flowcharts describing the operation of a memory system according to an embodiment of the present invention. Figures 7A to 7E are diagrams illustrating exemplary operation of a memory system according to an embodiment of the present invention. Figures 8A to 8H are diagrams illustrating exemplary operation of a memory system according to an embodiment of the present invention. Figure 9 is a block diagram illustrating a data storage device according to another embodiment of the present invention. Figure 10 is a block diagram illustrating a data storage device according to another embodiment of the present invention. Implementation

[0011] Referring to the drawings, various embodiments of the present invention will now be described in more detail. The present invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout the invention, the same reference numerals refer to the same parts in the various drawings and embodiments of the invention.

[0012] It will be understood that when an element is referred to as "coupled" or "connected" to another element, this may mean that the two elements are directly coupled, or that the two elements are electrically connected to each other through another circuit inserted therebetween. It will be further understood that the terms "comprising," "including," "having," etc., as used herein specify the presence of the stated features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In this invention, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0013] In the following embodiments, in order to focus on the refresh operation, the description of the configuration related to the data input / output operation will be omitted, and the main description column will control the operation.

[0014] Figure 1 is a block diagram illustrating a data storage device 1 according to an embodiment of the present invention.

[0015] Referring to FIG1, the data storage device 1 may include a host 10 and a memory system 20.

[0016] Host 10 can be a standalone and functional processor referred to as a core, and can be implemented using a single processor or as a multi-core processor including two or more processors. Host 10 can communicate with memory system 20 using at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), High Speed ​​Compute Link (CXL), Universal Flash (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0017] The memory system 20 can store or retrieve stored data according to requests provided by the host 10. The memory system 20 can be used as the main storage device or auxiliary storage device of the host 10. The memory system 20 can be used as a device for storing data under the control of the host 10, and examples of such devices include: mobile phones, smartphones, MP3 players, laptops, desktop computers, game consoles, TVs, tablet PCs, or in-vehicle infotainment systems.

[0018] Depending on the host interface, which serves as the communication method with host 10, memory system 20 can be manufactured as one of various types of devices. For example, memory system 20 can be configured as one of various types of memory modules such as: SSD, multimedia cards in the form of MMC, eMMC, RS-MMC and micro MMC, secure digital cards in the form of SD, mini SD, and micro SD, universal serial bus (USB) memory modules, universal flash (UFS) devices, PCMCIA card-type memory devices, peripheral component interconnect (PCI) card-type memory devices, high-speed PCI (PCI-e or PCIe) card-type memory devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0019] The memory system 20 can be manufactured in any of a variety of package types. For example, the memory system 20 can be manufactured in any of the following package types: POP (Package-on-Package), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-to-Bag (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0020] In detail, the memory system 20 may include a memory controller 100 and a memory device 200.

[0021] The memory controller 100 can control all operations of the memory system 20 and control data exchange between the host 10 and the memory device 200. By generating commands CMD and addresses ADDR according to requests REQ from the host 10 and providing these commands CMD and addresses ADDR to the memory device 200, the memory controller 100 can control write (or program) operations and read operations of the memory device 200. For example, during a write operation, the memory controller 100 can provide data DQ provided from the host 10 to the memory device 200. During a read operation, the memory controller 100 can provide data DQ read from the memory device 200 to the host 10.

[0022] The memory device 200 can operate in response to the control of the memory controller 100. The memory device 200 can perform write (or program) operations, read operations, etc., according to the commands CMD, address ADDR and / or data DQ provided by the memory controller 100.

[0023] In the embodiments, the memory device 200 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Fourth Generation Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Transfer Torque Random Access Memory (STT-RAM), etc.

[0024] In the following text, the data transferred between the host 10 and the memory controller 100 is referred to as host data HDATA, the data DQ provided from the memory controller 100 to the memory device 200 during a write operation is referred to as write data WDATA, and the data DQ read from the memory device 200 during a read operation is referred to as read data RDATA.

[0025] Figure 2 is a configuration diagram of a memory system 20 according to an embodiment of the present invention.

[0026] Referring to Figure 2, the memory controller 100 can respond to the request REQ from the host 10 by providing the command CMD and address ADDR to the memory device 200, exchanging host data HDATA with the host 10, and exchanging data DQ with the memory device 200. For example, during a read operation, the memory controller 100 can provide the read data RDATA read from the memory device 200 as host data HDATA to the host 10, and during a write operation, it can provide the host data HDATA provided by the host 10 as write data WDATA to the memory device 200.

[0027] Memory device 200 can receive commands CMD, addresses ADDR, and / or data DQ provided by memory controller 100. When command CMD indicates a write operation, memory device 200 can write write data WDATA to the memory region selected by address ADDR. When command CMD indicates a read operation, memory device 200 can read read data RDATA from the memory region selected by address ADDR and output the read data RDATA to memory controller 100. Memory device 200 may include main memory device 210 and cache memory device 220 for caching data stored in main memory device 210. Main memory device 210 may be configured using at least one of the memory devices described above with reference to FIG1. ​​Cache memory device 220 may include dynamic random access memory (DRAM) and static RAM (SRAM). Preferably, main memory device 210 may be implemented as DRAM, and cache memory device 220 may be implemented as SRAM.

[0028] Main memory device 210 may include memory cell array 212, in which multiple memory cells are arranged in an array between multiple word lines (hereinafter referred to as column lines (RL1 to RLn, where n is a natural number)) and multiple bit lines (hereinafter referred to as row lines). Main memory device 210 may access a region of memory cell array 212 selected by address ADDR to perform an operation indicated by command CMD. For example, main memory device 210 may perform write (or program) operations, read operations, etc. During a write operation, main memory device 210 may program write data WDATA into the region selected by address ADDR. During a read operation, main memory device 210 may read data RDATA from the region selected by address ADDR. In these instances, address ADDR may include column addresses and row addresses, and the region selected by address ADDR may be the region defined by the column lines specified by the column addresses and the row lines specified by the row addresses.

[0029] In the following, in embodiments of the present invention, a startup operation performed on a column-by-column basis may be defined as an access operation. For example, the access operation may include a write (or program) operation and a read operation that require accessing a column line specified by a column address. Additionally, in an embodiment, the main memory device 210 is a memory device having a memory cell array including column lines. Without being limited to any particular type or implementation, the memory device may generate column strikes.

[0030] The cache memory device 220 is a high-speed memory device that temporarily stores information between a processor with a relatively high processing speed (i.e., the memory controller 100) and a main memory device 210 with a relatively low processing speed. The cache memory device 220 may include a plurality of cache columns CL1 to CLm (where m is a natural number) for caching data stored in the column lines RL1 to RLn. Preferably, the number m of the cache columns CL1 to CLm may be less than the number n of the column lines RL1 to RLn (i.e., m < n). In an embodiment, each of the cache columns CL1 to CLm of the cache memory device 220 may correspond to one of the column lines RL1 to RLn, and may include a column strike status value ("RH_S" in FIG. 3) for storing the access count of the corresponding column line and an access selection bit ("AS" in FIG. 3) set according to the column strike status value RH_S. The detailed configuration of the cache memory device 220 will be described with reference to FIG. 3. <(

[0031] On the other hand, the cache memory device 220 may be characterized in that when the device is full of cache due to limited space, existing data must be deleted to load new data. For this purpose, data with a low data reference probability may be deleted according to a cache replacement policy, or may be written back to the main memory device 210 and the space may be replaced with new data.

[0032] The memory controller 100 may include a host interface (I / F) 110, a processor 120, a buffer memory 130, an access manager 140, a memory interface (I / F) 150, and a bus 170.

[0033] The host interface 110 can be configured to communicate with a host coupled to the memory system 20 under the control of the processor 120. For example, the host interface 110 can receive requests (REQ) and host data (HDATA) from the host, and can receive data (DQ) read from the memory device 200 through the memory interface 150 and output the data DQ as host data (HDATA) to the host. In particular, in embodiments of the present invention, the host interface 110 can communicate with the host through a compute link (CXL) interface or a dual in-line memory module (DIMM) interface.

[0034] Processor 120 can perform various operations or include firmware for controlling memory device 200. Processor 120 may include a microcontroller unit (MCU) and a central processing unit (CPU). Processor 120 can receive requests (REQ) and host data (HDATA) from a host through host interface 110. Processor 120 can generate various commands (e.g., start commands, read commands, and write commands) and addresses corresponding to requests (REQ) and transmit them along with host data (HDATA) to memory device 200 through memory interface 150. Processor 120 typically controls host interface 110, buffer memory 130, access manager 140, and memory interface 150.

[0035] Buffer memory 130 can temporarily store data to be transferred from the host to memory device 200 or from memory device 200 to the host. Preferably, buffer memory 130 can be configured as random access memory such as DRAM and SRAM. Although FIG2 shows buffer memory 130 located in memory controller 100, the invention is not particularly limited thereto, but buffer memory 130 can be located outside memory controller 100.

[0036] Access manager 140 can manage cache columns CL1 to CLm of cache memory device 220. For example, assuming that the second cache column CL2 corresponds to the k-th column line RLk, whenever an access operation is performed on the k-th column line RLk (i.e., when accessing or starting the k-th column line RLk), access manager 140 can increment the column knock status value RH_S of the second cache column CL2, which is the cache hit column. In addition, access manager 140 can set the access selection bit AS of the second cache column CL2 that is the cache hit based on the column knock status value RH_S. For example, access manager 140 can set a threshold for data corruption due to column knock, setting the access selection bit AS to a low bit when the column knock status value RH_S is less than the threshold, and setting the access selection bit AS to a high bit when the column knock status value RH_S reaches the threshold. The access manager 140 can control the access operation to the cache column that has been hit when the access selection bit AS of the cache column that has been hit is a high bit, and can control the access operation to the column line of the main memory device 320 or the cache column that has been hit when the access selection bit AS of the cache column that has been hit is a low bit.

[0037] The memory interface 150 can be configured to communicate with the memory device 200 under the control of the processor 120. For example, the memory interface 150 can transmit commands CMD, addresses ADDR, and / or write data WDATA to the memory device 200, and can transmit read data RDATA read from the memory device 200 to the host interface 110.

[0038] As described above, according to the present invention, the memory controller 100 is configured to control the execution of an access operation on one of the main memory device 210 and the cache memory device 220 based on the access selection bit AS of the cache column hit when performing an access operation in response to a request REQ from the host. Therefore, the memory system 20 can allow access to the column line of the main memory device 210 before the number of accesses to the column line reaches a threshold, and allow access to the cache column of the cache memory device 220 when the number of accesses to the column line reaches the threshold. Thus, column knocking, which causes data corruption in memory cells coupled to a specific column line or adjacent column lines due to a large number of activations of a specific column line, can be prevented.

[0039] Figure 3 is a detailed configuration diagram of the cache memory device 220 shown in Figure 2 according to an embodiment of the present invention.

[0040] Referring to FIG3, the cache memory device 220 may include multiple cache columns for caching data stored in the main memory device 210. For example, FIG3 shows a cache memory device 220 including cache columns 1 to 2048.

[0041] Each of the 1st to 2048th cache columns can include fields such as: a valid bit V, an access select bit AS, a column knock status value RH_S, a tag address TAG_A, and cache data CDATA. For example, Figure 3 shows each cache column CL, which includes a 1-bit valid bit V, a 1-bit access select bit AS, a 5-bit column knock status value RH_S, a 16-bit tag address TAG, and a 32-byte cache data CDATA field. According to an embodiment, each cache column may additionally include a column index to distinguish the 1st to 2048th cache columns.

[0042] The valid bit V can include information indicating whether a field in the corresponding cache column is valid, i.e., information indicating whether the corresponding cache column is in use. When a field is valid, the valid bit V can be set to a high bit. In the following text, a high bit is described as a set, and a low bit is described as a release.

[0043] The cached data CDATA can be write data WDATA stored in the main memory device 210 or read data RDATA to be read from the main memory device 210.

[0044] The tag address TAG_A may include address information (i.e., column address information) that specifies the position of the column line of the main memory device 210 corresponding to the respective cache column. For reference, when an access operation is requested from the host 10, the memory controller 100 can determine whether a cache hit or cache miss has occurred by searching the cache columns that have been hit based on the tag address TAG_A included in each cache column.

[0045] The column tap status value RH_S indicates the number of accesses to the column line corresponding to the corresponding cache column. The column tap status value RH_S can have a value that increments by "+1" each time the corresponding column line is accessed (or initiated) (i.e., each time an access operation (e.g., a read operation or a write operation) is performed on the corresponding column line). In Figure 3, the column tap status value RH_S consists of 5 bits, but embodiments of the invention are not limited to this, and the column tap status value RH_S can be set to 1 byte (i.e., 8 bits) or less.

[0046] The access selection bit AS can include information indicating the device performing the access operation, such as information about the main memory device 210 or the cache memory device 220. For example, an access operation can be performed on the column line of the main memory device 210 corresponding to the tag address TAG_A when the access selection bit AS is low, and an access operation can be performed on the corresponding cache column when the access selection bit AS is high.

[0047] Hereinafter, a method for operating a memory system according to an embodiment of the present invention will be described with reference to Figures 1 to 6.

[0048] Figures 4 to 6 are flowcharts describing the operation of a memory system according to an embodiment of the present invention.

[0049] Referring to FIG4, when a request REQ is received from the host 10 (in S410), the memory controller 100 can search the cache memory device 220 for a cache column with the tag address TAG_A corresponding to the request REQ (in S420). When a cache column with the tag address TAG_A corresponding to the request REQ is found (i.e., the cache column that is cached) (S420 is "Yes"), operation "A" will be described with reference to FIGS. 5 and 6.

[0050] If no cache column is found to be hit (S420 is "No"), that is, in the case of cache miss, the memory controller 100 can distinguish whether the request REQ is a request indicating a read operation (in S430).

[0051] When the request REQ is a request indicating a write operation (S430 is "No"), the memory controller 100 can control the memory device 200 to perform a write miss operation ("WRITE MISS"). The memory controller 100 can provide the main memory device 210 with a write command CMD, an address ADDR, and write data WDATA corresponding to the request REQ, and the main memory device 210 can perform a write operation to write the write data WDATA to the area selected by the address ADDR (in S440). In this case, one or more column lines can be selected through the column address in the address ADDR, and one or more row lines can be selected through the row address in the address ADDR, and a write operation can be performed on the area specified by the selected column line and the selected row line.

[0052] In the following description, the memory controller 100 may check whether the cache memory device 220 does not have empty cache columns (in S450). For example, the memory controller 100 may search for empty cache columns based on the valid bit V. The memory controller 100 may check the valid bit V of each cache column of the cache memory device 220 and obtain an empty cache column in which the valid bit V is freed to the low bit (S450 is "No").

[0053] If no empty cache column exists, the memory controller 100 can determine that the cache memory device 220 is full (S450: "Yes"), and can perform an eviction operation on one of the occupied cache columns by applying an eviction algorithm according to a cache replacement strategy (S460). For example, the eviction algorithm can be used based on a First-In-First-Out (FIFO) list, a Least Frequently Used (LFU) list, and a Least Recently Used (LRU) list, where the FIFO list selects the oldest cache column, the LFU list selects the least used cache column from those loaded into the cache memory device 220, and the LRU list selects the least recently used cache column from those loaded into the cache memory device 220. The memory controller 100 can initialize all fields of the selected cache column by applying the eviction algorithm. When the access select bit AS of the selected cache column is set to the high bit, the memory controller 100 can write the cache data CDATA back to the column line of the main memory device 210 corresponding to the tag address ADDR. Therefore, the memory controller 100 can acquire an empty cache column.

[0054] When an empty cache column is acquired, the memory controller 100 can add the new cache column to the cache memory device 220 by storing the write data WDATA as the cache data CDATA of the acquired cache column and setting the valid bit V of the acquired cache column to the high bit. In addition, the memory controller 100 can release the access selection bit AS of the acquired cache column to the low bit and initialize the column knock status value RH_S to "0" (in S470).

[0055] On the other hand, when the request REQ is a request indicating a read operation (S430 is "Yes"), the memory controller 100 can control the memory device 200 to perform a read miss operation ("READ MISS"). The memory controller 100 can provide the main memory device 210 with a read command CMD and an address ADDR corresponding to the request REQ, and the main memory device 210 can perform a read operation to read read data RDATA from the region selected by the address ADDR (in S480).

[0056] In the following description, the memory controller 100 can check whether the cache memory device 220 does not have an empty cache column based on the valid bit V (in S450). As described above, when there is no empty cache column (S450 is "yes"), the memory controller 100 can acquire an empty cache column by performing an eviction operation (in S460). After acquiring an empty cache column, the memory controller 100 can add the new cache column to the cache memory device 220 by storing the read data RDATA as the cache data CDATA of the acquired cache column and setting the valid bit V of the acquired cache column to a high bit. In addition, the memory controller 100 can release the access selection bit AS of the acquired cache column to a low bit and initialize the column knock status value RH_S to "0" (in S470).

[0057] Referring to Figure 5, operation "A" (S420 is "Yes") is shown for a cache hit. In the case of a cache hit, the memory controller 100 can distinguish whether the request REQ is a request indicating a read operation (in S510). When the request REQ is a request indicating a read operation (S510 is "Yes"), operation "B" will be described with reference to Figure 6.

[0058] Referring to Figure 5, if the request REQ is a request indicating a write operation (S510 is "No"), the memory controller 100 can control the memory device 200 to perform a write hit operation ("WRITE HIT"). The memory controller 100 can provide the memory device 200 with a write command CMD, address ADDR, and write data WDATA corresponding to the request REQ. The memory controller 100 can check whether the access select bit AS of the cache column hit has been released to low bits (in S520).

[0059] When the access select bit AS of the cache column hit is set to the high bit ("No" in S520), the memory controller 100 can control the cache memory device 220 to perform a write operation to write the data WDATA to the cache column hit in the cache memory device 220 (in S530). Therefore, the write operation is performed only on the cache column hit without accessing the main memory device 210, thereby preventing data corruption and distortion in the main memory device 210 due to column knock.

[0060] When the access select bit AS of the cache column that has been hit is released to a low bit (S520 is "Yes"), the memory controller 100 can check whether the column knock status value RH_S of the cache column that has been hit has reached a threshold (S540). If the column knock status value RH_S has not reached the threshold (S540 is "No"), the memory controller 100 can control the main memory device 210 to perform a write operation to write the write data WDATA to the area selected by the address ADDR (S550). After performing the write operation, the memory controller 100 can increment the column knock status value RH_S of the cache column that has been hit by "+1" (S560).

[0061] When the column knock status value RH_S reaches the threshold (S540 is "Yes"), the memory controller 100 can read data from the column line corresponding to address ADDR of the main memory device 210 and update the read data to the cache data CDATA of the cached column hit (S570). Additionally, the memory controller 100 can control the cache memory device 220 to perform a write operation that writes write data WDATA to the cached column hit (S580). For example, the write operation may include a mask write operation or a partial write operation. After performing the write operation, the memory controller 100 can set the access selection bit AS of the cached column hit to a high bit (S590).

[0062] According to the embodiment, when the column knock state value RH_S reaches a threshold (S540 is "Yes"), the memory controller 100 can control the main memory device 210 to perform a write operation and update the data read from the column line where the write operation is performed to the cache data CDATA of the cached column that was hit. On the other hand, in a memory system that does not perform a mask write operation or a partial write operation, the operation of reading data from the column line and updating the read data to the cache data CDATA of the cached column that was hit can be omitted (in S570).

[0063] Referring to Figure 6, operation "B" is shown, in which a read operation is requested via REQ (S510 is "Yes"). The memory controller 100 can control the memory device 200 to perform a read hit operation ("READ HIT"). The memory controller 100 can provide the memory device 200 with a read command CMD and address ADDR corresponding to the request REQ. The memory controller 100 can check whether the access select bit AS of the cache column hit has been released to low bit (in S610).

[0064] When the access select bit AS of the cache column that has been hit is set to a high bit ("No" in S610), the memory controller 100 can control the cache memory device 220 to perform a read operation to read data RDATA from the cache column that has been hit (in S620). Therefore, only the cache column that has been hit is read without accessing the main memory device 210, thereby preventing data corruption and distortion in the main memory device 210 caused by column knock.

[0065] When the access select bit AS of the cache column that has been hit is released to a low bit (S610 is "Yes"), the memory controller 100 can check whether the column knock status value RH_S of the cache column that has been hit is set to "0" (in S630). If the access select bit AS is released to a low bit and the column knock status value RH_S is "0" (S630 is "Yes"), no additional access operation is performed after adding the new cache column described in FIG4. That is, since the data stored in the column line is the same as the cache data CDATA of the cache column when no additional access operation is performed after adding the new cache column, the memory controller 100 can control the cache memory device 220 to perform a read operation (in S620). Therefore, column knocking can be prevented and operation latency and overhead can be reduced.

[0066] Referring to Figure 6, when the access select bit AS of the cache column hit is released to a low bit (S610 is "Yes") and the column knock status value RH_S of the cache column hit is not "0" (S630 is "No"), the memory controller 100 can check whether the column knock status value RH_S of the cache column hit has reached a threshold (in S640). When the column knock status value RH_S is greater than "0" but has not reached the threshold (S630 is "No" and S640 is "No"), the memory controller 100 can control the main memory device 210 to perform a read operation to read data RDATA from the region selected by address ADDR (in S650). After performing the read operation, the memory controller 100 can increment the column knock status value RH_S of the cache column hit by "+1" (in S660).

[0067] Alternatively, when the column knock status value RH_S reaches the threshold (S640 is "Yes"), the memory controller 100 can control the main memory device 210 to perform a read operation to read the read data RDATA (S670), and update the read data RDATA with the cache data CDATA of the cached column that was hit (S680). After performing the read operation, the memory controller 100 can set the access selection bit AS of the cached column that was hit to the high bit (S690).

[0068] The read or write operations according to embodiments of the present invention will be described in detail in the following examples.

[0069] Figures 7A to 7E are diagrams illustrating exemplary operation of a memory system according to an embodiment of the present invention. Figures 7A to 7E show the state of the cache column when write operations are performed sequentially.

[0070] Referring to FIG7A, based on the request REQ from host 10, memory controller 100 (not shown) can generate a write command CMD (hereinafter referred to as "WT"), address ADDR "0x10", and write data WDATA "0x1234" (①). If no cache column with a tag address TAG_A corresponding to address ADDR "0x10" is found (i.e., a cache hit) (②, "WRITE MISS"), memory controller 100 can control main memory device 210 to perform a write operation to write the write data WDATA "0x1234" to the region selected by address ADDR "0x10" (③). Thereafter, memory controller 100 can obtain an empty cache column from high-speed cache memory device 220 and add the new cache column to cache memory device 220 by storing the write data WDATA "0x1234" as cache data CDATA of the obtained cache column and setting the valid bit V to the high bit. The memory controller 100 can release the access selection bit AS of the added cache column to the low bit and initialize the column knock status value RH_S to "0" (④). On the other hand, when no empty cache column is found, the memory controller 100 can perform an eviction operation by applying an eviction algorithm to select one of the occupied cache columns according to the cache replacement policy.

[0071] Referring to Figure 7B, the memory controller 100 can generate a write command WT, address ADDR "0x10", and write data WDATA "0x2345" corresponding to the request REQ from the host 10 (①). Since a cache column hit is found based on address ADDR "0x10" (②, "WRITE HIT"), the memory controller 100 can check whether the access select bit AS of the cache column hit is set to high or released to low. If the access select bit AS is released to low and the column hit status value RH_S is "0", the memory controller 100 can control the main memory device 210 to perform a write operation to write the write data WDATA "0x2345" to the area selected by address ADDR "0x10" (③). After performing the write operation, the memory controller 100 can update the cache column hit by incrementing the column hit status value RH_S by "+1" (④).

[0072] Referring to Figure 7C, before the column knock status value RH_S reaches the threshold (e.g., "31"), the cached column hit can be updated by incrementing the column knock status value RH_S by "+1" whenever an access operation is performed on the column line corresponding to address ADDR "0x10" (④).

[0073] Referring to FIG7D, the memory controller 100 can generate a write command WT, address ADDR "0x10", and write data WDATA "0x5678" corresponding to the request REQ from the host 10 (①). Since the column knock status value RH_S of the cached column hit has reached the threshold "31", the memory controller 100 can read data from the column line corresponding to address ADDR "0x10" of the main memory device 210 and update the read data to the cache data CDATA of the cached column hit (③). In addition, the cache memory device 220 can perform a write operation to write the write data WDATA "0x5678" to the cached column hit (④). After performing the write operation, the memory controller 100 can update the cached column hit by setting the access selection bit AS to a high bit (⑤).

[0074] Referring to FIG7E, the memory controller 100 can generate a write command WT, address ADDR "0x10", and write data WDATA "0x6789" corresponding to the request REQ from the host 10 (①). Since the access select bit AS of the cache column hit is set to high bit (②), the memory controller 100 can control the cache memory device 220 to perform a write operation to write the write data WDATA "0x6789" to the cache column hit (③). That is, after the access select bit AS is set to high bit, whenever a read operation or write operation is performed on address ADDR "0x10", the read operation or write operation can be performed only on the cache column hit without accessing the main memory device 210. Therefore, data corruption and distortion of the main memory device 210 caused by column knock can be prevented.

[0075] Figures 8A to 8H are diagrams illustrating exemplary operation of a memory system according to an embodiment of the present invention. Figures 8A to 8H show the state of the cache column when read and write operations are performed sequentially.

[0076] Referring to Figure 8A, based on the request REQ from the host 10, the memory controller 100 can generate a read command CMD (hereinafter referred to as "RD"), address ADDR "0x10" (①). If no cache column with a tag address TAG_A corresponding to address ADDR "0x10" is found (i.e., a cache hit) (②, "READ MISS"), the memory controller 100 can control the main memory device to perform a read operation to read read data RDATA from the region selected by address ADDR "0x10" (③). Thereafter, the memory controller 100 can obtain an empty cache column from the cache memory device 220 and add the new cache column to the cache memory device 220 by storing the read data RDATA "0x1234" as the cache data CDATA of the obtained cache column and setting the valid bit V to the high bit. The memory controller 100 can release the access selection bit AS of the added cache column to the low bit and initialize the column knock status value RH_S to "0" (④). On the other hand, when no empty cache column is found, the memory controller 100 can perform an eviction operation by applying an eviction algorithm to select one of the occupied cache columns according to the cache replacement policy.

[0077] Referring to Figure 8B, the memory controller 100 can generate a read command RD and address ADDR "0x10" (①) corresponding to the request REQ of the host 10. Since a cached column hit is found based on the address ADDR "0x10" (②, "READ HIT"), the memory controller 100 can check the access select bit AS and the column hit status value RH_S. If the access select bit AS is released to a low bit and the column hit status value RH_S is "0", the data stored in the column line is the same as the cached data CDATA of the cached column hit. Therefore, the memory controller 100 can control the cache memory device 220 to perform a read operation to read the read data RDATA "0x1234" from the cached column hit (③). In this case, since the column line of the main memory device 210 is not accessed, the fields of the cached column hit, including the column hit status value RH_S, are not updated.

[0078] Referring to FIG8C, the memory controller 100 can generate a write command WT, address ADDR "0x10", and write data WDATA "0x2345" corresponding to the request REQ of the host 10 (①). Since a cache hit column is found (②, "WRITE HIT"), the memory controller 100 can check the access select bit AS and the column hit status value RH_S. When the access select bit AS is released to low bits and the column hit status value RH_S is "0", the memory controller 100 can control the main memory device 210 to perform a write operation to write the write data WDATA "0x2345" to the area selected by address ADDR "0x10" (③). After performing the write operation, the memory controller 100 can update the cache hit column by incrementing the column hit status value RH_S by "+1" (④).

[0079] Referring to FIG8D, the memory controller 100 can generate a read command RD and address ADDR "0x10" corresponding to the request REQ of the host 10 (①). Since a cache hit column is found (②, "READ HIT"), the memory controller 100 can check the access select bit AS and the column hit status value RH_S. When the access select bit (AS) is released to low bits and the column hit status value RH_S is "1", the memory controller 100 can control the main memory device 210 to perform a read operation to read the read data WDATA "0x2345" from the area selected by address ADDR "0x10" (③). After performing the read operation, the memory controller 100 can update the cache hit column by incrementing the column hit status value RH_S by "+1" (④).

[0080] Referring to Figure 8E, before the column knock status value RH_S reaches the threshold (e.g., "31"), the cached column hit can be updated by incrementing the column knock status value RH_S by "+1" whenever an access operation is performed on the column line corresponding to address ADDR "0x10" (④).

[0081] Referring to Figure 8F, the memory controller 100 can generate a read command RD and address ADDR "0x10" corresponding to the request REQ of the host 10 (①). Since the column knock status value RH_S of the cached column hit has reached the threshold "31", the memory controller 100 can control the main memory device 210 to perform a read operation to read the last stored read data RDATA "0x3456" from the column line corresponding to address ADDR "0x10" (③). In addition, the memory controller 100 can update the read data RDATA to the cache data CDATA of the cached column hit (④) and set the access select bit AS to the high bit (⑤).

[0082] Referring to Figures 8G and 8H, after the access select bit AS is set to the high bit, whenever a read or write operation is performed on address ADDR "0x10", the read or write operation can be performed only on the cache column hit without accessing the main memory device 210. Therefore, data corruption and distortion of the main memory device 210 caused by column knocks can be prevented.

[0083] Figure 9 is a block diagram illustrating a data storage device 1000 according to another embodiment of the present invention.

[0084] Referring to FIG9, the data storage device 1000 may include a host 1100 and a memory system 1200. The memory system 1200 may include a memory controller 1210, a first memory device 1220 and a second memory device 1230.

[0085] In some embodiments, the memory controller 1210 may communicate with the host 1100 via a compute link (CXL) interface or a dual in-line memory module (DIMM) interface. The memory controller 1210 may have a configuration substantially the same as that of the memory controller 100 of FIG2.

[0086] In Figure 9, the first memory device 1220 can be a first-level memory, and the second memory device 1230 can be a second-level memory. When the host 1100 requests access, the second-level memory can be a memory with a lower priority (i.e., a lower level) than the first-level memory. The host 1100 can first request the required data in the first-level memory, and if the data is not present in the first-level memory, the host 1100 can request the data in the second-level memory. If the data requested by the host 1100 is stored in either the first-level memory or the second-level memory, a cache hit can occur; if it is not stored in either the first-level memory or the second-level memory, a cache miss may occur.

[0087] In embodiments of the present invention, the first memory device 1220 may correspond to the main memory device 210 described in Figures 2 to 6, and the second memory device 1230 may correspond to the cache memory device 220 described in Figures 2 to 6. Therefore, according to embodiments of the present invention, in a memory system that communicates with the host via a Compute Xpress Link (CXL) interface, the existing second memory device can be used as a cache memory device, and limited memory resources can be used efficiently by managing the number of accesses to the column lines.

[0088] Figure 10 is a block diagram illustrating a data storage device 2000 according to another embodiment of the present invention. In Figure 10, a memory module is shown as an example of a memory system.

[0089] Referring to FIG10, the data storage device 2000 may include a host 2100, a first memory module 2200, and a second memory module 2300. The number of memory modules included in the data storage device 2000 is not limited to this embodiment.

[0090] The first memory module 2200 includes a memory controller 2210 and a memory device 2220, and can communicate with the host 2100 through a first interface. The second memory module 2300 may include a memory controller 2310 and a memory device 2320, and can communicate with the host 2100 through a second interface. The first interface and the second interface may be different from each other. For example, the first interface may include a dual in-line memory module (DIMM) interface, and the second interface may include a compute link (CXL) interface.

[0091] In Figure 10, the first memory module 2200 can be a first-level memory, and the second memory module 2300 can be a second-level memory. When the host 2100 requests access, the second-level memory can be a memory with a lower priority (i.e., a lower level) than the first-level memory. The host 2100 can first request the required data in the first-level memory, and if the data is not present in the first-level memory, request the data in the second-level memory. If the data requested by the host 2100 is stored in either the first-level or second-level memory, a cache hit can occur; if it is not stored in either the first-level or second-level memory, a cache miss may occur.

[0092] At least one of memory device 2220 and memory device 2320 may correspond to memory device 200 described in Figures 2 to 6 according to an embodiment of the present invention, and may similarly include a corresponding main memory device 210 and cache memory device 220.

[0093] Various embodiments of the invention have been described in the drawings and specification. While specific terminology is used herein, it is only for describing embodiments of the invention. Therefore, the invention is not limited to the embodiments described above, and many variations can be made within the spirit and scope of the invention. It will be apparent to those skilled in the art that various modifications can be made based on the scope of the invention in addition to the embodiments disclosed herein. These embodiments can be combined to form additional embodiments.

[0094] It should be noted that although the technical spirit of the present invention has been described in conjunction with embodiments thereof, this is for illustrative purposes only and should not be construed as limiting. Those skilled in the art will understand that various modifications can be made without departing from the technical spirit of the present invention and the appended claims.

[0095] For example, the logic gates and transistors provided as examples in the above embodiments can be implemented in different positions and types depending on the polarity of the input signal. Furthermore, these embodiments can be combined to form additional embodiments.

[0096] 1: Data storage device 10: Host 20: Memory System 100: Memory controller 110: Host Interface 120: Processor 130: Buffer memory 140: Access Manager 150: Memory Interface 170: Busbar 200:Memory device 210: Main memory device 212: Memory Cell Array 220: Cache memory device 1000: Data storage device 1100: Host 1200: Memory System 1210: Memory controller 1220: First Memory Device 1230: Second Memory Device 2000: Data storage device 2100: Host 2200: First Memory Module 2210: Memory controller 2220: Memory Device 2300: Second Memory Module 2310: Memory controller 2320: Memory Device A: Operation ADDR: address AS: Access Selection Bit B: Operation Cache HIT: Cache hit CDATA: Cache Data CL: Cache Column CL1~CLm: Cache columns CMD: Command DQ: Data HDATA: Host data RD: Read command RDATA: Read data READ: Read operation READ HIT: Read hit operation READ MISS: Read operation failed. REQ: Request RH_S: Column keystroke status value RL: Column line RL1~RLn: Column lines S410~S480: Steps S510~S590: Steps S610~S690: Steps TAG_A: Tag address V: Significant bits WDATA: Write data WRITE: Write operation WRITE HIT: Write hit operation WRITE MISS: Write miss operation WT: Write command

Claims

1. A memory system, comprising: Main memory device, including multiple column lines; A cache memory device includes a plurality of cache columns, column tap state values, and access selection bits. The plurality of cache columns are used to cache data stored in the column lines, each cache column including cached data. The column tap state values ​​are used to store the number of accesses for the corresponding column line, and the access selection bits are set according to the column tap state values. A memory controller, in response to a request from a host, controls the execution of an access operation on one of the main memory device and the cache memory device, the main memory device and the cache memory device being selected based on the access selection bits of the cache column hit by the cache.

2. The memory system as described in claim 1, wherein, When the access operation is performed on the column line corresponding to the request from the host, the memory controller increments the column knock status value of the cached column.

3. The memory system as described in claim 1, wherein, When the column knock state value of the cache column that is hit by the cache reaches a threshold, the memory controller sets the access selection bit of the cache column that is hit by the cache to a high bit.

4. The memory system as described in claim 1, wherein, The memory controller: When the access select bit of the cache column hit is a high bit, it controls the execution of the access operation on the cache column hit; and when the access select bit of the cache column hit is a low bit, it controls the execution of the access operation on the cache column hit or the column line corresponding to the request.

5. The memory system as described in claim 4, wherein, The access operation includes a write operation, and when the access select bit of the cache column hit is the low bit, the memory controller: before the column knock state value of the cache column hit reaches a threshold, controls the write operation to be performed on the column line and increments the column knock state value of the cache column hit; and when the column knock state value of the cache column hit reaches the threshold, controls the write operation to be performed on the cache column hit and sets the access select bit of the cache column hit to the high bit.

6. The memory system as described in claim 5, wherein, When the column knock state value of the cached column hit by the cache reaches the threshold, the memory controller reads data from the column line and updates the read data to the cached data of the cached column hit by the cache, and controls the write operation to be performed on the cached column hit by the cache.

7. The memory system as described in claim 4, wherein, The access operation includes a read operation, and when the access selection bit of the cached column hit by the cache is the least significant bit, the memory controller: controls the read operation to be performed on the column line, and controls the read operation to be performed on the cached column hit only when the column knock state value of the cached column hit by the cache is initialized.

8. The memory system as described in claim 1, wherein, The memory controller controls the execution of the access operation on the column line corresponding to the request, and adds the cache column corresponding to the column line to the cache memory device when a cache miss occurs.

9. The memory system as described in claim 8, wherein, When the cache of the cache memory device is full, the memory controller performs an eviction operation on the cache column selected according to the cache replacement strategy among the plurality of cache columns.

10. The memory system as described in claim 9, wherein, During the eviction operation, when the access select bit of the selected cache column is set to the high bit, the memory controller writes the cache data of the selected cache column back to the corresponding column line.

11. The memory system as described in claim 1, wherein, The memory controller communicates with the host via a high-speed compute link (CXL) interface or a dual in-line memory module (DIMM) interface.

12. The memory system as described in claim 1, wherein, Each cache column further includes a tag address, the tag address including address information specifying the position of the corresponding column line, and wherein the memory controller searches for the cache column that has been hit based on the tag address included in each of the plurality of cache columns.

13. A method of operating a memory system, comprising: When the host requests an access operation to a column line of the main memory device, it searches for the cache column that is matched from multiple cache columns of the cache memory device; The access operation is performed on one of the main memory device and the cache memory according to the access selection bit of the cache column hit; and when the access operation is performed on the column line, the column knock state value of the cache column hit is increased, and the access selection bit is set when the column knock state value reaches a threshold.

14. The operation method as described in claim 13, wherein performing the access operation includes: When the access selection bit is a high bit, the access operation is performed on the cache column that is hit in the cache. Furthermore, when the access selection bit is a low bit, the access operation is performed on the cache column or the column line that was hit in the cache.

15. The operating method as described in claim 14, wherein, The access operation includes a write operation, and when the access select bit of the cache column hit by the cache is the low bit, the execution of the access operation includes: performing the write operation on the column line and incrementing the column knock state value before the column knock state value reaches a threshold, and performing the write operation on the cache column hit by the cache when the column knock state value reaches the threshold, and setting the access select bit to the high bit.

16. The operating method as described in claim 15, wherein, When the column tap state value reaches the threshold, after reading data from the column line and updating the read data to the cache data of the cached column hit by the cache, the write operation is performed on the cached column hit by the cache.

17. The operating method as described in claim 14, wherein, The access operation includes a read operation, and when the access selection bit of the cached column hit by the cache is the low bit, the execution of the access operation includes: performing the read operation on the column line, while controlling the execution of the read operation on the cached column hit only when the column knock state value is initialized.

18. The operating method as described in claim 13, wherein, The search for a cached column that has been hit further includes: when a cache miss occurs, performing the access operation on the column line and adding the cached column corresponding to the column line to the cache memory.

19. The operating method as described in claim 18, wherein, Adding a cache column includes: when the cache of the cache memory device is full, performing an eviction operation on the cache column selected from the plurality of cache columns according to the cache replacement strategy.

20. The operating method as described in claim 19, further comprising: During the eviction operation, when the access select bit of the selected cache column is set to the high bit, the cache data of the selected cache column is written back to the corresponding column line.

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