Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for fabricating a semiconductor device, which mainly involves first forming a spin orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first masking layer on the MTJ, forming a first intermetallic dielectric layer on the first masking layer, forming a second masking layer on the first masking layer and the first intermetallic dielectric layer, forming a second intermetallic dielectric layer on the first masking layer, the first intermetallic dielectric layer and the second masking layer, and then planarizing the first masking layer, the first intermetallic dielectric layer, the second masking layer and the second intermetallic dielectric layer.

Description

Semiconductor Device and Method for Fabricating the Same The present invention discloses a semiconductor device and a method for fabricating the same, and particularly relates to a magnetoresistive random access memory (MRAM) and a method for fabricating the same. It is known that the magnetoresistance (MR) effect is the effect that the resistance of a material changes with the change of an externally applied magnetic field. The definition of its physical quantity is the resistance difference between the presence and absence of a magnetic field divided by the original resistance, which is used to represent the resistance change rate. Currently, the MR effect has been successfully applied in hard disk production and has important commercial application value. In addition, by utilizing the characteristic that giant magnetoresistive materials have different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be fabricated, and its advantage is that the stored data can continue to be retained without power supply. The above MR effect is also applied in the field of magnetic field sensors. For example, the electronic compass component in a mobile phone that is paired with a global positioning system (GPS) is used to provide information such as the moving direction of the user. Currently, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, and so on. However, the disadvantages of the above prior arts usually include: relatively large chip area occupation, relatively expensive manufacturing process, relatively high power consumption, insufficient sensitivity, and susceptibility to temperature changes, etc., and thus it is necessary to further improve. An embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a spin orbit torque (SOT) layer is formed on a substrate, then a magnetic tunneling junction (MTJ) is formed on the SOT layer, a first mask layer is formed on the MTJ, a first intermetal dielectric layer is formed on the first mask layer, a second mask layer is formed on the first mask layer and the first intermetal dielectric layer, a second intermetal dielectric layer is formed on the first mask layer, the first intermetal dielectric layer, and the second mask layer, and then the first mask layer, the first intermetal dielectric layer, the second mask layer, and the second intermetal dielectric layer are planarized. Another embodiment of the present invention discloses a semiconductor device, which mainly includes a spin orbit torque (SOT) layer disposed on a substrate, a magnetic tunneling junction (MTJ) disposed on the SOT layer, a first capping layer disposed on the MTJ, a first metal interlayer dielectric layer disposed beside the first capping layer, and a second capping layer disposed beside the first capping layer and the first metal interlayer dielectric layer. Please refer to FIGS. 1 to 8. FIGS. 1 to 8 are schematic diagrams showing a method of fabricating a semiconductor device, or more specifically, a MRAM cell, in a certain direction, for example, the Y direction, according to an embodiment of the present invention. As shown in FIG. 1, first, a substrate 12 is provided, for example, a substrate 12 made of a semiconductor material, where the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composites, silicon carbide, gallium arsenide, etc., and a MRAM region 14 and a logic region 40 are preferably defined on the substrate 12. The substrate 12 may include active devices, passive devices, conductive layers, such as metal-oxide semiconductor (MOS) transistors, and dielectric layers, such as an interlayer dielectric (ILD) 16, covering thereon. More specifically, the substrate 12 may include MOS transistor elements such as planar or non-planar (such as fin-shaped transistors), where the MOS transistor may include a gate structure (such as a metal gate) and source / drain regions, sidewalls, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 16 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 16 may have a plurality of contact plugs electrically connecting the gates and / or source / drain regions of the MOS transistors. Since the related processes of planar or non-planar transistors and the interlayer dielectric layer are well-known techniques in the art, they will not be elaborated here. Then, metal interconnect structures 18 and 20 are sequentially formed on the interlayer dielectric layer 16 in the MRAM region 14 to electrically connect the aforementioned contact plugs. The metal interconnect structure 18 includes a metal interlayer dielectric layer 22 and metal interconnects 24 embedded in the metal interlayer dielectric layer 22. The metal interconnect structure 20 includes a stop layer 26, a metal interlayer dielectric layer 28, and a plurality of metal interconnects 30 and 32 embedded in the stop layer 26 and the metal interlayer dielectric layer 28. It should be noted that, compared with the MRAM region 14 where the metal interconnects 24, 30, and 32 are simultaneously provided, only the metal interconnect 24 is disposed in the metal interlayer dielectric layer 22 in the logic region 40 at this stage, and there are no metal interconnects in the metal interlayer dielectric layer 28. In this embodiment, each metal interconnect 24 in the metal interconnect structure 18 preferably includes a trench conductor, and the metal interconnects 30 and 32 in the metal interconnect structure 20 include via conductors. Additionally, each of the metal interconnects 24, 30, and 32 in the metal interconnect structures 18 and 20 can be embedded in the intermetal dielectric layers 22, 28, and / or the stop layer 26 according to a single damascene process or a dual damascene process and electrically connected to each other. For example, each of the metal interconnects 24, 30, and 32 can more particularly include a barrier layer 34 and a metal layer 36. The barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since the single damascene or dual damascene process is a well-known technique in the art, it will not be elaborated herein. In addition, in this example, the metal layer 36 in the metal interconnect 24 preferably includes copper, the metal layer 36 in the metal interconnects 30 and 32 preferably includes tungsten, the intermetal dielectric layers 22 and 28 preferably include silicon oxide or an ultra-low dielectric constant dielectric layer, and the stop layer 26 includes a nitrogen doped carbide layer (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto. Next, a selective lower electrode 42, a spin orbit torque (SOT) layer 44, an MTJ stack structure 66, a capping layer 60, and a patterned hard mask 62 are formed on the metal interconnect structure 20. In this embodiment, the MTJ stack structure 66 can be formed by sequentially forming a free layer 46, a barrier layer 48, a reference layer (not shown), a spacer (not shown), and a pinned layer 50 on the SOT layer 44. The free layer 46 can be composed of a ferromagnetic material, such as iron, cobalt, nickel, or an alloy thereof such as cobalt-iron-boron (CoFeB), but is not limited thereto, and the magnetization direction of the free layer 46 can be "freely" changed by an external magnetic field. The barrier layer 48 can be composed of an insulating material containing an oxide, such as aluminum oxide (AlO x ) or magnesium oxide (MgO), but is not limited thereto. The reference layer is preferably disposed between the barrier layer 48 and the spacer layer, and may include those made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited thereto. The spacer layer includes a non-magnetic layer made of a non-magnetic material, such as a material selected from the group consisting of ruthenium, iridium, and rhodium. The fixed layer 50 may include ferromagnetic materials such as but not limited to cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), cobalt (Co), etc. In addition, the fixed layer 50 may also be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., for fixing or restricting the magnetic moment direction of the adjacent layer. In detail, the fixed layer 50 may include a lower synthetic antiferromagnetic (SAF) layer, a coupling layer, and an upper synthetic antiferromagnetic layer, wherein the lower synthetic antiferromagnetic layer and the upper synthetic antiferromagnetic layer may include the same or different materials and both may include ferromagnetic materials such as cobalt (Co), nickel (Ni), platinum (Pt), palladium (Pd), or a combination thereof, and the coupling layer preferably includes materials such as ruthenium (Ru), tantalum (Ta), gadolinium (Gd), platinum (Pt), hafnium (Hf), or a combination thereof that can provide mechanical and / or lattice structure support for the lower synthetic antiferromagnetic layer and the upper synthetic antiferromagnetic layer. In addition, in this embodiment, the selective lower electrode 42 preferably includes a conductive material, such as but not limited to tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al). The SOT layer 44 preferably serves as a channel of a spin orbit torque (SOT) MRAM, so its material may include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (Bi x Se 1-x ) or a combination thereof. The capping layer 60 preferably includes a metal such as ruthenium, and the hard mask 62 may include a conductive or dielectric material such as but not limited to tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or a combination thereof. It should be noted that, compared with the conventional SOT layer 44 which does not contain atoms other than metals, in this embodiment, when forming the SOT layer 44, nitrogen atoms or oxygen atoms can be implanted into the SOT layer 44 by ion implantation, so that the SOT layer 44 contains nitrogen atoms or oxygen atoms. According to an embodiment of the present invention, the formed SOT layer 44 can be composed of metal nitride or metal oxide. For example, if the original SOT layer 44 is composed of tungsten (W), the formed SOT layer 44 after implanting nitrogen atoms or oxygen atoms can contain tungsten nitride (WN) or tungsten oxide (WO). Additionally, if the original SOT layer 44 is composed of platinum (Pt), the formed SOT layer 44 after implanting nitrogen atoms or oxygen atoms can contain platinum nitride (PtN) or platinum oxide (PtO). These ways of forming the SOT layer 44 are all within the scope covered by the present invention. According to a preferred embodiment of the present invention, implanting nitrogen atoms or oxygen atoms into the SOT layer 44 can make the etching process stop more precisely at the SOT layer 44 when patterning the MTJ stack structure 66 to form the MTJ subsequently, without excessive consumption of the SOT layer 44. In addition, in this embodiment, the patterned hard mask 62 can be formed by forming a patterned dielectric layer 64 composed of silicon oxide on the unpatterned hard mask 62, and then using a patterned mask (not shown), such as a patterned photoresist as a mask, to remove part of the dielectric layer 64 and the hard mask 62 by, for example, reactive ion etching (RIE) to form the patterned dielectric layer 64 and the patterned hard mask 62, and then selectively removing the dielectric layer 64 composed of silicon oxide. As shown in Figure 2, then the patterned dielectric layer 64 or the patterned hard mask 62 can be used as a mask to remove part of the capping layer 60, part of the MTJ stack structure 66, and even part of the SOT layer 44 to form the MTJ 70, and then a first capping layer 72 is formed on the MTJ 70 in sequence and an intermetal dielectric layer 74 is formed on the first capping layer 72. In this embodiment, the first capping layer 72 preferably contains silicon nitride and the intermetal dielectric layer 74 contains silicon oxide. It should be noted that at this stage, when patterning the MTJ stack structure 66 with the patterned hard mask 62 to form the MTJ 70, part of the SOT layer 44 can be selectively removed, so that the top surfaces of the remaining SOT layers 44 on both sides of the MTJ 70 are slightly lower than the top surface of the SOT layer 44 directly below the MTJ 70. According to another embodiment of the present invention, if no SOT layer 44 is removed when forming the MTJ 70, then the top surfaces of the remaining SOT layers 44 on both sides of the MTJ 70 are preferably flush with the top surface of the SOT layer 44 directly below the MTJ 70. In addition, the first capping layer 72 and the intermetal dielectric layer 74 formed at this stage are preferably provided on both the MRAM region 14 and the logic region 40 at the same time. As shown in FIG. 3, a bottom anti-reflective coating (BARC) 76 can be first formed on the inter-metal dielectric layer 74, and then a patterning mask 78, such as a patterned photoresist, is used as a mask to perform an etching process. For example, another ion beam etching process is used to remove part of the bottom anti-reflective coating 76 and part of the inter-metal dielectric layer 74 in the MRAM region 14, as well as all of the bottom anti-reflective coating 76 and the inter-metal dielectric layer 74 in the logic region 40, and expose the underlying first capping layer 72, so that the remaining inter-metal dielectric layer 74 is only provided in the MRAM region 14, but the underlying first capping layer 72 is still provided in both the MRAM region 14 and the logic region 40. Subsequently, as shown in FIG. 4, the bottom anti-reflective coating 76 can be removed first to expose the inter-metal dielectric layer 74 in the MRAM region 14, and an etching process is performed without forming an additional patterning mask. For example, a different ion beam etching (IBE) process from the foregoing is used to remove part of the inter-metal dielectric layer 74, part of the first capping layer 72, part of the SOT layer 44, part of the lower electrode 42, and even part of the inter-metal dielectric layer 28 in the MRAM region 14, as well as all of the first capping layer 72, all of the SOT layer 44, all of the lower electrode 42, and part of the inter-metal dielectric layer 28 in the logic region 40, so that the left and right sidewalls of the first capping layer 72, the SOT layer 44, the lower electrode 42, and even part of the inter-metal dielectric layer 28 in the MRAM region 14 are slightly retracted, and the sidewalls of the metal interconnect 32 can be optionally trimmed approximately flush, while the top surface of the remaining inter-metal dielectric layer 28 in the logic region 40 can be optionally slightly lower than the top surface of the inter-metal dielectric layer 28 in the MRAM region 14. It should be noted that although the IBE process performed at this stage removes part of the underlying inter-metal dielectric layer 28 when patterning the first capping layer 72, the SOT layer 44, and the lower electrode 42, it is not limited thereto. According to other embodiments of the present invention, no inter-metal dielectric layer 28 may be removed when patterning the first capping layer 72, the SOT layer 44, and the lower electrode 42 using the IBE process. In other words, after patterning the first capping layer 72, the SOT layer 44, and the lower electrode 42, the left and right sidewalls of the first capping layer 72, the SOT layer 44, and the lower electrode 42 can be optionally trimmed flush with the sidewalls of the underlying metal interconnect 32, and at the same time, the top surfaces of the inter-metal dielectric layer 28 on both sides of the first capping layer 72 or the SOT layer 44 can still be trimmed flush with the top surface of the inter-metal dielectric layer 28 directly below the MTJ 70. This variant is also within the scope of the present invention. As shown in FIG. 5, a second masking layer 80 is then formed on the first masking layer 72, the inter-metal dielectric layer 74, and the inter-metal dielectric layer 28, wherein the second masking layer 80 preferably covers the top surface of the first masking layer 72, the top surface of the inter-metal dielectric layer 74, the sidewalls of the inter-metal dielectric layer 74, the sidewalls of the first masking layer 72, the sidewalls of the SOT layer 44, the sidewalls of the lower electrode 42, and the top surface of the inter-metal dielectric layer 28. In this embodiment, the first masking layer 72 and the second masking layer 80 preferably comprise the same material, for example, both preferably comprise silicon nitride. Then, as shown in FIG. 6, an etching process can be performed without forming a patterned mask to remove a portion of the second masking layer 80 in the MRAM region 14 and all of the second masking layer 80 in the logic region 40 and expose the top surface of the inter-metal dielectric layer 28, wherein the top surface of the second masking layer 80 disposed on the sidewall of the inter-metal dielectric layer 74 is preferably flush with the top surfaces of the inter-metal dielectric layer 74 and the first masking layer 72. Subsequently, as shown in FIG. 7, another inter-metal dielectric layer 84 is first formed in the MRAM region 14 and the logic region 40. A planarization process, such as a chemical mechanical polishing (CMP) process, is used to remove a portion of the inter-metal dielectric layer 84, a portion of the second masking layer 80, a portion of the inter-metal dielectric layer 74, and a portion of the first masking layer 72 so that the remaining top surface of the inter-metal dielectric layer 84 is flush with the top surface of the hard mask 62. Then, a pattern transfer process is performed. For example, a patterned mask can be used to remove a portion of the inter-metal dielectric layer 84, a portion of the inter-metal dielectric layer 28, and a portion of the stop layer 26 in the logic region 40 to form contact holes (not shown) and expose the underlying metal interconnect 24. Then, a desired conductive material is filled into the contact holes, such as a barrier layer comprising titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-impedance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., or a combination thereof. Then, a planarization process is performed, such as a chemical mechanical polishing process, to remove a portion of the conductive material to form a metal interconnect 86 in the contact hole electrically connecting the metal interconnect 24. Thereafter, a stop layer 88 is formed on the hard mask 62 and the metal interconnect 86. In this embodiment, the inter-metal dielectric layer 84 and the inter-metal dielectric layer 74 can comprise the same or different materials, for example, both comprise silicon oxide, and the stop layer 88 can comprise silicon dioxide, silicon nitride, or silicon carbon nitride (SiCN) and preferably comprises silicon carbon nitride, but is not limited thereto. Thereafter, as shown in FIG. 8, first, an inter-metal dielectric layer 90 is formed on the stop layer 88 of the MRAM region 14 and the logic region 40, and then a patterning process is performed. For example, a patterning mask (not shown) can be used to remove a part of the inter-metal dielectric layer 90 and a part of the stop layer 88 to form contact holes (not shown) and expose the underlying hard mask 62 and the metal interconnect 86. Then, a required conductive material is filled in the contact holes, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. and a low-impedance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. or a combination thereof. Then, a planarization process is performed. For example, a chemical mechanical polishing process is used to remove a part of the metal material to form a contact plug or a metal interconnect 92 in the contact hole to electrically connect the hard mask 62 and the metal interconnect 86. Thereafter, a stop layer 94 is selectively formed on the metal interconnect 92. In this embodiment, the inter-metal dielectric layer 90 preferably includes an ultra-low dielectric constant dielectric layer, such as a porous dielectric material including but not limited to silicon oxycarbide (SiOC) or silicon oxycarbide hydrogen (SiOCH). Please refer to FIG. 9 again. FIG. 9 is a schematic structural diagram of preparing an MRAM cell according to another angle, i.e., the X direction, in an embodiment of the present invention. As shown in FIG. 9, the MRAM cell mainly includes a SOT layer 44 disposed on a substrate 12, a MTJ 70 disposed on the SOT layer 44, a first capping layer 72 disposed beside the MTJ 70, an inter-metal dielectric layer 74 disposed beside the first capping layer 72, a second capping layer 80 disposed beside the first capping layer 72 and the inter-metal dielectric layer 74, and an inter-metal dielectric layer 82 disposed beside the second capping layer 80. Compared with the embodiment of FIG. 8, in which the bottom surface of the lower electrode 42 is directly connected to two metal interconnects 32, the bottom surface of the lower electrode 42 in this embodiment preferably does not contact any metal interconnects but only contacts the inter-metal dielectric layer 28. Looking in detail, the top surface of the second capping layer 80 preferably cuts the top surfaces of the inter-metal dielectric layer 74, the first capping layer 72, and the hard mask 62. The second capping layer 80 is disposed on the sidewalls of the inter-metal dielectric layer 74, the first capping layer 72, the SOT layer 44, the lower electrode 42, and the inter-metal dielectric layer 28. The bottom surface of the second capping layer 80 can be slightly lower than the bottom surface of the lower electrode 42 as in this embodiment or cut the bottom surface of the lower electrode 42 in other embodiments. In addition, the first capping layer 72 and the second capping layer 80 preferably include the same material, such as both being composed of silicon nitride. Please continue to refer to FIGS. 10 to 11. FIG. 10 is a top view of the MRAM cell and peripheral components in FIG. 8, and FIG. 11 is a top view of the MRAM cell and peripheral components in FIG. 9. As shown in FIGS. 10 and 11, the MRAM cell mainly includes at least one SOT layer 44 disposed on the substrate 12, a hard mask 62 or an MTJ 70 disposed on the SOT layer 44, a first cover layer 72 surrounding the MTJ 70, a metal interlayer dielectric layer 74 surrounding the first cover layer 62, a second cover layer 80 surrounding the metal interlayer dielectric layer 74, and another metal interlayer dielectric layer 84 surrounding the second cover layer 80. In the embodiments of FIGS. 10 and 11, the MTJ 70 includes a circular or more specifically an elliptical shape from a top view angle. The first cover layer 72 includes a first annular shape surrounding the MTJ 70 from a top view angle. The metal interlayer dielectric layer 74 includes a second annular shape surrounding the first cover layer 72 from a top view angle. The second cover layer 80 includes a third annular shape surrounding the metal interlayer dielectric layer 74 from a top view angle. And the metal interlayer dielectric layer 84 surrounds multiple MTJ 70s or the second cover layer 80 around the MTJ 70s at the same time. From a top view angle, the first cover layer 72 and the second cover layer 80 preferably include approximately the same width or thickness. The widths of the first cover layer 72 and the second cover layer 80 are respectively smaller than the width of the metal interlayer dielectric layer 74, and the width of the metal interlayer dielectric layer 74 is approximately equal to more than twice, such as three times, four times or even five times the individual width of the first cover layer 72 or the second cover layer 80. It should be noted that the SOT layer 44 in FIG. 10 is preferably represented by a dashed line from a top view angle, where the SOT layer 44 presents an approximately elliptical shape surrounding the metal interlayer dielectric layer 74 which also presents an elliptical shape. Different from the metal interlayer dielectric layer 74 where the diameter extending along the X direction is the major axis and the diameter extending along the Y direction is the minor axis, for the SOT layer 44X, the diameter extending along the X direction is the minor axis and the diameter extending along the Y direction is the major axis, where the minor axis of the SOT layer 44 extending along the X direction is approximately equal to the major axis of the metal interlayer dielectric layer 74 extending along the X direction, but the major axis of the SOT layer 44 extending along the Y direction is greater than the minor axis of the metal interlayer dielectric layer 74 extending along the Y direction by about 1.5 to 3 times. Different from the SOT layer 44 in FIG. 10 having major and minor axes in different directions from the metal interlayer dielectric layer 74 from a top view angle, the SOT layer 44 in FIG. 11 preferably has the same direction and the same distance of major and minor axes as the metal interlayer dielectric layer 74 from a top view angle. In other words, the range covered by the SOT layer 44 from a top view angle approximately overlaps the metal interlayer dielectric layer 74. The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention. 12: Substrate 14: MRAM Region 40: Logic Region 16: Interlayer Dielectric Layer 18: Metal Interconnection Structure 20: Metal Interconnection Structure 22: Intermetal Dielectric Layer 24: Metal Interconnection 26: Stop Layer 28: Intermetal Dielectric Layer 30: Metal Interconnection 32: Metal Interconnection 34: Barrier Layer 36: Metal Layer 40: Logic Region 42: Bottom Electrode 44: SOT Layer 46: Free Layer 48: Barrier Layer 50: Fixed Layer 60: Masking Layer 62: Hard Mask 64: Dielectric Layer 66: MTJ Stack Structure 70: MTJ 72: First Masking Layer 74: Intermetal Dielectric Layer 76: Bottom Anti-Reflection Layer 78: Patterned Mask 80: Second Masking Layer 84: Intermetal Dielectric Layer 86: Metal Interconnection 88: Stop Layer 90: Intermetal Dielectric Layer 92: Metal Interconnection 94: Stop Layer Figures 1 to 8 are schematic diagrams of the method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 9 is a schematic diagram of the structure of the prepared MRAM cell according to an embodiment of the present invention. Figure 10 is a top view of the MRAM cell and peripheral components in Figure 8. Figure 11 is a top view of the MRAM cell and peripheral components in Figure 9. 12: Substrate 14: MRAM Region 40: Logic Region 16: Interlayer Dielectric Layer 18: Metal Interconnection Structure 20: Metal Interconnection Structure 22: Intermetal Dielectric Layer 24: Metal Interconnection 26: Stop Layer 28: Intermetal Dielectric Layer 30: Metal Interconnection 32: Metal Interconnection 34: Barrier Layer 36: Metal Layer 40: Logic Region 42: Bottom Electrode 44: SOT Layer 46: Free Layer 48: Barrier Layer 50: Fixed Layer 60: Masking Layer 62: Hard Mask 70: MTJ 72: First Masking Layer 74: Intermetal Dielectric Layer 80: Second Masking Layer 84: Intermetal Dielectric Layer 86: Metal Interconnection 88: Stop layer 90: Inter-metal dielectric layer 92: Metal interconnect 94: Stop layer

Claims

1. A method for fabricating a semiconductor device, characterized in that it comprises: forming a spin orbit torque (SOT) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the SOT layer; forming a first masking layer on the MTJ; forming a first intermetallic dielectric layer on the first masking layer; forming a second masking layer on the first masking layer and the first intermetallic dielectric layer; forming a second intermetallic dielectric layer on the first masking layer, the first intermetallic dielectric layer and the second masking layer; and planarizing the first masking layer, the first intermetallic dielectric layer, the second masking layer and the second intermetallic dielectric layer.

2. The method as described in claim 1 further comprises: performing a first etching process to pattern the first intermetallic dielectric layer; and performing a second etching process to pattern the first masking layer and the first intermetallic dielectric layer.

3. The method as described in claim 2 further includes patterning the first intermetallic dielectric layer to expose the top surface of the first masking layer.

4. The method as described in claim 2 further includes performing the second etching process to align the top surface of the first masking layer with the top surface of the first intermetallic dielectric layer.

5. The method as described in claim 1 further includes forming the second covering layer on the sidewall of the SOT layer.

6. The method as described in claim 1, further comprising forming the second covering layer on the sidewall of the first covering layer.

7. The method as described in claim 1 further includes forming the second covering layer on the sidewall of the first intermetallic dielectric layer.

8. The method as described in claim 1, wherein the first covering layer and the second covering layer comprise the same material.

9. A semiconductor device, characterized in that it comprises: a spin orbit torque (SOT) layer disposed on a substrate; a magnetic tunneling junction (MTJ) disposed on the SOT layer; a first masking layer disposed next to the MTJ; a first intermetallic dielectric layer disposed next to the first masking layer; and a second masking layer disposed next to the first masking layer and the first intermetallic dielectric layer, wherein the top surface of the first masking layer is flush with the top surface of the second masking layer.

10. The semiconductor device as described in claim 9 further includes a second intermetallic dielectric layer disposed next to the second cover layer.

11. The semiconductor device as described in claim 9, wherein the second shielding layer is disposed on the sidewall of the first shielding layer.

12. The semiconductor device as described in claim 9, wherein the first cover layer and the second cover layer comprise the same material.

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