Semiconductor structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor structure comprising a substrate, a dielectric layer on the substrate, a plurality of gate structures located within the dielectric layer on the substrate, a plurality of first metal layers located on a portion of the gate structures and electrically connected to the corresponding gate structures, and at least one second metal layer, the second metal layer being connected across at least two of the gate structures, wherein a depth of the first metal layer is greater than a depth of the second metal layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for improving the quality of a metal layer (metal layer zero, M0) for electrically connecting a contact structure and a gate structure, and related structures thereof. Prior Art

[0002] As integrated circuit (IC) density continues to increase and feature sizes continue to decrease, the interconnect line widths and geometry sizes of semiconductor devices are also shrinking. Generally speaking, individual semiconductor devices in an IC are electrically connected via contact plugs and interconnect structures. Therefore, the plug structure and its manufacturing process are becoming increasingly important in next-generation semiconductor manufacturing processes.

[0003] Limited by the critical dimension (CD) of current semiconductor devices, complex or high-density patterns are difficult to achieve in a single lithography step. To overcome these process barriers, the industry is increasingly adopting a double patterning technique (develop-etch-develop-etch, or 2P2E) to create the desired device patterns.

[0004] However, conventional double patterning technology still has some shortcomings in use. For example, for some special patterns (such as relatively long and narrow patterns), the formed pattern is prone to cracking. Therefore, other methods are still needed to improve the double patterning technology. Summary of the Invention

[0005] The present invention provides a semiconductor structure comprising a substrate, a dielectric layer located on the substrate, a plurality of gate structures located within the dielectric layer on the substrate, a plurality of first metal layers located on a portion of the gate structures, and the first metal layers being electrically connected to corresponding gate structures, and at least one second metal layer, the second metal layer being connected across at least two of the gate structures, wherein a depth of the first metal layer is greater than a depth of the second metal layer.

[0006] The present invention further provides a semiconductor structure and a method for manufacturing the semiconductor structure, comprising providing a substrate, forming a dielectric layer on the substrate, forming a plurality of gate structures within the dielectric layer on the substrate, forming a plurality of first metal layers on a portion of the gate structures, wherein the first metal layers are electrically connected to corresponding gate structures, and forming at least one second metal layer, wherein the second metal layer bridges at least two of the gate structures, wherein a depth of the first metal layer is greater than a depth of the second metal layer.

[0007] The present invention provides a semiconductor structure and a method for fabricating the same. Specifically, for metal layer patterns of specific dimensions (particularly long strips of metal layer patterns spanning two gate structures), such patterns are split into two separate lithography steps. The pattern splitting is based not only on pattern density but also on the pattern's aspect ratio. In other words, patterns with particularly high aspect ratios are split into the second lithography step. This improves the quality of the resulting long strip contact structures and reduces the likelihood of breakage. Furthermore, after the two lithography steps, the contact structures formed by the first lithography step are deeper than those formed by the second lithography step. Simple diagram description

[0008] FIG. 1 is a top view schematically showing a semiconductor structure according to the present invention. FIG2 is a schematic cross-sectional view taken along the section lines AA′ and BB′ of FIG1 . FIG3 to FIG7 are cross-sectional structural diagrams respectively illustrating a semiconductor manufacturing method of the present invention continued with the structure of FIG2. Implementation Method

[0009] In order to enable those skilled in the art to further understand the present invention, the following lists preferred embodiments of the present invention and describes in detail the components and intended effects of the present invention in conjunction with the accompanying drawings.

[0010] For ease of explanation, the various figures of the present invention are merely illustrative to facilitate understanding of the present invention. The detailed proportions may be adjusted based on design requirements. Those skilled in the art will readily understand that the upper and lower relationships between components depicted in the figures refer to the relative positions of the objects. Therefore, the figures can be reversed to present the same components, and this is fully within the scope of this specification. This is further clarified.

[0011] Please refer to FIG. 1 and FIG. 2 , FIG. 1 is a top view schematically illustrating the semiconductor structure of the present invention, and FIG. 2 is a cross-sectional schematic diagram along section lines AA′ and BB′ of FIG. 1 .

[0012] First, a substrate 100 is provided. A first dielectric layer 101 and a second dielectric layer 102 are formed on the substrate 100. Multiple gate structures G are formed in the first dielectric layer 101, which are defined herein as gate structure G1, gate structure G2, gate structure G3, and gate structure G4. The substrate 100 can be a substrate made of a semiconductor material, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium semiconductor substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, or a substrate made of a non-semiconductor material, such as a glass substrate. The first dielectric layer 101 can be made of, for example, silicon nitride or silicon oxide, and the second dielectric layer 102 can be made of, for example, tetraethoxysilane (TEOS), but the present invention is not limited thereto. Furthermore, at least one shallow trench isolation (STI) may be pre-formed on the substrate 100 to define each active region. Furthermore, the present invention may further include multiple fin structures (not shown) located on the substrate 100, which also falls within the scope of the present invention.

[0013] For example, a typical integrated circuit (e.g., a semiconductor device) includes multiple active regions and multiple inactive regions. The active regions may contain components such as fin transistors (e.g., n-type fin transistors or p-type fin transistors). Each active region may contain different pattern densities, different fin transistor components, or contain fin transistors with different conductivity types.

[0014] Each gate structure G1, G2, G3, and G4 includes a gate dielectric layer 104, a high-k dielectric layer 106, a work function metal layer 108, and a gate conductive layer 110. The gate dielectric layer 104 may be made of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. The high-k dielectric layer 106 includes a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O5), etc. 3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST), or a combination thereof.

[0015] The work function metal layer 108 may include a p-type work function metal layer or an n-type work function metal layer (depending on whether a p-type transistor or an n-type transistor is to be formed). The p-type work function metal layer may include, but is not limited to, titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), or aluminum titanium nitride (TiAlN). Alternatively, the n-type work function metal layer may include, but is not limited to, a titanium aluminide (TiAl) layer, a zirconium aluminide (ZrAl) layer, a tungsten aluminide (WAl) layer, a tantalum aluminide (TaAl) layer, or a hafnium aluminide (HfAl) layer.

[0016] The material of the gate conductive layer 110 may include undoped polysilicon, heavily doped polysilicon, or a single or multiple metal layers, such as a work function metal layer, a barrier layer, and a low resistance metal layer, but the present invention is not limited thereto. The materials included in the above-mentioned gate structure can be adjusted according to actual needs.

[0017] Furthermore, the present invention further includes a plurality of sidewall sub-layers (SP) located on either side of each gate structure G1, G2, G3, and G4. The sidewall sub-layers (SP) are made of, for example, silicon nitride or silicon oxide. Subsequently, a contact etch stop layer (CESL) is formed on the substrate 100, covering each gate structure G1, G2, G3, and G4 and each sidewall sub-layer (SP). The CESL can be a single layer or a composite layer to apply the desired compressive or tensile stress to the gate structure G, but is not limited thereto. In other embodiments, the step of forming the CESL can be omitted. Furthermore, source / drain regions (S / D) are formed in the substrate 100 on either side of the sidewall sub-layers (SP). In some embodiments, the source / drain regions (S / D) can be formed as epitaxial layers. In another embodiment, a lightly doped drain (LDD, not shown) can be formed in the substrate before forming the sidewall sub-layers (SP), depending on actual device requirements.

[0018] Furthermore, a mask layer HM is included on top of the gate structure G. The mask layer HM may include a single-layer or multi-layer dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiON), or a combination thereof. The material of the mask layer HM is different from that of the first dielectric layer 101.

[0019] In addition, a partial contact hole 112 may be formed next to the gate structure G, wherein the contact hole 112 exposes the source / drain region S / D and will be filled with a conductive material such as metal in a subsequent process to form a contact structure connecting the source / drain region S / D with other electronic components.

[0020] In the structure described above, most of the components belong to the conventional technology in this field, and the details and manufacturing methods of each component are not described in detail here.

[0021] In semiconductor manufacturing, in order to connect the parts of electronic components (such as the gate, source, and drain of a transistor) to form a corresponding circuit, in addition to forming contact structures, a metal layer is also required to connect the components laterally (horizontally). As shown in Figure 1, substrate 100 includes multiple gate structures G1, G2, G3, and G4 arranged in parallel. The distances between the gate structures G may vary; for example, the distance between gate structures G3 and G4 is greater than the distance between gate structures G1, G2, and G3. Figure 1 also illustrates the location of contact hole 112 (corresponding to the location of contact structure CT to be formed later). Furthermore, Figure 1 also illustrates the location of metal layer 114 with dashed lines. Metal layer 114 is primarily used to connect gate structure G to other materials to be formed later, to connect gate structure G to adjacent contact structure CT, or to laterally connect different gate structures G.

[0022] Depending on the circuit, the manufacturer will design different metal layer patterns. For example, in Figure 1, metal layer 114 includes metal layer 114A, metal layer 114B, and metal layer 114C. All three are part of metal layer 114, differing in the components they connect to. Metal layer 114A is located on gate structure G1, connecting it to other components to be formed later. Metal layer 114B connects contact structure CT to gate structure G2, effectively connecting the gate and source / drain of the transistor. Metal layer 114C connects gate structure G3 to gate structure G4, effectively connecting the gates of the two transistors.

[0023] In some semiconductor device layouts, if the distance between gate structures is large, the length of metal layer 114C will be longer. However, due to device arrangement limitations, the width of metal layer 114C cannot be increased. This results in a significantly larger aspect ratio for metal layer 114C than for the other metal layers 114A and 114B. For example, in this embodiment, the aspect ratios of metal layers 114A and 114B are approximately 1:1 or 2:1, while the aspect ratio of metal layer 114C is greater than 25:1. Furthermore, metal layer 114C is closer to metal layers 114A and 114B (due to the proximity of gate structures G1-G3). Therefore, when metal layers 114A and 114B are formed simultaneously with metal layer 114C in a single lithography and etching process, differences in exposure conditions may result in defects such as cracks in metal layer 114C.

[0024] Therefore, one of the concepts of the present invention is to use a separate photolithography step to form thin and elongated metal layers, which are more prone to cracking. Unlike conventional techniques that split the pattern into two separate photolithography steps to avoid overly dense pattern formation, the present invention takes into account the slenderness of the pattern and performs an additional photolithography step on thinner and elongated patterns, thereby improving production yield.

[0025] In addition, for the sake of simplicity in FIG. 1 , some components shown in FIG. 2 , such as shallow trench isolation STI and source / drain regions S / D, are not drawn in FIG. 1 . However, these components should actually exist at corresponding positions in the substrate 100 , which will be explained here first.

[0026] Please continue to refer to Figures 3 to 7, which each illustrate a cross-sectional schematic diagram of a semiconductor process method according to the present invention, continuing with the structure of Figure 2. As shown in Figure 3, a photoresist layer 116 is further stacked. The photoresist layer 116 comprises an organic dielectric layer (ODL) 116A, a silicon-containing hardmask bottom anti-reflecting coating (SHB) 116B, and a photoresist layer (PR) 116C. In short, the photoresist layer 116 in this embodiment comprises a three-layer structure consisting of ODL / SHB / PR. The photoresist layer 116C includes a plurality of openings 118. These openings 118 correspond to the non-elongated patterns in the semiconductor pattern, namely, the patterns of the metal layers 114A and 114B in Figure 1.

[0027] Next, as shown in FIG. 4 , a first etching step E1 is performed to transfer the pattern of the opening 118 to the underlying layers. The first etching step E1 includes, from top to bottom, sequentially etching the silicon-containing mask anti-reflective layer 116B, the organic dielectric layer 116A, the second dielectric layer 102, and the first dielectric layer 101, forming at least two contact holes until the mask layer HM at the top of the gate structure G is exposed. However, according to the applicant's actual observations, during the first etching step E1, although the etching step stops at the top of the mask layer HM, the mask layer HM at the top of the gate structure G is often partially etched due to over-etching. As a result, the top surface of the mask layer HM at the top of the gate structures G1 and G2 is slightly lower than the top surface of the mask layer HM at the top of the remaining unetched gate structures G3 and G4. That is, at this point, the top surface of the mask layer HM on top of the gate structures G1 and G2 is slightly lower than the top surface of the gate structure G3 (or the top surface of the first dielectric layer 101) by a depth D1. Furthermore, as the first etching step E1 proceeds, the photoresist layer 116 is gradually consumed.

[0028] As shown in FIG. 5 , another photoresist layer 120 is then formed. Photoresist layer 120 includes an organic dielectric layer (ODL) 120A, a silicon-containing mask antireflective layer (SHB) 120B, and a photoresist layer (PR) 120C. In short, in this embodiment, photoresist layer 120 comprises a three-layer structure consisting of ODL / SHB / PR. Photoresist layer 120C includes a plurality of openings 122. These openings 122 correspond to the elongated patterns in the semiconductor pattern, i.e., the pattern of metal layer 114C in FIG. 1 .

[0029] Next, as shown in FIG. 6 , a second etching step E2 is performed to transfer the pattern of the opening 122 to the underlying layers. The second etching step E2 includes, from top to bottom, sequentially etching the silicon-containing mask anti-reflective layer 120B, the organic dielectric layer 120A, the second dielectric layer 102, the first dielectric layer 101, and the mask layer HM until the gate structure G is exposed. Furthermore, as the second etching step E2 proceeds, the photoresist layer 120 is gradually consumed. During this process, the previously patterned second dielectric layer 102 can serve to resist etching in the second etching step E2.

[0030] It is worth noting that, because the mask layer HM above the gate structures G1 and G2 has already been partially etched during the first etching step E1, after the second etching step E2 is completed, the gate structures G1 and G2 are etched to a greater extent than the gate structures G3 and G4, resulting in the top surfaces of the gate structures G1 and G2 being lower than the top surfaces of the gate structures G3 and G4. The difference between the top surfaces is a depth D2. Therefore, after the second etching step E2, the substrate 100 includes contact holes 112 exposing the source / drain regions S / D, recesses 113A exposing the gate structure G1, recesses 113B exposing the gate structure G2, and recesses 113C exposing the gate structures G3 and G4. The bottom surfaces of recesses 113A and 113B are lower than the bottom surface of recess 113C.

[0031] As shown in FIG. 7 , a barrier layer 124 and a metal layer 126 are filled into the contact hole 112 and recesses 113A, 113B, and 113C. The barrier layer 124 may comprise titanium nitride (TiN) and tantalum nitride (TaN), or a multilayer barrier layer such as titanium / titanium nitride, to enhance adhesion between the inner walls of each recess and the subsequently formed metal layer. The metal layer 126 preferably comprises tungsten (W), which has excellent gap-filling performance. This forms the contact structure CT and metal layers 114A, 114B, and 114C shown in FIG. 1 (corresponding to the recesses 113A, 113B, and 113C after the barrier layer 124 and metal layer 126 are filled, respectively).

[0032] Furthermore, because the gate structures G1 and G2 are over-etched during the second etching step E2, resulting in the etching of portions of the sidewall sub-SP, a recessed portion 128 may be formed at the tops of the gate structures G1 and G2 after the second etching step E2 (as shown in FIG. 6 ). Furthermore, after the recesses 113A, 113B, and 113C are formed behind the barrier layer 124 and the metal layer 126, a recessed portion 130 (also known as a tiger tooth) may be formed at the bottoms of the metal layers 114A and 114B. The bottom surface of the recessed portion 130 is lower than the bottom surfaces of the metal layers 114A and 114B, and the recessed portion 130 may be located within a portion of the sidewall sub-SP.

[0033] In summary, the present invention provides a semiconductor structure comprising a substrate 100, a dielectric layer 101 disposed on the substrate 100, a plurality of gate structures G1, G2, G3, and G4 disposed within the dielectric layer 101 on the substrate 100, a plurality of first metal layers (i.e., metal layers 114A and 114B) disposed on a portion of the gate structures G1 and G2, wherein the first metal layers 114A and 114B are electrically connected to the corresponding gate structures G1 and G2, respectively, and at least one second metal layer (metal layer 114C), wherein the second metal layer 114C bridges at least two of the gate structures (gate structures G3 and G4), wherein the depth of the first metal layer 114A is greater than the depth of the second metal layer 114C.

[0034] In some embodiments of the present invention, a top surface of the first metal layers 114A and 114B is flush with a top surface of the second metal layer 114C.

[0035] In some embodiments of the present invention, a plurality of contact structures CT are further included in the dielectric layer 101, and the plurality of contact structures are electrically connected to a plurality of source / drain regions adjacent to the gate structures.

[0036] In some embodiments of the present invention, at least one first metal layer 114B is directly connected to one of the contact structures CT.

[0037] In some embodiments of the present invention, a top surface of the contact structure CT is flush with the top surfaces of the first metal layers 114A and 114B.

[0038] In some embodiments of the present invention, a plurality of sidewall sub-SPs are further included on both sides of each gate structure G.

[0039] In some embodiments of the present invention, a bottom surface of at least one first gate structure G1 includes a concave portion 130, wherein the concave portion 130 is located within the sidewall sub-SP, and a depth of the concave portion 130 is greater than a depth of the first metal layer 114A.

[0040] In some embodiments of the present invention, the second metal layer 114C is in a strip shape, and a ratio of a length to a width of the second metal layer 114C is greater than 25.

[0041] In some embodiments of the present invention, the dielectric layer 101 further includes a first dielectric layer 101 and a second dielectric layer 102 stacked on the first dielectric layer, wherein a top surface of the first metal layer 114A, a top surface of the second metal layer 11C, and a top surface of the second dielectric layer 102 are aligned.

[0042] The present invention further provides a method for manufacturing a semiconductor structure, comprising providing a substrate 100, forming a dielectric layer 101 on the substrate 100, forming a plurality of gate structures G within the dielectric layer 101 on the substrate 100, forming a plurality of first metal layers (i.e., metal layers 114A and 114B) on a portion of the gate structures G1 and G2, wherein the first metal layers 114A and 114B are electrically connected to the corresponding gate structures G1 and G2, respectively, and forming at least one second metal layer 114C, wherein the second metal layer 114C is connected across at least two of the gate structures G3 and G4, wherein a depth of the first metal layer 114A is greater than a depth of the second metal layer 114C.

[0043] In some embodiments of the present invention, a plurality of mask layers HM are formed, respectively located on each gate structure G1, G2, G3, and G4, and a method for forming the first metal layer 114A, 114B and the second metal layer 11C includes: performing a first etching step E1 to form a plurality of first recesses 113A, 113B corresponding to portions of the gate structures G1, G2, wherein the first recesses 113A, 113B expose the mask layer at the top of the corresponding gate structures G1, G2; performing a second etching step E2 to form at least one second recess 113C corresponding to another portion of the gate structure G4, G4, wherein the second recess 113C exposes the mask layer at the top of the corresponding gate structure G3, G4; removing each mask layer HM; and filling a conductive material (barrier layer 124 and metal layer 126) into the first recesses 113A, 113B and the second recess 113C.

[0044] In some embodiments of the present invention, after the first etching step E1, the mask layer HM exposed in the first grooves 113A and 113B is partially etched and the top surface thereof is lowered (corresponding to FIG. 4 ).

[0045] The present invention provides a semiconductor structure and a method for fabricating the same. Specifically, for metal layer patterns of specific dimensions (particularly long strips of metal layer patterns spanning two gate structures), such patterns are split into two separate lithography steps. The pattern splitting is based not only on pattern density but also on the pattern's aspect ratio. In other words, patterns with particularly high aspect ratios are split into the second lithography step. This improves the quality of the resulting long strip contact structures and reduces the likelihood of breakage. Furthermore, after the two lithography steps, the contact structures formed by the first lithography step are deeper than those formed by the second lithography step. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0046] 100: Base 101: first dielectric layer 102: second dielectric layer 104: Gate dielectric layer 106: High dielectric constant layer 108: Work function metal layer 110: Gate conductive layer 112: contact hole 113A: Groove 113B: Groove 113C: Groove 114:Metal layer 114A: Metal layer (first metal layer) 114B: Metal layer (first metal layer) 114C: Metal layer (second metal layer) 116: Photoresist layer 116A: organic dielectric layer 116B: Silicon mask anti-reflective layer 116C: Photoresist layer 118: Open 120: Photoresist layer 120A: Organic dielectric layer 120B: Silicon mask anti-reflective layer 120C: Photoresist layer 122: Open 124: Barrier layer 126:Metal layer 128: concave part 130: concave part CT: Contact structure CESL: Contact Etch Stop Layer D1: Depth D2: Depth G: Gate structure G1, G2, G3, G4: Gate structure HM: Mask layer SP: Sidewall S / D: Source / Drain region STI: Shallow Trench Isolation

Claims

1. A semiconductor structure comprising: a substrate; a dielectric layer on the substrate; a plurality of gate structures located within the dielectric layer on the substrate; a plurality of first metal layers located on a portion of the gate structures, and the first metal layers being electrically connected to corresponding gate structures; and at least one second metal layer bridging at least two of the gate structures, wherein a depth of the first metal layer is greater than a depth of the second metal layer; and a plurality of sidewalls located on either side of each gate structure, wherein a bottom portion of at least one first gate structure includes a recessed portion located within the sidewall, and a depth of the recessed portion is greater than the depth of the first metal layer.

2. The semiconductor structure as described in claim 1, wherein a top surface of the first metal layer is flush with a top surface of the second metal layer.

3. The semiconductor structure as described in claim 2, further comprising a plurality of contact structures located in the dielectric layer, wherein the plurality of contact structures are electrically connected to a plurality of source / drain regions adjacent to the gate structures.

4. The semiconductor structure as described in claim 3, wherein at least one first metal layer is directly connected to one of the contact structures.

5. The semiconductor structure as described in claim 3, wherein a top surface of the contact structure is flush with the top surface of the first metal layer.

6. The semiconductor structure as described in claim 1, wherein the second metal layer is elongated and the ratio of the length to the width of the second metal layer is greater than 25.

7. The semiconductor structure as described in claim 1, wherein the dielectric layer further comprises a first dielectric layer and a second dielectric layer stacked on the first dielectric layer, wherein a top surface of the first metal layer, a top surface of the second metal layer, and a top surface of the second dielectric layer are flush.

8. A method of fabricating a semiconductor structure, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a plurality of gate structures within the dielectric layer on the substrate; forming a plurality of first metal layers on a portion of the gate structures, wherein the first metal layers are electrically connected to corresponding gate structures; forming at least one second metal layer, the second metal layer bridging at least two of the gate structures, wherein a depth of the first metal layer is greater than a depth of the second metal layer; and forming a plurality of sidewalls on either side of each gate structure, wherein a bottom portion of at least one first gate structure includes a recessed portion within the sidewall, and a depth of the recessed portion is greater than the depth of the first metal layer.

9. The method for fabricating a semiconductor structure as described in claim 8, wherein a top surface of the first metal layer is flush with a top surface of the second metal layer.

10. The method of fabricating a semiconductor structure as described in claim 9, further comprising forming a plurality of contact structures located in the dielectric layer, wherein the plurality of contact structures are electrically connected to a plurality of source / drain regions adjacent to the gate structures.

11. The method of fabricating a semiconductor structure as described in claim 10, wherein at least one first metal layer is directly connected to one of the contact structures.

12. The method of fabricating a semiconductor structure as described in claim 10, wherein a top surface of the contact structure is flush with the top surface of the first metal layer.

13. The method for fabricating a semiconductor structure as described in claim 8, wherein the second metal layer is an elongated shape and the ratio of the length to the width of the second metal layer is greater than 25.

14. The method for fabricating a semiconductor structure as described in claim 8, wherein the dielectric layer further comprises a first dielectric layer and a second dielectric layer stacked on the first dielectric layer, wherein a top surface of the first metal layer, a top surface of the second metal layer, and a top surface of the second dielectric layer are flush.

15. A method for fabricating a semiconductor structure as described in claim 8, further comprising forming a plurality of masking layers respectively located on each of the gate structures, wherein the method for forming the first metal layer and the second metal layer comprises: performing a first etching step to form a plurality of first grooves corresponding to portions of the gate structures, wherein the first grooves expose the masking layers at the top ends of the corresponding gate structures; performing a second etching step to form at least one second groove corresponding to another portion of the gate structure, wherein the second groove exposes the masking layers at the top ends of the corresponding gate structures; removing each of the masking layers; and filling a conductive material into the first grooves and the second grooves.

16. The method of fabricating a semiconductor structure as described in claim 15, wherein after the first etching step, the mask layer exposed in the first groove is partially etched and the top surface is lowered.

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