Selective capping of contact layer for CMOS devices

Abstract

A method for forming electrical contacts in a semiconductor structure includes performing a patterning process to form a hard mask on the semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening in the first semiconductor region and a second opening in the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening, performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening, and performing a second selective deposition process to form a capping layer on the contact layer.

Description

Technical Field

[0001] Embodiments described herein generally relate to semiconductor device fabrication, and more particularly, to systems and methods for forming contacts within semiconductor structures. Prior Art

[0002] Multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), such as complementary metal-oxide semiconductor (CMOS) devices, present manufacturing challenges due to their three-dimensional (3D) design and small size. In advanced CMOS devices, an epitaxial layer of silicon-containing material (e.g., boron-doped p-type silicon germanium or phosphorus-doped n-type silicon) formed at the bottom of the trench contact is often used to reduce contact resistivity to the 10-9 Ω·cm2 range and achieve the performance required by advanced CMOS technologies. Typically, the p-type epitaxial layer is formed of silicon germanium (SiGe) with a high germanium (Ge) concentration, for example, between approximately 60% and approximately 80%, or in some cases, 100%, to minimize contact resistance. However, SiGe epitaxial layers with high Ge concentrations are sensitive to oxidation and wet etching chemistries and, therefore, can be removed in subsequent processing steps.

[0003] Therefore, there is a need for a method and system for forming a capping material to protect a silicon germanium (SiGe) epitaxial layer having a high germanium (Ge) concentration from oxidation and contamination. Summary of the Invention

[0004] Embodiments of the present disclosure provide a method for forming an electrical contact in a semiconductor structure. The method includes performing a patterning process to form a hard mask on the semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening on the first semiconductor region and a second opening on the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening, performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening, and performing a second selective deposition process to form a capping layer on the contact layer.

[0005] Embodiments of the present disclosure also provide a method for forming an electrical contact in a semiconductor structure. The method includes performing a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening on the first semiconductor region and a second opening on the second semiconductor region, wherein the exposed surface of the semiconductor structure is disposed on the first semiconductor region within the first opening and on the second semiconductor region within the second opening; performing a patterning process to form a hard mask on the exposed surface of the first semiconductor region within the first opening; performing an etching process to form a recess at the exposed surface of the second semiconductor region; performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening; performing a second selective deposition process to form a capping layer on the contact layer; performing a removal process to remove the hard mask; performing a third selective deposition process to form a metal layer on the exposed surface of the first semiconductor region and the capping layer; and performing a metal filling process to form a first contact plug in the first opening and a second contact plug in the second opening, wherein the first selective deposition process and the second selective deposition process are performed without breaking a vacuum environment.

[0006] Embodiments of the present disclosure also provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, and a system controller, the system controller being configured to cause the processing system to perform a patterning process in the first processing chamber to form a hard mask on a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening in the first semiconductor region and a second opening in the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening; perform a first selective deposition process in the second processing chamber to form a contact layer on an exposed surface of the second semiconductor region within the second opening; and perform a second selective deposition process in the third processing chamber to form a capping layer on the contact layer. Simple diagram description

[0007] In order to provide a detailed understanding of the manner in which the above-described features of the present disclosure are achieved, a more particular description of the present disclosure, briefly summarized above, may be given by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments.

[0008] FIG. 1 is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure.

[0009] FIG. 2A is a cross-sectional view of a processing chamber according to one or more embodiments.

[0010] FIG. 2B is an enlarged view of a portion of the processing chamber of FIG. 2A .

[0011] FIG. 3 is a cross-sectional view of a processing chamber according to one or more embodiments.

[0012] FIG. 4 illustrates a process flow diagram of a method for forming a contact layer in a semiconductor structure according to one or more embodiments of the present disclosure.

[0013] 5A , 5B, 5C, 5D, 5E, 5F, 5G, and 5H are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 4 .

[0014] To facilitate understanding, identical reference numerals are used, where possible, to denote identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. It is contemplated that elements and features of one embodiment may be beneficially incorporated into other embodiments without further elaboration. Implementation Method

[0015] Embodiments described herein provide methods and systems for forming contacts comprising an epitaxial layer of a silicon-containing material (e.g., boron-doped p-type silicon germanium or phosphorus-doped n-type silicon) at selected portions of a structure used to form a CMOS device (e.g., on exposed surfaces of a silicon layer or silicon germanium layer). These methods and systems are particularly useful for selectively forming an epitaxial layer comprising silicon germanium on exposed surfaces of the silicon germanium material within an opening or feature (e.g., a contact trench) formed in a dielectric layer in a semiconductor structure having a region comprising silicon, a region comprising silicon germanium, and a dielectric layer formed thereover. The processes described herein are configured to form a capping layer to protect contacts formed in the semiconductor structure from oxidation and contamination.

[0016] FIG1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104 and 106, transfer chambers 108 and 110 with respective transfer robots 112 and 114, holding chambers 116 and 118, and processing chambers 120, 122, 124, 126, 128, and 130. As described in detail herein, substrates in the processing system 100 can be processed in and transferred between various chambers without exposing the substrates to an ambient environment external to the processing system 100 (e.g., such as the ambient atmosphere that may exist in a wafer fab). For example, during various processes performed on substrates in the processing system 100, substrates can be processed in and transferred between various chambers maintained at a low pressure (e.g., less than or equal to approximately 300 Torr) or vacuum environment without disrupting the low pressure or vacuum environment. Thus, the processing system 100 can provide an integrated solution for a variety of substrate processing operations.

[0017] Examples of processing systems that may be suitably modified according to the teachings provided herein include Endura®, Producer®, or Centura® integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, Calif. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from the aspects described herein.

[0018] In the example shown in FIG. 1 , the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate substrate transfer. The docking station 132 is adapted to receive one or more front-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed on one end of the respective factory interface robot 134, which is adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0019] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 also has respective ports 148, 150 coupled to the holding chambers 116, 118, and respective ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118, and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 may be, for example, slit valve openings with slit valves for allowing substrates to pass through these slit valve openings by transfer robots 112 and 114 and for providing a seal between the respective chambers to prevent gas from passing between the respective chambers. In general, any port may be opened for transferring a substrate therethrough. Otherwise, the port is closed.

[0020] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits that fluidly connect the various chambers. In operation, the factory interface robot 134 transfers a substrate from a FOUP 136 to a load lock chamber 104 or 106 via port 140 or 142. The gas and pressure control system then evacuates the load lock chamber 104 or 106. The gas and pressure control system further maintains a low-pressure or vacuum environment (which may include an inert gas) within the transfer chambers 108, 110 and holding chambers 116, 118. Thus, pumping of the load lock chamber 104 or 106 facilitates the passage of substrates between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 .

[0021] With the substrate in the already evacuated load lock chamber 104 or 106, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 to the transfer chamber 108 via port 144 or 146. The transfer robot 112 can then transfer the substrate to the processing chambers 120, 122 for processing via respective ports 152, 154, and to the holding chambers 116, 118 for holding pending further transfer via respective ports 148, 150, and / or transfer the substrate between any of these chambers. Similarly, the transfer robot 114 can access substrates in the holding chamber 116 or 118 via port 156 or 158 and can transfer the substrates to the processing chambers 124, 126, 128, 130 for processing via respective ports 160, 162, 164, 166, and to the holding chambers 116, 118 for holding pending further transfer via respective ports 156, 158, and / or transfer substrates between any of these chambers. The substrates can be transferred and held within and between the various chambers in a low pressure or vacuum environment provided by a gas and pressure control system.

[0022] Processing chambers 120, 122, 124, 126, 128, and 130 can be any suitable chamber for processing substrates. In some examples, processing chamber 120 can perform an etch process, processing chamber 122 can perform a clean process, processing chamber 124 can perform a selective removal process, and processing chambers 126, 128, and 130 can each perform an epitaxial growth process. Processing chamber 120 can be a Selectra™ etch chamber available from Applied Materials, Inc., Santa Clara, California. Processing chamber 122 can be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc., Santa Clara, California. Processing chambers 126, 128, and 130 can be Centura™ epitaxial chambers available from Applied Materials, Inc., Santa Clara, California.

[0023] A system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, the system controller 168 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 enables data to be collected and fed back from the various chambers to coordinate the performance of the processing system 100.

[0024] System controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuits 174. CPU 170 can be any general-purpose processor suitable for use in an industrial environment. Memory 172, or non-transitory computer-readable media, is accessible by CPU 170 and can be one or more of random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. Support circuits 174 are coupled to CPU 170 and can include cache memory, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented under the control of CPU 170 by CPU 170 executing computer instruction code stored, for example, as software routines, in memory 172 (or the memory of a particular processing chamber). When the computer instruction code is executed by CPU 170, CPU 170 controls the chamber to perform processing according to the various methods.

[0025] Other processing systems may employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108 and 110 and holding chambers 116 and 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer device in the processing system.

[0026] FIG. 2A is a cross-sectional view of a processing chamber 200 suitable for performing a pre-cleaning process as described in detail below, according to one or more embodiments. The processing chamber 200 may be the processing chamber 122 shown in FIG. 1 . FIG. 2B is an enlarged view of a portion of the processing chamber 200 of FIG. 2A .

[0027] Processing chamber 200 can be particularly useful for performing thermal or plasma-based cleaning processes and / or plasma-assisted dry etching processes. Processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. Lid assembly 204 is disposed at an upper end of chamber body 202, and support assembly 206 is at least partially disposed within chamber body 202. A vacuum system can be used to remove gases from processing chamber 200. The vacuum system includes a vacuum pump 208 coupled to a vacuum port 210 disposed in chamber body 202. Processing chamber 200 also includes a controller 212 for controlling processes within processing chamber 200.

[0028] The lid assembly 204 includes a stack of components adapted to provide precursor gases and / or plasma to a processing region 214 within the processing chamber 200. A first plate 216 is coupled to a second plate 218. A third plate 220 is coupled to the second plate 218. The lid assembly 204 can be connected to a power supply (not shown) for supplying plasma to a conical chamber 222 formed in the lid assembly 204. The lid assembly 204 can also be connected to a remote plasma source 224, which generates plasma upstream of the lid stack. The remote plasma chamber (e.g., the processing region 214, the first plate 216, and the second plate 218 in Figures 2A-2B) is coupled to a gas source 226 via the remote plasma source 224 (or, in the absence of a remote plasma source 224, the gas source 226 is coupled directly to the lid assembly 204). The gas source 226 may include a gas source adapted to provide helium, argon, or other inert gas. In some configurations, the gas provided by the gas source 226 can be excited into a plasma that is provided to the lid assembly 204 using a remote plasma source 224. In alternative embodiments, the gas source 226 can provide a process gas that can be activated by the remote plasma source 224 before being introduced to the surface of a substrate disposed within the processing chamber 200. Referring to FIG. 2B , the tapered chamber 222 has an opening 228 that allows the formed plasma to flow from the remote plasma source 224 to a volume 230 formed in a fourth plate 232 of the lid assembly 204.

[0029] In some configurations of the lid assembly 204, plasma is generated within the conical chamber 222 by applying energy delivered from a plasma source. In one example, energy can be provided by biasing the lid assembly 204 to capacitively couple RF, VHF, and / or UHF energy to the gas located within the conical chamber 222. In such configurations of the lid assembly 204, the remote plasma source 224 may not be used or may not be installed within the lid assembly 204.

[0030] A central conduit 234 formed in the fourth plate 232 is adapted to provide plasma-generated species provided from the volume 230 to a mixing chamber 238 formed in the sixth plate 240 of the lid assembly 204 via the fifth plate 236. The central conduit 234 communicates with the mixing chamber 238 via an opening 242 in the fifth plate 236. The diameter of the opening 242 can be smaller than, larger than, or equal to the diameter of the central conduit 234. In the embodiment of FIG. 2B , the opening 242 has the same diameter as the central conduit 234.

[0031] Fourth plate 232 also includes inlets 244 and 246 adapted to provide gas to mixing chamber 238. Inlet 244 is coupled to a first gas source 248, and inlet 246 is coupled to a second gas source 250. First gas source 248 and second gas source 250 may include a process gas and an inert gas, such as argon and / or helium, used as a carrier gas. First gas source 248 may include ammonia (NH3) and argon (Ar). Second gas source 250 may include a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof. In one example, second gas source 250 may include hydrogen fluoride (HF) and argon (Ar).

[0032] As shown in FIG. 2B , in some configurations, inlet 244 is coupled to mixing chamber 238 via cylindrical channel 252 (shown in phantom) and holes 254 formed in fifth plate 236. Inlet 246 is coupled to mixing chamber 238 via cylindrical channel 256 (shown in phantom) and holes 258 formed in fifth plate 236. The holes 254, 258 formed in fifth plate 236 are generally sized to uniformly flow gas provided from their respective gas sources 248, 250 into mixing chamber 238. In one configuration, the diameter of holes 258 is smaller than the width of the opening defined by opposing sidewalls of cylindrical channel 256 formed in fourth plate 232. The holes 258 are generally distributed circumferentially around the centerline of cylindrical channel 256 to provide uniform fluid flow into mixing chamber 238. In one configuration, the diameter of the holes 254 is smaller than the width of the opening defined by opposing sidewalls of the cylindrical passage 252 formed in the fourth plate 232. The holes 254 are generally distributed circumferentially about the centerline of the cylindrical passage 252 to provide uniform fluid flow into the mixing chamber 238.

[0033] Inlets 244 and 246 provide respective fluid flow paths that traverse fourth plate 232, turn, and penetrate fifth plate 236 to reach mixing chamber 238. Lid assembly 204 also includes a seventh plate or first gas distributor 260, which may be a gas distribution plate, such as a showerhead, wherein the various gases mixed within lid assembly 204 flow through perforations 262 formed therein. Perforations 262 are in fluid communication with mixing chamber 238 to provide a flow path from mixing chamber 238 through first gas distributor 260. Returning to FIG. 2A , barrier plate 264 and a gas distribution plate, such as second gas distributor 266, which may be a gas distribution plate, such as a showerhead, are positioned beneath lid assembly 204.

[0034] Alternatively, different cleaning processes may be used to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH 3) may be introduced into the processing chamber 200 via the lid assembly 204 , while ammonia (NH 3) may be injected directly into the processing chamber 200 via a separate gas inlet 268 disposed on a side of the chamber body 202 and coupled to a gas source (not shown).

[0035] The support assembly 206 may include a substrate support 270 to support a substrate 272 thereon during processing. The substrate support 270 may be coupled to an actuator 274 via a shaft 276 that extends through a centrally located opening formed in the bottom of the chamber body 202. The actuator 274 may be flexibly sealed to the chamber body 202 via a bellows (not shown) that prevents vacuum leakage around the shaft 276. The actuator 274 allows the substrate support 270 to move vertically within the chamber body 202 between a processing position and a loading position. The loading position is slightly lower than the opening of a channel (not shown) formed in the sidewall of the chamber body 202.

[0036] The substrate support 270 has a flat or substantially flat substrate support surface for supporting a substrate 272 to be processed thereon. The substrate support 270 can be moved vertically within the chamber body 202 by an actuator 274 coupled to the substrate support 270 by a shaft 276. For some process operations, the substrate support 270 can be raised proximate to the lid assembly 204 to control the temperature of the substrate 272 being processed. Thus, the substrate 272 can be heated via radiation emitted from the second gas distributor 266 or another radiation source, or via convection or conduction through an intermediate gas from the second gas distributor 266. During some process steps, the substrate can be positioned on lift pins 278 to perform additional thermal processing operations, such as an annealing step.

[0037] FIG3 is a cross-sectional view of a processing chamber 300 suitable for performing an epitaxial (Epi) deposition process as described below, according to one or more embodiments. The processing chamber 300 may be the processing chamber 126, 128, or 130 shown in FIG1.

[0038] Processing chamber 300 includes a housing structure 302 made of a process-resistant material, such as aluminum or stainless steel, for example, 316L stainless steel. Housing structure 302 encloses various functional components of processing chamber 300, such as a quartz chamber 304, which includes an upper quartz chamber 306 and a lower quartz chamber 308, containing a processing volume 310. Reactive species are supplied to quartz chamber 304 via a gas distribution assembly 312, and process byproducts are removed from processing volume 310 via an outlet port 314, which is typically connected to a vacuum source (not shown).

[0039] The substrate support 316 is adapted to receive a substrate 318 that is transferred to the processing volume 310. The substrate support 316 is positioned along the longitudinal axis 320 of the processing chamber 300. The substrate support 316 can be made of a ceramic material, a graphite material coated with a silicon material (e.g., silicon carbide), or other process-resistant material. Reactive species from the precursor reactant materials are applied to the surface 322 of the substrate 318, and byproducts can subsequently be removed from the surface 322 of the substrate 318. Heating of the substrate 318 and / or the processing volume 310 can be provided by a radiation source, such as an upper lamp module 324A and a lower lamp module 324B.

[0040] In one embodiment, upper lamp module 324A and lower lamp module 324B are infrared (IR) lamps. Non-thermal energy or radiation from lamp modules 324A and 324B travels through upper quartz window 326 of upper quartz chamber 306 and through lower quartz window 328 of lower quartz chamber 308. If desired, cooling gas for upper quartz chamber 306 enters via inlet 330 and exits via outlet 332. Precursor reactant materials, as well as diluent, purge, and exhaust gases for processing chamber 300, enter via gas distribution assembly 312 and exit via outlet port 314. Although upper quartz window 326 is shown as curved or convex, upper quartz window 326 can be flat or concave because the pressure on both sides of upper quartz window 326 is substantially the same (i.e., atmospheric pressure).

[0041] Low-wavelength radiation in the processing volume 310 is used to excite reactive species and aid in the adsorption of reactants and desorption of process byproducts from the surface 322 of the substrate 318. The low-wavelength radiation typically ranges from about 0.8 µm to about 1.2 µm, such as from about 0.95 µm to about 1.05 µm, with various wavelength combinations being provided depending, for example, on the composition of the film being epitaxially grown.

[0042] Component gases enter processing volume 310 via gas distribution assembly 312. Gases flow from gas distribution assembly 312 and exit via outlet port 314, as generally indicated by flow path 334. The combination of component gases used to clean / passivate the substrate surface or form the epitaxially grown silicon- and / or germanium-containing film is typically mixed prior to entering processing volume 310. The total pressure in processing volume 310 can be regulated via a valve (not shown) on outlet port 314. At least a portion of the interior surface of processing volume 310 is covered by a liner 336. In one embodiment, liner 336 comprises an opaque quartz material. In this manner, the chamber walls are insulated from heat within processing volume 310.

[0043] The surface temperature in the processing volume 310 can be controlled within a temperature range of about 200° C. to about 600° C. or higher by the flow of cooling gas entering through inlet 330 and exiting through outlet 332 in combination with radiation from an upper lamp module 324A located above the upper quartz window 326. The temperature in the lower quartz chamber 308 can be controlled within a temperature range of about 200° C. to about 600° C. or higher by adjusting the speed of a blower unit (not shown) and by radiation from a lower lamp module 324B positioned below the lower quartz chamber 308. The pressure in the processing volume 310 can be between about 0.1 Torr and about 600 Torr, for example, between about 5 Torr and about 30 Torr.

[0044] The temperature on the surface 322 of the substrate 318 can be controlled by adjusting the power to the lower lamp module 324B in the lower quartz chamber 308, or by adjusting the power to both the upper lamp module 324A covering the upper quartz window 326 and the lower lamp module 324B in the lower quartz chamber 308. The power density in the processing volume 310 can be between about 40 W / cm2 and about 400 W / cm2, for example, about 80 W / cm2 and about 120 W / cm2.

[0045] In one aspect, the gas distribution assembly 312 is positioned perpendicular to or radially relative to the longitudinal axis 320 of the processing chamber 300 or substrate 318. In this orientation, the gas distribution assembly 312 is adapted to flow the process gas in the radial direction 338 across or parallel to the surface 322 of the substrate 318. In one processing application, the process gas is preheated at the point of introduction into the processing chamber 300 to initiate preheating of the gas and / or to break specific bonds in the gas prior to introduction into the processing volume 310. In this manner, surface reaction kinetics can be modified independently of the thermal temperature of the substrate 318.

[0046] In operation, precursors for forming blanket or selective epitaxial films of silicon (Si) and silicon germanium (SiGe) are provided to gas distribution assembly 312 from one or more gas sources 340A and 340B. IR lamps 342 (only one shown in FIG. 3 ) may be used to heat the precursors within gas distribution assembly 312 and along flow path 334. Gas sources 340A, 340B may be coupled to gas distribution assembly 312 in a manner suitable for facilitating introduction into a region within gas distribution assembly 312, such as a radially inner region between a radially outer region and an outer region when viewed inwardly from a top plan view. Gas sources 340A, 340B may include valves (not shown) to control the rate of introduction into the region.

[0047] Gas sources 340A and 340B may include silicon precursors, such as silanes, including silane (SiH₄), disilane (Si₂H₆), dichlorosilane (SiH₂Cl₂), hexachlorodisilane (Si₂Cl₂), dibromosilane (SiH₂Br₂), higher silanes, derivatives thereof, and combinations thereof. Gas sources 340A and 340B may also include germanium-containing precursors, such as germanium (GeH₄), digermane (Ge₂H₆), germanium tetrachloride (GeCl₄), dichlorogermane (GeH₂Cl₂), derivatives thereof, and combinations thereof. Silicon- and / or germanium-containing precursors may be used in combination with hydrogen chloride (HCl), chlorine (Cl₂), hydrogen bromide (HBr), and combinations thereof. The gas sources 340A, 340B may include one or more silicon and germanium containing precursors in one or both of the gas sources 340A, 340B.

[0048] In this excited state, the precursor material enters the processing volume 310 through openings or holes 344 (only one shown in FIG. 3 ) in a perforated plate 346. In one embodiment, the perforated plate 346 is a quartz material, with holes 344 formed through the perforated plate 346. The perforated plate 346 is transparent to IR energy and can be made of clear quartz. In other embodiments, the perforated plate 346 can be any material that is transparent to IR energy and resistant to process chemicals and other processing chemicals. The excited precursor material passes through the holes 344 in the perforated plate 346 and flows through channels 348 (only one shown in FIG. 3 ) toward the processing volume 310. A portion of the photons and non-thermal energy from the IR lamp 342 also passes through the holes 344, perforated plate 346, and channels 348, aided by reflective materials and / or surfaces disposed on the interior surfaces of the gas distribution assembly 312, thereby illuminating the precursor material flow path 334. In this way, the vibrational energy of the precursor material can be maintained along the flow path from the point of introduction into the processing volume 310.

[0049] FIG. 4 depicts a process flow diagram of a method 400 for forming a contact layer in a semiconductor structure 500 according to a first embodiment of the present disclosure. FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D, FIG. 5E, FIG. 5F, FIG. 5G, and FIG. 5H are cross-sectional views of a portion of semiconductor structure 500 corresponding to various states of method 400. It should be understood that FIG. 5A, FIG. 5B, FIG. 5C, FIG. 5D, FIG. 5E, FIG. 5F, FIG. 5G, and FIG. 5H illustrate only a partial schematic representation of semiconductor structure 500, and that semiconductor structure 500 may include any number of transistor portions and additional materials having the aspects shown. It should also be noted that while the method shown in FIG. 4 is described sequentially, other process sequences including one or more operations that have been omitted and / or added, and / or rearranged in another desired order fall within the scope of the embodiments of the present disclosure provided herein.

[0050] 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H, a semiconductor structure 500 may include a first transistor element 502 and a second transistor element 504 formed on a substrate (not shown).

[0051] As used herein, the term "substrate" refers to a layer of material that serves as a foundation for subsequent processing operations and includes the surface to be cleaned. The substrate may be a silicon substrate or any suitable insulating or conductive material, as desired. The substrate may include materials such as crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass or sapphire materials.

[0052] As shown in FIG. 5A , a portion of a first transistor element 502 among a plurality of first transistor elements formed on a substrate includes a first semiconductor region 506 formed of a first material. A portion of a second transistor element 504 among a plurality of second transistor elements formed on the substrate includes a second semiconductor region 508 formed of a second material. The first and second materials comprise materials having different compositions, such that the second material can be selectively etched relative to the first material (i.e., the etching rate of the second material is higher than the etching rate of the first material). The etching selectivity of the second material (i.e., the ratio of the etching rate of the second material to the etching rate of the first material) is between approximately 10:1 and 500:1. Example combinations of the first and second materials include silicon (Si) / silicon germanium (SiGe), germanium (Ge) / silicon germanium (SiGe), or silicon (Si) / germanium tin (GeSn), respectively.

[0053] The first semiconductor region 506 may be doped with an n-type dopant, such as phosphorus (P) or antimony (Sb), at a concentration between approximately 10 20 cm -3 and 5×10 21 cm -3, depending on the desired conductivity characteristics of the first transistor element 502. The second semiconductor region 508 may be doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration between approximately 10 20 cm -3 and approximately 5×10 21 cm -3, depending on the desired conductivity characteristics of the second transistor element 504.

[0054] The semiconductor structure 500 further includes a dielectric layer 510 having a first opening 512 formed on each first semiconductor region 506 and a second opening 514 formed on each second semiconductor region 508. The dielectric layer 510 may be formed of a dielectric material, such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ).

[0055] The first semiconductor region 506 and the second semiconductor region 508 may be formed using any suitable deposition technique, such as epitaxial deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the openings 512 and 514 may be formed by patterning techniques, such as photolithography and etching processes.

[0056] The method 400 begins with a pre-cleaning process at block 410. The pre-cleaning process may be performed in a processing chamber, such as the processing chamber 122 shown in FIG. 1 or the processing chamber 200 shown in FIG.

[0057] The pre-cleaning process is configured to remove contaminants, such as a native oxide layer or patterning residues (e.g., fluorocarbons) formed on the exposed surface of the first semiconductor region 506 within the first opening 512 and the exposed surface of the second semiconductor region 508 within the second opening 514. The pre-cleaning process is used to prepare the exposed surface of the first semiconductor region 506 within the first opening 512 and the exposed surface of the second semiconductor region 508 within the second opening 514. In a subsequent epitaxial deposition process, an epitaxial layer may be formed on these exposed surfaces.

[0058] The pre-cleaning process may include an anisotropic remote plasma-assisted dry etching process, such as a reactive ion etching (RIE) process using a plasma formed from a gas including argon (Ar), helium (He), or a combination thereof. The plasma effluent directionally bombards and removes the remaining dielectric layer within the first opening 512 and the second opening 514.

[0059] The pre-clean process can include an isotropic plasma etch process, such as the SiCoNi™ dry chemical etch process, using a plasma formed from a gas including ammonia (NH₃), nitrogen trifluoride (NF₃), hydrogen fluoride (HF), or a combination thereof, and a carrier gas such as nitrogen (N₂), hydrogen (H₂), or a combination thereof. The dry chemical etch process is selective for oxide layers and therefore does not readily etch silicon, germanium, or nitride layers, regardless of whether these layers are amorphous, crystalline, or polycrystalline. The dry chemical etch process has a selectivity of at least approximately 3:1 for oxide relative to silicon or germanium, and is typically 5:1 or better, and sometimes 10:1. The dry chemical etch process also has a high selectivity for oxide relative to nitride. The dry chemical etch process has a selectivity of at least approximately 3:1 for nitride relative to nitride, and is typically 5:1 or better, and sometimes 10:1.

[0060] The pre-clean process may include an inductively coupled plasma (ICP) etch process, which uses a plasma formed from gases including chlorine (Cl2) and hydrogen (H2) and a carrier gas including argon (Ar) and helium (He). The ICP etch process is used to form deep ridges with smooth sidewalls in silicon.

[0061] At block 420, a patterning process is performed to form a hard mask 516 within the first opening 512 of the dielectric layer 510 above the first semiconductor region 506, thereby covering the exposed surface of the first semiconductor region 506 within the first opening 512, as shown in FIG. 5B . The patterning process can be performed in a processing chamber, such as processing chambers 126, 128, or 130 shown in FIG. The patterning process can be performed using any conventional deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and a spin coating process, and then patterned using a patterned photoresist layer (not shown) covering the hard mask 516 by a conventional photolithography process.

[0062] The hard mask 516 may be formed of tetra-ethyl-orthosilicate (TEOS) or silicon oxynitride (SiON) and have a thickness of about 500 nm and about 2 μm.

[0063] At block 430, an etching process is performed to form a recess 508A at the exposed surface of the second semiconductor region 508 within the second opening 514, as shown in FIG5C. The etching process may be performed in an etching chamber, such as the processing chamber 120 shown in FIG1.

[0064] The groove 508A may have a V-shape, a U-shape, or any other shape, and expands the contact area of ​​the contact layer to be formed between the second semiconductor region 508 and the metal contact plug to be formed in the second opening 514 to minimize parasitic resistance.

[0065] At block 440, a first selective deposition is performed to epitaxially form a contact layer 518 on the exposed surface of the second semiconductor region 508 within the recess 508A and within the second opening 514, as shown in FIG5D. The first selective deposition can be performed in a processing chamber, such as the processing chambers 126, 128, or 130 shown in FIG1, or the processing chamber 300 shown in FIG3.

[0066] Contact layer 518 is formed as an interface between second semiconductor region 508 and a metal contact plug to be formed within second opening 514 to minimize parasitic resistance. Contact layer 518 is formed of a third material. Examples of the third material include silicon germanium (SiGe) with a germanium (Ge) ratio ranging between 20% and 100%, for example, between approximately 60% and approximately 80%, between approximately 60% and approximately 100%, or between approximately 80% and approximately 100%. Contact layer 518 may be doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration between approximately 10 20 cm -3 and 5×10 21 cm -3, depending on the desired conductive properties of contact layer 518.

[0067] In some embodiments, the first selective deposition includes an epitaxial deposition process and an etching process. The selectivity in the first selective deposition may be caused by a difference in nucleation of the third material on the second semiconductor region 508 (e.g., silicon germanium (SiGe)) and the third material on the exposed surface of the dielectric layer 510 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). When the semiconductor structure 500 is exposed to a deposition gas during a deposition process, nucleation can occur at a faster rate on the second semiconductor region 508 (e.g., silicon germanium (SiGe)) than on the exposed surface of the dielectric layer 510 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). As a result, an epitaxial layer of the third material can be selectively formed on the exposed surface of the second semiconductor region 508 (e.g., silicon (Si) or silicon germanium (SiGe)), while an amorphous layer of the third material can be formed on the exposed surface of the dielectric layer 510 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). In a subsequent etching process, the amorphous layer of the third material formed on the exposed surface of the dielectric layer 510 can be etched by an appropriate etching gas at a faster rate than the epitaxial layer of the third material formed on the exposed surface of the second semiconductor region 508. Therefore, the overall result of the epitaxial deposition process and the etching process combination can be epitaxial growth of the third material on the exposed surface of the second semiconductor region 508 while minimizing the growth (if any) of the third material on the exposed surface of the dielectric layer 510.

[0068] In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor may include silane (SiH4), disilane (Si2H6), tetrasilane (Si4H10), or a combination thereof. The germanium-containing precursor may include germane (GeH4), germanium tetrachloride (GeCl4), and digermane (Ge2H6). Depending on the desired conductive properties of the contact layer 518, the dopant source may include, for example, boron or gallium. The dopant source may include the precursor diborane (B2H6). The etching gas includes an etchant gas and a carrier gas. The etchant gas may include a halide-containing gas, such as hydrogen chloride (HCl), chlorine (Cl2), or hydrogen fluoride (HF). The carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2).

[0069] The first selective deposition may be performed at a low temperature below about 450° C. and a pressure of 5 to 600 Torr.

[0070] The cycle of epitaxial deposition and etching processes may be repeated as needed to obtain a desired thickness of the contact layer 518. The thickness of the contact layer 518 may be between about 30 angstroms and about 100 angstroms.

[0071] At block 450, a second selective deposition process is performed to form a capping layer 520 on the contact layer 518, as shown in FIG5E. The second selective deposition process can be performed in a processing chamber, such as processing chambers 126, 128, or 130 shown in FIG1, or processing chamber 300 shown in FIG3, or the same processing chamber used for the first selective deposition in block 440. The first selective deposition in block 440 and the second selective deposition process in block 450 can be performed without breaking the vacuum environment in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in FIG1.

[0072] The capping layer 520 protects the contact layer 518 from oxidation and contamination in the atmosphere during the transition from the epitaxial process to subsequent processes (e.g., silicidation and patterning), while maintaining electrical connection through the contact layer 518 and reducing parasitic resistance. The capping layer 520 can be formed of a first metal material, such as molybdenum (Mo), ruthenium (Ru), or a silicide thereof.

[0073] In some embodiments, the second selective deposition process includes a chemical vapor deposition (CVD) process and an etching process.

[0074] In some embodiments, the deposition gas used in the deposition process includes a metal source, such as a halide precursor containing molybdenum (Mo), or a ruthenium (Ru)-containing organometallic. The second selective deposition process can be performed at a temperature between approximately 240°C and approximately 450°C and a pressure between 3° Torr and 300° Torr. For example, during the deposition process, argon (Ar) gas can be supplied at a flow rate between approximately 0 sccm and approximately 1,000 sccm, and hydrogen (H2) gas can be supplied at a flow rate between approximately 500 sccm and approximately 15,000 sccm.

[0075] The cycle of the second selective deposition process may be repeated as needed to obtain a desired thickness of the capping layer 520, for example, between about 5 times and about 1000 times.

[0076] At block 460, a stripping process is performed to remove the hard mask 516, as shown in FIG5F. The stripping process may be a suitable etching process performed in an etching chamber, such as the processing chamber 120 shown in FIG1.

[0077] At block 470, a third selective deposition process is performed to form a metal layer 522 on the capping layer 520, as shown in FIG5G. The third selective deposition process may be performed in a processing chamber, such as the processing chambers 126, 128, or 130 shown in FIG1, or the processing chamber 300 shown in FIG3.

[0078] Metal layer 522 contacts capping layer 520 and provides electrical connection between the contact plug to be formed in second opening 514 and second semiconductor region 508, while maintaining electrical connection therethrough. Metal layer 522 may be formed of a second metal material, such as titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), or tantalum (Ta), or a silicide thereof.

[0079] In some embodiments, the third selective deposition process includes a deposition process, such as epitaxial deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., and an etching process.

[0080] In some embodiments, the deposition gas used in the deposition process includes a metal source, such as a precursor containing titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), or molybdenum (Mo), or a combination thereof. The third selective deposition process can be performed at a temperature between about 300° C. and about 800° C. and a pressure between 1° Torr and 50° Torr.

[0081] During the third selective deposition process, a barrier metal layer 524 may also be formed on the exposed inner surfaces of the first and second openings 512, 514, and on the exposed surface of the dielectric layer 510. The barrier metal layer 524 protects the metal layer 522 and allows contact plugs to nucleate and grow in the first and second openings 512, 514. The barrier metal layer 524 may be formed of a barrier metal material such as titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the metal layer 522 is a silicide layer formed from a portion of the barrier metal layer 524 using a spike annealing process.

[0082] At block 480, a metal fill process is performed to form a first contact plug 526 in the first opening 512 and a second contact plug 528 in the second opening 514, as shown in FIG. The first contact plug 526 and the second contact plug 528 can be formed of a contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The first contact plug 526 and the second contact plug 528 can include a metal having a desired work function. The metal fill process at block 470 can include a chemical vapor deposition (CVD) process using a tungsten-containing precursor or a cobalt-containing precursor, such as WF6, in a processing chamber, such as processing chambers 126, 128, or 130 shown in FIG. 1 .

[0083] After the metal filling process, the semiconductor structure 500 may be planarized by using a chemical mechanical planarization (CMP) process.

[0084] Embodiments described herein provide methods and systems for forming a contact epitaxial layer within a trench on a selected portion of a transistor structure and forming a capping layer on the contact epitaxial layer to protect the contact epitaxial layer from oxidation and contamination. The contact trench structure includes a metal contact plug formed within a trench between adjacent device modules, and a contact between the contact plug and a silicon-based channel in the device module. The contact is formed by selective deposition, reducing parasitic resistance. The metal contact plug is formed void-free by a deposition-etch-deposition process, reducing contact resistance. The contact epitaxial layer can be p-type silicon germanium formed on the exposed surface of a p-type MOS device (e.g., silicon germanium), while no epitaxial layer can be formed on an n-type MOS device (e.g., silicon) or on a dielectric layer formed on both the p-type MOS device and the n-type MOS device. The capping layer reduces damage to the fabricated contact epitaxial layer.

[0085] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the scope of the claims that follow.

[0086] 100:Multi-chamber processing system 102:Factory Interface 104: Loading lock chamber 106: Loading lock chamber 108: Loading lock chamber 112:Transfer Robot 114:Transportation Robot 116: Chamber 118: Chamber 120: Processing chamber 122: Processing chamber 124: Processing chamber 126: Processing chamber 128: Processing chamber 130: Processing chamber 132: Docking Station 134:Factory Interface Robot 136: Front-opening wafer transfer box 138: Blade 140: Port 142: Port 144: Port 146: Port 148: Port 150: Port 152: Port 154: Port 156: Port 158: Port 160: Port 162: Port 164: Port 166: Port 168: System Controller 170: Central Processing Unit 172: Memory 174: Support circuit 200: Processing chamber 202: Chamber body 204: Cover assembly 206:Support component 208: Vacuum pump 210: Vacuum port 212: Controller 214:Processing area 216: First Board 218: Second board 220: Third board 222: Conical chamber 226: Gas Source 228: Opening 230: Volume 232: Fourth Plate 234: Central catheter 236: Fifth Plate 238: Mixing chamber 240: Sixth Plate 242: Opening 244: Entrance 246: Entrance 248: Gas Source 250: Gas source 252: Cylindrical channel 254: Hole 256: Cylindrical channel 258: Hole 260: First gas distributor 262:Piercing 264: Barrier Plate 266: Second gas distributor 268: Gas inlet 270: substrate support 272:Substrate 274: Actuator 276: Axis 278: Lifting Pin 300: Processing chamber 302: Shell structure 304: Quartz chamber 306: Upper quartz chamber 308: lower quartz chamber 310: Processing volume 312: Gas distribution assembly 314: Export Port 316: substrate support 318:Substrate 320: vertical axis 322: Surface 324A: Lighting module 324B: Downlight module 326: Upper quartz chamber 328: Lower quartz window 330: Entrance 332:Export 334: Flow Path 336:Padding 338: Radial 340A: Gas Source 340B: Gas Source 342:IR lamp 344: Hole 346: Perforated plate 348: Channel 400:Method 410: Block 420: Block 430: Block 440: Block 450: Block 460: Block 470: Block 480: Block 500:Semiconductor Structure 502: first transistor element 504: second transistor element 506: first semiconductor region 508: Second semiconductor region 508A: Groove 510: dielectric layer 512: First Opening 514: Second opening 516:Hard Mask 518: contact layer 520: Covering layer 522: Metal layer 524: barrier metal layer 526: first contact plug 528: second contact plug X: horizontal axis Y: Far point Z: vertical axis

[0087] Domestic storage information (please note the order of storage institution, date, and number) none Overseas deposit information (please note the order of deposit country, institution, date, and number) none

Claims

1. A method for forming an electrical contact in a semiconductor structure, comprising the steps of: performing a patterning process to form a hard mask on a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening in the first semiconductor region and a second opening in the second semiconductor region, wherein the first semiconductor region includes silicon doped with an n-type dopant, the second semiconductor region includes silicon germanium doped with a p-type dopant, and wherein the hard mask covers a surface of the first semiconductor region within the first opening and exposes a surface of the second semiconductor region within the second opening; performing an etching process to form a groove at the exposed surface of the second semiconductor region within the second opening, wherein the groove has a shape to increase a contact area of ​​a contact layer; A first selective deposition process is performed to epitaxially form the contact layer on the exposed surface of the second semiconductor region within the groove and the second opening, wherein the contact layer comprises silicon germanium doped with a p-type dopant; and a second selective deposition process is performed to form a capping layer on the contact layer, wherein the etching process, the first selective deposition process, and the second selective deposition process are performed with the surface of the first semiconductor region within the first opening covered by a hard mask.

2. The method as described in claim 1, wherein the capping layer comprises a material selected from molybdenum silicide (Mo) and ruthenium silicide (Ru).

3. The method as described in claim 1 further includes the following steps: performing a pre-cleaning process on the surface of the first semiconductor region within the first opening and the surface of the second semiconductor region within the second opening prior to the patterning process.

4. The method as described in claim 1, wherein the first selective deposition process, the second selective deposition process, and the etching process are performed without disrupting the vacuum environment.

5. The method as described in claim 1, further comprising the steps of: performing a removal process after the second selective deposition process to remove the hard mask; performing a third selective deposition process to form a metal layer on the exposed surface of the first semiconductor region and the cover layer; and performing a metal filling process to form a first contact plug in the first opening and a second contact plug in the second opening.

6. The method as described in claim 5, wherein the metal layer comprises a material selected from titanium silicon (Ti), cobalt silicon (Co), nickel silicon (Ni), molybdenum silicon (Mo), and tantalum silicon (Ta).

7. A method for forming an electrical contact in a semiconductor structure, comprising the steps of: performing a pre-cleaning process on the surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening in the first semiconductor region and a second opening in the second semiconductor region, wherein the first semiconductor region includes silicon doped with an n-type dopant, and the second semiconductor region includes silicon germanium doped with a p-type dopant; performing a patterning process to form a hard mask on the semiconductor structure, wherein the hard mask covers the surface of the first semiconductor region within the first opening and exposes the surface of the second semiconductor region within the second opening; performing an etching process to form a groove at the exposed surface of the second semiconductor region within the second opening, wherein the groove has a shape to increase a contact area of ​​a contact layer; performing a first selective deposition process to epitaxially form the contact layer within the groove and on the exposed surface of the second semiconductor region within the second opening, wherein the contact layer includes silicon germanium doped with a p-type dopant; Perform a second selective deposition process to form a capping layer on the contact layer, wherein the etching process, the first selective deposition process, and the second selective deposition process are performed while the surface of the first semiconductor region within the first opening is covered by the hard mask; perform a removal process to remove the hard mask and expose the surface of the first semiconductor region within the first opening; perform a third selective deposition process to form a metal layer on the exposed surface of the first semiconductor region and the capping layer; and perform a metal filling process to form a first contact plug in the first opening and a second contact plug in the second opening.

8. The method as described in claim 7, wherein, The etching process, the first selective deposition process, and the second selective deposition process are performed without disrupting the vacuum environment.

9. The method as described in claim 7, wherein the coating layer comprises a material selected from molybdenum silicide (Mo) and ruthenium silicide (Ru).

10. The method as described in claim 7, wherein the metal layer comprises a material selected from titanium silicon (Ti), cobalt silicon (Co), nickel silicon (Ni), molybdenum silicon (Mo), and tantalum silicon (Ta).

11. A processing system, comprising: A first processing chamber; a second processing chamber; a third processing chamber; a fourth processing chamber; The system controller is configured to cause the processing system to: perform a patterning process in the first processing chamber to form a hard mask on a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region, and a dielectric layer having a first opening in the first semiconductor region and a second opening in the second semiconductor region, wherein the first semiconductor region includes silicon doped with an n-type dopant, the second semiconductor region includes silicon germanium doped with a p-type dopant, and wherein the hard mask covers a surface of the first semiconductor region within the first opening and exposes a surface of the second semiconductor region within the second opening; and perform an etching process in the second processing chamber to form a groove at the exposed surface of the second semiconductor region within the second opening, wherein the groove has a shape to increase a contact area of ​​a contact layer. A first selective deposition process is performed in the third processing chamber to epitaxially form the contact layer on the exposed surface of the second semiconductor region within the groove and the second opening, wherein the contact layer comprises silicon germanium doped with p-type dopant; and a second selective deposition process is performed in the fourth processing chamber to form a capping layer on the contact layer, wherein the etching process, the first selective deposition process, and the second selective deposition process are performed with the surface of the first semiconductor region within the first opening covered by a hard mask.

12. The processing system as claimed in claim 11, wherein the system controller is further configured to allow the processing system to transfer the semiconductor structure between the second, third, and fourth processing chambers without disrupting the vacuum environment.

13. The processing system as described in claim 11, further comprising: A fifth processing chamber, wherein the system controller is further configured to perform a pre-cleaning process in the fifth processing chamber prior to the patterning process on the surface of the first semiconductor region within the first opening and the surface of the second semiconductor region within the second opening.

14. The processing system as described in claim 13, further comprising: The sixth processing chamber; The seventh processing chamber; And an eighth processing chamber, wherein the system controller is further configured to cause the processing system to: perform a removal process in the sixth processing chamber after the second selective deposition process to remove the hard mask and expose the surface of the first semiconductor region within the first opening; and perform a third selective deposition process in the seventh processing chamber to form a metal layer on the exposed surface of the first semiconductor region and the capping layer; And perform a metal filling process in the eighth processing chamber to form a first contact plug in the first opening and a second contact plug in the second opening.

15. The processing system as claimed in claim 11, wherein the coating comprises a material selected from molybdenum silicide (Mo) and ruthenium silicide (Ru).

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