Semiconductor device and manufacturing method thereof

Abstract

This invention provides a transistor with stable electrical properties. One embodiment of this invention is a semiconductor device comprising: a first insulator formed on a substrate; a second insulator formed on the first insulator; an oxide semiconductor formed in contact with at least a portion of the top surface of the second insulator; a third insulator formed in contact with at least a portion of the top surface of the oxide semiconductor; a first conductor and a second conductor electrically connected to the oxide semiconductor; a fourth insulator formed on the third insulator; a third conductor formed on the fourth insulator with at least a portion located between the first conductor and the second conductor; and a fifth insulator formed on the third conductor, wherein the first insulator contains a halogen element.

Description

Technical Field

[0001] The present invention relates, for example, to a transistor and a semiconductor device. Furthermore, the present invention relates, for example, to a method for manufacturing a transistor and a semiconductor device. Furthermore, the present invention relates, for example, to a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a processor, and an electronic device. Furthermore, the present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, and an electronic device. Furthermore, the present invention relates to a method for driving a display device, a liquid crystal display device, a light-emitting device, a memory device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the aforementioned technical fields. The technical fields of one embodiment of the invention disclosed in this specification and other disclosures relate to an object, method, or manufacturing method. Alternatively, one embodiment of the present invention relates to a process, machine, product, or composition of matter.

[0003] Note that in this specification and other documents, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting equipment, electro-optical devices, semiconductor circuits, and electronic devices may also include semiconductor devices. Prior Art

[0004] Technology that uses semiconductors on a substrate with an insulating surface to form transistors has attracted attention. These transistors are widely used in semiconductor devices such as integrated circuits and display devices. Silicon is a well-known semiconductor that can be used in transistors.

[0005] As the semiconductor silicon used in transistors, either amorphous silicon or polycrystalline silicon is used, depending on the application. For example, when silicon is used in transistors for large-scale display devices, amorphous silicon, for which film formation technology has been established on large-area substrates, is preferred. On the other hand, when used in transistors for high-performance display devices with integrated driver circuits, polycrystalline silicon, which can produce transistors with high field-effect mobility, is preferred. Known methods for forming polycrystalline silicon include high-temperature heating or laser treatment of amorphous silicon.

[0006] In recent years, transistors using oxide semiconductors (typically In-Ga-Zn oxide) have been actively developed. Oxide semiconductors have been studied since the early days, and in 1988, crystalline In-Ga-Zn oxide, which can be used in semiconductor devices, was disclosed (see Patent Document 1). Furthermore, in 1995, a transistor using an oxide semiconductor was invented, and its electrical properties were disclosed (see Patent Document 2).

[0007] Transistors using oxide semiconductors have different characteristics from transistors using amorphous silicon and transistors using polycrystalline silicon. For example, display devices using transistors using oxide semiconductors are known to have low power consumption. Oxide semiconductors can be formed using methods such as sputtering, so they can be used to form transistors for large display devices. In addition, transistors using oxide semiconductors have high field-effect mobility, making it possible to realize high-performance display devices with integrated driver circuits. Furthermore, since some of the production equipment for transistors using amorphous silicon can be modified and reused, there is also the advantage of reducing equipment investment.

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 63-239117 [Patent Document 2] Japanese PCT International Application Translation No. 11-505377 Summary of the Invention

[0009] One object of one embodiment of the present invention is to provide a transistor having stable electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor having low leakage current in the off-state. Another object of one embodiment of the present invention is to provide a transistor having high frequency characteristics. Another object of one embodiment of the present invention is to provide a transistor having normally-off electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor having a small subthreshold swing value. Another object of one embodiment of the present invention is to provide a transistor having high reliability.

[0010] Another object of one embodiment of the present invention is to provide a semiconductor device including the above-mentioned transistor. Another object of one embodiment of the present invention is to provide a module including the semiconductor device. Another object of one embodiment of the present invention is to provide an electronic device including the semiconductor device or the module. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel module. Another object of one embodiment of the present invention is to provide a novel electronic device.

[0011] Note that the inclusion of the above-mentioned objectives does not preclude the existence of other objectives. A single embodiment of the present invention does not necessarily achieve all of the above-mentioned objectives. Furthermore, objectives other than those listed above may be apparent and derived from the description, drawings, and claims.

[0012] One embodiment of the present invention is a semiconductor device comprising a first insulator on a substrate, a second insulator on the first insulator, an oxide semiconductor in contact with at least a portion of a top surface of the second insulator, a third insulator in contact with at least a portion of the top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator on the third insulator, a third conductor on the fourth insulator and at least a portion of which is located between the first conductor and the second conductor, and a fifth insulator on the third conductor, wherein the first insulator contains a halogen element.

[0013] In addition, one embodiment of the present invention is a semiconductor device according to the above invention, further comprising a sixth insulator below the first insulator, the sixth insulator being less susceptible to hydrogen and water permeation than the first insulator.

[0014] In addition, one embodiment of the present invention is a semiconductor device according to the above invention, further comprising a fourth conductor between the sixth insulator and the first insulator, at least a portion of which overlaps with the oxide semiconductor.

[0015] In addition, one embodiment of the present invention is a semiconductor device, wherein, in the above invention, when thermal desorption spectroscopy is performed, the amount of water molecules released from the first insulator is greater than 1.0×1013 molecules / cm2 and less than 1.4×1016 molecules / cm2.

[0016] In addition, one embodiment of the present invention is a semiconductor device according to the above invention, further comprising a seventh insulator between the fourth conductor and the first insulator, wherein the seventh insulator contains hafnium.

[0017] In addition, one embodiment of the present invention is a semiconductor device, wherein, in the above invention, when performing thermal desorption spectrum analysis, the amount of water molecules released from the stacked film of the first insulator and the seventh insulator is greater than 1.0×1013 molecules / cm2 and less than 1.4×1016 molecules / cm2.

[0018] In addition, one embodiment of the present invention is a semiconductor device, wherein, in the above invention, when performing thermal desorption spectrum analysis, the amount of hydrogen molecules released from the stacked film of the first insulator and the seventh insulator is greater than 1.0×1013 molecules / cm2 and less than 1.2×1015 molecules / cm2.

[0019] Furthermore, one embodiment of the present invention is a semiconductor device, wherein in the above invention, the halogen element is one of fluorine, chlorine, and bromine.

[0020] One embodiment of the present invention can provide a transistor with stable electrical characteristics. Furthermore, one embodiment of the present invention can provide a transistor with low leakage current in the off state. Furthermore, one embodiment of the present invention can provide a transistor with high frequency characteristics. Furthermore, one embodiment of the present invention can provide a transistor with normally-off electrical characteristics. Furthermore, one embodiment of the present invention can provide a transistor with a small subthreshold swing value. Furthermore, one embodiment of the present invention can provide a transistor with high reliability.

[0021] Furthermore, one embodiment of the present invention may provide a semiconductor device including the above-described transistor. Furthermore, one embodiment of the present invention may provide a module including the semiconductor device. Furthermore, one embodiment of the present invention may provide an electronic device including the semiconductor device or the module. Furthermore, one embodiment of the present invention may provide a novel semiconductor device. Furthermore, one embodiment of the present invention may provide a novel module. Furthermore, one embodiment of the present invention may provide a novel electronic device.

[0022] Note that the description of the above effects does not preclude the existence of other effects. A single embodiment of the present invention does not necessarily achieve all of the above effects. Furthermore, effects other than those listed above may be apparent and derived from the description in the specification, drawings, patent claims, and the like. Simple diagram description

[0023] In the diagram: Figures 1A to 1D are top views and cross-sectional views of a transistor according to one embodiment of the present invention; 2A to 2E are diagrams illustrating structural analysis of CAAC-OS and a single crystal oxide semiconductor obtained by XRD, and diagrams showing selected area electron diffraction patterns of CAAC-OS; Figures 3A to 3E are cross-sectional TEM images, planar TEM images, and images obtained by analysis of CAAC-OS; 4A to 4D are diagrams showing electron diffraction patterns of nc-OS and cross-sectional TEM images of nc-OS; Figures 5A and 5B are cross-sectional TEM images of a-like OS; Figure 6 is a diagram showing changes in the crystal portion of the In-Ga-Zn oxide caused by electron irradiation; Figures 7A to 7D are cross-sectional views illustrating a transistor according to an embodiment of the present invention; Figures 8A to 8D are cross-sectional views illustrating a transistor according to an embodiment of the present invention; Figures 9A and 9B are cross-sectional views illustrating a transistor according to an embodiment of the present invention; Figures 10A to 10D are cross-sectional views illustrating a transistor according to an embodiment of the present invention; Figures 11A and 11B are cross-sectional views illustrating a transistor according to an embodiment of the present invention; Figures 12A to 12D are cross-sectional views illustrating a transistor according to an embodiment of the present invention; Figures 13A to 13H are cross-sectional views illustrating a method for manufacturing a transistor according to an embodiment of the present invention; Figures 14A to 14F are cross-sectional views illustrating a method for manufacturing a transistor according to an embodiment of the present invention; Figures 15A to 15D are cross-sectional views illustrating a method for manufacturing a transistor according to an embodiment of the present invention; Figures 16A and 16B are schematic diagrams and cross-sectional views illustrating a film-forming apparatus; Figures 17A to 17H are cross-sectional views illustrating a method for manufacturing a transistor according to an embodiment of the present invention; Figures 18A to 18F are cross-sectional views illustrating a method for manufacturing a transistor according to an embodiment of the present invention; Figures 19A to 19F are cross-sectional views illustrating a method for manufacturing a transistor according to an embodiment of the present invention; Figure 20 is a plan view showing a manufacturing apparatus according to one embodiment of the present invention; Figure 21 is a plan view showing a processing chamber according to one embodiment of the present invention; Figure 22 is a plan view showing a processing chamber according to one embodiment of the present invention; Figures 23A and 23B are circuit diagrams showing a semiconductor device according to an embodiment of the present invention; Figure 24 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figure 25 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figure 26 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figures 27A to 27C are circuit diagrams showing a memory device according to an embodiment of the present invention; Figure 28 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figure 29 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figure 30 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figure 31 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention; Figure 32 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figure 33 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figure 34 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; 35A and 35B are plan views showing a semiconductor device according to an embodiment of the present invention; 36A and 36B are block diagrams showing a semiconductor device according to an embodiment of the present invention; 37A and 37B are cross-sectional views showing a semiconductor device according to an embodiment of the present invention; 38A and 38B are cross-sectional views showing a semiconductor device according to an embodiment of the present invention; 39A1 to 39A3 and 39B1 to 39B3 are perspective views and cross-sectional views showing a semiconductor device according to an embodiment of the present invention; Figure 40 is a block diagram showing a semiconductor device according to one embodiment of the present invention; Figure 41 is a circuit diagram showing a semiconductor device according to one embodiment of the present invention; 42A to 42C are circuit diagrams, plan views, and cross-sectional views of a semiconductor device according to an embodiment of the present invention; 43A and 43B are a circuit diagram and a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figures 44A to 44F are perspective views showing an electronic device according to an embodiment of the present invention; Figures 45A to 45D are graphs showing the results of TDS analysis measured in Examples; Figures 46A to 46D are graphs showing the results of TDS analysis measured in Examples; Figures 47A to 47D are graphs showing the results of TDS analysis measured in Examples; Figure 48 is a graph showing the results of ESR measurements shown in Examples; 49A and 49B are graphs of Id-Vg characteristics measured in the embodiment; Figure 50 is a graph of the deviation of the shift measured in the embodiment; Figures 51A to 51D are charts showing the results of stress tests measured in the embodiments; Figure 52 is a graph showing the results of the deposition rate measured in Example; Figures 53A and 53B are graphs showing the amount of hydrogen molecules released calculated based on TDS analysis measured in the examples; Figures 54A and 54B are charts showing the amount of water molecules released calculated based on TDS analysis measured in the examples; Figures 55A to 55H are graphs showing the results of TDS analysis measured in Examples; Figures 56A to 56H are graphs showing the results of TDS analysis measured in Examples; Figures 57A to 57H are graphs showing the results of TDS analysis measured in Examples; Figures 58A to 58H are graphs showing the results of TDS analysis measured in Examples; 59A to 59C are graphs showing the results of SIMS measurements in Examples; 60A to 60C are graphs showing the results of SIMS measurements in Examples; 61A to 61C are graphs showing the results of XPS measurements in Examples; 62A and 62B show the conditions for ALD performed in the embodiment; 63A and 63B are graphs showing the results of TDS analysis measured in the embodiment and a graph showing the amount of water molecules released calculated based on the graph; 64A and 64B are diagrams showing TDS analysis results; Figures 65A and 65B are diagrams showing the total release amount calculated based on the TDS analysis results; 66A and 66B are diagrams showing TDS analysis results; 67A and 67B are diagrams showing TDS analysis results; 68A and 68B are diagrams showing TDS analysis results; 69A and 69B are diagrams showing TDS analysis results; Figures 70A and 70B are diagrams showing the total release amount calculated based on the TDS analysis results; Figures 71A and 71B are diagrams showing the total release amount calculated based on the TDS analysis results; Figures 72A and 72B are diagrams showing the total release amount calculated based on the TDS analysis results; Figures 73A and 73B are diagrams showing the total release amount calculated based on the TDS analysis results; 74A and 74B are diagrams illustrating the bonding state of silicon oxide; 75A to 75C are diagrams illustrating a heating process; Figure 76 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; Figure 77 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention; 78A to 78D are graphs showing the results of stress tests performed in the examples; 79A and 79B are graphs showing the results of TDS analysis measured in Examples; Figures 80A and 80B are graphs showing the results of TDS analysis measured in Examples; Figures 81A and 81B are graphs showing the results of SIMS analysis measured in Examples; Figure 82 is a graph of the results of HX-PES analysis measured in Examples; 83A to 83E are graphs of Id-Vg characteristics, threshold voltage, and Shift measured in the embodiment, and a model of the transistor used in this embodiment. Implementation Method

[0024] The embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description; those skilled in the art will readily understand that its methods and details can be modified in various forms. Furthermore, the present invention should not be construed as being limited solely to the embodiments described below. Note that when illustrating the structure of the invention using drawings, reference numerals representing the same object may be used across different drawings. In addition, the same shading pattern may be used to represent the same part without the addition of a specific reference numeral.

[0025] The structures described in the following embodiments can be appropriately applied to, combined with, or replaced with other structures described in the embodiments, and used as one embodiment of the present invention.

[0026] In the drawings, the size, thickness of films (layers), or regions may be exaggerated for easier understanding.

[0027] In this specification, the terms "film" and "layer" may be used interchangeably.

[0028] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be interchangeably referred to as potential. Generally speaking, potential (voltage) is relative and is determined by the difference from a reference potential. Therefore, even when described as "ground potential," the potential is not limited to 0V. For example, the lowest potential in a circuit may be "ground potential." Alternatively, the actual intermediate potential in a circuit may be "ground potential." In these cases, positive and negative potentials are defined relative to this potential.

[0029] Additionally, ordinal numbers such as "first" and "second" are used for convenience, but they do not indicate the order of manufacturing or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" to provide a more detailed description. Furthermore, ordinal numbers used in this specification and other documents may not always match those used to designate an embodiment of the present invention.

[0030] Note that, for example, when conductivity is sufficiently low, a substance may exhibit the properties of an "insulator" even when described as a "semiconductor." Furthermore, the distinction between "semiconductor" and "insulator" is unclear, making it difficult to accurately distinguish them. Therefore, the term "semiconductor" in this specification may sometimes be replaced with "insulator." Similarly, the term "insulator" in this specification may sometimes be replaced with "semiconductor."

[0031] Furthermore, for example, when conductivity is sufficiently high, a material may exhibit the characteristics of a "conductor" even when described as a "semiconductor." Furthermore, the distinction between "semiconductor" and "conductor" is unclear, making it difficult to accurately distinguish them. Therefore, the term "semiconductor" in this specification may sometimes be replaced with "conductor." Similarly, the term "conductor" in this specification may sometimes be replaced with "semiconductor."

[0032] Note that semiconductor impurities refer to substances other than the main components of the semiconductor. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are present, for example, DOS (Density of State) may form in the semiconductor, carrier mobility may decrease, or crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor properties include, for example, Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, especially hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. When the semiconductor is an oxide semiconductor, oxygen vacancies may sometimes be generated due to the incorporation of impurities such as hydrogen. In addition, when the semiconductor is silicon, impurities that change the semiconductor properties include, for example, oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

[0033] Note that the channel length refers to, for example, the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the channel is formed. Furthermore, the channel length of a transistor is not necessarily the same in all regions. In other words, the channel length of a transistor is not always limited to a single value. Therefore, in this specification, the channel length refers to any value, maximum value, minimum value, or average value, in the region where the channel is formed.

[0034] The channel width refers to, for example, the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is on) overlaps with the gate electrode, or the length of the portion of the region where the source and drain electrodes face each other within the region where the channel is formed. Furthermore, the channel width of a transistor is not necessarily the same across all regions. In other words, the channel width of a transistor is not always limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum value, minimum value, or average value, within the region where the channel is formed.

[0035] Furthermore, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may differ from the channel width shown in a top view of the transistor (hereinafter referred to as the apparent channel width). For example, in transistors with a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in a top view of the transistor, and this effect cannot be ignored. For example, in transistors with a miniature, three-dimensional structure, a large proportion of the channel region may be formed on the side surfaces of the semiconductor. In such cases, the effective channel width, where the channel is actually formed, may be larger than the apparent channel width shown in a top view.

[0036] In transistors with a three-dimensional structure, estimating the effective channel width through actual measurement is sometimes difficult. For example, estimating the effective channel width from the design value requires assuming the semiconductor shape is known. Therefore, accurately measuring the effective channel width is difficult when the semiconductor shape is unknown.

[0037] Therefore, in this specification, the apparent channel width, which is the length of the portion where the source and drain electrodes face each other in the region where the semiconductor and gate electrodes overlap in a top view of a transistor, may sometimes be referred to as the "surrounded channel width (SCW)." Furthermore, in this specification, simply referring to "channel width" may sometimes refer to the surrounded channel width or the apparent channel width. Alternatively, simply referring to "channel width" may sometimes refer to the effective channel width. Note that the values ​​of channel length, channel width, effective channel width, apparent channel width, and surrounded channel width can be determined by obtaining and analyzing cross-sectional TEM images, for example.

[0038] When calculating the field-effect mobility of a transistor or the current per channel width, calculations may be performed around the channel width. In such cases, the calculated values ​​may differ from those calculated using the actual channel width.

[0039] In this specification, the phrase "A has a shape in which an end portion thereof protrudes beyond an end portion thereof" may mean that, in a plan view or a cross-sectional view, at least one end portion thereof is located outside at least one end portion thereof. Thus, for example, the phrase "A has a shape in which an end portion thereof protrudes beyond an end portion thereof" may be interpreted as meaning that, in a plan view, one end portion thereof is located outside one end portion thereof.

[0040] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, this also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "substantially parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, this also includes a state where the angle is greater than 85° and less than 95°. "Substantially perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0041] In addition, in this specification, the hexagonal crystal system includes the trigonal crystal system and the rhombohedral crystal system.

[0042] Implementation Method 1 In this embodiment, the structure of a semiconductor device according to an embodiment of the present invention is described using Figures 1A to 1D, Figures 2A to 2E, Figures 3A to 3E, Figures 4A to 4D, Figures 5A and 5B, Figure 6, Figures 7A to 7D, Figures 8A to 8D, Figures 9A and 9B, Figures 10A to 10D, Figures 11A and 11B, and Figures 12A to 12D.

[0043] Transistor Structure Next, the structure of a transistor will be described as an example of a semiconductor device according to one embodiment of the present invention.

[0044] The structure of transistor 10 is described with reference to Figures 1A to 1C. Figure 1A is a top view of transistor 10. Figure 1B is a cross-sectional view corresponding to dashed line A1-A2 in Figure 1A, and Figure 1C is a cross-sectional view corresponding to dashed line A3-A4 in Figure 1A. Note that the region indicated by dashed line A1-A2 shows the structure of transistor 10 in the channel length direction, while the region indicated by dashed line A3-A4 shows the structure of transistor 10 in the channel width direction. The channel length direction of a transistor refers to the direction of carrier movement between the source (source region or source electrode) and the drain (drain region or drain electrode), and the channel width direction refers to the direction perpendicular to the channel length direction within a plane parallel to the substrate. In addition, in Figure 1A, the insulator 106a, the semiconductor 106b, and the insulator 106c can be arranged in a manner that roughly overlaps with the conductors 108a, 108b, etc., but for clarity, the insulator 106a, the semiconductor 106b, and the insulator 106c are represented by thin dotted lines in a manner that is slightly offset from the conductors 108a, 108b, etc. in the top view.

[0045] The transistor 10 includes an insulator 104 on a substrate 100, an insulator 106a on the insulator 104, a semiconductor 106b in contact with at least a portion of the top surface of the insulator 106a, an insulator 106c in contact with at least a portion of the top surface of the semiconductor 106b, a conductor 108a and a conductor 108b electrically connected to the semiconductor 106b, an insulator 112 on the insulator 106c, a conductor 114 on the insulator 112 with at least a portion thereof located between the conductors 108a and 108b, and an insulator 116 on the conductor 114.

[0046] For example, as shown in Figures 1A to 1C, the transistor 10 includes: an insulator 101, a conductor 102, an insulator 105, an insulator 103, and an insulator 104 formed on a substrate 100; an insulator 106a, a semiconductor 106b, and an insulator 106c formed on the insulator 104; conductors 108a, 108b, 110a, and 110b formed on the semiconductor 106b; an insulator 112 formed on the insulator 106c; a conductor 114 formed on the insulator 112; and an insulator 116, an insulator 118, a conductor 120a, and a conductor 120b formed on the conductor 114.

[0047] Here, the insulators 101, 103, 104, 105, 106a, 106c, 112, 116, and 118 may also be referred to as insulating films or insulating layers. Furthermore, the conductors 102, 108a, 108b, 110a, 110b, 114, 120a, and 120b may also be referred to as conductive films or conductive layers. Furthermore, the semiconductor 106b may also be referred to as a semiconductor film or semiconductor layer.

[0048] As will be explained in detail later, when insulators 106a and 106c are used alone, materials that can function as conductors, semiconductors, or insulators are sometimes used. However, when stacked with semiconductor 106b to form a transistor, electrons flow within semiconductor 106b, near the interface between semiconductor 106b and insulator 106a, and near the interface between semiconductor 106b and insulator 106c. Insulators 106a and 106c include regions that do not serve as channels for the transistor. Therefore, in this specification and other documents, insulators 106a and 106c are referred to as insulators, not conductors or semiconductors.

[0049] Conductor 102 is formed on insulator 101 formed on substrate 100. At least a portion of conductor 102 overlaps insulator 106a, semiconductor 106b, and insulator 106c. Insulator 105 is formed in contact with and covers conductor 102. Insulator 103 is formed on insulator 105, and insulator 104 is formed on insulator 103.

[0050] An insulator 106a is formed on the insulator 104, and a semiconductor 106b is formed in contact with at least a portion of the top surface of the insulator 106a. In FIG1B , the ends of the insulator 106a and the semiconductor 106b are substantially aligned, but the structure of the semiconductor device described in this embodiment is not limited to this.

[0051] Conductors 108a and 108b are formed in contact with at least a portion of the top surface of semiconductor 106b. Conductors 108a and 108b are formed separately, preferably facing each other with conductor 114 interposed therebetween as shown in FIG1A.

[0052] Insulator 106c is formed so as to contact at least a portion of the top surface of semiconductor 106b. Insulator 106c preferably contacts semiconductor 106b in a region sandwiched between conductors 108a and 108b. In FIG1B , insulator 106c is formed so as to substantially cover the top surfaces of conductors 108a and 108b. However, the structure of the semiconductor device described in this embodiment is not limited to this.

[0053] Insulator 112 is formed on insulator 106c. Conductor 114 is formed on insulator 112 so as to overlap the region between conductors 108a and 108b. In FIG1B , insulator 112 and insulator 106c are formed so that their ends substantially coincide with each other. However, the structure of the semiconductor device described in this embodiment is not limited to this.

[0054] An insulator 116 is formed on the conductor 114 and the insulator 112, and an insulator 118 is formed on the insulator 116. Conductors 120a and 120b are formed on the insulator 118. Conductors 120a and 120b are connected to conductors 108a and 108b via openings formed in the insulator 106c, the insulator 112, the insulator 116, and the insulator 118.

[0055] In addition, the conductor 114 can also be connected to the conductor 102 through an opening formed in the insulator 112, the insulator 106c, the insulator 104, the insulator 103, the insulator 105, etc.

[0056] <semiconductor> Next, the detailed structure of the semiconductor 106b will be described.

[0057] Note that in this section, in addition to the semiconductor 106b, the detailed structures of the insulator 106a and the insulator 106c are also described.

[0058] The semiconductor 106b is, for example, an oxide semiconductor containing indium. For example, when the semiconductor 106b contains indium, its carrier mobility (electron mobility) is improved. In addition, the semiconductor 106b preferably contains element M. The element M is preferably Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf. Note that the element M may sometimes be a combination of multiple elements. The element M is, for example, an element having a high bond energy with oxygen. The element M is, for example, an element having a higher bond energy with oxygen than indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. In addition, the semiconductor 106b preferably contains zinc. When the oxide semiconductor contains zinc, it may be easy to crystallize.

[0059] Note that the semiconductor 106b is not limited to an oxide semiconductor containing indium. The semiconductor 106b may be an oxide semiconductor containing zinc, gallium, or tin, such as zinc tin oxide or gallium tin oxide, which does not contain indium.

[0060] For example, the insulator 106a and the insulator 106c are oxide semiconductors containing one or more, or two or more, elements constituting the semiconductor 106b other than oxygen. Because the insulator 106a and the insulator 106c contain one or more, or two or more, elements constituting the semiconductor 106b other than oxygen, defect levels are less likely to form at the interface between the insulator 106a and the semiconductor 106b, and at the interface between the semiconductor 106b and the insulator 106c.

[0061] Insulator 106a, semiconductor 106b, and insulator 106c preferably contain at least indium. Furthermore, when insulator 106a is an In-M-Zn oxide, when the total of In and M is 100 atomic%, preferably, In is less than 50 atomic%, and M is greater than 50 atomic%, more preferably, In is less than 25 atomic%, and M is greater than 75 atomic%. Furthermore, when semiconductor 106b is an In-M-Zn oxide, when the total of In and M is 100 atomic%, preferably, In is greater than 25 atomic%, and M is less than 75 atomic%, more preferably, In is greater than 34 atomic%, and M is less than 66 atomic%. Furthermore, when insulator 106c is an In-M-Zn oxide, when the total of In and M is 100 atomic%, preferably, In is less than 50 atomic%, and M is greater than 50 atomic%, more preferably, In is less than 25 atomic%, and M is greater than 75 atomic%. Alternatively, the insulator 106c may be made of the same type of oxide as the insulator 106a. Note that the insulator 106a and / or the insulator 106c may not contain indium. For example, the insulator 106a and / or the insulator 106c may be made of gallium oxide or Ga-Zn oxide. The atomic ratios of the elements contained in the insulator 106a, semiconductor 106b, and insulator 106c may not be simple integer ratios.

[0062] For example, when a film is formed by sputtering, typical examples of the atomic ratio of the metal elements in the target material used for the insulator 106a or the insulator 106c include In:M:Zn=1:2:4, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:6:3, In:M:Zn=1:6:4, In:M:Zn=1:6:5, In:M:Zn=1:6:6, In:M:Zn=1:6:7, In:M:Zn=1:6:8, In:M:Zn=1:6:9, In:M:Zn=1:10:1, etc. Alternatively, the atomic ratio of the metal elements in the target material used for the insulator 106 a or the insulator 106 c may be M:Zn=10:1.

[0063] For example, when sputtering is used for film formation, typical examples of atomic ratios of metal elements in the target material for the semiconductor 106b include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:1.5, In:M:Zn = 2:1:2.3, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1, and In:M:Zn = 5:1:7. In particular, when the atomic ratio of In:Ga:Zn is 4:2:4.1 as a sputtering target, the atomic ratio of the formed semiconductor 106b may be close to In:Ga:Zn = 4:2:3.

[0064] Note that indium gallium oxide has a low electron affinity and high oxygen barrier properties. Therefore, the insulator 106c preferably comprises indium gallium oxide. The gallium atomic ratio [Ga / (In+Ga)] is, for example, 70% or greater, preferably 80% or greater, and more preferably 90% or greater.

[0065] For example, an oxide with a large energy gap is used as semiconductor 106b. The energy gap of semiconductor 106b is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV. Here, the energy gap of insulator 106a is larger than that of semiconductor 106b. Furthermore, the energy gap of insulator 106c is larger than that of semiconductor 106b.

[0066] Semiconductor 106b uses an oxide with a greater electron affinity than insulator 106a or insulator 106c. For example, semiconductor 106b uses an oxide whose electron affinity is greater than that of insulator 106a or insulator 106c by 0.07 eV or more and 1.3 eV or less, preferably by 0.1 eV or more and 0.7 eV or less, and more preferably by 0.15 eV or more and 0.4 eV or less. Note that electron affinity is the energy difference between the vacuum level and the conduction band bottom. In other words, the conduction band bottom energy level of insulator 106a or insulator 106c is closer to the vacuum level than the conduction band bottom energy level of semiconductor 106b.

[0067] At this time, when a gate voltage is applied, a channel is formed in the semiconductor 106b, which has the highest electron affinity among the insulator 106a, the semiconductor 106b, and the insulator 106c. Note that when a high gate voltage is applied, current may flow near the interface between the insulator 106a and the semiconductor 106b, and near the interface between the insulator 106c and the semiconductor 106b.

[0068] As described above, when used alone, insulators 106a and 106c include materials that can function as conductors, semiconductors, or insulators. However, when stacked with semiconductor 106b to form a transistor, electrons flow within semiconductor 106b, near the interface between semiconductor 106b and insulator 106a, and near the interface between semiconductor 106b and insulator 106c. Insulators 106a and 106c include regions that do not serve as channels for the transistor. Therefore, in this specification and other documents, insulators 106a and 106c are referred to as insulators, not semiconductors. Note that insulators 106a and 106c are referred to as insulators simply because they function closer to insulators in a transistor than semiconductor 106b. Therefore, materials that can function as semiconductor 106b are sometimes used as insulators 106a and 106c.

[0069] Here, a mixed region of insulator 106a and semiconductor 106b may exist between insulator 106a and semiconductor 106b. Alternatively, a mixed region of semiconductor 106b and insulator 106c may exist between semiconductor 106b and insulator 106c. The density of defect levels in this mixed region is low. Therefore, in the band structure of the stacked film of insulator 106a, semiconductor 106b, and insulator 106c, the energy at and near the interfaces between the layers changes continuously (also known as continuous junction). Note that the interfaces between insulator 106a and semiconductor 106b, and between insulator 106c and semiconductor 106b, may not be clearly distinguished.

[0070] At this point, electrons primarily move within semiconductor 106b, rather than within insulator 106a or insulator 106c. As described above, by reducing the defect level density at the interface between insulator 106a and semiconductor 106b, and the defect level density at the interface between semiconductor 106b and insulator 106c, the amount of interference with electron movement within semiconductor 106b is reduced, thereby increasing the transistor's on-state current.

[0071] Furthermore, reducing factors that hinder electron movement increases the transistor's on-state current. For example, if there are no factors hindering electron movement, electrons are expected to move efficiently. For example, if there are large physical irregularities in the channel formation region, electron movement can also be hindered.

[0072] To increase the on-state current of the transistor, for example, the root mean square (RMS) roughness of the top or bottom surface of the semiconductor 106b (the surface on which it is formed, in this case, the top surface of the insulator 106a) within a 1 μm x 1 μm area should be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Furthermore, the average surface roughness (also known as Ra) within a 1 μm x 1 μm area should be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. The maximum height difference (also known as PV) within a 1 μm x 1 μm area should be less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably less than 7 nm. RMS roughness, Ra, and PV can be measured using a scanning probe microscope, such as the SPA-500 manufactured by Seiko Nano Technology Co., Ltd.

[0073] Furthermore, to increase the on-state current of the transistor, the thickness of insulator 106c is preferably as small as possible. Preferably, the thickness of insulator 106c is smaller than that of insulator 106a and smaller than that of semiconductor 106b. For example, insulator 106c may have a thickness of less than 10 nm, preferably less than 5 nm, and more preferably less than 3 nm. On the other hand, insulator 106c has the function of preventing elements other than oxygen (hydrogen, silicon, etc.) that constitute adjacent insulators from invading semiconductor 106b, where the channel is formed. Therefore, insulator 106c preferably has a certain thickness. For example, insulator 106c may have a thickness of at least 0.3 nm, preferably at least 1 nm, and more preferably at least 2 nm.

[0074] Furthermore, to improve reliability, the insulator 106a is preferably thick. For example, the insulator 106a may have a thickness of, for example, 10 nm or greater, preferably 20 nm or greater, more preferably 40 nm or greater, and even more preferably 60 nm or greater. By making the insulator 106a thicker, the distance from the interface between adjacent insulators and the semiconductor 106b forming the channel can be increased. Note that because the productivity of semiconductor devices may decrease, the insulator 106a may have a thickness of, for example, 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less.

[0075] Silicon in oxide semiconductors can sometimes act as a carrier trap or carrier generation source. Therefore, the lower the silicon concentration in semiconductor 106b, the better. For example, a region between semiconductor 106b and insulator 106a has a silicon concentration, as measured by secondary ion mass spectrometry (SIMS), of 1×1016 atoms / cm3 or higher and 1×1019 atoms / cm3 or lower, preferably 1×1016 atoms / cm3 or higher and 5×1018 atoms / cm3 or lower, and even more preferably 1×1016 atoms / cm3 or higher and 2×1018 atoms / cm3 or lower. In addition, there is a region between the semiconductor 106b and the insulator 106c, where the silicon concentration obtained by SIMS is greater than 1×1016 atoms / cm3 and less than 1×1019 atoms / cm3, preferably greater than 1×1016 atoms / cm3 and less than 5×1018 atoms / cm3, and more preferably greater than 1×1016 atoms / cm3 and less than 2×1018 atoms / cm3.

[0076] Furthermore, to reduce the hydrogen concentration in semiconductor 106b, it is preferable to reduce the hydrogen concentration in insulators 106a and 106c. Insulators 106a and 106c have regions where the hydrogen concentration, as determined by SIMS, is 1×1016 atoms / cm3 or higher and 2×1020 atoms / cm3 or lower, preferably 1×1016 atoms / cm3 or higher and 5×1019 atoms / cm3 or lower, more preferably 1×1016 atoms / cm3 or higher and 1×1019 atoms / cm3 or lower, and even more preferably 1×1016 atoms / cm3 or higher and 5×1018 atoms / cm3 or lower. Furthermore, to reduce the nitrogen concentration in semiconductor 106b, it is preferable to reduce the nitrogen concentration in insulators 106a and 106c. Insulator 106a and insulator 106c have a region in which the nitrogen concentration obtained by SIMS is greater than 1×1015 atoms / cm3 and less than 5×1019 atoms / cm3, preferably greater than 1×1015 atoms / cm3 and less than 5×1018 atoms / cm3, more preferably greater than 1×1015 atoms / cm3 and less than 1×1018 atoms / cm3, and further preferably greater than 1×1015 atoms / cm3 and less than 5×1017 atoms / cm3.

[0077] The insulator 106a, semiconductor 106b, and insulator 106c shown in this embodiment, especially semiconductor 106b, are oxide semiconductors with low impurity concentration and low defect energy level density (few oxygen vacancies). They can also be referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have fewer carrier generation sources, the carrier density can be reduced. Therefore, a transistor in which a channel region is formed in this oxide semiconductor is less likely to have an electrical characteristic of a negative threshold voltage (also called a normally-on characteristic). Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect energy level density, they may have a low trap state density. The off-state current of high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors is significantly low. Even for an element with a channel width W of 1×106μm and a channel length L of 10μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, the off-state current can be below the measurement limit of a semiconductor parameter analyzer, that is, below 1×10-13A.

[0078] Therefore, transistors with a channel region formed in the aforementioned high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor can exhibit minimal fluctuations in electrical characteristics and high reliability. Furthermore, charges trapped in trap states in the oxide semiconductor take a long time to dissipate, sometimes acting like fixed charges. Therefore, transistors with a channel region formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, and the like.

[0079] Hydrogen contained in insulator 106a, semiconductor 106b, and insulator 106c reacts with oxygen bonded to metal atoms to produce water. Simultaneously, oxygen vacancies are formed in the crystal lattice where oxygen is released (or in the region where oxygen is released). When hydrogen enters these oxygen vacancies, electrons are sometimes generated as carriers. Alternatively, electrons are sometimes generated as carriers by some of the hydrogen bonding to oxygen bonded to metal atoms. In particular, hydrogen trapped in oxygen vacancies sometimes forms a shallow donor level in the semiconductor's band structure. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. Therefore, it is desirable to minimize the amount of hydrogen in insulator 106a, semiconductor 106b, and insulator 106c. Specifically, in the insulator 106a, the semiconductor 106b and the insulator 106c, the hydrogen concentration measured by SIMS (Secondary Ion Mass Spectrometry) is less than 2×1020 atoms / cm3, preferably less than 5×1019 atoms / cm3, more preferably less than 1×1019 atoms / cm3, more preferably less than 5×1018 atoms / cm3, more preferably less than 1×1018 atoms / cm3, more preferably less than 5×1017 atoms / cm3, and more preferably less than 1×1016 atoms / cm3.

[0080] Furthermore, when the insulator 106a, semiconductor 106b, and insulator 106c contain silicon or carbon, which is a Group 14 element, oxygen vacancies increase in the insulator 106a, semiconductor 106b, and insulator 106c, causing the oxide insulator 106a, semiconductor 106b, and insulator 106c to become n-type. Therefore, the concentration of silicon or carbon in the insulator 106a, semiconductor 106b, and insulator 106c, as well as the concentration of silicon or carbon near the interface with the insulator 106a, semiconductor 106b, and insulator 106c (measured by SIMS analysis), is 2×1018 atoms / cm3 or less, preferably 2×1017 atoms / cm3 or less.

[0081] Furthermore, the concentration of alkali metals or alkaline earth metals in the insulator 106a, semiconductor 106b, and insulator 106c, as measured by SIMS analysis, is 1×1018 atoms / cm3 or less, preferably 2×1016 atoms / cm3 or less. When alkali metals or alkaline earth metals bond with oxide semiconductors, carriers are sometimes generated, increasing the off-state current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the insulator 106a, semiconductor 106b, and insulator 106c.

[0082] When nitrogen is contained in the insulator 106a, the semiconductor 106b, and the insulator 106c, electrons acting as carriers are generated, increasing the carrier density and facilitating n-type conversion. As a result, transistors using oxide semiconductor films containing nitrogen tend to exhibit normally-on characteristics. Therefore, it is desirable to minimize the amount of nitrogen in the oxide semiconductor film. For example, the nitrogen concentration measured by SIMS analysis is preferably 5×1018 atoms / cm3 or less.

[0083] FIG1D shows an enlarged cross-sectional view of the center and vicinity of the center of the insulator 106a and semiconductor 106b. As shown in FIG1B and FIG1D , low-resistance regions 109a and 109b may be formed in the region of the semiconductor 106b or insulator 106c that contacts the conductor 108a or 108b (indicated by dashed lines in FIG1B and FIG1D ). Low-resistance regions 109a and 109b are primarily formed by oxygen being extracted from the semiconductor 106b by the conductor 108a or 108b in contact with the semiconductor 106b, or by the conductive material contained in the conductor 108a or 108b bonding with elements in the semiconductor 106b. The formation of these low-resistance regions 109a and 109b reduces the contact resistance between the conductor 108a or 108b and the semiconductor 106b, thereby increasing the on-state current of the transistor 10.

[0084] Although not shown, a low-resistance region may also be formed in the region where the insulator 106a contacts the conductor 108a or the conductor 108b. In the following figures, the low-resistance region is also indicated by the same dotted line.

[0085] Furthermore, as shown in FIG1D , semiconductor 106b may include a region between conductors 108a and 108b that is thinner than the region overlapping conductors 108a and 108b. This region is formed by removing a portion of the top surface of semiconductor 106b when forming conductors 108a and 108b. When the conductors that will become conductors 108a and 108b are formed on the top surface of semiconductor 106b, a low-resistance region similar to low-resistance regions 109a and 109b may be formed. By removing the region between conductors 108a and 108b on the top surface of semiconductor 106b in this way, a channel can be prevented from forming in the low-resistance region on the top surface of semiconductor 106b. Furthermore, in the following figures, even if the thinner region is not shown in enlarged views, similar thinner regions may be formed.

[0086] The three-layer structure of the insulator 106a, semiconductor 106b, and insulator 106c described above is an example. For example, a two-layer structure may be employed without either the insulator 106a or the insulator 106c. Alternatively, a single-layer structure may be employed without either the insulator 106a or the insulator 106c. Furthermore, an n-layer structure (n is an integer greater than or equal to 4) may be employed that includes one or more layers in addition to the insulator 106a, semiconductor 106b, and insulator 106c. This additional layer may be made of a material that can be used for any of the insulator 106a, semiconductor 106b, and insulator 106c.

[0087] <Structure of Oxide Semiconductor> The structure of the oxide semiconductor is described below.

[0088] Oxide semiconductors are classified into single-crystalline oxide semiconductors and non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0089] From another perspective, oxide semiconductors are classified into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0090] Generally speaking, amorphous structures have the following characteristics: they are isotropic rather than inhomogeneous; they are in a metastable state and the atomic configuration is not fixed; the bond angles are not fixed; they have short-range order rather than long-range order; etc.

[0091] From a different perspective, a stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Furthermore, an oxide semiconductor that lacks isotropy (for example, possesses a periodic structure within a small region) cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like oxide semiconductors lack isotropy and possess an unstable structure with voids. In this instability, a-like oxide semiconductors are physically closer to amorphous oxide semiconductors.

[0092] CAAC-OS First, let’s explain CAAC-OS.

[0093] CAAC-OS is a type of oxide semiconductor including a plurality of c-axis aligned crystal parts (also referred to as grains).

[0094] The following describes the analysis of CAAC-OS using an X-ray diffraction (XRD) device. For example, when analyzing the structure of CAAC-OS containing InGaZnO4 crystals classified as space group R-3m using the out-of-plane method, a peak appears near a diffraction angle (2θ) of 31°, as shown in Figure 2A. This peak originates from the (009) plane of the InGaZnO4 crystals, confirming that the crystals in CAAC-OS have a c-axis orientation, with the c-axis oriented approximately perpendicular to the plane (also called the formed surface) or top surface of the film forming the CAAC-OS. Note that in addition to the peak near 2θ of 31°, a peak may also appear near 2θ of 36°. The peak near 2θ of 36° originates from a crystal structure classified as space group Fd-3m. Therefore, it is preferable that this peak not appear in CAAC-OS.

[0095] On the other hand, when the structure of CAAC-OS is analyzed using the in-plane method, in which X-rays are incident on the sample from a direction parallel to the formed surface, a peak appears at 2θ of approximately 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. Furthermore, even when 2θ is fixed at approximately 56° and the sample is rotated about the normal vector to the sample surface (Φ axis) (Φ scan), no clear peak is observed, as shown in Figure 2B. On the other hand, when Φ scan is performed on single crystal InGaZnO4 with 2θ fixed at approximately 56°, six peaks originating from crystal planes equivalent to the (110) plane are observed, as shown in Figure 2C. Therefore, structural analysis using XRD confirms that there is no regularity in the orientation of the a-axis and b-axis in CAAC-OS.

[0096] Next, we will describe CAAC-OS analyzed using electron diffraction. For example, when an electron beam with a beam diameter of 300 nm is incident on a CAAC-OS containing InGaZnO4 crystals in a direction parallel to the surface on which the CAAC-OS is formed, the diffraction pattern shown in Figure 2D (also called a selected electron diffraction pattern) may appear. This diffraction pattern includes spots originating from the (009) plane of the InGaZnO4 crystals. Therefore, electron diffraction also shows that the particles contained in the CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction roughly perpendicular to the formed surface or top surface. On the other hand, Figure 2E shows the diffraction pattern when an electron beam with a beam diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is observed in Figure 2E. Therefore, electron diffraction using an electron beam with a beam diameter of 300 nm also shows that the a-axis and b-axis of the particles contained in the CAAC-OS have no orientation. The first ring in FIG2E is considered to originate from the (010) and (100) planes of the InGaZnO4 crystal, etc. The second ring in FIG2E is considered to originate from the (110) plane, etc.

[0097] Furthermore, in a composite analysis image (also known as a high-resolution TEM image) of CAAC-OS obtained using a transmission electron microscope (TEM) and a bright-field image of the diffraction pattern, multiple particles can be observed. However, even in high-resolution TEM images, clear boundaries between particles, known as grain boundaries, are sometimes not visible. Therefore, it can be said that CAAC-OS is less susceptible to the reduction in electron mobility caused by grain boundaries.

[0098] Figure 3A shows a high-resolution TEM image of a CAAC-OS cross section, obtained from a direction roughly parallel to the sample surface. High-resolution TEM images are obtained using the spherical aberration corrector function. High-resolution TEM images obtained using the spherical aberration corrector function are particularly referred to as Cs-corrected high-resolution TEM images. For example, Cs-corrected high-resolution TEM images can be observed using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by JEOL Ltd.

[0099] Figure 3A shows particles in which metal atoms are arranged in layers. The size of each particle is found to be greater than 1 nm or greater than 3 nm. Therefore, the particles can also be referred to as nanocrystals (nc). Alternatively, CAAC-OS can be referred to as an oxide semiconductor with CANC (C-Axis Aligned nanocrystals). The particles reflect the unevenness of the surface or top surface of the CAAC-OS and are parallel to the surface or top surface of the CAAC-OS.

[0100] In addition, Figures 3B and 3C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS, obtained by observing it from a direction approximately perpendicular to the sample surface. Figures 3D and 3E are images obtained by performing image processing on Figures 3B and 3C. The image processing method is described below. First, a Fast Fourier Transform (FFT) is performed on Figure 3B to obtain an FFT image. Next, a mask is performed to retain the range of 2.8 nm-1 to 5.0 nm-1 from the origin in the obtained FFT image. Next, an Inverse Fast Fourier Transform (IFFT) is performed on the masked FFT image to obtain a processed image. The obtained image is referred to as an FFT filtered image. The FFT filtered image is an image obtained by extracting the periodic component from the Cs-corrected high-resolution TEM image, which shows the lattice arrangement.

[0101] In Figure 3D, the dotted lines indicate areas where the lattice arrangement is disrupted. The area enclosed by the dotted lines represents a single particle. Furthermore, the dotted lines represent the connection between particles. The dotted lines represent hexagons, indicating that the particles are hexagonal. Note that the shape of particles is not limited to a regular hexagon; non-regular hexagons are common.

[0102] In Figure 3E, dotted lines indicate the area between regions with consistent lattice arrangement and other regions with consistent lattice arrangement, and dashed lines indicate the direction of the lattice arrangement. Clear grain boundaries cannot be identified near the dotted lines. When lattice points around a lattice point near the dotted lines are connected, distorted hexagons, pentagons, and / or heptagons can form. This indicates that distorting the lattice arrangement can suppress the formation of grain boundaries. This is likely because CAAC-OS tolerates distortion caused by factors such as low density of atomic arrangement in the ab plane and changes in interatomic bond distances due to substitution of metal elements.

[0103] As shown above, CAAC-OS has c-axis alignment, with its multiple particles (nanocrystals) linked in the ab-plane direction, resulting in a distorted crystal structure. Therefore, CAAC-OS can also be referred to as an oxide semiconductor with CAA crystals (c-axis-aligned ab-plane-anchored crystals).

[0104] CAAC-OS is a highly crystalline oxide semiconductor. Because the crystallinity of oxide semiconductors can sometimes be reduced by the incorporation of impurities or the formation of defects, CAAC-OS is an oxide semiconductor with low levels of impurities and defects (such as oxygen vacancies).

[0105] Impurities refer to elements other than the main components of an oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, elements such as silicon, which have a stronger bond with oxygen than the metal elements that make up the oxide semiconductor, can remove oxygen from the oxide semiconductor, disrupting the atomic arrangement of the oxide semiconductor and reducing its crystallinity. Furthermore, heavy metals such as iron and nickel, argon, and carbon dioxide, due to their large atomic radii (or molecular radii), can disrupt the atomic arrangement of the oxide semiconductor, reducing its crystallinity.

[0106] When an oxide semiconductor contains impurities or defects, its properties may fluctuate due to exposure to light, heat, or other factors. Impurities contained in an oxide semiconductor may act as carrier traps or carrier generators. Furthermore, oxygen vacancies in an oxide semiconductor may act as carrier traps or carrier generators by trapping hydrogen.

[0107] CAAC-OS, with its low impurity and oxygen vacancy levels, is an oxide semiconductor with a low carrier density. Specifically, oxide semiconductors with a carrier density of less than 8×10⁻¹ / cm³, preferably less than 1×10⁻¹ / cm³, and more preferably less than 1×10⁻¹ / cm³, and at least 1×10⁻¹ / cm³, can be used. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has a low impurity concentration and defect level density. In other words, CAAC-OS can be said to be an oxide semiconductor with stable characteristics.

[0108] nc-OS Next, nc-OS is explained.

[0109] The following describes the analysis of nc-OS using XRD. For example, when analyzing the structure of nc-OS using the out-of-plane method, no peak indicating orientation appears. In other words, the nc-OS crystals do not have orientation.

[0110] For example, when an nc-OS composed of InGaZnO4 crystals is thinned and an electron beam with a beam diameter of 50 nm is incident on a region with a thickness of 34 nm in a direction parallel to the formed surface, a ring-shaped diffraction pattern (nanobeam electron diffraction pattern) is observed as shown in Figure 4A. Furthermore, Figure 4B shows the diffraction pattern (nanobeam electron diffraction pattern) when an electron beam with a beam diameter of 1 nm is incident on the same sample. Multiple spots are observed within the ring-shaped region in Figure 4B. Therefore, while order is not observed in the nc-OS when an electron beam with a beam diameter of 50 nm is incident, order is confirmed when an electron beam with a beam diameter of 1 nm is incident.

[0111] Furthermore, when an electron beam with a beam diameter of 1 nm is incident on an area less than 10 nm thick, an electron diffraction pattern with spots arranged in a quasi-regular hexagonal pattern is sometimes observed, as shown in Figure 4C. This suggests that nc-OS contains highly ordered regions, or crystals, within a thickness less than 10 nm. Note that because the crystals are oriented in various directions, there are also regions where no regular electron diffraction pattern is observed.

[0112] FIG4D shows a Cs-corrected high-resolution TEM image of a cross section of nc-OS observed from a direction roughly parallel to the formed surface. In the high-resolution TEM image of nc-OS, there are regions where crystals can be observed, as shown by the auxiliary lines, and regions where no clear crystals can be observed. The size of the crystals contained in nc-OS is greater than 1 nm and less than 10 nm, and in particular, most are greater than 1 nm and less than 3 nm. Note that oxide semiconductors whose crystals are greater than 10 nm and less than 100 nm are sometimes referred to as microcrystalline oxide semiconductors. For example, in the high-resolution TEM image of nc-OS, grain boundaries are sometimes not clearly observed. Note that the source of the nanocrystals may be the same as the particles in CAAC-OS. Therefore, the crystals of nc-OS are sometimes referred to as particles below.

[0113] Thus, in nc-OS, the atomic arrangement within tiny regions (e.g., regions between 1 nm and 10 nm, and particularly between 1 nm and 3 nm) exhibits periodicity. Furthermore, in nc-OS, no regularity in crystal orientation is observed between different particles. Consequently, no orientation is observed across the entire film. Consequently, nc-OS can sometimes be indistinguishable from a-like OS or amorphous oxide semiconductors using certain analytical methods.

[0114] In addition, since there is no regularity in the crystal orientation between particles (nanocrystals), nc-OS can also be called an oxide semiconductor containing RANC (Random Aligned nanocrystals) or an oxide semiconductor containing NANC (Non-Aligned nanocrystals).

[0115] nc-OS is an oxide semiconductor with a higher regularity than amorphous oxide semiconductors. Therefore, the defect level density of nc-OS is lower than that of a-like OS or amorphous oxide semiconductors. However, regularity in crystal orientation is not observed between different particles in nc-OS. Therefore, the defect level density of nc-OS is higher than that of CAAC-OS.

[0116] a-like OS An a-like OS is an oxide semiconductor having a structure between an nc-OS and an amorphous oxide semiconductor.

[0117] Figures 5A and 5B show high-resolution cross-sectional TEM images of the a-like OS. Figure 5A shows a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. Figure 5B shows a high-resolution cross-sectional TEM image of the a-like OS after irradiation with 4.3×10⁻⁻ e⁻ / nm² of electrons (e⁻). Figures 5A and 5B show that the a-like OS is observed as a stripe-shaped bright region extending in the longitudinal direction from the start of electron irradiation. Furthermore, the shape of the bright region changes after electron irradiation. The bright region is estimated to be a void or low-density region.

[0118] Because a-like OS contains voids, its structure is unstable. To demonstrate its structural instability compared to CAAC-OS and nc-OS, the structural changes induced by electron irradiation are shown below.

[0119] As samples, a-like OS, nc-OS, and CAAC-OS were prepared. Each sample was made of In-Ga-Zn oxide.

[0120] First, high-resolution cross-sectional TEM images of each sample were obtained. High-resolution cross-sectional TEM images revealed that each sample had a crystalline portion.

[0121] It is known that the unit cell of an InGaZnO4 crystal has a structure consisting of three In-O layers and six Ga-Zn-O layers, totaling nine layers stacked in a layered pattern along the c-axis. The spacing between these adjacent layers is nearly equal to the lattice surface spacing of the (009) plane (also known as the d value), which was determined to be 0.29 nm from crystal structure analysis. Therefore, the portion where the lattice fringes are spaced between 0.28 nm and 0.30 nm can be considered an InGaZnO4 crystal portion. These lattice fringes correspond to the ab planes of the InGaZnO4 crystal.

[0122] Figure 6 shows an example of the average size of the crystal parts (22 to 30 locations) for each sample. Note that the crystal part size corresponds to the length of the lattice fringes described above. Figure 6 shows that in a-like OS, the crystal part gradually increases in size depending on the cumulative electron irradiation dose used to obtain TEM images. Figure 6 shows that the crystal part (also called the initial crystal nucleus), which was initially approximately 1.2 nm in size when observed using TEM, grew to approximately 1.9 nm at a cumulative electron (e-) irradiation dose of 4.2×108 e- / nm2. On the other hand, the crystal part size of nc-OS and CAAC-OS remained unchanged from the start of electron irradiation to a cumulative electron irradiation dose of 4.2×108 e- / nm2. Figure 6 shows that the crystal part size of nc-OS and CAAC-OS remained approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron irradiation dose. Electron beam irradiation and TEM observations were performed using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were as follows: the acceleration voltage was 300 kV; the current density was 6.7×105 e- / (nm2.s), and the diameter of the irradiated area was 230 nm.

[0123] Thus, electron irradiation sometimes causes crystal growth in a-like OS. On the other hand, nc-OS and CAAC-OS show little crystal growth in response to electron irradiation. This suggests that a-like OS has an unstable structure compared to CAAC-OS and nc-OS.

[0124] Furthermore, because a-like OS contains voids, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or higher and less than 92.3% of that of a single-crystalline oxide semiconductor with the same composition. The density of nc-OS and CAAC-OS is 92.3% or higher and less than 100% of that of a single-crystalline oxide semiconductor with the same composition. Note that it is difficult to form an oxide semiconductor with a density less than 78% of that of a single-crystalline oxide semiconductor.

[0125] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of single-crystalline InGaZnO4 with a rhombohedral structure is 6.357 g / cm3. Therefore, for example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of a-like OS is 5.0 g / cm3 or higher and less than 5.9 g / cm3. Furthermore, for example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of nc-OS and CAAC-OS is 5.9 g / cm3 or higher and less than 6.3 g / cm3.

[0126] Note that when single-crystalline oxide semiconductors of the same composition do not exist, the density of a single-crystalline oxide semiconductor corresponding to a desired composition can be estimated by combining single-crystalline oxide semiconductors of different compositions in arbitrary ratios. The density of a single-crystalline oxide semiconductor corresponding to a desired composition can be estimated using a weighted average based on the ratio of the combined single-crystalline oxide semiconductors of different compositions. Note that it is preferable to estimate the density using as few types of combined single-crystalline oxide semiconductors as possible.

[0127] As described above, oxide semiconductors have various structures and various characteristics. Note that the oxide semiconductor may be, for example, a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, a nc-OS, and a CAAC-OS.

[0128] <Substrate, insulator, conductor> Next, each component other than the semiconductor of the transistor 10 will be described in detail.

[0129] Substrate 100 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttrium-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include single-material semiconductor substrates made of silicon or germanium, or semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having an insulating region within these semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates containing metal nitrides and metal oxides. Furthermore, there are insulating substrates provided with conductors or semiconductors, semiconductor substrates provided with conductors or insulators, and conductive substrates provided with semiconductors or insulators. Alternatively, substrates with components provided on these substrates may be used. Components provided on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0130] Alternatively, a flexible substrate capable of withstanding the heat treatment required to manufacture transistors can be used as substrate 100. Another method for placing a transistor on a flexible substrate is to form a transistor on a non-flexible substrate, then peel the transistor off and transfer it to substrate 100, which is a flexible substrate. In this case, a peeling layer is preferably provided between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil containing fibers can be used as substrate 100. Substrate 100 can also be stretchable. Furthermore, substrate 100 can have the property of returning to its original shape upon cessation of bending or stretching. Alternatively, it can have the property of not returning to its original shape. The thickness of substrate 100 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. By making substrate 100 thin, the semiconductor device can be made lighter. Furthermore, by making the substrate 100 thin, even when using glass or other materials, it can exhibit stretchability or return to its original shape after bending or stretching. This can mitigate shock to the semiconductor device on the substrate 100 caused by dropping or the like. This allows for a highly durable semiconductor device.

[0131] For example, the flexible substrate 100 can be made of metal, alloy, resin, glass, or fiber. A lower linear expansion coefficient for the flexible substrate 100 is preferred, as deformation due to the environment is more suppressed. For example, the flexible substrate 100 can be made of a material with a linear expansion coefficient of 1×10-3 / K or less, 5×10-5 / K or less, or 1×10-5 / K or less. Examples of resins include polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, and acrylic resin. Aromatic polyamide, in particular, has a low linear expansion coefficient and is therefore suitable for the flexible substrate 100.

[0132] An insulator 101 that blocks hydrogen or water is used. Hydrogen or water in the insulators located near insulator 106a, semiconductor 106b, and insulator 106c may contribute to carrier generation in insulator 106a, semiconductor 106b, and insulator 106c, which also function as oxide semiconductors. This may reduce the reliability of transistor 10. In particular, when a substrate 100 containing a silicon-based semiconductor element such as a switching element is used, hydrogen is used to terminate dangling bonds in the semiconductor element, and this hydrogen may diffuse into transistor 10. In contrast, by providing insulator 101 that blocks hydrogen or water, the diffusion of hydrogen or water from below transistor 10 can be suppressed, thereby improving the reliability of transistor 10. Insulator 101 is preferably less permeable to hydrogen or water than insulator 105 or insulator 104.

[0133] The insulator 101 preferably also has a function of blocking oxygen. By having the insulator 101 block oxygen diffusing from the insulator 104, oxygen can be efficiently supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c.

[0134] For example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride can be used as the insulator 101. By using these materials to form the insulator 101, the insulator 101 can function as an insulating film that effectively blocks the diffusion of oxygen, hydrogen, or water. Alternatively, silicon nitride or silicon oxynitride can be used as the insulator 101. By using these materials to form the insulator 101, the insulator 101 can function as an insulating film that effectively blocks the diffusion of hydrogen or water. In this specification, "silicon oxynitride" refers to a substance whose composition contains more nitrogen than oxygen, while "silicon oxynitride" refers to a substance whose composition contains more oxygen than nitrogen.

[0135] Preferably, at least a portion of conductor 102 overlaps semiconductor 106b in the region sandwiched between conductors 108a and 108b. Conductor 102 serves as the back gate of transistor 10. Providing such conductor 102 allows for control of the threshold voltage of transistor 10. Controlling the threshold voltage prevents transistor 10 from being turned on when the voltage applied to the gate (conductor 114) of transistor 10 is low, for example, below 0V. This makes it easier to shift the electrical characteristics of transistor 10 toward the normally-off state.

[0136] As the conductor 102, for example, a single layer or a stack of conductors containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten can be used. For example, alloys or compounds can be used, and conductors containing aluminum, copper and titanium, copper and manganese, indium, tin, and oxygen, or titanium and nitrogen can also be used.

[0137] The insulator 105 is provided so as to cover the conductor 102. As the insulator 105, the same insulator as the insulator 104 or the insulator 112 described later can be used.

[0138] Insulator 103 is provided to cover insulator 105. Insulator 103 preferably has an oxygen barrier function. Providing such insulator 103 prevents conductor 102 from extracting oxygen from insulator 104. This effectively supplies oxygen from insulator 104 to insulator 106a, semiconductor 106b, and insulator 106c. Furthermore, by improving the coverage of insulator 103, oxygen extraction from insulator 104 can be further reduced, enabling efficient oxygen supply from insulator 104 to insulator 106a, semiconductor 106b, and insulator 106c.

[0139] An oxide or nitride containing boron, aluminum, silicon, scandium, titanium, gallium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, hafnium, or thallium is used as the insulator 103. Preferably, hafnium oxide or aluminum oxide is used.

[0140] Of insulator 105, insulator 103, and insulator 104, insulator 103 preferably has an electron-trapping region. When insulators 105 and 104 suppress electron release, the electrons trapped in insulator 103 behave like fixed negative charges. Therefore, injecting electrons into insulator 103 can change the threshold voltage of transistor 10. Electrons can be injected into insulator 103 by applying a positive or negative potential to conductor 102.

[0141] Furthermore, the amount of electron injection can be adjusted by the duration of application of a potential to the conductor 102 and / or the applied potential. Therefore, the potential applied to the conductor 102 to achieve a desired threshold voltage of the transistor can be a potential at which a tunneling current flows through the insulator 105, for example, a potential of 20 V to 60 V, preferably 24 V to 50 V, and more preferably 30 V to 45 V. The duration of application of the potential is, for example, in the range of 0.1 seconds to 20 seconds, and preferably 0.2 seconds to 10 seconds.

[0142] Furthermore, it is preferred that the amount of hydrogen or water contained in insulator 103 be low. For example, in thermal desorption spectroscopy (TDS) analysis at a surface temperature range of 100°C to 700°C or 100°C to 500°C, the amount of water molecules released from insulator 103 is 1.0×1013 molecules / cm2 or higher and 1.0×1016 molecules / cm2 or lower, preferably 1.0×1013 molecules / cm2 or higher and 3.0×1015 molecules / cm2 or lower. The method for measuring the amount of released molecules using TDS analysis will be described in detail later.

[0143] The insulator 104 preferably contains a low amount of water or hydrogen in the film. Furthermore, the insulator 104 preferably contains an excess of oxygen. For example, a single layer or a stack of layers of an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used as the insulator 104. For example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide can be used as the insulator 104. Silicon oxide or silicon oxynitride is preferably used as the insulator 104.

[0144] The amount of water or hydrogen contained in the insulator 104 is preferably small. For example, in a TDS analysis at a surface temperature range of 100°C to 700°C or 100°C to 500°C, the amount of water molecules released from the insulator 104 is 1.0×1013 molecules / cm2 or more and 1.4×1016 molecules / cm2 or less, preferably 1.0×1013 molecules / cm2 or more and 4.0×1015 molecules / cm2 or less, and more preferably 1.0×1013 molecules / cm2 or more and 2.0×1015 molecules / cm2 or less. Furthermore, in TDS analysis, the amount of hydrogen molecules released within the surface temperature range of 100°C to 700°C or 100°C to 500°C is 1.0×1013 molecules / cm2 or higher and 1.2×1015 molecules / cm2 or lower, preferably 1.0×1013 molecules / cm2 or higher and 9.0×1014 molecules / cm2 or lower. Note that the method for measuring the amount of released molecules using TDS analysis will be described in detail later.

[0145] The above results indicate that impurities such as water and hydrogen form defect levels in the insulator 106a, semiconductor 106b, and insulator 106c, particularly in semiconductor 106b, causing fluctuations in the transistor's electrical characteristics. Therefore, by reducing the amount of water or hydrogen in the insulator 104 disposed beneath the insulators 106a, semiconductor 106b, and insulator 106c, the supply of water, hydrogen, and the like from the insulator 104 to the semiconductor 106b and the like, which creates defect levels, can be reduced. By using an oxide semiconductor with such a reduced defect level density, a transistor with stable electrical characteristics can be provided.

[0146] As will be described in detail later, heat treatment is required for dehydration, dehydrogenation, and the reduction of oxygen vacancies in insulator 104, insulator 106a, semiconductor 106b, and insulator 106c. However, high-temperature heat treatment can degrade the layers beneath insulator 104. In particular, when transistor 10, as described in this embodiment, is stacked on a semiconductor element layer (e.g., silicon) that is an active layer other than semiconductor 106b, the heat treatment can damage or degrade the various elements and wiring included in the semiconductor element layer.

[0147] For example, when forming a semiconductor device layer on a silicon substrate, miniaturization of the devices requires reducing the resistance of each device. To reduce resistance, for example, low-resistivity Cu wiring can be used as the wiring material, or nickel silicide can be provided in the source and drain regions of the transistor to form these regions. However, both Cu wiring and nickel silicide have low heat resistance. For example, high-temperature heating of Cu wiring can lead to degradation such as the formation of voids or hillocks, or Cu diffusion. Furthermore, high-temperature heating of nickel silicide can expand the silicide region, causing degradation such as short circuits in the source and drain regions of the transistor.

[0148] Therefore, the aforementioned heat treatment needs to be performed within a temperature range that does not degrade the underlying semiconductor element layer. However, if the insulator 104 contains a large amount of water or hydrogen when it is formed, even if the heat treatment is performed within a temperature range that does not degrade the underlying semiconductor element layer, the water, hydrogen, etc. cannot be fully removed from the insulator 104. Furthermore, if the insulator 106a, semiconductor 106b, and insulator 106c are heat treated within the same temperature range after formation, water, hydrogen, etc. may be supplied from the insulator 104 to the semiconductor 106b, etc., resulting in the formation of defect levels.

[0149] In contrast, because the water and hydrogen content of the insulator 104 described in this embodiment is reduced as described above, heating at a relatively low temperature (e.g., within a temperature range of approximately 350°C to 445°C) can sufficiently remove water, hydrogen, and the like. Furthermore, even after forming the insulator 106a, semiconductor 106b, and insulator 106c, heat treatment within the same temperature range can be performed. Because the water, hydrogen, and other contents of the insulator 104 are sufficiently reduced, the formation of defect states in the semiconductor 106b and the like can be suppressed.

[0150] The insulator 104 is preferably formed using a PECVD method, which produces high-quality films at relatively low temperatures. However, when forming a silicon oxide film, for example, using PECVD, silicon hydride is often used as a source gas, so hydrogen, water, or the like is introduced into the insulator 104 during film formation. Therefore, when forming the insulator 104 described in this embodiment, a silicon halide is preferably used as a source gas. Examples of silicon halides that can be used include SiF4 (silicon tetrafluoride), SiCl4 (silicon tetrachloride), SiHCl3 (silicon trichloride), SiH2Cl2 (dichlorosilane), and SiBr4 (silicon tetrabromide).

[0151] When forming insulator 104, using a silicon halide as a source gas may cause halogen to be contained in insulator 104. Furthermore, components of insulator 104 may form covalent bonds with the halogen. For example, when forming insulator 104 using SiF4 as a source gas, fluorine may be contained in insulator 104, forming Si-F covalent bonds. Insulator 104 containing SiF covalent bonds may have a spectral peak within the range of 685.4 eV to 687.5 eV, as evaluated by X-ray photoelectron spectroscopy (XPS).

[0152] Furthermore, when using silicon halide as a source gas when forming insulator 104, silicon hydride can be added in addition to the silicon halide. This can further reduce the hydrogen and water content in insulator 104 compared to using only silicon hydride as a source gas, and can further increase the deposition rate compared to using only silicon halide as a source gas. For example, SiF4 and SiH4 can be used as source gases to form insulator 104. The flow rate ratio of SiF4 and SiH4 is appropriately set based on the water and hydrogen content in insulator 104 and the deposition rate. The method for forming insulator 104 will be described in detail later.

[0153] Furthermore, it is preferable that the water or hydrogen content in the stacked film of insulators provided between insulator 101 and insulator 106a (in this embodiment, the stacked film of insulators 105, 103, and 104) other than insulator 104 is low. As described above, when insulator 101 is used as an insulator having a water and hydrogen barrier function, the water and hydrogen supplied to the oxide when forming the insulator 106a or semiconductor 106b are contained in insulators 105, 103, and 104. Therefore, if the water or hydrogen content in the stacked film of insulators 105, 103, and 104 is sufficiently low when forming the oxide of insulator 106a or semiconductor 106b, the water or hydrogen supplied to insulator 106a or semiconductor 106b can be reduced.

[0154] For example, in a TDS analysis of the laminated film of insulator 105, insulator 103, and insulator 104 at a surface temperature range of 100°C to 700°C or 100°C to 500°C, the amount of water molecules released is greater than 1.0×1013 molecules / cm2 and less than 1.4×1016 molecules / cm2, preferably greater than 1.0×1013 molecules / cm2 and less than 4.0×1015 molecules / cm2, and more preferably greater than 1.0×1013 molecules / cm2 and less than 2.0×1015 molecules / cm2. Furthermore, in TDS analysis, the amount of hydrogen molecules released within the surface temperature range of 100°C to 700°C or 100°C to 500°C is 1.0×1013 molecules / cm2 or higher and 1.2×1015 molecules / cm2 or lower, preferably 1.0×1013 molecules / cm2 or higher and 9.0×1014 molecules / cm2 or lower. Note that the method for measuring the amount of released molecules using TDS analysis will be described in detail later.

[0155] Furthermore, this insulator with reduced water or hydrogen content can be used for other insulators, not just insulator 104. For example, an insulator with reduced water or hydrogen content can be used for insulator 105 as well as insulators 112 and 118, described later. Furthermore, as long as it satisfies the barrier properties to hydrogen or water, an insulator with reduced water or hydrogen content can be used for insulators 101, 116, and the like. Furthermore, when a semiconductor device layer or wiring layer is provided below insulator 101, this insulator can be used as an interlayer insulating film between the semiconductor device layer and the wiring layer. Furthermore, when a semiconductor device layer or wiring layer is provided above insulator 118, this insulator can be used as an interlayer insulating film between insulator 118 and the semiconductor device layer or wiring layer.

[0156] Furthermore, the insulator 104 is preferably an insulator containing excess oxygen. Providing such an insulator 104 allows oxygen to be supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c. This oxygen can reduce oxygen vacancies in the oxide semiconductors of the insulators 106a, the semiconductor 106b, and the insulator 106c. Consequently, the insulators 106a, the semiconductor 106b, and the insulator 106c can be made into oxide semiconductors having a low defect level density and stable properties.

[0157] Note that in this specification and other documents, excess oxygen refers to, for example, oxygen exceeding the stoichiometric composition. Alternatively, excess oxygen refers to oxygen released from a film or layer containing this excess oxygen, for example, by heating. Excess oxygen can migrate within the film or layer. This migration of excess oxygen includes both migration between atoms in the film or layer and migration of the excess oxygen atoms one by one, replacing them with oxygen constituents of the film or layer.

[0158] In the TDS analysis with a surface temperature range of 100°C to 700°C or 100°C to 500°C, the amount of oxygen molecules released from the insulator 104 containing excess oxygen is greater than 1.0×1014 molecules / cm2 and less than 1.0×1016 molecules / cm2, preferably greater than 1.0×1015 molecules / cm2 and less than 5.0×1015 molecules / cm2.

[0159] The following describes the method of measuring molecular release using TDS analysis, using oxygen release as an example.

[0160] The total amount of gas released during TDS analysis of a sample is proportional to the integrated value of the ion intensity of the released gas. Furthermore, the total amount of gas released can be calculated by comparing the sample with a standard sample.

[0161] For example, the following formula can be used to calculate the amount of oxygen molecules released (NO₂) from the measurement sample using the TDS analysis results of a silicon substrate containing a specified density of hydrogen as a standard sample and the TDS analysis results of the measurement sample. Here, it is assumed that all gases with a mass-to-charge ratio of 32 obtained by TDS analysis are derived from oxygen molecules. Although CH₃OH has a mass-to-charge ratio of 32, its presence is unlikely and is therefore not considered here. Furthermore, oxygen molecules containing oxygen atoms with mass numbers 17 and 18, which are isotopes of oxygen atoms, are also not considered because their abundance ratio in nature is extremely low.

[0162] NO2=NH2 / SH2×SO2×α

[0163] NH2 is the density-converted value of hydrogen molecules released from the standard sample. SH2 is the integrated value of the ion intensity obtained by TDS analysis of the standard sample. Here, the baseline value of the standard sample is set to NH2 / SH2. SO2 is the integrated value of the ion intensity obtained by TDS analysis of the measurement sample. α is the coefficient that affects the ion intensity in TDS analysis. For details of the formula shown above, please refer to Japanese Patent Application Publication No. 6-275697. Note that the above oxygen release amount was measured using the thermal desorption device EMD-WA1000S / W manufactured by ESCO Ltd., using a silicon substrate containing a certain amount of hydrogen atoms as the standard sample.

[0164] In TDS analysis, some oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Furthermore, since the above α includes the ionization rate of oxygen molecules, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released.

[0165] Note that NO2 is the amount of oxygen molecules released. When converted to oxygen atoms, the amount released is twice the amount of oxygen molecules released.

[0166] Alternatively, insulators that release oxygen through heat treatment may contain peroxide radicals. Specifically, the spin density of these peroxide radicals is 5×10⁻¹⁷ spins / cm³ or higher. Furthermore, insulators containing peroxide radicals may exhibit an asymmetric signal around a g-value of 2.01 in electron spin resonance (ESR) measurements.

[0167] The insulator 104 may also have a function of preventing impurities from diffusing from the substrate 100 .

[0168] As described above, the top surface or bottom surface of the semiconductor 106b is preferably flat. Therefore, the top surface of the insulator 104 can be flattened by using a chemical mechanical polishing (CMP) method to improve the flatness.

[0169] The conductor 108 a or the conductor 108 b is used as either a source electrode or a drain electrode of the transistor 10 .

[0170] For example, the conductors 108a and 108b may be single layers or stacked layers of conductors containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. For example, alloys or compounds containing the above elements may be used. Conductors containing aluminum, copper and titanium, copper and manganese, indium, tin, and oxygen, or titanium and nitrogen may also be used.

[0171] Here, the bottom surfaces of conductors 108a and 108b preferably do not contact the top surface of insulator 104. For example, as shown in FIG1B , the bottom surfaces of conductors 108a and 108b only need to contact the top surface of semiconductor 106b. This structure prevents oxygen from being extracted from insulator 104 at the bottom surfaces of conductors 108a and 108b. This prevents an increase in resistivity due to partial oxidation of conductors 108a and 108b, and allows for efficient oxygen supply from insulator 104 to insulator 106a, semiconductor 106b, and insulator 106c.

[0172] At least a portion of conductors 108a and 108b preferably overlaps insulator 112 via insulator 106c in areas that do not overlap with conductor 114. For example, as shown in FIG1B , a structure can be employed in which the majority of the top surfaces of conductors 108a and 108b are covered by insulator 106c. This structure can suppress oxygen extraction from insulator 112 on the top surfaces of conductors 108a and 108b. This prevents an increase in resistivity due to partial oxidation of conductors 108a and 108b, and allows for efficient oxygen supply from insulator 112 to insulator 106a, semiconductor 106b, and insulator 106c.

[0173] Insulator 112 serves as a gate insulating film for transistor 10. Like insulator 104, insulator 112 may also contain excess oxygen. Providing such insulator 112 allows oxygen to be supplied from insulator 112 to insulator 106a, semiconductor 106b, and insulator 106c.

[0174] As the insulator 112, for example, a single layer or a stack of layers of an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. For example, the insulator 112 can be made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide.

[0175] The conductor 114 is used as a gate electrode of the transistor 10. As the conductor 114, a conductor that can be used as the conductor 102 can be used.

[0176] Here, as shown in Figure 1C, the electric field of conductors 102 and 114 can electrically surround semiconductor 106b (a transistor structure in which the electric field of a conductor electrically surrounds the semiconductor is called a surrounded channel (s-channel) structure). Consequently, a channel may be formed across the entirety of semiconductor 106b (top, bottom, and side surfaces). The s-channel structure allows a large current to flow between the transistor's source and drain, thereby increasing the on-state current (on-state current).

[0177] Note that when the transistor has an s-channel structure, a channel is also formed on the side of semiconductor 106b. Therefore, the thicker the semiconductor 106b, the larger the channel region. In other words, the thicker the semiconductor 106b, the higher the on-state current of the transistor. Furthermore, the thicker the semiconductor 106b, the greater the proportion of the region with high carrier controllability, thereby reducing the subthreshold swing value. For example, semiconductor 106b may have a region with a thickness of at least 10 nm, preferably at least 20 nm, more preferably at least 30 nm, and even more preferably at least 50 nm. Note that the productivity of semiconductor devices may sometimes decrease, so, for example, semiconductor 106b may have a region with a thickness of at most 300 nm, preferably at most 200 nm, and even more preferably at most 150 nm.

[0178] Because it can achieve high on-state current, the s-channel structure is well-suited for microtransistors. Semiconductor devices including microtransistors can achieve high integration and density. For example, the transistor channel length is preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. Furthermore, the transistor channel width is preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less.

[0179] Insulator 116 serves as a protective insulating film for transistor 10. The thickness of insulator 116 can be, for example, 5 nm or greater, or 20 nm or greater. Preferably, at least a portion of insulator 116 contacts the top surface of insulator 104 or the top surface of insulator 112.

[0180] As insulator 116, for example, a single layer or stack of insulators containing carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Insulator 116 preferably has a barrier effect against oxygen, hydrogen, water, alkali metals, alkaline earth metals, and the like. As such an insulator, for example, a nitride insulating film can be used. Examples of such nitride insulating films include silicon nitride films, silicon oxynitride films, aluminum nitride films, and aluminum oxynitride films. Alternatively, an oxide insulating film having a barrier effect against oxygen, hydrogen, water, and the like can be provided in place of the nitride insulating film. Examples of such oxide insulating films include aluminum oxide films, aluminum oxynitride films, gallium oxide films, gallium oxynitride films, yttrium oxide films, yttrium oxynitride films, hafnium oxide films, and hafnium oxynitride films.

[0181] Here, insulator 116 is preferably formed by sputtering, more preferably in an atmosphere containing oxygen. Sputtering forms insulator 116, and oxygen is added to the surface of insulator 104 or 112 (and the interface between insulator 104 or 112 and insulator 116 after insulator 116 is formed) simultaneously with film formation.

[0182] Preferably, insulator 116 is less permeable to oxygen than insulators 104 and 112, and has an oxygen barrier function. Providing such insulator 116 prevents oxygen from being released to the outside above insulator 116 when oxygen is supplied from insulators 104 and 112 to insulator 106a, semiconductor 106b, and insulator 106c.

[0183] Aluminum oxide has a high barrier effect against the permeation of impurities such as hydrogen and water, as well as oxygen, and is therefore preferably used for the insulator 116 .

[0184] Alternatively, the oxides described above for insulator 106a or insulator 106c can be used as insulator 116. These oxides can be easily formed using sputtering, effectively adding oxygen to insulators 104 and 112. Insulator oxides containing indium are preferably used as insulator 116, such as In-Al oxide, In-Ga oxide, or In-Ga-Zn oxide. Insulator oxides containing indium are suitable for insulator 116 because they generate fewer particles when deposited using sputtering.

[0185] The insulator 118 serves as an interlayer insulating film. As the insulator 118, an insulator that can be used as the insulator 105 can be used.

[0186] The conductors 120a and 120b are used as wiring electrically connected to the source electrode and the drain electrode of the transistor 10. As the conductors 120a and 120b, conductors that can be used as the conductors 108a and 108b can be used.

[0187] By adopting the above structure, a transistor with stable electrical characteristics can be provided. Alternatively, a transistor with low leakage current in the off state can be provided. Alternatively, a transistor with high frequency characteristics can be provided. Alternatively, a transistor with normally-off electrical characteristics can be provided. Alternatively, a transistor with a small subthreshold swing value can be provided. Alternatively, a transistor with high reliability can be provided.

[0188] Transistor Deformation Examples Next, a modified example of the transistor 10 will be described with reference to FIG7A to FIG7D, FIG8A to FIG8D, FIG9A and FIG9B, FIG10A to FIG10D, FIG11A and FIG11B, and FIG12A to FIG12D. Note that, similar to FIG1B and FIG1C, FIG7A to FIG7D, FIG8A to FIG8D, FIG9A and FIG9B, FIG10A to FIG10D, FIG11A and FIG11B, and FIG12A to FIG12D illustrate cross-sectional views of the transistor along the channel length direction and cross-sectional views of the transistor along the channel width direction.

[0189] Transistor 12 shown in Figures 7A and 7B differs from transistor 10 in that insulator 105 is not formed. Thus, conductor 102 is surrounded by insulators 101 and 103. Insulators 101 and 103 preferably function as oxygen shields. This structure prevents oxygen from being extracted from insulator 104 and other materials, which could cause oxidation of conductor 102. This prevents an increase in resistivity due to partial oxidation of conductor 102 and allows for efficient oxygen supply to insulator 106a, semiconductor 106b, and insulator 106c.

[0190] Transistor 14 shown in Figures 7C and 7D differs from transistor 10 in that insulators 103 and 105 are not formed. Thus, insulator 104 covers conductor 102. Insulator 101 preferably has an oxygen shielding function. This structure prevents oxygen that diffuses into insulator 104 when oxygen is supplied from insulator 104 to insulator 106a, semiconductor 106b, and insulator 106c from diffusing into the layers below insulator 104. This allows for efficient oxygen supply to insulator 106a, semiconductor 106b, and insulator 106c.

[0191] Furthermore, in transistor 14, a highly oxidizing conductive material such as Ru, titanium nitride, tungsten silicide, platinum, iridium, ruthenium oxide, or iridium oxide can be used as conductive material 102. This structure prevents oxidation of conductive material 102 due to its high oxidation resistance against halogens such as fluorine contained in the atmosphere used to form insulator 104.

[0192] Transistor 16 shown in Figures 8A and 8B differs from transistor 10 in that conductor 102, insulator 103, and insulator 105 are not formed. Insulator 101 preferably has an oxygen shielding function. This structure prevents oxygen that diffuses into insulator 104 when oxygen is supplied from insulator 104 to insulator 106a, semiconductor 106b, and insulator 106c from diffusing into the layers below insulator 104. This allows for efficient oxygen supply to insulator 106a, semiconductor 106b, and insulator 106c.

[0193] Transistor 18 shown in Figures 8C and 8D differs from transistor 14 in having a stacked structure in which conductor 102b is provided on conductor 102a, replacing conductor 102. Conductor 102a can use any material that can be used as conductor 102, while conductor 102b can use a highly oxidizing material such as Ru, titanium nitride, tungsten silicide, platinum, iridium, ruthenium oxide, or iridium oxide. This structure prevents oxidation of conductor 102a because conductor 102b has high oxidation resistance against halogens such as fluorine contained in the atmosphere used to form insulator 104.

[0194] Transistor 20 shown in Figures 9A and 9B differs from transistor 10 in that insulator 107 is provided on insulator 101, and conductor 102 is filled in the opening in insulator 107. Any insulator that can be used as insulator 105 can be used as insulator 107. Furthermore, it is preferable to perform a planarization process on the top surfaces of insulator 107 and conductor 102, such as by CMP, to improve their flatness. This ensures that even when conductor 102 is provided as a back gate, the flatness of the surface forming semiconductor 106b is not affected, thereby increasing carrier mobility and the on-state current of transistor 20. Furthermore, since the step on the surface of insulator 104 caused by the shape of conductor 102 disappears, leakage current generated through the step portion of insulator 104 between the drain of conductor 108a or conductor 108b and conductor 102 can be reduced. Consequently, the off-state current of transistor 20 can be reduced.

[0195] Transistor 22 shown in Figures 10A and 10B differs from transistor 20 in that insulator 117 is formed to cover conductors 108a, 108b, and insulator 104. Insulator 117 has an opening that reaches semiconductor 106b, and insulator 106c, insulator 112, and conductor 114 are embedded in this opening. Furthermore, conductors 108a and 108b are separated from each other by this opening. In transistor 22, conductor 114, serving as a gate electrode, is formed to self-align within the opening formed in insulator 117. Therefore, transistor 22 can be referred to as a TGSA (Trench Gate Self Align) s-channel FET.

[0196] Here, the insulator 117 can be formed using an insulator that can be used for the insulator 104. In addition, the top surface of the insulator 117 can be planarized by a CMP method or the like.

[0197] Here, similar to the above-described insulator 104, when a silicon halide such as SiF4 is used to form insulator 117, a halogen such as fluorine is included in insulator 117. As a result, during the heat treatment, oxygen in insulator 117 is replaced by fluorine and released. This released oxygen can also be supplied to insulator 106a and semiconductor 106b. Furthermore, by including a halogen such as fluorine in insulator 117, insulator 117 is preferably used as a low-k film having a relative dielectric constant of less than 3.5, more preferably, as a low-k film having a relative dielectric constant of less than 3. When insulator 117 has this structure, parasitic capacitance can be further reduced.

[0198] In transistor 22, insulator 117, insulator 106c, and insulator 112 are provided between conductor 108a and conductor 114. Furthermore, insulator 117, insulator 106c, and insulator 112 are provided between conductor 108b and conductor 114. Consequently, the distance between the top surface of conductor 108a and the bottom surface of conductor 114, and the distance between the top surface of conductor 108b and the bottom surface of conductor 114, are increased by the thickness of insulator 117. This reduces parasitic capacitance generated in the region where conductor 114 overlaps with conductor 108a or conductor 108b. Reducing parasitic capacitance increases the switching speed of the transistor, thereby providing a transistor with high-frequency characteristics.

[0199] 10C and 10D differ from transistor 22 in that the top surfaces of insulator 117, insulator 106c, insulator 112, and conductor 114 are substantially uniform and flat. The top surfaces of insulator 117, insulator 106c, insulator 112, and conductor 114 can be planarized by CMP or the like.

[0200] As a result, there is almost no overlap between conductor 114 and conductors 108a or 108b, thereby reducing parasitic capacitance between the gate and source, and between the gate and drain, of transistor 24. By reducing parasitic capacitance, the switching speed of the transistor can be increased, thereby providing a transistor with high-frequency characteristics.

[0201] Transistor 29 shown in Figures 11A and 11B differs from transistor 24 in that insulator 107 is disposed on insulator 101, and the opening in insulator 107 is filled with conductor 102. Furthermore, transistor 29 differs from transistor 24 in that insulator 106c covers insulator 106a and semiconductor 106b. In transistor 29, insulator 106c is not disposed on the sides of the opening in insulator 117. Therefore, the length of conductor 114 in the channel length direction at the opening in insulator 117 can be longer than that of transistor 24.

[0202] Note that in transistor 29, metal oxide 111a and metal oxide 111b are provided on the top and side surfaces of conductors 108a and 108b, respectively. The thickness of metal oxide 111a and metal oxide 111b on the top surfaces of conductors 108a and 108b may be greater than the thickness on the side surfaces of conductors 108a and 108b. This is because the metal oxide 111a and metal oxide 111b on the top and side surfaces of conductors 108a and 108b are formed in different steps.

[0203] For example, during one or more steps such as forming the insulator 117, forming the insulator 112, or performing plasma treatment, the conductors 108a and 108b are oxidized to form the metal oxides 111a and 111b. In this case, the metal oxides 111a and 111b are oxides containing the elements that constitute the conductors 108a and 108b.

[0204] The total volume of the conductor 108a and the metal oxide 111a may be larger than the volume of the conductor 108a before the metal oxide 111a is formed. Similarly, the total volume of the conductor 108b and the metal oxide 111b may be larger than the volume of the conductor 108b before the metal oxide 111b is formed.

[0205] Since metal oxide 111a and metal oxide 111b are provided on the top and side surfaces of conductors 108a and 108b, respectively, transistor 29 has a structure that alleviates electric field concentration at the drain electrode end. As a result, transistor 29 can be highly reliable and have minimal short-channel effects.

[0206] However, the metal oxide 111a and the metal oxide 111b are not limited to being used in the transistor 29. For example, other transistors may also include the metal oxide 111a and the metal oxide 111b.

[0207] Transistor 26 shown in Figures 12A and 12B differs from transistor 20 in that conductors 108a and 108b are not provided, and the end side surfaces of conductor 114 and insulator 112 are substantially aligned. Transistor 10 and the like employ a gate-last method, meaning that during the transistor manufacturing process, low-resistance regions 109a and 109b, which serve as source or drain regions, are formed before conductor 114, which serves as a gate, is formed. In contrast, transistor 26 employs a gate-first method, meaning that during the transistor manufacturing process, low-resistance regions 109a and 109b, which serve as source or drain regions, are formed after conductor 114, which serves as a gate, is formed.

[0208] In transistor 26, low-resistance regions 109a and 109b contain at least one of the elements contained in insulator 116. Preferably, portions of low-resistance regions 109a and 109b substantially contact or overlap a region (channel formation region) in semiconductor 106b that overlaps with conductor 114.

[0209] In addition, since the element contained in the insulator 116 is added to the resistance region 109a and the low resistance region 109b, the concentration of the element obtained by SIMS analysis is higher than that in the region other than the low resistance region 109a and the low resistance region 109b in the semiconductor 106b (for example, the region of the semiconductor 106b overlapping with the conductor 114).

[0210] For example, preferred elements to be added to the low-resistance regions 109a and 109b include boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, or tungsten. These elements readily form oxides, and these oxides can function as semiconductors or insulators. Therefore, they are preferred as elements to be added to the insulator 106a, semiconductor 106b, or insulator 106c. For example, it is preferred that the low-resistance regions 109a and 109b contain at least 1×1014 molecules / cm2 and no more than 2×1016 molecules / cm2 of these elements. In addition, the concentration of the above elements in the low resistance regions 109a and 109b in the insulator 106c is higher than that in regions other than the low resistance regions 109a and 109b in the insulator 106c (for example, regions in the insulator 106c overlapping with the conductor 114).

[0211] In addition, since the low-resistance regions 109a and 109b can be made n-type by including nitrogen, the nitrogen concentration obtained by SIMS analysis is higher than that in regions other than the low-resistance regions 109a and 109b in the semiconductor 106b (for example, the region in the semiconductor 106b that overlaps with the conductor 114).

[0212] By forming such low resistance regions 109a and 109b, the contact resistance between the conductor 108a or 108b and the insulator 106a, semiconductor 106b or insulator 106c can be reduced, thereby increasing the on-state current of the transistor 10.

[0213] Furthermore, in transistor 26, semiconductor 106b is surrounded by insulators 106a and 106c. Consequently, the end side surfaces of semiconductor 106b, particularly those near the end side surfaces in the channel width direction, are in contact with insulators 106a and 106c. This creates a continuous bond between the end side surfaces of semiconductor 106b and insulators 106a and 106c near the end side surfaces, thereby reducing the density of defect levels. Consequently, even when the low-resistance regions 109a and 109b facilitate the flow of on-state current, the end side surfaces of semiconductor 106b in the channel width direction do not become parasitic channels, resulting in stable electrical characteristics.

[0214] 12C and 12D differ from transistor 10 in that transistor 28 does not include insulator 112 and conductor 114. In other words, transistor 28 is a so-called bottom-gate transistor.

[0215] The structure and method described in this embodiment can be used in combination with the structure and method described in other embodiment modes as appropriate.

[0216] Implementation Method 2 In this embodiment, a method for manufacturing a semiconductor device according to one embodiment of the present invention is described with reference to FIGS. 13A to 13H , 14A to 14F , 15A to 15D , 16A and 16B , 17A to 17H , 18A to 18F , and 19A to 19F .

[0217] <Method for Manufacturing a Transistor> Next, a method for manufacturing the transistor 10 will be described with reference to FIG. 13A to FIG. 13H , FIG. 14A to FIG. 14F , and FIG. 15A to FIG. 15D .

[0218] First, prepare the substrate 100. As the substrate 100, the above-mentioned substrates can be used.

[0219] Next, the insulator 101 is formed. As the insulator 101, the above-mentioned insulators can be used.

[0220] The insulator 101 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like.

[0221] Next, a conductor is formed to serve as the conductor 102. The above-mentioned conductors can be used as the conductor 102. The conductor can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0222] Next, a photoresist or the like is formed on the conductor, and the conductor is processed using the photoresist or the like, thereby forming the conductor 102 (see FIG13A and FIG13B). Note that simply stating "forming a photoresist" also includes forming an antireflection layer under the photoresist.

[0223] After processing the object using etching or other methods, the photoresist is removed. Plasma treatment and / or wet etching are used to remove the photoresist. Plasma ashing is preferred as the plasma treatment. If the photoresist is not completely removed, hydrofluoric acid or / and ozone water at a concentration of 0.001 vol.% to 1 vol.% can be used to remove the remaining photoresist.

[0224] Next, insulator 105 is formed. The aforementioned insulators can be used as insulator 105. Insulator 105 can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Furthermore, to reduce the amount of water or hydrogen contained in insulator 105, insulator 105 can be formed while heating the substrate. For example, if a semiconductor device layer is provided below transistor 10, heating can be performed within a relatively low temperature range (e.g., a temperature range of approximately 350°C to 445°C).

[0225] In addition, by forming the insulator 105 using the PECVD method in the same way as the insulator 104 described later, the water or hydrogen contained in the insulator 105 can be reduced.

[0226] Next, insulator 103 is formed. The aforementioned insulators can be used as insulator 103. Insulator 103 can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Furthermore, to reduce the amount of water or hydrogen contained in insulator 103, insulator 103 can be formed while heating the substrate. When a semiconductor device layer is provided below transistor 10, heating is preferably performed within a relatively low temperature range (e.g., a temperature range of approximately 350°C to 445°C).

[0227] CVD methods can be divided into plasma enhanced CVD (PECVD) using plasma, thermal CVD (TCVD) using heat, and photo CVD (photo CVD) using light. Furthermore, based on the source gas used, they can be divided into metal CVD (MCVD) and metal organic CVD (MOCVD).

[0228] The PECVD method can produce high-quality films at lower temperatures. Furthermore, because TCVD doesn't use plasma, it can reduce plasma damage to the substrate being processed. For example, the wiring, electrodes, and components (transistors, capacitors, etc.) included in a semiconductor device sometimes receive charge from plasma, causing charge buildup. This accumulated charge can damage the wiring, electrodes, and components of the semiconductor device. On the other hand, the TCVD method, which doesn't use plasma, eliminates plasma damage, thereby improving the yield of semiconductor devices. Furthermore, because TCVD eliminates plasma damage during film formation, films with fewer defects can be produced.

[0229] Furthermore, the ALD method can reduce plasma damage to the treated object. Furthermore, the ALD method does not cause plasma damage during film formation, resulting in films with fewer defects.

[0230] Unlike film-forming methods that deposit particles released from a target, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, films formed using CVD and ALD have excellent step coverage and are less susceptible to the shape of the workpiece. In particular, ALD films have excellent step coverage and uniform thickness, making them suitable for covering surfaces with high-aspect-ratio openings. This reduces the risk of pinholes and other defects in the formed films. However, because ALD has a relatively slow deposition rate, it is best used in combination with other film-forming methods, such as CVD, which have faster deposition rates.

[0231] CVD and ALD methods can control the composition of the resulting film by adjusting the source gas flow ratio. For example, CVD and ALD methods can form films of any composition by adjusting the source gas flow ratio. Furthermore, by varying the source gas flow ratio while the film is being formed, CVD and ALD methods can form films whose composition continuously changes. Changing the source gas flow ratio while film formation is in progress eliminates the time required for transfer and pressure adjustment, shortening film formation time compared to using multiple film formation chambers. This can sometimes improve semiconductor device productivity.

[0232] Conventional film-forming apparatuses utilizing the CVD method simultaneously supply one or more source gases for a reaction into a process chamber during film formation. In film-forming apparatuses utilizing the ALD method, a source gas (also called a precursor) and a gas serving as a reactant (also called a reactant) are sequentially introduced into the process chamber, and film formation is performed by repeatedly introducing these two gases. Note that the switching of the introduced gases can be accomplished, for example, by switching respective on / off valves (also called high-speed valves).

[0233] For example, film formation can be performed using the following steps. First, a precursor is introduced into the processing chamber and allowed to adhere to the substrate surface (step 1). Since the precursor adheres to the substrate surface, the self-limiting mechanism of the surface chemical reaction takes effect, preventing the precursor from further adhering to the precursor layer on the substrate. Note that the optimal substrate temperature range within which the self-stopping mechanism of the surface chemical reaction takes effect is also referred to as the ALD window. The ALD window depends on the temperature characteristics, vapor pressure, and decomposition temperature of the precursor. Next, an inert gas (such as argon or nitrogen) is introduced into the processing chamber, and the remaining precursor and reaction products are evacuated from the processing chamber (step 2). Alternatively, the remaining precursor and reaction products can be evacuated from the processing chamber by vacuum evacuation without introducing an inert gas. Next, a reactant (such as an oxidizing agent (H2O, O3, etc.)) is introduced into the processing chamber and reacts with the precursor adhered to the substrate surface, removing a portion of the precursor while the constituent molecules of the film adhere to the substrate (step 3). Next, the remaining reactants and reaction products are exhausted from the processing chamber by introducing an inert gas or vacuum pumping (the fourth step).

[0234] Alternatively, the introduction of the reactants in the third step and the introduction of the inert gas in the fourth step may be repeated multiple times. That is, for example, the third step, the fourth step, the third step, and the fourth step may be performed after the first and second steps.

[0235] For example, O 3 may be introduced as an oxidant in the third step and N 2 may be purged in the fourth step, and these steps may be repeated.

[0236] Furthermore, when the third and fourth steps are repeated, it is not necessary to repeatedly introduce the same type of reactant. For example, H2O may be used as the oxidant in the first third step, while O3 may be used as the oxidant in the second and subsequent third steps.

[0237] By repeatedly introducing an oxidizing agent and introducing an inert gas (or vacuum evacuating) multiple times within a short period of time within the processing chamber, it is possible to more reliably remove excess hydrogen atoms and the like from the precursor adhering to the substrate surface and expel them outside the processing chamber. Furthermore, by introducing both oxidizing agents, even more excess hydrogen atoms and the like can be removed from the precursor adhering to the substrate surface. By preventing hydrogen atoms from being incorporated into the film during film formation, the amount of water, hydrogen, and the like contained in the formed insulator 103 and the like can be reduced.

[0238] By adopting this method, the insulator 103 can be an insulator in which the amount of water molecules released in TDS analysis at a surface temperature range of 100°C to 700°C or 100°C to 500°C is greater than 1.0×1013 molecules / cm2 and less than 1.0×1016 molecules / cm2, preferably greater than 1.0×1013 molecules / cm2 and less than 3.0×1015 molecules / cm2.

[0239] In this way, a first single layer can be formed on the substrate surface. By repeating steps 1 through 4 again, a second single layer can be stacked on top of the first single layer. By repeating steps 1 through 4 multiple times while controlling the introduction of gases until the desired thickness is achieved, a thin film with good step coverage can be formed. Because the film thickness can be adjusted by the number of repetitions, the ALD method allows for precise thickness control, making it suitable for manufacturing micro-transistors.

[0240] ALD is a film-forming method that utilizes thermal energy to cause precursors to react. ALD methods that utilize plasma to convert reactants into radicals are sometimes referred to as plasma ALD. On the other hand, ALD methods that utilize thermal energy to cause precursor and reactant reactions are sometimes referred to as thermal ALD.

[0241] The ALD method enables the formation of extremely thin films with uniform thickness. Furthermore, even films with uneven surfaces can achieve high surface coverage.

[0242] Plasma ALD allows for film formation at lower temperatures than thermal ALD. For example, plasma ALD allows for film formation at temperatures below 100°C without reducing the deposition rate. Furthermore, plasma ALD can use a wider range of reactants, such as nitrogen gas, in addition to oxidants. This allows for the formation of a wider variety of films, including nitride, fluoride, and metal films, in addition to oxide films.

[0243] When using plasma ALD, plasma can be generated away from the substrate, as in ICP (Inductively Coupled Plasma). Generating plasma in this way can suppress plasma damage.

[0244] Here, as an example of an apparatus capable of forming films using the ALD method, the structure of a film forming apparatus 1000 will be described with reference to Figures 16A and 16B. Figure 16A is a schematic diagram of the multi-chamber film forming apparatus 1000, and Figure 16B is a cross-sectional view of an ALD apparatus that can be used in the film forming apparatus 1000.

[0245] 《Structural example of film forming equipment》 Film formation apparatus 1000 includes a loading chamber 1002, a loading chamber 1004, a transfer chamber 1006, a film formation chamber 1008, a film formation chamber 1009, a film formation chamber 1010, and a transfer arm 1014. Loading chamber 1002, loading chamber 1004, and film formation chambers 1008 to 1010 are connected to transfer chamber 1006. This allows continuous film formation in film formation chambers 1008 to 1010 without exposure to the atmosphere, preventing impurities from entering the film.

[0246] Note that in order to prevent moisture adhesion, etc., it is preferred to fill the loading chamber 1002, the unloading chamber 1004, the transfer chamber 1006, and the film forming chambers 1008 to 1010 with an inert gas (nitrogen gas, etc.) with a controlled dew point, and it is more preferred to maintain a reduced pressure state.

[0247] An ALD system can be used in the film forming chambers 1008 to 1010. Alternatively, a film forming system other than the ALD system can be used in any of the film forming chambers 1008 to 1010. Examples of film forming systems used in the film forming chambers 1008 to 1010 include sputtering systems, PECVD equipment, TCVD equipment, and MOCVD equipment.

[0248] For example, by installing an ALD device and a PECVD apparatus in the film formation chambers 1008 to 1010, it is possible to form the insulator 105 made of silicon oxide by PECVD, the insulator 103 made of hafnium oxide by ALD, and the insulator 104 made of silicon oxide containing a halogen by PECVD in the transistor 10 shown in FIG1B and FIG1C. Since the above film formation is performed continuously without exposing the film to the atmosphere, the film formation can be performed without impurities being mixed into the film.

[0249] While film forming apparatus 1000 includes a loading chamber 1002, an unloading chamber 1004, and film forming chambers 1008 to 1010, the present invention is not limited thereto. Film forming apparatus 1000 may include four or more film forming chambers, or may include a processing chamber for performing heat treatment or plasma treatment. Furthermore, film forming apparatus 1000 may be either a single wafer type film forming apparatus or a batch type film forming apparatus that simultaneously forms films on multiple substrates.

[0250] ALD Device Next, the structure of an ALD apparatus that can be used in film formation apparatus 1000 will be described. The ALD apparatus includes: a film formation chamber (processing chamber 1020); raw material supply units 1021a and 1021b; high-speed valves 1022a and 1022b serving as flow controllers; raw material inlets 1023a and 1023b; a raw material outlet 1024; and an exhaust device 1025. The raw material inlets 1023a and 1023b within the processing chamber 1020 are connected to the raw material supply units 1021a and 1021b, respectively, via supply pipes or valves, while the raw material outlet 1024 is connected to the exhaust device 1025 via an exhaust pipe, valve, or pressure regulator.

[0251] As shown in FIG16B , by connecting a plasma generator 1028 to the processing chamber 1020, plasma ALD can be used instead of thermal ALD for film formation. Plasma ALD allows film formation even at low temperatures without reducing the film formation rate, making it a preferred method for single-wafer film formation systems, which have lower film formation efficiency.

[0252] A substrate holder 1026 equipped with a heater is provided inside the processing chamber, and a substrate 1030 on which a film is to be formed is placed on the substrate holder 1026.

[0253] In the raw material supply units 1021a and 1021b, a source gas is formed from a solid or liquid raw material using a vaporizer or a heating unit. Alternatively, the raw material supply units 1021a and 1021b may also supply the source gas.

[0254] While two raw material supply units, 1021a and 1021b, are shown here as an example, this is not limiting; three or more raw material supply units may be provided. Furthermore, high-speed valves 1022a and 1022b can be precisely controlled in time to supply either source gas or inert gas. High-speed valves 1022a and 1022b serve as flow controllers for both the source gas and the inert gas.

[0255] In the film forming device shown in Figure 16B, the substrate 1030 is placed on the substrate holder 1026, and the processing chamber 1020 is placed in a closed state. Then, the substrate 1030 is heated to a desired temperature (for example, above 80°C, above 100°C, or above 150°C) using the heater of the substrate holder 1026, and the supply of source gas, exhaust using the exhaust device 1025, supply of inert gas, and exhaust using the exhaust device 1025 are repeated, thereby forming a thin film on the surface of the substrate.

[0256] In the film-forming apparatus shown in FIG16B , by appropriately selecting the raw materials (volatile organic metal compounds, etc.) used in the raw material supply units 1021a and 1021b, it is possible to form an insulating layer comprising an oxide (including composite oxides) containing one or more elements selected from hafnium, aluminum, tantalum, and zirconium. Specifically, insulating layers can be formed comprising hafnium oxide, aluminum oxide, hafnium silicate, or aluminum silicate. Furthermore, by appropriately selecting the raw materials (volatile organic metal compounds, etc.) used in the raw material supply units 1021a and 1021b, it is also possible to form thin films such as metal layers such as tungsten and titanium layers, and nitride layers such as titanium nitride layers.

[0257] For example, when forming a hafnium oxide layer using an ALD device, two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, hafnium tetrakisdimethylamide (TDMAH), or other hafnium amide); and ozone (O3) as an oxidizer. In this case, the first source gas supplied from the raw material supply unit 1021a is TDMAH, and the second source gas supplied from the raw material supply unit 1021b is ozone. Note that the chemical formula of hafnium tetrakisdimethylamide is Hf[N(CH3)2]4. Other material liquids include hafnium tetrakis(ethylmethylamide).

[0258] When forming an aluminum oxide layer using an ALD device, two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as TMA: trimethylaluminum); and H₂O, which serves as an oxidizer. In this case, the first source gas supplied from the raw material supply unit 1021a is TMA, and the second source gas supplied from the raw material supply unit 1021b is H₂O. Note that the chemical formula of trimethylaluminum is Al(CH₃)₃. Other possible material liquids include aluminum tris(dimethylamide), triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione).

[0259] Note that when forming a tungsten layer using an ALD apparatus, WF₆ gas and B₂H₆ gas are introduced repeatedly to form the initial tungsten layer, and then WF₆ gas and H₂ gas are introduced repeatedly to form the tungsten layer. Note that SiH₄ gas can also be used instead of B₂H₆ gas. These gases can also be controlled using mass flow controllers.

[0260] Next, an insulator 104 is formed (see FIG. 13C and FIG. 13D ). The above-mentioned insulators can be used as the insulator 104. The insulator 104 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0261] The insulator 104 is preferably formed by a CVD method, and more preferably by a PECVD method.

[0262] When forming the insulator 104 by PECVD, it is preferable to use a substance containing no hydrogen or a low hydrogen content as the source gas, such as a halide. For example, when forming silicon oxide or silicon oxynitride as the insulator 104, it is preferable to use a silicon halide as the source gas, such as SiF4 (silicon tetrafluoride), SiCl4 (silicon tetrachloride), SiHCl3 (silicon trichloride), SiH2Cl2 (dichlorosilane), or SiBr4 (silicon tetrabromide).

[0263] When forming insulator 104 by PECVD, an oxidizing gas (e.g., N2O) is introduced for film formation. Silicon halides are less reactive than SiH4, so the oxidizing gas easily acts on insulator 103. This oxidizing gas can potentially remove water or hydrogen contained in insulator 103, thereby reducing the water and hydrogen content in insulator 103.

[0264] Furthermore, when using a silicon halide as a source gas when forming the insulator 104, silicon hydride can be added in addition to the silicon halide. This can further reduce the hydrogen and water content in the insulator 104 compared to using only silicon hydride as a source gas, and further increase the deposition rate compared to using only silicon halide as a source gas. For example, SiF4 and SiH4 can be used as source gases to form the insulator 104. For example, by setting the SiH4 flow rate to greater than 1 sccm and less than 10 sccm, and more preferably to greater than 2 sccm and less than 4 sccm, both the water and hydrogen content in the insulator 104 and the deposition rate can be optimized. Note that the flow rate ratio of SiF4 and SiH4 can be appropriately set depending on the water and hydrogen content in the insulator 104 and the deposition rate.

[0265] Furthermore, in order to reduce the amount of water or hydrogen contained in insulator 104, it is preferable to form insulator 104 while heating the substrate. For example, even if a semiconductor device layer is provided below transistor 10, water, hydrogen, etc. can be sufficiently removed by forming insulator 104 using the method described below while heating within a relatively low temperature range (e.g., a temperature range of approximately 350°C to 445°C).

[0266] In addition, by introducing SiH 4 into the processing chamber before forming the insulator 104 on the substrate, the silicon oxide containing fluorine can be more easily formed on the hafnium oxide film on which the silicon oxide film containing fluorine is not easily formed.

[0267] By adopting this method, the insulator 104 can be an insulator having a water molecule release rate of 1.0×1013 molecules / cm2 or more and 1.4×1016 molecules / cm2 or less, preferably 1.0×1013 molecules / cm2 or more and 4.0×1015 molecules / cm2 or less, and more preferably 1.0×1013 molecules / cm2 or more and 2.0×1015 molecules / cm2 or less, in a TDS analysis at a surface temperature range of 100°C to 700°C or 100°C to 500°C. In addition, the insulator 104 can be an insulator in which the amount of hydrogen molecules released in TDS analysis at a surface temperature range of 100°C to 700°C or 100°C to 500°C is greater than 1.0×1013 molecules / cm2 and less than 1.2×1015 molecules / cm2, preferably greater than 1.0×1013 molecules / cm2 and less than 9.0×1014 molecules / cm2.

[0268] In addition, the top surface or bottom surface of the semiconductor 106b to be formed later preferably has high flatness. Therefore, the top surface of the insulator 104 can be flattened by CMP or the like to improve its flatness.

[0269] Next, heat treatment is preferably performed. Heat treatment can further reduce water or hydrogen in insulators 105, 103, and 104. In some cases, excess oxygen can be contained in insulator 104. This heat treatment can be performed at a temperature of 250°C to 650°C, preferably 450°C to 600°C, and more preferably 520°C to 570°C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more. The heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an inert gas atmosphere followed by another heat treatment in an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more to replace the released oxygen. Heat treatment can improve the crystallinity of insulator 126a and semiconductor 126b and remove impurities such as hydrogen and water. For heat treatment, an RTA device using lamp heating can be used. Heat treatment using an RTA device can be completed in a shorter time than using a furnace, making it an effective method for improving productivity.

[0270] Note that when a semiconductor device layer is provided below the transistor 10, heating can be performed within a relatively low temperature range (e.g., a temperature range of approximately 350°C to 445°C). For example, it is preferable to set the temperature to be lower than the highest heating temperature of the substrate when forming the insulators 105, 103, and 104.

[0271] Next, the insulator 126a is formed. As the insulator 126a, the insulator or semiconductor described above that can be used as the insulator 106a can be used. The insulator 126a can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0272] Next, semiconductor 126b is formed. The semiconductor 126b described above as semiconductor 106b can be used as semiconductor 126b. Semiconductor 126b can be formed using sputtering, CVD, MBE, PLD, ALD, or the like. Note that by forming the insulator 126a and semiconductor 126b consecutively without exposure to the atmosphere, impurities can be reduced from entering the films and at the interface.

[0273] Next, heat treatment is preferably performed. Heat treatment can sometimes reduce the hydrogen concentration in the insulator 126a and the semiconductor 126b. It can also sometimes reduce oxygen vacancies in the insulator 126a and the semiconductor 126b. This heat treatment can be performed at a temperature of 250°C to 650°C, preferably 450°C to 600°C, and more preferably 520°C to 570°C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more. The heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an inert gas atmosphere followed by another heat treatment in an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more to replace the oxygen that has been released. Heat treatment can improve the crystallinity of the insulator 126a and the semiconductor 126b and remove impurities such as hydrogen and water. For heat treatment, an RTA apparatus using lamp heating can be used. Heat treatment using an RTA apparatus can be completed in a shorter time than in a furnace, making this method effective for improving productivity. When CAAC-OS is used as the insulator 126a and the semiconductor 126b, heat treatment increases peak intensity and reduces the full width at half maximum (FWHM). In other words, the crystallinity of the CAAC-OS increases with heat treatment.

[0274] Note that when a semiconductor device layer is provided below the transistor 10, heating can be performed within a relatively low temperature range (e.g., a temperature range of approximately 350°C to 445°C). For example, it is preferable to set the heating temperature to be lower than the highest heating temperature of the substrate heating temperature during the formation of the insulators 105, 103, and 104, or the temperature of the heat treatment after the formation of the insulator 104. Forming the insulator 104 using the method described above can sufficiently remove water, hydrogen, and the like from the insulator 104, thereby significantly reducing the supply of water or hydrogen to the insulator 126a and the semiconductor 126b.

[0275] This heat treatment allows oxygen to be supplied from the insulator 104 to the insulator 126a and the semiconductor 126b. By heat treating the insulator 104, oxygen can be supplied to the insulator 126a and the semiconductor 126b very easily.

[0276] Here, the insulator 103 functions as a barrier film to block oxygen. Since the insulator 103 is provided below the insulator 104, oxygen diffused into the insulator 104 can be prevented from diffusing to the layer below the insulator 104.

[0277] In this manner, by supplying oxygen to the insulator 126a and the semiconductor 126b to reduce oxygen vacancies, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor having a low defect energy level density can be obtained.

[0278] Alternatively, high-density plasma treatment can be performed. High-density plasma can be generated using microwaves. In high-density plasma treatment, for example, oxidizing gases such as oxygen and nitrous oxide can be used. Alternatively, a mixed gas of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe can be used. During high-density plasma treatment, a bias voltage can be applied to the substrate. This allows oxygen ions and the like in the plasma to be introduced to one side of the substrate. High-density plasma treatment can be performed while heating the substrate. For example, when high-density plasma treatment is performed instead of the above-described heat treatment, the same effect as the above-described heat treatment can be obtained at a temperature lower than that of the above-described heat treatment. High-density plasma treatment can be performed before forming the insulator 126a, after forming the insulator 112, or after forming the insulator 116.

[0279] Next, a conductor 128 is formed (see FIG. 13E and FIG. 13F ). The conductor 128 can be any of the conductors described above for the conductors 108 a and 108 b. The conductor 128 can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0280] Next, a photoresist or the like is formed on the conductor 128, and the conductors 108a and 108b are formed by processing using the photoresist.

[0281] Next, a photoresist or the like is formed on the semiconductor 126b, and the photoresist, the conductor 108a, and the conductor 108b are processed to form the insulator 106a and the semiconductor 106b (see FIG. 13G and FIG. 13H).

[0282] Here, low-resistance regions 109a and 109b may be formed in the regions of semiconductor 106b that are in contact with conductors 108a and 108b. Furthermore, semiconductor 106b may include a region between conductors 108a and 108b that is thinner than the region overlapping conductors 108a and 108b. This region is formed by removing a portion of the top surface of semiconductor 106b when forming conductors 108a and 108b.

[0283] Next, heat treatment is preferably performed. Heat treatment can further reduce water or hydrogen in insulator 104, insulator 103, insulator 105, insulator 106a, and semiconductor 106b. This heat treatment can be performed at a temperature of 250°C to 650°C, preferably 450°C to 600°C, and more preferably 520°C to 570°C. The heat treatment can be performed under an inert gas atmosphere. Alternatively, the heat treatment can be performed under reduced pressure. Alternatively, after heat treatment under an inert gas atmosphere, another heat treatment can be performed under an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replace the released oxygen. For the heat treatment, a lamp-heated RTA apparatus can be used. Heat treatment using an RTA apparatus can be completed in a shorter time than in a furnace, making this method effective for improving productivity.

[0284] Note that when a semiconductor element layer is provided below the transistor 10 , heating is preferably performed within a relatively low temperature range (eg, a temperature range of approximately 350° C. to 445° C.) in order to prevent degradation of the semiconductor element layer below.

[0285] If the insulator 104 contains a large amount of water or hydrogen when it is formed, even if the heat treatment is performed within a temperature range that does not degrade the underlying semiconductor element layer, there is a concern that the water, hydrogen, etc. may not be fully removed from the insulator 104. Furthermore, if the heat treatment is performed within the same temperature range after the insulator 106c is formed, there is a concern that water, hydrogen, etc. may be supplied from the insulator 104 to the semiconductor 106b, etc., leading to the formation of defect states.

[0286] In contrast, as described above, when heat treatment is performed at the stage where the insulator 106a and the semiconductor 106b are formed and the surface of the insulator 104 is exposed, the supply of water and hydrogen to the insulator 106a and the semiconductor 106b can be suppressed, while further reducing the amount of water and hydrogen in the insulators 104, 103, and 105. By further reducing the amount of water and hydrogen in the insulators 104, 103, and 105, water and hydrogen can be sufficiently removed by heating at a relatively low temperature (e.g., a temperature range of approximately 350°C to 445°C), and the formation of defect levels in the semiconductor 106b and the like can be suppressed. This allows for the provision of a highly reliable transistor.

[0287] Furthermore, when etching gases containing impurities such as hydrogen and carbon are used during the formation of the insulator 106a and the semiconductor 106b, impurities such as hydrogen and carbon may be introduced into the insulator 106a and the semiconductor 106b. By performing a heat treatment after forming the insulator 106a and the semiconductor 106b, impurities such as hydrogen and carbon introduced during etching can be removed.

[0288] Alternatively, the high-density plasma treatment may be performed instead of the heat treatment or after the heat treatment. This allows the introduction of impurities such as hydrogen and carbon into the semiconductor 106b and the like, thereby filling oxygen vacancies with oxygen.

[0289] Alternatively, after forming the conductor 128, the insulator 126a, the semiconductor 126b, and the conductor 128 may be processed simultaneously to form a conductor overlapping the insulator 106a, the semiconductor 106b, and the semiconductor 106b, and the conductor overlapping the semiconductor 106b may be further processed to form the conductor 108a and the conductor 108b.

[0290] Next, insulator 126c is formed. As insulator 126c, any of the aforementioned insulators or semiconductors that can be used as insulator 106c can be used. Insulator 126c can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Before forming insulator 126c, the surfaces of semiconductor 106b, conductor 108a, and conductor 108b can be etched. For example, etching can be performed using plasma containing a rare gas. By continuously forming insulator 126c without exposure to the atmosphere, impurities can be suppressed from entering the interfaces between semiconductor 106b, conductor 108a, conductor 108b, and insulator 106c. Impurities present at interfaces between films sometimes diffuse more easily than impurities within the film itself. Therefore, by reducing the influx of these impurities, a transistor with stable electrical characteristics can be achieved.

[0291] Next, the insulator 132 is formed. The insulator 132 can be any of the insulators described above that can be used as the insulator 112. The insulator 132 can be formed using sputtering, CVD, MBE, PLD, ALD, or the like. By forming the insulator 126c and the insulator 132 successively without exposure to the atmosphere, incorporation of impurities into the films and at the interfaces can be suppressed.

[0292] Next, the conductor 134 is formed (see FIG. 14A and FIG. 14B ). The conductor 134 can be any of the conductors described above for the conductor 114. The conductor 134 can be formed using sputtering, CVD, MBE, PLD, ALD, or the like. By forming the insulator 132 and the conductor 134 successively without exposure to the atmosphere, the incorporation of impurities into the film and at the interface can be suppressed.

[0293] Next, a photoresist or the like is formed on the conductor 134 , and the conductor 134 is processed using the photoresist, thereby forming the conductor 114 .

[0294] Next, a photoresist or the like is formed on the conductor 114 and the insulator 132, and the conductor 114 and the insulator 132 are processed using the photoresist or the like, thereby forming the insulator 106c and the insulator 112 (see Figures 14C and 14D). Note that at this point, the insulator 106c and the insulator 112 can also be formed so that the areas where the conductors 120a and 120b, which will be formed later, will contact the conductors 108a and 108b are exposed.

[0295] Next, an insulator 116 is formed (see FIG. 14E and FIG. 14F ). The above-mentioned insulators can be used as the insulator 116. The insulator 116 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0296] Here, as the insulator 116, it is preferable to set an oxide insulating film such as an aluminum oxide film that has a barrier effect against oxygen, hydrogen, water, etc.

[0297] In addition, the insulator 116 is preferably formed using plasma, more preferably using sputtering, and further preferably using sputtering in an atmosphere containing oxygen.

[0298] Sputtering methods include DC (direct current) sputtering, which uses a direct current power source as the sputtering power source; pulsed DC sputtering, which applies a bias voltage in a pulsed manner; and RF (radio frequency) sputtering, which uses a high-frequency power source as the sputtering power source. Other methods include magnetron sputtering, which utilizes a magnet system within the processing chamber; bias sputtering, which applies a voltage to the substrate during film formation; and reactive sputtering, which is performed in a reactive gas atmosphere. Furthermore, the aforementioned PESP or VDSP can also be used. During sputtering, the oxygen gas flow rate and film-forming power can be appropriately determined based on factors such as the amount of oxygen added.

[0299] Here, by forming the insulator 116 by sputtering, oxygen can be added to the surface of the insulator 104 or 112 (the interface between the insulator 104 or 112 and the insulator 116 after the insulator 116 is formed) simultaneously with the formation of the insulator 116. Here, oxygen is added to the insulator 104 or 112 as oxygen radicals, for example, but the state of oxygen during addition is not limited to this. Oxygen can be added to the insulator 104 or 112 as oxygen atoms or oxygen ions. Note that the addition of oxygen may result in the inclusion of oxygen in the insulator 104 or 112 exceeding the stoichiometric composition. This oxygen may also be referred to as excess oxygen.

[0300] Next, heat treatment is preferably performed (see Figures 15A and 15B). Heat treatment allows oxygen added to insulator 104 or insulator 112 to diffuse and be supplied to insulator 106a, semiconductor 106b, and insulator 106c. Heat treatment can be performed at a temperature of 250°C to 650°C, preferably 350°C to 450°C. Heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more. Heat treatment can also be performed under reduced pressure. Lamp-heating RTA equipment can also be used for heat treatment.

[0301] Furthermore, the temperature of this heat treatment is preferably lower than the temperature of the heat treatment after forming semiconductor 126b. The temperature difference between this heat treatment and the heat treatment after forming semiconductor 126b is 20°C to 150°C, preferably 40°C to 100°C. This can suppress the release of excess oxygen from insulator 104 and the like. Note that if the heating during the formation of each layer can also serve as the heat treatment after forming insulator 118 (for example, heating is performed during the formation of insulator 118), the heat treatment after forming insulator 118 may not be performed.

[0302] This heat treatment causes oxygen (hereinafter referred to as oxygen 186) added to insulators 104 and 112 by the formation of insulator 116 to diffuse into insulators 104 and 112 (see Figures 15A and 15B). Insulator 116 is less permeable to oxygen than insulator 104 and 112 and serves as a barrier film to block oxygen. Because insulator 116 is formed on insulator 104 and 112, oxygen 186 diffused into insulator 104 and 112 does not diffuse upwards. As a result, oxygen 186 primarily diffuses laterally or downwards within insulator 104 and 112.

[0303] Oxygen 186 diffused into insulator 104 or insulator 112 is supplied to insulator 106a, insulator 106c, and semiconductor 106b. In this case, since insulator 103, which functions as an oxygen barrier, is provided below insulator 104, oxygen 186 diffused into insulator 104 can be prevented from diffusing into the layers below insulator 104.

[0304] In this manner, oxygen 186 can be efficiently supplied to the insulator 106a, the insulator 106c, and the semiconductor 106b, particularly the channel-forming region of the semiconductor 106b. By supplying oxygen to the insulator 106a, the insulator 106c, and the semiconductor 106b, oxygen vacancies are reduced, resulting in a high-purity intrinsic or substantially high-purity oxide semiconductor with a low defect level density.

[0305] Note that the heat treatment after forming the insulator 116 can be performed at any time after forming the insulator 116. For example, it can be performed after forming the insulator 118 or after forming the conductors 120a and 120b.

[0306] Next, the insulator 118 is formed. The above-mentioned insulators can be used as the insulator 118. The insulator 118 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0307] Next, a photoresist or the like is formed on insulator 118, and openings are formed in insulator 118, insulator 116, insulator 112, and insulator 106c. Then, conductors to become conductors 120a and 120b are formed. The conductors described above can be used as conductors 120a and 120b. These conductors can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0308] Next, a photoresist or the like is formed on the conductor, and the conductor is processed using the photoresist, thereby forming the conductor 120a and the conductor 120b (see FIG. 15C and FIG. 15D).

[0309] Through the above-mentioned process, a transistor according to one embodiment of the present invention can be manufactured.

[0310] 17A to 17H , 18A to 18F , and 19A to 19F , a method for manufacturing the transistor 29 will be described. Note that the method for manufacturing the transistor 29 may refer to the aforementioned method for manufacturing the transistor as appropriate.

[0311] First, prepare the substrate 100. As the substrate 100, the above-mentioned substrates can be used.

[0312] Next, the insulator 101 is formed. As the insulator 101, the above-mentioned insulators can be used.

[0313] Next, an insulator serving as the insulator 107 is formed. The above-mentioned insulators can be used as the insulator. The insulator can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0314] Next, a photoresist or the like is formed on the insulator, and processing is performed using the photoresist to form the insulator 107 having an opening.

[0315] Next, a conductor is formed to serve as the conductor 102. The above-mentioned conductors can be used as the conductor 102. The conductor can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0316] Next, the conductor is polished until the insulator 107 is exposed to form the conductor 102 (see FIG. 17A and FIG. 17B ). The polishing can be performed by CMP treatment or the like.

[0317] Next, insulator 105 is formed. The aforementioned insulators can be used as insulator 105. Insulator 105 can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Furthermore, to reduce the amount of water or hydrogen contained in insulator 105, insulator 105 can be formed while heating the substrate. For example, if a semiconductor element layer is provided below transistor 29, heating can be performed within a relatively low temperature range (e.g., a temperature range of approximately 350°C to 445°C).

[0318] In addition, by forming the insulator 105 using the same method as the insulator 104 described later and using the PECVD method, the water or hydrogen contained in the insulator 105 can be reduced.

[0319] Next, insulator 103 is formed. The aforementioned insulators can be used as insulator 103. Insulator 103 can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Furthermore, to reduce the amount of water or hydrogen contained in insulator 103, insulator 103 can be formed while heating the substrate. When a semiconductor device layer is provided below transistor 10, heating is preferably performed within a relatively low temperature range (e.g., a temperature range of approximately 350°C to 445°C).

[0320] Next, an insulator 104 is formed (see FIG. 17C and FIG. 17D ). The above-mentioned insulators can be used as the insulator 104. The insulator 104 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0321] In addition, the top surface or bottom surface of the semiconductor 106b to be formed later preferably has high flatness. Therefore, the top surface of the insulator 104 can be flattened by CMP or the like to improve its flatness.

[0322] Next, a heat treatment is preferably performed.

[0323] Next, an insulator to be the insulator 106a is formed. The insulator can be any of the above-mentioned insulators that can be used as the insulator 106a, or a semiconductor. The insulator can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0324] Next, the semiconductor that will become semiconductor 106b is formed. Any of the aforementioned semiconductors that can be used as semiconductor 106b can be used as the semiconductor. The semiconductor can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Furthermore, by forming the insulator and semiconductor sequentially without exposure to the atmosphere, impurities can be suppressed from entering the film and at the interface.

[0325] Next, heat treatment is preferably performed. Heat treatment can further reduce water or hydrogen in insulators 105, 103, and 104. In some cases, excess oxygen can be contained in insulator 104. This heat treatment can be performed at a temperature of 250°C to 650°C, preferably 450°C to 600°C, and more preferably 520°C to 570°C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more. The heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an inert gas atmosphere followed by another heat treatment in an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more to replace the released oxygen. Heat treatment can improve the crystallinity of the insulator (to become insulator 106a) and the semiconductor (to become semiconductor 106b), and can also remove impurities such as hydrogen and water. For heat treatment, an RTA device using lamp heating can be used. Heat treatment using an RTA device can be completed in a shorter time than using a furnace, making it an effective method for improving productivity.

[0326] Note that when a semiconductor device layer is provided below the transistor 10, heating can be performed within a relatively low temperature range (e.g., a temperature range of approximately 350°C to 445°C). For example, it is preferable to set the temperature to be lower than the highest heating temperature of the substrate when forming the insulators 105, 103, and 104.

[0327] When a silicon halide such as SiF4 is used to form the insulator 104, the insulator 104 contains a halogen such as fluorine. It is presumed that during the heat treatment, oxygen in the insulator 104 is replaced by fluorine and released (SiO + F → SiF + O). This oxygen is then supplied to the insulator 106a and the semiconductor 106b. This mechanism is described below.

[0328] <Fluorine-containing silicon oxide> Next, silicon oxide containing fluorine as an example of an insulator containing excess oxygen is described with reference to Figures 74A and 74B.

[0329] Assume silicon oxide (SiO2) with two oxygen atoms for every silicon atom. As shown in Figure 74A, one silicon atom is bonded to four oxygen atoms. Furthermore, one oxygen atom is bonded to two silicon atoms.

[0330] When two fluorine atoms enter silicon oxide, the bond between one oxygen atom and the two silicon atoms is broken (…Si-O-Si…+2F →…Si- -O- -Si…+2F). The silicon atom whose bond with the oxygen atom was broken then bonds with a fluorine atom (…Si- -O- -Si…+2F →…Si- FF-Si…+O). At this point, the broken oxygen atom becomes excess oxygen (see Figure 74B).

[0331] The excess oxygen contained in silicon oxide can reduce oxygen vacancies in the oxide semiconductor. Oxygen vacancies in the oxide semiconductor act as hole traps, etc. Therefore, when silicon oxide contains excess oxygen, the transistor can have stable electrical characteristics.

[0332] When fluorine enters the silicon oxide, excess oxygen is generated. Note that when excess oxygen is consumed by reducing oxygen vacancies in the oxide semiconductor, the amount of oxygen in the silicon oxide decreases compared to before the fluorine enters.

[0333] In order to make the transistor have stable electrical characteristics and make its characteristics close to normally-off electrical characteristics, it is sufficient to make the silicon oxide contain sufficient excess oxygen.

[0334] Heat treatment Here, a method for controlling a furnace that can be used when performing heat treatment will be described with reference to Figures 75A to 75C. The heat treatment atmosphere described is merely an example and can be modified as appropriate.

[0335] Figure 75A shows an example of performing two heat treatments by switching the atmosphere. First, place the object to be processed in a furnace. Next, add nitrogen gas to the furnace and set the furnace temperature to the first temperature. Next, raise the temperature to the second temperature over one hour. Next, maintain the second temperature for one hour. Next, cool the temperature to the third temperature over one hour. Next, add nitrogen and oxygen gas to the furnace. Next, maintain the third temperature for one hour. Next, raise the temperature to the fourth temperature over one hour. Next, maintain the fourth temperature for one hour. Next, cool the temperature to the fifth temperature over one hour. Finally, remove the object from the furnace.

[0336] Note that the first, third, and fifth temperatures are within the temperature range (e.g., 50°C to 200°C) that allows for the insertion and removal of the workpiece. If the first, third, and fifth temperatures are too low, the cooling time becomes longer, potentially reducing productivity. If the first and fifth temperatures are too high, the workpiece may be damaged during insertion and removal. The second and fourth temperatures are the maximum temperatures for the heat treatment in each atmosphere (e.g., 250°C to 650°C). Throughout this specification, the term "heat treatment time" refers to the time during which the maximum temperature is maintained in each atmosphere.

[0337] In the method shown in FIG. 75A , it can be seen that when heating treatment is performed for 1 hour in each of the two atmospheres, a total of 7 hours is required.

[0338] Figure 75B shows an example of a single heat treatment without switching the atmosphere. First, place the object to be processed in the furnace. Next, add clean dry air (CDA) to the furnace and set the furnace temperature to the sixth temperature. CDA is air with a moisture content of 20 ppm or less, 1 ppm or less, or 10 ppb or less. Next, raise the temperature to the seventh temperature over one hour. Maintain the seventh temperature for two hours. Next, lower the temperature to the eighth temperature over one hour. Finally, remove the object from the furnace.

[0339] Note that the sixth and eighth temperatures are within the temperature range where the object to be processed can be placed in and taken out. The seventh temperature is the maximum temperature for the heat treatment under each atmosphere.

[0340] In the method shown in FIG. 75B , it can be seen that when the heating treatment is performed in one atmosphere for 2 hours, a total of 4 hours is required.

[0341] Figure 75C shows an example of a single heat treatment performed by switching the atmosphere. First, the object to be processed is placed in the furnace. Next, nitrogen gas is added to the furnace, and the furnace temperature is set to the ninth temperature. The temperature is then raised to the tenth temperature over one hour. The temperature is then maintained at the tenth temperature for one hour. Next, CDA is added to the furnace. The temperature is then maintained at the tenth temperature for one hour. The temperature is then lowered to the eleventh temperature over one hour. Finally, the object to be processed is removed from the furnace.

[0342] Note that the ninth and eleventh temperatures are within the temperature range where the object to be processed can be placed in and taken out. The tenth temperature is the maximum temperature of the heat treatment in each atmosphere.

[0343] In the method shown in FIG. 75C , it can be seen that when the heating treatment is performed for 2 hours in two atmospheres, a total of 4 hours is required.

[0344] By performing the heat treatment using the method shown in FIG75B and FIG75C, the heat treatment time can be shortened compared to the heat treatment time using the method shown in FIG75A. As a result, the productivity of semiconductor devices can be improved.

[0345] Next, a photoresist or the like is formed on the semiconductor, and the semiconductor is processed using the photoresist, thereby forming an insulator 106a and a semiconductor 106b (see FIG. 17E and FIG. 17F).

[0346] Next, heat treatment is preferably performed. Heat treatment can further reduce water or hydrogen in insulators 105, 103, and 104. In some cases, excess oxygen can be contained in insulator 104. This heat treatment can be performed at a temperature of 250°C to 650°C, preferably 450°C to 600°C, and more preferably 520°C to 570°C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more. The heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an inert gas atmosphere followed by another heat treatment in an atmosphere containing an oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more to replace the released oxygen. Heat treatment can improve the crystallinity of the insulator (to become insulator 106a) and the semiconductor (to become semiconductor 106b), and can also remove impurities such as hydrogen and water. For heat treatment, an RTA device using lamp heating can be used. Heat treatment using an RTA device can be completed in a shorter time than using a furnace, making it an effective method for improving productivity.

[0347] Note that when a semiconductor device layer is provided below the transistor 10, heating can be performed within a relatively low temperature range (e.g., a temperature range of approximately 350°C to 445°C). For example, it is preferable to set the temperature to be lower than the highest heating temperature of the substrate when forming the insulators 105, 103, and 104.

[0348] Next, an insulator 106c is formed (see FIG. 17G and FIG. 17H ). As the insulator 106c, any of the above-mentioned insulators or semiconductors that can be used as the insulator 106c can be used. The insulator 106c can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0349] Next, conductors to be the conductors 108a and 108b are formed. The conductors described above for the conductors 108a and 108b can be used. The conductors can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0350] Here, a low-resistance region 109 may be formed in a region near the conductor to be the conductor 108 of the semiconductor 106 b and the insulator 106 c.

[0351] Next, a photoresist or the like is formed on the conductor, and the conductor 108 is formed by processing using the photoresist.

[0352] Next, an insulator 113 is formed to serve as the insulator 110. The insulator 113 can be any of the above-described insulators that can be used as the insulator 110. The insulator 113 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0353] When the insulator 113 is formed, a portion of the top surface and side surfaces of the conductor 108 may be oxidized to form a metal oxide 111 (see FIG. 18A and FIG. 18B ).

[0354] Next, a photoresist or the like is formed over the insulator 113, and the photoresist is processed to form the insulator 110, the metal oxide 111a, the metal oxide 111b, the conductor 108a, and the conductor 108b (see FIG. 18C and FIG. 18D).

[0355] Next, high-density plasma treatment can be performed. High-density plasma treatment is preferably performed in an oxygen atmosphere. An oxygen atmosphere refers to a gas atmosphere containing oxygen atoms, generally referring to an atmosphere of oxygen, ozone, or nitrogen oxides (such as nitrogen monoxide, nitrogen dioxide, nitrous oxide, nitrogen trioxide, nitrogen tetroxide, or nitrogen pentoxide). Alternatively, an oxygen atmosphere may contain an inert gas containing nitrogen or a rare gas (helium, argon, etc.). Performing high-density plasma treatment in an oxygen atmosphere in this manner can, for example, remove carbon, hydrogen, etc. Furthermore, performing high-density plasma treatment in an oxygen atmosphere can easily remove organic compounds such as hydrocarbons from the object being treated.

[0356] Annealing can also be performed before or after high-density plasma treatment. To increase the plasma density, it's sometimes desirable to introduce a sufficient amount of gas. If the amount of gas is insufficient, the deactivation rate of free radicals may outpace the generation rate. For example, introducing a gas flow rate of 100 sccm or more, 300 sccm or more, or even 800 sccm or more is sometimes desirable.

[0357] For example, high-density plasma processing can use microwaves generated by a high-frequency generator with a frequency of 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz (typically 2.45 GHz). Furthermore, the processing pressure can be set to 10 Pa to 5000 Pa, preferably 200 Pa to 1500 Pa, and more preferably 300 Pa to 1000 Pa. The substrate temperature can be set to 100°C to 600°C (typically 400°C), and a mixed gas of oxygen and argon can be used.

[0358] For example, by using 2.45 GHz microwaves to generate high-density plasma, the electron density is preferably between 1×10⁻¹⁰ / cm³ and 1×10⁻¹³ / cm³, the electron temperature is preferably below 2 eV, and the ion energy is preferably below 5 eV. This high-density plasma treatment has low kinetic energy of free radicals, resulting in less plasma damage than conventional plasma treatments. Consequently, films with fewer defects can be formed. The distance from the microwave-generating antenna to the object being treated is preferably between 5 mm and 120 mm, more preferably between 20 mm and 60 mm.

[0359] Alternatively, a plasma power source can be provided to apply an RF (Radio Frequency) bias to the substrate. For example, the RF bias frequency can be 13.56 MHz or 27.12 MHz. High-density plasma can generate a high density of oxygen ions, and applying the RF bias to the substrate allows the oxygen ions generated by the high-density plasma to be efficiently introduced into the workpiece. Furthermore, oxygen ions can be efficiently introduced into openings with high aspect ratios. Therefore, it is preferred to perform high-density plasma treatment while applying the bias to the substrate.

[0360] Alternatively, annealing can be performed continuously after high-density plasma treatment without exposure to air. High-density plasma treatment can also be performed continuously after annealing without exposure to air. By performing high-density plasma treatment and annealing sequentially, impurity incorporation during the treatment period can be suppressed. Furthermore, by performing annealing after high-density plasma treatment in an oxygen atmosphere, unnecessary oxygen that is not used to fill oxygen vacancies in the oxygen added to the treated object can be removed. Furthermore, the annealing can be performed, for example, using lamp annealing.

[0361] In addition, the processing time of the high-density plasma treatment is preferably 30 seconds to 120 minutes, 1 minute to 90 minutes, 2 minutes to 30 minutes, or 3 minutes to 15 minutes.

[0362] In addition, the annealing treatment temperature is preferably 250°C to 800°C, 300°C to 700°C, or 400°C to 600°C, and the treatment time is preferably 30 seconds to 120 minutes, 1 minute to 90 minutes, 2 minutes to 30 minutes, or 3 minutes to 15 minutes.

[0363] By performing high-density plasma treatment and / or annealing, the defect energy levels in the region that will become the channel formation region of semiconductor 106b can be reduced. In other words, the channel formation region can be made highly pure. At this point, a portion of low-resistance region 109 is also rendered highly resistive, dividing it into low-resistance region 109a and low-resistance region 109b. Furthermore, metal oxides 111a and 111b are formed on the side surfaces of conductors 108a and 108b (see Figures 18E and 18F).

[0364] Next, the insulator 132 is formed. The insulator 132 can be any of the insulators described above that can be used as the insulator 112. The insulator 132 can be formed using sputtering, CVD, MBE, PLD, ALD, or the like. By forming the insulator 126c and the insulator 132 successively without exposure to the atmosphere, incorporation of impurities into the films and at the interfaces can be suppressed.

[0365] Next, the conductor 134 is formed (see FIG. 19A and FIG. 19B ). The conductor 134 can be any of the conductors described above for the conductor 114. The conductor 134 can be formed using sputtering, CVD, MBE, PLD, ALD, or the like. By forming the insulator 132 and the conductor 134 successively without exposure to the atmosphere, the incorporation of impurities into the film and at the interface can be suppressed.

[0366] Next, conductor 134, insulator 132, and insulator 113 are polished until insulator 113 is exposed, thereby forming conductor 114, insulator 112, and insulator 110 (see Figures 19C and 19D). Conductor 114 and insulator 112 respectively function as the gate electrode and gate insulator of transistor 29. This method allows for the self-aligned formation of conductor 114 and insulator 112.

[0367] Next, an insulator 116 is formed (see FIG. 19E and FIG. 19F ). The above-described insulators can be used as the insulator 116. The insulator 116 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0368] Next, a heat treatment is preferably performed.

[0369] Through the above process, a transistor according to one embodiment of the present invention can be manufactured.

[0370] By forming a transistor using the method described in this embodiment, the supply of water, hydrogen, etc. to the semiconductor 106b and the like can be suppressed. Consequently, a transistor having stable electrical characteristics can be provided. Furthermore, a transistor having low leakage current in the off state can be provided. Furthermore, a transistor having normally-off electrical characteristics can be provided. Furthermore, a transistor having a small subthreshold swing value can be provided. Furthermore, a transistor having high reliability can be provided.

[0371] Furthermore, by manufacturing a transistor using the method shown in this embodiment, since the heat treatment within a relatively low temperature range can suppress the supply of water, hydrogen, etc. to the semiconductor 106b, etc., even if a semiconductor element layer or a wiring layer is formed in a layer below the transistor, the transistor can be manufactured without causing the semiconductor element layer or the wiring layer to deteriorate due to high temperature.

[0372] The structure and method described in this embodiment can be used in combination with the structure and method described in other embodiment modes as appropriate.

[0373] Implementation 3 Manufacturing equipment Next, a manufacturing apparatus for performing high-density plasma processing according to one embodiment of the present invention will be described.

[0374] First, the structure of a manufacturing apparatus with little impurity contamination when manufacturing semiconductor devices and the like will be described with reference to FIG. 20 , FIG. 21 , and FIG. 22 .

[0375] FIG20 is a schematic top view of a single wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric-side substrate supply chamber 2701 equipped with a cassette port 2761 for storing substrates and an alignment port 2762 for performing substrate alignment; an atmospheric-side substrate transfer chamber 2702 for transferring substrates from the atmospheric-side substrate supply chamber 2701; a load-lock chamber 2703a for loading substrates and switching the pressure within the chamber from atmospheric pressure to reduced pressure or vice versa; an unload-lock chamber 2703b for unloading substrates and switching the pressure within the chamber from reduced pressure to atmospheric pressure or vice versa; a transfer chamber 2704 for transferring substrates in a vacuum; and processing chambers 2706a, 2706b, 2706c, and 2706d.

[0376] In addition, the atmospheric side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the processing chambers 2706a, 2706b, 2706c, and 2706d.

[0377] Gate valves GV are installed at the connections between the chambers, allowing each chamber, except for the atmospheric-side substrate supply chamber 2701 and the atmospheric-side substrate transfer chamber 2702, to be independently maintained in a vacuum state. A transfer robot 2763a is installed in the atmospheric-side substrate transfer chamber 2702, and a transfer robot 2763b is installed in the transfer chamber 2704. Transfer robots 2763a and 2763b enable substrate transfer within the manufacturing apparatus 2700.

[0378] For example, the back pressure (total pressure) of the transfer chamber 2704 and each of the processing chambers 2706a to 2706d is set to 1×10-4 Pa or less, preferably 3×10-5 Pa or less, and more preferably 1×10-5 Pa or less. Furthermore, for example, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each of the processing chambers 2706a to 2706d is set to 3×10-5 Pa or less, preferably 1×10-5 Pa or less, and more preferably 3×10-6 Pa or less. Furthermore, for example, the partial pressure of gas molecules (atoms) with an m / z of 28 in the transfer chamber 2704 and each of the processing chambers 2706a to 2706d is set to 3×10-5 Pa or less, preferably 1×10-5 Pa or less, and more preferably 3×10-6 Pa or less. In addition, for example, the partial pressure of gas molecules (atoms) with m / z 44 in the transfer chamber 2704 and each processing chamber 2706a to 2706d is set to below 3×10-5Pa, preferably below 1×10-5Pa, and more preferably below 3×10-6Pa.

[0379] The total pressure and partial pressure in the transfer chamber 2704 and each of the process chambers 2706a to 2706d can be measured using a mass analyzer. For example, a quadrupole mass analyzer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0380] Furthermore, it is preferred that the transfer chamber 2704 and each of the processing chambers 2706a to 2706d have minimal external and internal leakage. For example, the leak rate of the transfer chamber 2704 and each of the processing chambers 2706a to 2706d is set to 3×10-6 Pa.m3 / s or less, preferably 1×10-6 Pa.m3 / s or less. Furthermore, for example, the leak rate of gas molecules (atoms) with an m / z of 18 is set to 1×10-7 Pa.m3 / s or less, preferably 3×10-8 Pa.m3 / s or less. Furthermore, for example, the leak rate of gas molecules (atoms) with an m / z of 28 is set to 1×10-5 Pa.m3 / s or less, preferably 1×10-6 Pa.m3 / s or less. In addition, for example, the leakage rate of gas molecules (atoms) with m / z of 44 is set to 3×10-6 Pa.m3 / s or less, preferably to 1×10-6 Pa.m3 / s or less.

[0381] Note that the leak rate can be calculated from the total and partial pressures measured by the mass analyzer. The leak rate is determined by both external and internal leakage. External leakage refers to the inflow of gas from outside the vacuum system due to microscopic holes or poor seals. Internal leakage is caused by leakage from valves and other partitions within the vacuum system or by outgassing from internal components. To keep the leak rate below the above values, measures must be taken to address both external and internal leakage.

[0382] For example, it is preferable to use metal gaskets to seal the openings and closings of the transfer chamber 2704 and each of the processing chambers 2706a to 2706d. Metal gaskets preferably use metals coated with ferric fluoride, aluminum oxide, or chromium oxide. Metal gaskets offer greater tightness than O-rings, thus reducing external leakage. By using passive metals coated with ferric fluoride, aluminum oxide, or chromium oxide, the release of gases containing impurities from the metal gaskets can be suppressed, thereby reducing internal leakage.

[0383] The components of manufacturing apparatus 2700 are made of aluminum, chromium, titanium, zirconium, nickel, or vanadium, which contain impurities and release low amounts of gas. These components can also be coated with alloys containing iron, chromium, or nickel. Alloys containing iron, chromium, or nickel are rigid, heat-resistant, and suitable for processing. Polishing or other methods can be used to reduce surface irregularities and surface area, thereby reducing released gas.

[0384] Alternatively, the components of the manufacturing apparatus 2700 may be covered with ferric fluoride, aluminum oxide, chromium oxide, or the like.

[0385] The components of the manufacturing device 2700 are preferably made of metal as much as possible. For example, when a viewing window made of quartz or the like is provided, in order to suppress the release of gas, it is preferable to cover the surface of the viewing window with a thin layer of iron fluoride, aluminum oxide or chromium oxide.

[0386] Although adsorbed matter within the transfer chamber 2704 and each processing chamber 2706a through 2706d adheres to the inner walls and does not affect the pressure of the transfer chamber 2704 and each processing chamber 2706a through 2706d, it does contribute to the release of gases during evacuation of the transfer chamber 2704 and each processing chamber 2706a through 2706d. Therefore, while the leakage rate is unrelated to the evacuation speed, it is crucial to use a high-capacity pump to remove as much adsorbed matter as possible from the transfer chamber 2704 and each processing chamber 2706a through 2706d and to pre-evacuate the chamber. To facilitate the removal of adsorbed matter, the transfer chamber 2704 and each processing chamber 2706a through 2706d can be baked. This baking process can increase the adsorbed matter removal rate by approximately 10 times. Baking can be performed at a temperature of 100°C to 450°C. At this time, by introducing an inert gas into the transfer chamber 2704 and each of the processing chambers 2706a to 2706d while removing adsorbed materials, the removal rate of water, which is difficult to remove by exhaust alone, can be further increased. Heating the introduced inert gas to a temperature comparable to the baking temperature can further increase the removal rate of adsorbed materials. Here, a noble gas is preferably used as the inert gas.

[0387] Furthermore, it is preferred to increase the pressure within the transfer chamber 2704 and each of the processing chambers 2706a to 2706d by introducing an inert gas such as a heated rare gas or oxygen, and then vent the transfer chamber 2704 and each of the processing chambers 2706a to 2706d again after a certain period of time. The introduction of the heated gas can desorb adsorbed matter within the transfer chamber 2704 and each of the processing chambers 2706a to 2706d, thereby reducing impurities within the transfer chamber 2704 and each of the processing chambers 2706a to 2706d. This process is effectively repeated two to thirty times, preferably five to fifteen times. Specifically, an inert gas or oxygen, etc., at a temperature of 40°C to 400°C, preferably 50°C to 200°C, is introduced to set the pressure within the transfer chamber 2704 and each of the processing chambers 2706a to 2706d to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa. The pressure is maintained for a period of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. The transfer chamber 2704 and each of the processing chambers 2706a to 2706d are then evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0388] Next, the processing chamber 2706b and the processing chamber 2706c will be described with reference to the cross-sectional schematic diagram shown in FIG. 21 .

[0389] For example, processing chambers 2706b and 2706c are chambers capable of performing high-density plasma treatment on a workpiece. The only difference between processing chambers 2706b and 2706c is the atmosphere during high-density plasma treatment. Because the other structures of processing chambers 2706b and 2706c are identical, they will be described together below.

[0390] Processing chambers 2706b and 2706c include a slot antenna plate 2808, a dielectric plate 2809, a substrate stage 2812, and an exhaust port 2819. Furthermore, outside processing chambers 2706b and 2706c, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0391] The high-frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is arranged in contact with the dielectric plate 2809. Furthermore, a gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is introduced into the processing chambers 2706b and 2706c via a gas pipe 2806 passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. A vacuum pump 2817 exhausts gas from the processing chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. Furthermore, a high-frequency power source 2816 is connected to the substrate stage 2812 via a matching unit 2815.

[0392] The substrate stage 2812 has the function of holding the substrate 2811. For example, the substrate stage 2812 has the function of electrostatically or mechanically chuck- ing the substrate 2811. Furthermore, the substrate stage 2812 functions as an electrode to which power is supplied by a high-frequency power supply 2816. Furthermore, the substrate stage 2812 includes a heating mechanism 2813 therein and has the function of heating the substrate 2811.

[0393] As vacuum pump 2817, for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used. In addition to vacuum pump 2817, a cryogenic cold trap can also be used. Using a cryogenic cold trap is particularly preferred because it allows for efficient water removal.

[0394] As the heating mechanism 2813, for example, a heating mechanism using a resistance heating element or the like can be used. Alternatively, a heating mechanism using heat conduction or heat radiation from a heated medium such as a gas can be used. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA uses high-temperature gas for heating. An inert gas is used as the gas.

[0395] In addition, the gas supply source 2801 can be connected to the purifier via a mass flow controller. Gases with a dew point of -80°C or lower, preferably -100°C or lower, are preferably used. For example, oxygen, nitrogen, and rare gases (such as argon) can be used.

[0396] For example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide can be used for dielectric plate 2809. Furthermore, another protective layer may be formed on the surface of dielectric plate 2809. Examples of such protective layers include magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because dielectric plate 2809 is exposed to the particularly high-density region of high-density plasma 2810, described later, the provision of a protective layer can mitigate damage. This, in turn, can suppress the increase in particles during processing.

[0397] High-frequency generator 2803 has the function of generating microwaves, for example, at frequencies between 0.3 GHz and 3.0 GHz, between 0.7 GHz and 1.1 GHz, or between 2.2 GHz and 2.8 GHz. The microwaves generated by high-frequency generator 2803 are transmitted to mode converter 2805 via waveguide 2804. Mode converter 2805 converts the transmitted TE-mode microwaves into TEM-mode microwaves. These microwaves are then transmitted to slot antenna plate 2808 via waveguide 2807. Slot antenna plate 2808 has multiple slots, and the microwaves pass through these slots and dielectric plate 2809. An electric field is then generated beneath dielectric plate 2809, generating high-density plasma 2810. High-density plasma 2810 contains ions and radicals based on the type of gas supplied from gas supply source 2801. For example, high-density plasma 2810 contains oxygen radicals or nitrogen radicals.

[0398] At this time, the film on substrate 2811 can be improved by utilizing the ions and radicals generated in high-density plasma 2810. Furthermore, it may be desirable to apply a bias voltage to one side of substrate 2811 using high-frequency power source 2816. For example, an RF (Radio Frequency) power source with a frequency of 13.56 MHz or 27.12 MHz can be used as high-frequency power source 2816. Applying a bias voltage to the substrate side allows the ions in high-density plasma 2810 to efficiently reach deep within openings in the film on substrate 2811.

[0399] For example, in the processing chamber 2706b, oxygen radical treatment using the high-density plasma 2810 can be performed by introducing oxygen from the gas supply source 2801, and in the processing chamber 2706c, nitrogen radical treatment using the high-density plasma 2810 can be performed by introducing nitrogen from the gas supply source 2801.

[0400] Next, the processing chamber 2706a and the processing chamber 2706d will be described with reference to the cross-sectional schematic diagram shown in FIG. 22 .

[0401] For example, processing chambers 2706a and 2706d are chambers capable of irradiating an object with electromagnetic waves. The only difference between processing chambers 2706a and 2706d is the type of electromagnetic waves used. Because the other structures of processing chambers 2706a and 2706d are common, they will be described together below.

[0402] The processing chamber 2706a and the processing chamber 2706d include one or more lamps 2820, a substrate stage 2825, a gas inlet 2823, and an exhaust port 2830. Furthermore, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the processing chamber 2706a and the processing chamber 2706d.

[0403] A gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. A vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is positioned opposite a substrate stage 2825. The substrate stage 2825 holds a substrate 2824. Furthermore, the substrate stage 2825 includes a heating mechanism 2826 therein, which heats the substrate 2824.

[0404] For example, a light source capable of emitting electromagnetic waves such as visible light or ultraviolet light can be used as the lamp 2820. For example, a light source capable of emitting electromagnetic waves having a peak in a wavelength range of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm can be used.

[0405] For example, as the lamp 2820, a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp can be used.

[0406] For example, by partially or entirely absorbing the electromagnetic waves emitted from lamp 2820 into substrate 2824, the quality of the film or the like on substrate 2824 can be improved. For example, defects can be generated or reduced, or impurities can be removed. Furthermore, by generating or reducing defects or removing impurities while heating substrate 2824, defects can be generated or reduced, or impurities can be removed efficiently.

[0407] Alternatively, for example, the substrate stage 2825 may be heated by electromagnetic waves radiated from the lamp 2820 to heat the substrate 2824. In this case, the heating mechanism 2826 does not need to be included in the substrate stage 2825.

[0408] The vacuum pump 2828 can refer to the description of the vacuum pump 2817. The heating mechanism 2826 can refer to the description of the heating mechanism 2813. The gas supply source 2821 can refer to the description of the gas supply source 2801.

[0409] By using the above-mentioned manufacturing apparatus, it is possible to suppress the mixing of impurities into the treated object and improve the film quality.

[0410] The structure and method described in this embodiment can be used in combination with the structure and method described in other embodiment modes as appropriate.

[0411] Implementation 4 In this embodiment, an example of a circuit using a semiconductor device such as a transistor according to one embodiment of the present invention is described. Circuit Next, an example of a circuit using a semiconductor device such as a transistor according to one embodiment of the present invention will be described.

[0412] CMOS Inverter The circuit diagram shown in FIG. 23A shows the structure of a so-called CMOS inverter, in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series, and their gates are connected.

[0413] <Structure of Semiconductor Device> FIG24 is a cross-sectional view of the semiconductor device corresponding to FIG23A. The semiconductor device shown in FIG24 includes a transistor 2200 and a transistor 2100. Transistor 2100 is arranged above transistor 2200. Note that while the example here uses transistor 20 shown in FIG9A and FIG9B as transistor 2100, the semiconductor device of one embodiment of the present invention is not limited to this. Any of the transistors shown in the above embodiments can be used as transistor 2100. Therefore, regarding transistor 2100, reference should be made to the description of the above transistors as appropriate.

[0414] 24 is a transistor using a semiconductor substrate 450 . The transistor 2200 includes a region 472 a in the semiconductor substrate 450 , a region 472 b in the semiconductor substrate 450 , an insulator 462 , and a conductor 454 .

[0415] In transistor 2200, regions 472a and 472b function as source and drain regions. Furthermore, insulator 462 functions as a gate insulator. Furthermore, conductor 454 functions as a gate electrode. Therefore, the resistance of the channel-forming region can be controlled by the potential applied to conductor 454. In other words, the conduction / non-conduction between regions 472a and 472b can be controlled by the potential applied to conductor 454.

[0416] As the semiconductor substrate 450, for example, a single-material semiconductor substrate made of silicon or germanium, or a semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be used. Preferably, a single-crystal silicon substrate is used as the semiconductor substrate 450.

[0417] A semiconductor substrate containing impurities imparting n-type conductivity is used as semiconductor substrate 450. Note that a semiconductor substrate containing impurities imparting p-type conductivity may also be used as semiconductor substrate 450. In this case, a well containing impurities imparting n-type conductivity may be provided in the region where transistor 2200 is formed. Alternatively, semiconductor substrate 450 may be i-type.

[0418] The top surface of the semiconductor substrate 450 preferably has a (110) plane, thereby improving the conduction characteristics of the transistor 2200.

[0419] Regions 472a and 472b contain impurities imparting p-type conductivity. Thus, transistor 2200 has a p-channel structure.

[0420] Note that the transistor 2200 is separated from adjacent transistors by a region 460 or the like. The region 460 has insulating properties.

[0421] The semiconductor device shown in Figure 24 includes insulator 464, insulator 466, insulator 468, conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, insulator 489, insulator 490, insulator 491, insulator 492, insulator 493 and insulator 494.

[0422] Insulator 464 is disposed on transistor 2200. Insulator 466 is disposed on insulator 464. Insulator 468 is disposed on insulator 466. Insulator 489 is disposed on insulator 468. Transistor 2100 is disposed on insulator 489. Insulator 493 is disposed on transistor 2100. Insulator 494 is disposed on insulator 493.

[0423] The insulator 464 includes an opening that reaches the region 472a, an opening that reaches the region 472b, and an opening that reaches the conductor 454. The conductor 480a, the conductor 480b, or the conductor 480c is filled in each of the openings.

[0424] The insulator 466 includes an opening that reaches the conductor 480a, an opening that reaches the conductor 480b, and an opening that reaches the conductor 480c. The conductor 478a, the conductor 478b, or the conductor 478c is filled in each opening.

[0425] The insulator 468 includes an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The conductor 476a or the conductor 476b is filled in each opening.

[0426] The insulator 489 includes an opening that overlaps with the channel forming region of the transistor 2100, an opening that reaches the conductor 476a, and an opening that reaches the conductor 476b. Each opening is filled with the conductor 474a, the conductor 474b, or the conductor 474c.

[0427] Conductor 474a can also function as the gate electrode of transistor 2100. Alternatively, for example, by applying a fixed potential to conductor 474a, the electrical characteristics of transistor 2100, such as the threshold voltage, can be controlled. Alternatively, for example, conductor 474a can be electrically connected to conductor 504, which functions as the gate electrode of transistor 2100. This can increase the on-state current of transistor 2100. Furthermore, since punch-through can be suppressed, the electrical characteristics of transistor 2100 in the saturation region can be stabilized. Since conductor 474a corresponds to conductor 102 in the above-described embodiment, its details can be referred to the description of conductor 102.

[0428] The insulator 490 includes an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. Note that since the insulator 490 corresponds to the insulator 103 described in the above embodiment, its details can be referred to the description of the insulator 103. As described in the above embodiment, by providing the insulator 490 so as to cover the conductors 474a to 474c except for the openings, the conductors 474a to 474c can be prevented from extracting oxygen from the insulator 491. This allows oxygen to be efficiently supplied from the insulator 491 to the oxide semiconductor of the transistor 2100.

[0429] The insulator 491 includes an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. Note that since the insulator 491 corresponds to the insulator 104 described in the above embodiment mode, the details thereof can be referred to the description of the insulator 104.

[0430] As described in the above embodiment, by reducing the water or hydrogen content of the insulator 491, the formation of defect levels in the oxide semiconductor of the transistor 2100 can be suppressed. As a result, the electrical characteristics of the transistor 2100 can be stabilized.

[0431] Furthermore, this insulator with reduced water or hydrogen content can be used not only for the insulator 491 but also for other insulators. For example, this insulator can be used for the insulator 466, the insulator 468, the insulator 489, the insulator 493, and the like.

[0432] Although FIG24 does not illustrate insulators equivalent to insulator 105 and insulator 101 in transistor 20, these insulators may be provided. For example, an insulator equivalent to insulator 101 may be provided between insulator 468 and insulator 489, or an insulator equivalent to insulator 105 may be provided between insulator 489 and insulator 490. In particular, by providing an insulator equivalent to insulator 101 between insulator 468 and insulator 489 that has a function of blocking water, hydrogen, etc., and thereby reducing the water or hydrogen content of insulator 491 as described above, the formation of defect levels in the oxide semiconductor of transistor 2100 can be further suppressed.

[0433] Insulator 492 includes an opening that passes through conductor 516b, one of the source and drain electrodes of transistor 2100, and reaches conductor 474b; an opening that reaches conductor 516a, the other of the source and drain electrodes of transistor 2100; an opening that reaches conductor 504, the gate electrode of transistor 2100; and an opening that reaches conductor 474c. Note that insulator 492 corresponds to insulator 116 in the above embodiment, and therefore, for details thereof, refer to the description of insulator 116.

[0434] Insulator 493 includes an opening that passes through conductor 516b, one of the source and drain electrodes of transistor 2100, and reaches conductor 474b; an opening that reaches conductor 516a, the other of the source and drain electrodes of transistor 2100; an opening that reaches conductor 504, the gate electrode of transistor 2100; and an opening that reaches conductor 474c. Conductor 496a, conductor 496b, conductor 496c, or conductor 496d fills each opening. Note that each opening may sandwich an opening included in any component, such as transistor 2100.

[0435] The insulator 494 includes an opening that reaches the conductor 496a, an opening that reaches the conductor 496b and the conductor 496d, and an opening that reaches the conductor 496c. Each opening is filled with the conductor 498a, the conductor 498b, or the conductor 498c.

[0436] As insulator 464, insulator 466, insulator 468, insulator 489, insulator 493 and insulator 494, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used.

[0437] Preferably, at least one of insulators 464, 466, 468, 489, 493, and 494 has a function of blocking impurities such as hydrogen and oxygen. Providing an insulator that blocks impurities such as hydrogen and oxygen near transistor 2100 stabilizes the electrical characteristics of transistor 2100.

[0438] As an insulator having the function of blocking impurities such as hydrogen and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used.

[0439] As conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, conductor 498a, conductor 498b and conductor 498c, for example, a single layer or a stack of conductors containing one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and tungsten can be used. For example, alloys or compounds may be used, and conductors containing aluminum, copper and titanium, copper and manganese, indium, tin, and oxygen, titanium and nitrogen, etc. may also be used.

[0440] Note that the semiconductor device shown in FIG25 differs from the semiconductor device shown in FIG24 only in the structure of transistor 2200. Therefore, the description of the semiconductor device shown in FIG25 refers to the description of the semiconductor device shown in FIG24. Specifically, in the semiconductor device shown in FIG25, transistor 2200 is a Fin-type transistor. By making transistor 2200 a Fin-type transistor, the effective channel width is increased, thereby improving the on-state characteristics of transistor 2200. Furthermore, since the influence of the electric field on the gate electrode is increased, the off-state characteristics of transistor 2200 are improved.

[0441] The semiconductor device shown in FIG26 differs from the semiconductor device shown in FIG24 only in the structure of transistor 2200. Therefore, the description of the semiconductor device shown in FIG24 will be referred to for the semiconductor device shown in FIG26. Specifically, in the semiconductor device shown in FIG26, transistor 2200 is provided on semiconductor substrate 450, which is an SOI substrate. FIG26 shows a structure in which region 456 and semiconductor substrate 450 are separated by insulator 452. By using an SOI substrate as semiconductor substrate 450, punch-through and other phenomena can be suppressed, thereby improving the off-state characteristics of transistor 2200. Note that insulator 452 can be formed by insulating semiconductor substrate 450. For example, silicon oxide can be used as insulator 452.

[0442] In the semiconductor devices shown in Figures 24 to 26 , because the p-channel transistor is formed using a semiconductor substrate and the n-channel transistor is formed above it, the area occupied by the components can be reduced. This means that the integration density of the semiconductor device can be increased. Furthermore, compared to forming both n-channel and p-channel transistors using the same semiconductor substrate, the manufacturing process can be simplified, thereby improving the productivity of the semiconductor device. Furthermore, the yield of the semiconductor device can be improved. Furthermore, the p-channel transistor can sometimes omit complex manufacturing processes such as forming an LDD (Lightly Doped Drain) region, forming a shallow trench structure, or designing a curved structure. Therefore, compared to semiconductor devices in which n-channel transistors are formed using a semiconductor substrate, the semiconductor devices shown in Figures 24 to 26 can sometimes improve productivity and yield.

[0443] CMOS Analog Switch 23B shows a structure in which the source and drain of transistors 2100 and 2200 are connected. By adopting this structure, the function of a so-called CMOS analog switch can be realized.

[0444] 〈Memory device 1〉 27A to 27C illustrate an example of a semiconductor device (memory device) using a transistor according to one embodiment of the present invention, which can retain stored data even when power is lost and has no limit on the number of write operations.

[0445] 27A includes a transistor 3200 using a first semiconductor, a transistor 3300 using a second semiconductor, and a capacitor 3400. The transistor 3300 can be the same as the transistor 2100 described above.

[0446] Transistor 3300 preferably uses a transistor with low off-state current. For example, transistor 3300 may be a transistor comprising an oxide semiconductor. Because transistor 3300 has a low off-state current, it is possible to maintain memory data at a specific node in the semiconductor device for a long period of time. This eliminates the need for refresh operations or allows for extremely low refresh frequency, resulting in a low-power semiconductor device.

[0447] In FIG27A , first wiring 3001 is electrically connected to the source of transistor 3200, and second wiring 3002 is electrically connected to the drain of transistor 3200. Furthermore, third wiring 3003 is electrically connected to one of the source and drain of transistor 3300, and fourth wiring 3004 is electrically connected to the gate of transistor 3300. Furthermore, the gate of transistor 3200 and the other of the source and drain of transistor 3300 are electrically connected to one electrode of capacitor 3400, and fifth wiring 3005 is electrically connected to the other electrode of capacitor 3400.

[0448] The semiconductor device shown in FIG27A has a feature of being able to maintain the potential of the gate of the transistor 3200, thereby enabling writing, retaining, and reading of information as shown below.

[0449] The writing and retention of information will be described. First, the potential of the fourth wiring 3004 is set to a potential that puts transistor 3300 into the on state, thereby placing transistor 3300 in the on state. Consequently, the potential of the third wiring 3003 is applied to node FG, which is electrically connected to the gate of transistor 3200 and one electrode of capacitor 3400. In other words, a predetermined charge is applied to the gate of transistor 3200 (writing). Here, one of two different levels of charge (hereinafter referred to as low-level charge and high-level charge) is applied. Then, by setting the potential of the fourth wiring 3004 to a potential that puts transistor 3300 into the off state, transistor 3300 is placed in the off state, and node FG is retained (retention).

[0450] Since the off-state current of transistor 3300 is small, the charge of node FG is maintained for a long time.

[0451] Next, the reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring 3005 while a prescribed potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a potential corresponding to the amount of charge held in the node FG. This is because: when the transistor 3200 is an n-channel transistor, the apparent threshold voltage Vth_H when a high-level charge is applied to the gate of the transistor 3200 is lower than the apparent threshold voltage Vth_L when a low-level charge is applied to the gate of the transistor 3200. Here, the apparent threshold voltage means the potential of the fifth wiring 3005 required to make the transistor 3200 into a "conducting state". Thus, by setting the potential of the fifth wiring 3005 to a potential V0 between Vth_H and Vth_L, the charge applied to the node FG can be discriminated. For example, when the node FG is supplied with a high-level charge during writing, if the potential of the fifth wiring 3005 is V0 (>Vth_H), the transistor 3200 becomes a "conducting state". On the other hand, when the node FG is supplied with a low-level charge, even if the potential of the fifth wiring 3005 is V0 (<Vth_L), the transistor 3200 remains in a "non-conducting state". Therefore, by discriminating the potential of the second wiring 3002, the information held in the node FG can be read.

[0452] Note that when the memory cells are arranged in an array, the information of the desired memory cell must be read during reading. For example, in a memory cell where information is not read, a potential that makes the transistor 3200 into a "non-conducting state" regardless of the charge applied to the node FG, that is, a potential lower than Vth_H, is applied to the fifth wiring 3005 to read only the information of the desired memory cell. Or, in a memory cell where information is not read, a potential that makes the transistor 3200 into a "conducting state" regardless of the charge applied to the node FG, that is, a potential higher than Vth_L, is applied to the fifth wiring 3005 to read only the information of the desired memory cell.

[0453] Note that although an example where two kinds of charges are held in the node FG is shown above, the semiconductor device of the present invention is not limited thereto. For example, three or more kinds of charges can be held in the node FG of the semiconductor device. By adopting the above structure, multi-levels of the semiconductor device can be realized, and the memory capacity can be increased.

[0454] <Structure of Memory Device 1> FIG28 is a cross-sectional view of the semiconductor device corresponding to FIG27A . The semiconductor device shown in FIG28 includes a transistor 3200, a transistor 3300, and a capacitor 3400. Transistor 3300 and capacitor 3400 are arranged above transistor 3200. Regarding transistor 3300, refer to the description of transistor 2100 described above. Regarding transistor 3200, refer to the description of transistor 2200 shown in FIG24 . FIG24 illustrates the case where transistor 2200 is a p-channel transistor, but transistor 3200 may also be an n-channel transistor.

[0455] 28 is a transistor using a semiconductor substrate 450 . The transistor 3200 includes a region 472 a in the semiconductor substrate 450 , a region 472 b in the semiconductor substrate 450 , an insulator 462 , and a conductor 454 .

[0456] The semiconductor device shown in Figure 28 includes insulator 464, insulator 466, insulator 468, conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, insulator 489, insulator 490, insulator 491, insulator 492, insulator 493 and insulator 494.

[0457] Insulator 464 is disposed on transistor 3200. Insulator 466 is disposed on insulator 464. Insulator 468 is disposed on insulator 466. Insulator 489 is disposed on insulator 468. Transistor 3300 is disposed on insulator 489. Insulator 493 is disposed on transistor 3300. Insulator 494 is disposed on insulator 493.

[0458] The insulator 464 includes an opening that reaches the region 472a, an opening that reaches the region 472b, and an opening that reaches the conductor 454. The conductors 480a, 480b, and 480c are respectively filled in the respective openings.

[0459] The insulator 466 includes an opening that reaches the conductor 480a, an opening that reaches the conductor 480b, and an opening that reaches the conductor 480c. The conductors 478a, 478b, and 478c are filled in each of the openings.

[0460] The insulator 468 includes an opening that reaches the conductor 478b and an opening that reaches the conductor 478c. The conductors 476a and 476b are respectively filled in the respective openings.

[0461] The insulator 489 includes an opening that overlaps with the channel forming region of the transistor 3300, an opening that reaches the conductor 476a, and an opening that reaches the conductor 476b. The conductors 474a, 474b, and 474c are respectively filled in the openings.

[0462] Conductor 474a can function as the bottom gate electrode of transistor 3300. Alternatively, for example, by applying a predetermined potential to conductor 474a, electrical characteristics such as the threshold voltage of transistor 3300 can be controlled. Alternatively, for example, conductor 474a can be electrically connected to conductor 504, which serves as the top gate electrode of transistor 3300. This can increase the on-state current of transistor 3300. Furthermore, since punch-through can be suppressed, the electrical characteristics of transistor 3300 in the saturation region can be stabilized.

[0463] Insulator 490 includes an opening that reaches conductor 474b and an opening that reaches conductor 474c. Note that since insulator 490 corresponds to insulator 103 described in the above embodiment, its details can be referred to the description of insulator 103. As described in the above embodiment, by providing insulator 490 to cover conductors 474a to 474c except for the openings, it is possible to prevent conductors 474a to 474c from extracting oxygen from insulator 491. This allows oxygen to be efficiently supplied from insulator 491 to the oxide semiconductor of transistor 3300.

[0464] The insulator 491 includes an opening that reaches the conductor 474b and an opening that reaches the conductor 474c. Note that since the insulator 491 corresponds to the insulator 104 described in the above embodiment mode, its details can be referred to the description of the insulator 104.

[0465] As described in the above embodiment, by reducing the water or hydrogen content of the insulator 491, the formation of defect levels in the oxide semiconductor of the transistor 2100 can be suppressed. As a result, the electrical characteristics of the transistor 2100 can be stabilized.

[0466] Furthermore, this insulator with reduced water or hydrogen content can be used not only for the insulator 491 but also for other insulators. For example, this insulator can be used for the insulator 466, the insulator 468, the insulator 489, the insulator 493, and the like.

[0467] Although FIG24 does not illustrate insulators equivalent to insulator 105 and insulator 101 in transistor 20, these insulators may be provided. For example, an insulator equivalent to insulator 101 may be provided between insulator 468 and insulator 489, or an insulator equivalent to insulator 105 may be provided between insulator 489 and insulator 490. In particular, by providing an insulator equivalent to insulator 101 between insulator 468 and insulator 489 that has a function of blocking water, hydrogen, etc., and thereby reducing the water or hydrogen content of insulator 491 as described above, the formation of defect levels in the oxide semiconductor of transistor 3300 can be further suppressed.

[0468] Insulator 492 includes an opening that passes through conductor 516b, one of the source and drain electrodes of transistor 3300, and reaches conductor 474b; an opening that reaches conductor 514, which overlaps with conductor 516a, the other of the source and drain electrodes of transistor 3300, via insulator 511; an opening that reaches conductor 504, which reaches the gate electrode of transistor 3300; and an opening that passes through conductor 516a, the other of the source and drain electrodes of transistor 3300, and reaches conductor 474c. Note that insulator 492 corresponds to insulator 116 described in the above embodiment mode. Therefore, for details, refer to the description of insulator 116.

[0469] Insulator 493 includes an opening that extends from conductor 516b, which passes through one of the source and drain electrodes of transistor 3300, to conductor 474b; an opening that extends from conductor 514, which overlaps with conductor 516a, which is the other of the source and drain electrodes of transistor 3300, across insulator 511; an opening that extends from conductor 504, which reaches the gate electrode of transistor 3300; and an opening that extends from conductor 516a, which passes through the other of the source and drain electrodes of transistor 3300, to conductor 474c. Conductors 496a, 496b, 496c, and 496d fill each of these openings. Note that each opening may sandwich an opening included in any component, such as transistor 3300.

[0470] The insulator 494 includes an opening that reaches the conductor 496a, an opening that reaches the conductor 496b, and an opening that reaches the conductor 496c. The conductors 498a, 498b, and 498c are filled in each of the openings.

[0471] Preferably, at least one of insulators 464, 466, 468, 489, 493, and 494 has a function of blocking impurities such as hydrogen and oxygen. Providing an insulator that blocks impurities such as hydrogen and oxygen near transistor 3300 stabilizes the electrical characteristics of transistor 3300.

[0472] The source or drain of transistor 3200 is electrically connected to conductor 516b, which is one of the source and drain electrodes of transistor 3300, via conductor 480b, conductor 478b, conductor 476a, conductor 474b, and conductor 496c. Conductor 454, which is the gate electrode of transistor 3200, is electrically connected to conductor 516a, which is the other of the source and drain electrodes of transistor 3300, via conductor 480c, conductor 478c, conductor 476b, conductor 474c, and conductor 496d.

[0473] Capacitor 3400 includes a conductor 516a, which serves as the other of the source and drain electrodes of transistor 3300, a conductor 514, and an insulator 511. Note that insulator 511 can be formed in the same process as the insulator used as the gate insulator of transistor 3300, which can improve productivity and is sometimes preferable. Furthermore, using a layer formed in the same process as conductor 504, which serves as the gate electrode of transistor 3300, as conductor 514 can improve productivity and is sometimes preferable.

[0474] The structures of other components can refer to the description about Figure 24 and the like as appropriate.

[0475] Note that the semiconductor device shown in FIG29 differs from the semiconductor device shown in FIG28 only in the structure of transistor 3200. Therefore, the semiconductor device shown in FIG29 refers to the description of the semiconductor device shown in FIG28. Specifically, in the semiconductor device shown in FIG29, transistor 3200 is a Fin-type transistor. Fin-type transistor 3200 refers to the description of transistor 2200 shown in FIG25. FIG25 illustrates the case where transistor 2200 is a p-channel transistor, but transistor 3200 may also be an n-channel transistor.

[0476] The semiconductor device shown in FIG30 differs from the semiconductor device shown in FIG28 only in the structure of transistor 3200. Therefore, the semiconductor device shown in FIG30 refers to the description of the semiconductor device shown in FIG28. Specifically, in the semiconductor device shown in FIG30, transistor 3200 is provided in semiconductor substrate 450, which is an SOI substrate. Transistor 3200 provided in semiconductor substrate 450, which is an SOI substrate, refers to the description of transistor 2200 shown in FIG26. FIG26 illustrates the case where transistor 2200 is a p-channel transistor, but transistor 3200 may also be an n-channel transistor.

[0477] Memory device 2 The semiconductor device shown in FIG27B differs from the semiconductor device shown in FIG27A in that it does not include the transistor 3200. In this case as well, data writing and retention operations can be performed by the same operations as those of the semiconductor device shown in FIG27A.

[0478] Data reading in the semiconductor device shown in FIG. 27B is described. When transistor 3300 is turned on, third wiring 3003 and capacitor 3400, which were in a floating state, become conductive, and charge is redistributed between third wiring 3003 and capacitor 3400. As a result, the potential of third wiring 3003 changes. The amount of change in the potential of third wiring 3003 varies depending on the potential of one electrode of capacitor 3400 (or the charge accumulated in capacitor 3400).

[0479] For example, if the potential of one electrode of capacitor 3400 is V, the capacitance of capacitor 3400 is C, the capacitance component of third wiring 3003 is CB, and the potential of third wiring 3003 before charge redistribution is VB0, the potential of third wiring 3003 after charge redistribution is (CB×VB0+C×V) / (CB+C). Therefore, assuming that the memory cell has two states where the potential of one electrode of capacitor 3400 is V1 and V0 (V1>V0), the potential of third wiring 3003 when holding potential V1 (=(CB×VB0+C×V1) / (CB+C)) is higher than the potential of third wiring 3003 when holding potential V0 (=(CB×VB0+C×V0) / (CB+C)).

[0480] Furthermore, data can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

[0481] In this case, the transistor using the first semiconductor can be used in a drive circuit for driving the memory cell, and a transistor using the second semiconductor can be stacked on the drive circuit as the transistor 3300.

[0482] The semiconductor device utilizes a transistor with a low off-state current using an oxide semiconductor to retain stored data for a long period of time. This eliminates the need for a refresh operation or allows for extremely low refresh frequency, resulting in a low-power semiconductor device. Furthermore, even in the absence of power (preferably at a fixed potential), stored data can be retained for a long period of time.

[0483] Furthermore, because this semiconductor device does not require high voltages when writing data, component degradation is less likely to occur. For example, unlike conventional non-volatile memory, there is no need to inject or extract electrons into or from the floating gate, thus preventing problems such as insulator degradation. In other words, in a semiconductor device according to one embodiment of the present invention, the number of rewrite cycles, a problem with conventional non-volatile memory, is not limited, and reliability is significantly improved. Furthermore, data is written based on the on / off state of the transistor, enabling high-speed operation.

[0484] Memory device 3 A modified example of the semiconductor device (memory device) shown in FIG. 27A will be described with reference to the circuit diagram shown in FIG. 31 .

[0485] The semiconductor device shown in FIG31 includes transistors 4100 to 4400, capacitors 4500, and capacitor 4600. Here, transistor 4100 can be the same as transistor 3200, and transistors 4200 to 4400 can be the same as transistor 3300. Note that although not shown in FIG31 , multiple semiconductor devices shown in FIG31 are arranged in a matrix. The semiconductor device shown in FIG31 can control the writing and reading of data voltages based on signals or potentials supplied to wiring 4001, wiring 4003, and wirings 4005 to 4009.

[0486] One of the source and drain of the transistor 4100 is connected to the wiring 4003. The other of the source and drain of the transistor 4100 is connected to the wiring 4001. Note that although FIG31 shows the case where the transistor 4100 is a p-channel transistor, the transistor 4100 may also be an n-channel transistor.

[0487] The semiconductor device shown in FIG31 includes two data retention units. For example, the first data retention unit retains charge between one of the source and drain of transistor 4400 connected to node FG1, one electrode of capacitor 4600, and one of the source and drain of transistor 4200. Furthermore, the second data retention unit retains charge between the gate of transistor 4100 connected to node FG2, the other of the source and drain of transistor 4200, one of the source and drain of transistor 4300, and one electrode of capacitor 4500.

[0488] The other of the source and drain of transistor 4300 is connected to wiring 4003. The other of the source and drain of transistor 4400 is connected to wiring 4001. The gate of transistor 4400 is connected to wiring 4005. The gate of transistor 4200 is connected to wiring 4006. The gate of transistor 4300 is connected to wiring 4007. The other electrode of capacitor 4600 is connected to wiring 4008. The other electrode of capacitor 4500 is connected to wiring 4009.

[0489] Transistors 4200 to 4400 have a switching function that controls the writing of data voltages and the retention of electric charge. Note that transistors 4200 to 4400 preferably have a low current (off-state current) flowing between the source and drain in the off state. Transistors having a low off-state current are preferably transistors including an oxide semiconductor in their channel formation region (OS transistors). OS transistors have advantages such as low off-state current and the ability to be manufactured in an overlapping manner with transistors including silicon. Note that although FIG31 illustrates transistors 4200 to 4400 as n-channel transistors, these transistors 4200 to 4400 may also be p-channel transistors.

[0490] Even if transistors 4200, 4300, and 4400 use oxide semiconductors, it is preferable to provide transistors 4200, 4300, and 4400 in different layers. Specifically, as shown in FIG31 , the semiconductor device shown in FIG31 preferably includes a first layer 4021 including transistor 4100, a second layer 4022 including transistors 4200 and 4300, and a third layer 4023 including transistor 4400. By stacking layers including transistors, the circuit area can be reduced, thereby miniaturizing the semiconductor device.

[0491] Next, the data writing operation performed on the semiconductor device shown in FIG31 will be described.

[0492] First, the data voltage writing operation to the data storage unit connected to node FG1 (hereinafter referred to as writing operation 1) is described. Note that, hereinafter, the data voltage written to the data storage unit connected to node FG1 is VD1, and the threshold voltage of transistor 4100 is Vth.

[0493] In write operation 1, after setting the potential of wiring 4003 to VD1 and the potential of wiring 4001 to ground potential, wiring 4001 is placed in an electrically floating state. Furthermore, the potentials of wirings 4005 and 4006 are set to a high level. Furthermore, the potentials of wirings 4007 to 4009 are set to a low level. This causes the potential of node FG2, which is already in an electrically floating state, to rise, allowing current to flow through transistor 4100. This flow of current also increases the potential of wiring 4001. Furthermore, transistors 4400 and 4200 become conductive. Consequently, as the potential of wiring 4001 rises, the potentials of nodes FG1 and FG2 also rise. When the potential of node FG2 rises and the voltage (Vgs) between the gate and source of transistor 4100 reaches its threshold voltage Vth, the current flowing through transistor 4100 decreases. Therefore, the potentials of the wiring 4001 and the nodes FG1 and FG2 stop rising and are fixed to "VD1-Vth" which is lower than VD1 by Vth.

[0494] That is, when current flows through transistor 4100, VD1 applied to wiring 4003 is applied to wiring 4001, causing the potentials of nodes FG1 and FG2 to rise. When the potential of node FG2 reaches "VD1 - Vth" due to this potential rise, Vgs of transistor 4100 reaches Vth, and the current stops.

[0495] Next, the data voltage writing operation to the data storage unit connected to the node FG2 (hereinafter referred to as writing operation 2) will be described. Note that in this description, the data voltage written to the data storage unit connected to the node FG2 is VD2.

[0496] In write operation 2, after setting the potential of wiring 4001 to VD2 and the potential of wiring 4003 to ground potential, wiring 4003 is placed in an electrically floating state. Furthermore, the potential of wiring 4007 is set to a high level. Furthermore, the potentials of wirings 4005, 4006, 4008, and 4009 are set to a low level. Transistor 4300 is placed in an on-state, and the potential of wiring 4003 is set to a low level. Consequently, the potential of node FG2 also drops to a low level, causing current to flow through transistor 4100. As current flows, the potential of wiring 4003 rises. Furthermore, transistor 4300 is placed in an on-state. Therefore, as the potential of wiring 4003 rises, the potential of node FG2 also rises. When the potential of node FG2 rises and the Vgs of transistor 4100 reaches its Vth, the current flowing through transistor 4100 decreases. Therefore, the potential of the wiring 4003 and the node FG2 stops rising and is fixed to "VD2-Vth" which is lower than VD2 by Vth.

[0497] Specifically, when current flows through transistor 4100, VD2 applied to wiring 4001 is applied to wiring 4003, causing the potential of node FG2 to rise. When this potential rises and the potential of node FG2 reaches "VD2 - Vth," Vgs of transistor 4100 reaches Vth, stopping the current flow. At this point, transistors 4200 and 4400 are both off, and the potential of node FG1 remains at "VD1 - Vth," which was written in write operation 1.

[0498] In the semiconductor device shown in FIG31 , after data voltages are written into the multiple data retention portions, the potential of wiring 4009 is set to a high level, raising the potentials of nodes FG1 and FG2. Subsequently, each transistor is turned off to stop charge transfer, thereby retaining the written data voltage.

[0499] By writing data voltages to nodes FG1 and FG2 as described above, data voltages can be retained in multiple data retention units. Note that while "VD1-Vth" and "VD2-Vth" are used as examples of the potentials to be written, these potentials correspond to data voltages with multiple values. Therefore, if 4 bits of data are retained in each data retention unit, 16 values ​​of "VD1-Vth" and 16 bits of "VD2-Vth" can be obtained.

[0500] Next, the data reading operation performed on the semiconductor device shown in FIG31 will be described.

[0501] First, a description will be given of an operation of reading a data voltage from a data holding portion connected to a node FG2 (hereinafter referred to as a read operation 1 ).

[0502] In read operation 1, wiring 4003, which is in an electrically floating state after precharging, is discharged. The potentials of wirings 4005 to 4008 are set to a low level. Furthermore, the potential of wiring 4009 is set to a low level, so that the potential of node FG2, which is in an electrically floating state, is "VD2 - Vth." When the potential of node FG2 decreases, current flows through transistor 4100. As current flows, the potential of wiring 4003, which is in an electrically floating state, decreases. As the potential of wiring 4003 decreases, the Vgs of transistor 4100 decreases. When the Vgs of transistor 4100 reaches its Vth, the current flowing through transistor 4100 decreases. In other words, the potential of wiring 4003 reaches "VD2," which is Vth higher than the potential of node FG2, "VD2 - Vth." This potential of wiring 4003 corresponds to the data voltage of the data retention unit connected to node FG2. The data voltage of the read analog value is A / D converted to obtain data of the data holding portion connected to the node FG2.

[0503] Specifically, the precharged wiring 4003 is placed in a floating state, and the potential of wiring 4009 is switched from a high level to a low level, causing current to flow through transistor 4100. As the current flows, the potential of the floating wiring 4003 drops to "VD2." In transistor 4100, the Vgs between "VD2-Vth" at node FG2 and "VD2" on wiring 4003 reaches Vth, stopping the current flow. Then, VD2 written in write operation 2 is read out to wiring 4003.

[0504] After acquiring the data from the data holding portion connected to the node FG2, the transistor 4300 is turned on to discharge "VD2-Vth" at the node FG2.

[0505] Next, the charge held at node FG1 is distributed between nodes FG1 and FG2, and the data voltage of the data storage unit connected to node FG1 is moved to the data storage unit connected to node FG2. Here, the potentials of wires 4001 and 4003 are set to a low level. The potential of wire 4006 is set to a high level. The potentials of wires 4005 and wires 4007 through 4009 are also set to a low level. By turning on transistor 4200, the charge at node FG1 is distributed between nodes FG1 and FG2.

[0506] Here, the potential after charge distribution is lower than the written potential "VD1 - Vth." Therefore, the capacitance value of capacitor 4600 is preferably greater than the capacitance value of capacitor 4500. Alternatively, the potential "VD1 - Vth" written to node FG1 is preferably greater than the potential "VD2 - Vth" representing the same data. By increasing the pre-written potential by changing the capacitance ratio in this way, the potential drop after charge distribution can be suppressed. The potential fluctuation caused by charge distribution will be described later.

[0507] Next, an operation of reading the data voltage of the data holding portion connected to the node FG1 (hereinafter referred to as read operation 2 ) will be described.

[0508] In read operation 2, wiring 4003, which was in an electrically floating state after precharging, is discharged. The potentials of wirings 4005 to 4008 are set to a low level. Furthermore, the potential of wiring 4009 is set to a high level during precharging and then to a low level. Setting the potential of wiring 4009 to a low level causes the potential of node FG2, which is in an electrically floating state, to reach "VD1 - Vth." As the potential of node FG2 decreases, current flows through transistor 4100. As current flows, the potential of wiring 4003, which is in an electrically floating state, decreases. As the potential of wiring 4003 decreases, the Vgs of transistor 4100 decreases. When the Vgs of transistor 4100 reaches its Vth, the current flowing through transistor 4100 decreases. In other words, the potential of wiring 4003 reaches "VD1," which is Vth higher than the potential of node FG2, "VD1 - Vth." The potential of wiring 4003 corresponds to the data voltage of the data storage unit connected to node FG1. The read analog value data voltage is A / D converted to obtain the data from the data storage unit connected to node FG1. This completes the data voltage reading operation for the data storage unit connected to node FG1.

[0509] Specifically, the precharged wiring 4003 is placed in a floating state, and the potential of wiring 4009 is switched from a high level to a low level, causing current to flow through transistor 4100. As current flows, the potential of the floating wiring 4003 drops to VD1. In transistor 4100, the Vgs between "VD1-Vth" at node FG2 and "VD1" at wiring 4003 reaches Vth, stopping the current flow. Then, "VD1" written in write operation 1 is read out to wiring 4003.

[0510] By reading the data voltages at nodes FG1 and FG2 as described above, data voltages can be read from multiple data storage units. For example, by storing 4 bits (16 values) of data in each of nodes FG1 and FG2, a total of 8 bits (256 values) of data can be stored. Furthermore, while FIG31 illustrates a structure consisting of the first to third layers 4021 to 4023, forming more layers can increase memory capacity without increasing the area of ​​the semiconductor device.

[0511] Note that the read potential can be read as a voltage higher by Vth than the written data voltage. Therefore, reading can be performed by offsetting the Vth of "VD1 - Vth" or "VD2 - Vth" written during the write operation. As a result, while maintaining the maximum memory capacity per memory cell, the read data can be closer to the correct data, achieving higher data reliability.

[0512] FIG32 shows a cross-sectional view of the semiconductor device corresponding to FIG31. The semiconductor device shown in FIG32 includes transistors 4100 to 4400, capacitors 4500, and capacitor 4600. Here, transistor 4100 is formed in the first layer 4021, transistors 4200 and 4300, and capacitor 4500 are formed in the second layer 4022, and transistor 4400 and capacitor 4600 are formed in the third layer 4023.

[0513] Here, regarding transistors 4200 to 4400, reference can be made to the description of transistor 3300, and regarding transistor 4100, reference can be made to the description of transistor 3200. Furthermore, regarding other wirings and insulators, reference can also be made to the description of FIG. 28 as appropriate.

[0514] Note that in the semiconductor device shown in FIG28 , capacitor 3400 is formed by providing a conductive layer parallel to the substrate, whereas capacitors 4500 and 4600 are formed by providing a conductive layer in a trench shape. This structure ensures a higher capacitance value even with the same occupied area.

[0515] <Memory device 4> The semiconductor device shown in FIG27C differs from the semiconductor device shown in FIG27A in that it includes a transistor 3500 and a sixth wiring 3006. In this case, data can also be written and retained using the same operations as the semiconductor device shown in FIG27A. Furthermore, transistor 3500 can be the same as transistor 3200 described above.

[0516] The sixth wiring 3006 is electrically connected to the gate of the transistor 3500 , one of the source and the drain of the transistor 3500 is electrically connected to the drain of the transistor 3200 , and the other of the source and the drain of the transistor 3500 is electrically connected to the third wiring 3003 .

[0517] FIG33 shows an example of a cross-sectional view of the semiconductor device shown in FIG27C. FIG34 shows an example of a cross-sectional view taken along the B3-B4 direction, which is substantially perpendicular to the B1-B2 direction shown in FIG33. The semiconductor device shown in FIG27C in FIG33 and FIG34 includes five layers: layer 1627 through layer 1631. Layer 1627 includes transistor 3200, transistor 3500, and transistor 3600. Layers 1628 and 1629 include transistor 3300.

[0518] Layer 1627 includes substrate 1400, insulator 1464 on transistors 3200, 3500, 3600, and 3200 on substrate 1400, and plugs such as plug 1541. Plug 1541 is connected to, for example, the gate electrode, source electrode, or drain electrode of transistor 3200. Plug 1541 is preferably formed by filling insulator 1464.

[0519] Regarding transistor 3200, transistor 3500, and transistor 3600, please refer to the description of transistor 2200.

[0520] As the insulator 1464, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0521] The insulator 1464 can be formed by sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PLD. CVD, preferably plasma CVD, is particularly preferred because it improves coverage. Furthermore, thermal CVD, MOCVD, or ALD is preferred to reduce damage caused by plasma.

[0522] Silicon carbonitride, silicon oxycarbide, or the like can be used as the insulator 1464. Furthermore, materials such as USG (Undoped Silicate Glass), BPSG (Boron Phosphorus Silicate Glass), and BSG (Borosilicate Glass) can be used. USG, BPSG, and the like can be formed using atmospheric pressure CVD. Furthermore, materials such as HSQ (Hydrogen Silsesquioxane) can be formed using a coating method.

[0523] The insulator 1464 may be a single layer or a stacked layer in which a plurality of materials are stacked.

[0524] Here, FIG. 33 shows an example in which the insulator 1464 includes two layers: an insulator 1464a and an insulator 1464b on the insulator 1464a.

[0525] The insulator 1464a preferably has good tightness and coverage with the region 1476 of the transistor 3200 and the conductor 1454 etc. used as the gate of the transistor 3200 etc.

[0526] As an example, silicon nitride formed by CVD can be used as the insulator 1464a. Here, the insulator 1464a may preferably contain hydrogen. When the insulator 1464a contains hydrogen, defects in the substrate 1400 may be reduced, thereby improving the characteristics of the transistor 3200. For example, when a material containing silicon is used as the substrate 1400, hydrogen can terminate defects such as dangling bonds in the silicon.

[0527] Here, it is preferable that the parasitic capacitance formed between conductors such as conductor 1454 located below insulator 1464a and conductors such as conductor 1511 formed on insulator 1464b be small. Therefore, the dielectric constant of insulator 1464b is preferably low. The dielectric constant of insulator 1464b is preferably lower than that of insulator 1462, which serves as a gate insulator for transistor 3200, etc. Furthermore, the dielectric constant of insulator 1464b is preferably lower than that of insulator 1464a. For example, the relative dielectric constant of insulator 1464b is preferably less than 4, more preferably less than 3. Furthermore, for example, the relative dielectric constant of insulator 1464b is preferably no greater than 0.7 times, more preferably no greater than 0.6 times, the relative dielectric constant of insulator 1464a.

[0528] Here, as an example, silicon nitride can be used as the insulator 1464a, and USG can be used as the insulator 1464b.

[0529] By using a material with low copper permeability such as silicon nitride or silicon carbonitride as the insulator 1464a and the insulator 1581a, when copper is used as the conductor 1511, it is sometimes possible to suppress the diffusion of copper into the layers above and below the insulator 1464a and the insulator 1581a.

[0530] Furthermore, impurities such as copper may diffuse from the top surface of conductor 1511b, which is not covered by conductor 1511a, through insulator 1584 and the like to the layers above it. Therefore, insulator 1584 on conductor 1511b is preferably made of a material with low permeability to impurities such as copper. For example, insulator 1584 can have a multilayer structure similar to that of insulators 1581a and 1581b.

[0531] Layer 1628 includes insulator 1581, insulator 1584 on insulator 1581, insulator 1571 on insulator 1584, and insulator 1585 on insulator 1571. Furthermore, layer 1628 includes conductors 1511 and the like on insulator 1464, plugs 1543 and the like connected to conductors 1511 and the like, and conductors 1513 on insulator 1571. Conductor 1511 is preferably formed so as to fill insulator 1581. Plugs 1543 and the like are preferably formed so as to fill insulator 1584 and insulator 1571. Conductor 1513 is preferably formed so as to fill insulator 1585.

[0532] In addition, the layer 1628 may also include the conductor 1413. The conductor 1413 is preferably formed by filling the insulator 1585.

[0533] As the insulator 1584 and the insulator 1585, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0534] Insulators 1584 and 1585 can be formed by sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PLD. CVD, preferably plasma CVD, is particularly preferred because it improves coverage. Furthermore, it is preferred to use tetraethoxysilane (TEOS: Si(OC2H5)4) as the deposition gas for film formation, and it is preferred to perform film formation while heating. Forming insulators 1584 and 1585 in this manner can reduce the hydrogen concentration in the film. Heating is preferably performed within a relatively low temperature range (e.g., approximately 350°C to 445°C). Furthermore, insulators with reduced hydrogen concentrations can be used as other interlayer insulating films.

[0535] In addition, in order to reduce damage caused by plasma, it is preferred to use thermal CVD, MOCVD or ALD.

[0536] Silicon carbide, silicon carbonitride, silicon oxycarbide, or the like can be used as the insulator 1584 and the insulator 1585. Furthermore, USG (Undoped Silicate Glass), BPSG (Boron Phosphorus Silicate Glass), and BSG (Borosilicate Glass) can also be used. USG, BPSG, and the like can be formed using atmospheric pressure CVD. Furthermore, HSQ (Hydrogen Silsesquioxane) can be formed using a coating method, for example.

[0537] The insulator 1584 and the insulator 1585 may be a single layer or a stacked layer in which a plurality of materials are stacked.

[0538] The insulator 1581 may be formed by stacking a plurality of layers. For example, as shown in FIG33 , the insulator 1581 may include two layers: an insulator 1581 a and an insulator 1581 b on the insulator 1581 a.

[0539] In addition, the plug 1543 has a protrusion on the insulator 1571.

[0540] Conductors 1511, 1513, 1413, and plugs 1543 can be made of conductive materials such as metals, alloys, or metal oxides. For example, single-layer or multi-layer structures of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, niobium, molybdenum, silver, tantalum, or tungsten, or alloys primarily composed of these metals, can be used. Furthermore, metal nitrides such as tungsten nitride, molybdenum nitride, and titanium nitride can be used.

[0541] Here, conductors such as conductor 1511 and conductor 1513 are preferably used as wiring for the semiconductor device shown in FIG. 27C . Therefore, these conductors are sometimes referred to as wiring or wiring layers. Furthermore, these conductors are preferably connected using plugs such as plug 1543 .

[0542] Regarding insulator 1581, refer to the description of insulator 1464. Furthermore, insulator 1581 may be a single layer or a laminated layer composed of multiple materials. FIG. 33 illustrates an example insulator 1581 comprising two layers: insulator 1581a and insulator 1581b on top of insulator 1581a. Regarding the materials and formation methods that can be used for insulators 1581a and 1581b, refer to the description of the materials and formation methods that can be used for insulators 1464a and 1464b, respectively.

[0543] Silicon nitride formed by CVD can be used as an example of insulator 1581a. When hydrogen diffuses into a semiconductor element, such as transistor 3300, included in the semiconductor device of FIG. 27C , the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that releases little hydrogen as insulator 1581a. The amount of hydrogen released can be analyzed, for example, using thermal desorption spectroscopy (TDS). The amount of hydrogen released from insulator 1581a in the temperature range of 50°C to 500°C, as determined by TDS analysis, is, for example, 5×1020 atoms / cm3 or less, preferably 2×1020 atoms / cm3 or less, and even more preferably 1×1020 atoms / cm3 or less. Alternatively, the amount of hydrogen released per unit area of ​​the insulator 1581a in terms of hydrogen atoms may be, for example, less than 5×10 15 atoms / cm 2 , preferably less than 2×10 15 atoms / cm 2 , and more preferably less than 1×10 15 atoms / cm 2 .

[0544] This silicon nitride with a low amount of hydrogen atoms released can be used not only for the insulator 1581a but also for the insulator layer above the insulator 1581a shown in FIG33. In addition to the silicon nitride, an insulator similar to the insulator 104 with reduced hydrogen and water content described in the above embodiment mode can also be used.

[0545] The dielectric constant of insulator 1581b is preferably lower than that of insulator 1581a. For example, the relative dielectric constant of insulator 1581b is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of insulator 1581b is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of insulator 1581a.

[0546] Insulator 1571 is preferably formed of an insulating material with low permeability to impurities. For example, insulator 1571 preferably has low oxygen permeability. Furthermore, insulator 1571 preferably has low hydrogen permeability. Furthermore, insulator 1571 preferably has low water permeability.

[0547] As the insulator 1571, for example, a single layer or a stack of aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), or silicon nitride can be used. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, or gallium oxide can be added to these insulators. Furthermore, these insulators can be nitrided to form oxynitrides. Silicon oxide, silicon oxynitride, or silicon nitride can be stacked on top of the above insulators. Aluminum oxide is particularly preferred due to its excellent barrier properties to water and hydrogen.

[0548] In addition, as the insulator 1571, for example, silicon carbide, silicon carbonitride, silicon oxycarbide, or the like can be used.

[0549] The insulator 1571 may be a stack of a layer of a material having low permeability to water or hydrogen and a layer containing another insulating material. For example, a stack of a layer containing silicon oxide or silicon oxynitride and a layer containing a metal oxide can be used.

[0550] Here, for example, when the semiconductor device shown in Figure 27C includes the insulator 1571, the elements contained in the conductor 1513 and the conductor 1413 can be suppressed from diffusing into the insulator 1571 and the layers therebelow (insulator 1584, insulator 1581, layer 1627, etc.).

[0551] Here, when the dielectric constant of insulator 1571 is higher than that of insulator 1584, the thickness of insulator 1571 is preferably smaller than that of insulator 1584. The relative dielectric constant of insulator 1584 is preferably, for example, 0.7 times or less, and more preferably 0.6 times or less, that of insulator 1571. Furthermore, for example, the thickness of insulator 1571 is preferably 5 nm to 200 nm, more preferably 5 nm to 60 nm, while the thickness of insulator 1584 is preferably 30 nm to 800 nm, more preferably 50 nm to 500 nm. For example, the thickness of insulator 1571 is preferably one-third or less of the thickness of insulator 1584.

[0552] Layer 1629 includes transistor 3300, plugs 1544, plug 1544b, and other plugs. Plugs 1544, plug 1544b, and other plugs are connected to conductor 1513, layer 1628, and the gate, source, or drain electrodes of transistor 3300. The structure of transistor 3300 can be found in the description of transistor 20, transistor 2100, and other components.

[0553] Transistor 3300 includes a conductor 1413, an insulator 1571a, an insulator 1402, a conductor 1416a, a conductor 1416b, a conductor 1404, an insulator 1408, and an insulator 1591. The conductor 1413, the insulator 1571a, the insulator 1402, the conductor 1416a, the conductor 1416b, the conductor 1404, the insulator 1408, and the insulator 1591 may be referred to as the conductor 102, the insulator 103, the insulator 104, the conductor 108a, the conductor 108b, the conductor 114, the insulator 116, and the insulator 118, respectively.

[0554] Furthermore, as shown in Figures 76 and 77, an insulator 1402a equivalent to insulator 105 in transistor 20 can be provided. Figures 76 and 77 correspond to Figures 33 and 34, and differ from Figures 33 and 34 only in the provision of insulator 1402a. For example, insulator 1402a can be provided between insulator 1585 and insulator 1571a. Of insulators 1402a, 1571a, and 1402, insulator 1571a preferably has an electron-trapping region. When insulators 1402a and 1402 have the function of suppressing electron release, the electrons captured by insulator 1571a behave as fixed negative charges. Therefore, by injecting electrons into insulator 1571a, the threshold voltage of transistor 3300 can be changed. By applying a positive potential or a negative potential to the conductor 1413 , electrons can be injected into the insulator 1571 a .

[0555] Furthermore, the amount of electron injection can be adjusted by the duration of application of a potential to the conductor 1413 and / or the applied potential, thereby achieving a desired threshold voltage of the transistor. The potential applied to the conductor 1413 can be set to a level sufficient to cause a tunneling current to flow through the insulator 1402a. For example, a potential of 20 V to 60 V, preferably 24 V to 50 V, and more preferably 30 V to 45 V can be applied. The duration of application of the potential can be, for example, 0.1 seconds to 20 seconds, preferably 0.2 seconds to 10 seconds.

[0556] As in the above embodiment, the amount of water or hydrogen contained in the stacked film of insulators provided between insulator 1571 and the insulator corresponding to insulator 106a of transistor 20 (in this embodiment, the stacked film of insulators 1585, insulator 1402a, insulator 1571a, and insulator 1402) is preferably low. As described above, if insulator 1571 is an insulator that has a function of blocking water or hydrogen, when an oxide is formed that becomes insulator 106a and semiconductor 106b of transistor 20, the water or hydrogen supplied to the oxide is contained in insulators 1585, insulator 1402a, insulator 1571a, and insulator 1402. Therefore, if the amount of water or hydrogen contained in the stacked film of insulators 1585, insulator 1402a, insulator 1571a, and insulator 1402, particularly in insulator 1402, is sufficiently low when the oxide is formed, the amount of water or hydrogen supplied to the oxide can be reduced.

[0557] In addition, the conductors 1416a and 1416b are preferably made of a material having low permeability to the elements contained in the plug 1544b that contacts the top surface thereof.

[0558] Conductor 1416a and conductor 1416b may be a stacked film. As an example, conductor 1416a and conductor 1416b are stacked as a first layer and a second layer. Here, the first layer is formed on the oxide semiconductor layer, and the second layer is formed on the first layer. For example, tungsten is used for the first layer, and tantalum nitride is used for the second layer. Here, copper is used, for example, for plug 1544b and the like. Copper has low resistivity and is a suitable conductor for plugs, wiring, and the like. On the other hand, copper diffuses easily, and when it diffuses into the semiconductor layer or gate insulating film of a transistor, it may cause a decrease in transistor characteristics. When conductor 1416a and conductor 1416b include tantalum nitride, diffusion of copper contained in plug 1544b and the like into the oxide semiconductor layer may be suppressed.

[0559] The semiconductor device shown in FIG. 27C according to one embodiment of the present invention preferably has a structure that can suppress diffusion of elements and compounds that degrade the characteristics of the semiconductor element into the semiconductor element when plugs, wirings, etc. contain such elements and compounds.

[0560] Layer 1630 includes insulator 1592, electrical conductors such as conductor 1514, and plugs such as plug 1545. Plug 1545 is connected to electrical conductor 1514.

[0561] Layer 1631 includes capacitor 3400. Capacitor 3400 includes conductor 1516, conductor 1517, and insulator 1572. Insulator 1572 has a region sandwiched between conductors 1516 and 1517. Layer 1631 preferably includes insulator 1594 and plug 1547 on conductor 1517. Plug 1547 is preferably formed to fill insulator 1594. Layer 1631 preferably includes conductor 1516b connected to the plug included in layer 1630 and plug 1547b on conductor 1516b.

[0562] Layer 1631 may also include a wiring layer connected to plug 1547 or plug 1547b. In the example shown in FIG33 , the wiring layer includes conductor 1518 connected to plug 1547 or plug 1547b, plug 1548 on conductor 1518, insulator 1595, conductor 1519 on plug 1548, and insulator 1599 on conductor 1519. Plug 1548 is preferably formed to fill insulator 1595. Insulator 1599 has an opening on conductor 1519.

[0563] The structure described in this embodiment can be used in combination with the structures described in other embodiment modes as appropriate.

[0564] Implementation 5 In this embodiment, an example of an imaging device using a transistor or the like according to one embodiment of the present invention is described.

[0565] Camera An imaging device according to an embodiment of the present invention will be described below.

[0566] FIG35A is a plan view illustrating an example of an imaging device 200 according to an embodiment of the present invention. The imaging device 200 includes a pixel portion 210, and peripheral circuits 260, 270, 280, and 290 for driving the pixel portion 210. The pixel portion 210 includes a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers greater than or equal to 2). The peripheral circuits 260, 270, 280, and 290 are each connected to the plurality of pixels 211 and have the function of supplying signals for driving the plurality of pixels 211. In this specification, the peripheral circuits 260, 270, 280, and 290 may sometimes be collectively referred to as "peripheral circuits" or "driving circuits." For example, the peripheral circuit 260 may also be considered a portion of the peripheral circuits.

[0567] The imaging device 200 preferably includes a light source 291. The light source 291 can emit detection light P1.

[0568] The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, or a conversion circuit. Alternatively, the peripheral circuit may be fabricated on the substrate forming the pixel portion 210. Furthermore, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that one or more of peripheral circuits 260, 270, 280, and 290 may be omitted.

[0569] As shown in FIG35B , in the pixel portion 210 included in the imaging device 200, the pixels 211 may be arranged at an angle. By arranging the pixels 211 at an angle, the pixel spacing (pitch) in the row and column directions can be shortened. This improves the image quality of the imaging device 200.

[0570] <Pixel Structure Example 1> By making one pixel 211 included in the imaging device 200 comprise a plurality of sub-pixels 212 and combining each sub-pixel 212 with a filter (color filter) that transmits light in a specific wavelength region, data for realizing color image display can be obtained.

[0571] FIG36A is a plan view showing an example of a pixel 211 for capturing a color image. The pixel 211 shown in FIG36A includes a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") provided with a color filter that transmits light in the red (R) wavelength range, a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") provided with a color filter that transmits light in the green (G) wavelength range, and a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212B") provided with a color filter that transmits light in the blue (B) wavelength range. Sub-pixels 212 can be used as photosensors.

[0572] Subpixels 212 (subpixel 212R, subpixel 212G, and subpixel 212B) are electrically connected to wiring 231, wiring 247, wiring 248, wiring 249, and wiring 250. Furthermore, subpixels 212R, 212G, and 212B are each connected to an independent wiring 253. In this specification, for example, wiring 248 and wiring 249 connected to pixel 211 in the nth row are referred to as wiring 248[n] and wiring 249[n], respectively. Furthermore, for example, wiring 253 connected to pixel 211 in the mth column is referred to as wiring 253[m]. In FIG36A , the wiring 253 connected to the sub-pixel 212R included in the pixel 211 in the mth column is referred to as wiring 253[m]R, the wiring 253 connected to the sub-pixel 212G is referred to as wiring 253[m]G, and the wiring 253 connected to the sub-pixel 212B is referred to as wiring 253[m]B. Sub-pixels 212 are electrically connected to peripheral circuits via these wirings.

[0573] The imaging device 200 has a structure in which sub-pixels 212 of adjacent pixels 211, each provided with a color filter that transmits light in the same wavelength range, are electrically connected to each other via a switch. FIG36B illustrates an example of the connection between a sub-pixel 212 included in a pixel 211 located in the nth row (n is an integer from 1 to p) and the mth column (m is an integer from 1 to q) and a sub-pixel 212 included in a pixel 211 located in the n+1th row and the mth column adjacent to that pixel 211. In FIG36B , sub-pixel 212R located in the nth row and the mth column is connected to sub-pixel 212R located in the n+1th row and the mth column via a switch 201. Furthermore, sub-pixel 212G located in the nth row and the mth column is connected to sub-pixel 212G located in the n+1th row and the mth column via a switch 202. In addition, the sub-pixel 212B arranged at the nth row and the mth column is connected to the sub-pixel 212B arranged at the (n+1th)th row and the mth column via the switch 203 .

[0574] The color filters used for sub-pixels 212 are not limited to red (R), green (G), and blue (B) filters; filters that transmit cyan (C), yellow (Y), and magenta (M) light may also be used. By providing sub-pixels 212 that detect light in three different wavelength regions within a single pixel 211, a full-color image can be obtained.

[0575] Alternatively, a pixel 211 may be used that includes, in addition to sub-pixels 212 each having color filters that transmit red (R), green (G), and blue (B), a sub-pixel 212 having a color filter that transmits yellow (Y). Alternatively, a pixel 211 may be used that includes, in addition to sub-pixels 212 each having color filters that transmit cyan (C), yellow (Y), and magenta (M), a sub-pixel 212 having a color filter that transmits blue (B). By providing sub-pixels 212 that detect light in four different wavelength regions within a single pixel 211, the color reproducibility of the resulting image can be further improved.

[0576] For example, in FIG36A , the pixel count ratio (or light-receiving area ratio) of sub-pixels 212 detecting light in the red wavelength range, sub-pixels 212 detecting light in the green wavelength range, and sub-pixels 212 detecting light in the blue wavelength range is not limited to 1:1:1. For example, a Bayer arrangement with a pixel count ratio (light-receiving area ratio) of red:green:blue = 1:2:1 may be employed. Alternatively, the pixel count ratio (light-receiving area ratio) may be red:green:blue = 1:6:1.

[0577] The number of sub-pixels 212 provided in pixel 211 may be one, but preferably two or more. For example, by providing two or more sub-pixels 212 that detect light in the same wavelength range, redundancy can be increased, thereby improving the reliability of imaging device 200.

[0578] In addition, by using an IR (Infrared) filter that reflects or absorbs visible light and transmits infrared light, an imaging device 200 that detects infrared light can be realized.

[0579] Neutral Density (ND) filters can be used to prevent output saturation caused by high-intensity light entering photoelectric converters (light-receiving elements). Combining ND filters with varying light reduction levels can increase the dynamic range of the imaging device.

[0580] In addition to the aforementioned filters, a lens may also be provided in the pixel 211. Here, an example configuration of the pixel 211, the filter 254, and the lens 255 is described with reference to the cross-sectional views of FIG37A and FIG37B. The provision of the lens 255 allows the photoelectric conversion element to efficiently receive light. Specifically, as shown in FIG37A , light 256 can pass through the lens 255, the filter 254 (filter 254R, filter 254G, and filter 254B), and the pixel circuit 230 formed in the pixel 211 and enter the photoelectric conversion element 220.

[0581] Note that, as indicated by the area surrounded by the dotted line, a portion of the light 256 indicated by the arrow may be blocked by a portion of the wiring 257. Therefore, as shown in FIG37B , it is preferable to employ a structure in which a lens 255 and a filter 254 are disposed on the photoelectric conversion element 220 side so that the photoelectric conversion element 220 efficiently receives the light 256. By allowing the light 256 to enter the photoelectric conversion element 220 from the photoelectric conversion element 220 side, an imaging device 200 with high detection sensitivity can be provided.

[0582] As the photoelectric conversion element 220 shown in FIG. 37A and FIG. 37B , a photoelectric conversion element having a pn junction or a pin junction may be used.

[0583] The photoelectric conversion element 220 may also be formed using a material that absorbs radiation and generates charge. Examples of materials that absorb radiation and generate charge include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium-zinc alloys.

[0584] For example, when selenium is used for the photoelectric conversion element 220, a photoelectric conversion element 220 having a light absorption coefficient in a wide wavelength range such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays can be realized.

[0585] Here, a pixel 211 included in the imaging device 200 may further include a sub-pixel 212 having a first filter in addition to the sub-pixel 212 shown in FIG. 36A and FIG. 36B .

[0586] <Pixel Structure Example 2> Next, an example of a pixel including a transistor using silicon and a transistor using an oxide semiconductor is described.

[0587] Figures 38A and 38B are cross-sectional views of the components that make up the imaging device. The imaging device shown in Figure 38A includes a transistor 351 formed of silicon and disposed on a silicon substrate 300; transistors 352 and 353 formed of an oxide semiconductor and stacked on transistor 351; and a photodiode 360 ​​disposed within the silicon substrate 300. Each transistor and photodiode 360 ​​is electrically connected to various plugs 370 and wiring 371. Furthermore, the anode 361 of the photodiode 360 ​​is electrically connected to the plug 370 via a low-resistance region 363.

[0588] The imaging device includes: a layer 310 including a transistor 351 and a photodiode 360 ​​arranged on a silicon substrate 300, a layer 320 arranged in contact with the layer 310 and including a wiring 371, a layer 330 arranged in contact with the layer 320 and including a transistor 352 and a transistor 353, and a layer 340 arranged in contact with the layer 330 and including a wiring 372 and a wiring 373.

[0589] In the cross-sectional example of Figure 38A , the light-receiving surface of a photodiode 360 ​​is provided on the opposite side of the silicon substrate 300 from the surface on which the transistor 351 is formed. This structure ensures a secure optical path without being affected by various transistors or wiring. Consequently, a pixel with a high aperture ratio can be formed. Furthermore, the light-receiving surface of the photodiode 360 ​​can also be the same surface as the surface on which the transistor 351 is formed.

[0590] When the pixel includes only transistors using an oxide semiconductor, layer 310 may be a layer including transistors using an oxide semiconductor. Alternatively, the pixel may include only transistors using an oxide semiconductor and layer 310 may be omitted.

[0591] When the pixel includes only transistors using silicon, layer 330 can also be omitted. FIG38B shows an example of a cross-sectional view in which layer 330 is omitted.

[0592] The silicon substrate 300 may also be an SOI substrate. In addition, a substrate containing germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used instead of the silicon substrate 300.

[0593] Here, an insulator 380 is provided between the layer 310 including the transistor 351 and the photodiode 360 ​​and the layer 330 including the transistor 352 and the transistor 353. Note that the position of the insulator 380 is not limited to this.

[0594] Hydrogen in the insulator near the channel formation region of transistor 351 terminates dangling bonds in silicon, thereby improving the reliability of transistor 351. On the other hand, hydrogen in the insulator near transistors 352 and 353 can contribute to carrier generation in the oxide semiconductor. Consequently, this can sometimes reduce the reliability of transistors 352 and 353. Therefore, when stacking a transistor using an oxide semiconductor on a transistor using a silicon-based semiconductor, it is preferable to provide an insulator 380 between them to block hydrogen. By trapping hydrogen beneath insulator 380, the reliability of transistor 351 can be improved. Furthermore, since hydrogen diffusion from below insulator 380 to above insulator 380 is suppressed, the reliability of transistors 352 and 353 can be improved.

[0595] As the insulator 380 , for example, an insulator having a function of blocking oxygen or hydrogen is used.

[0596] In the cross-sectional view of FIG38A , the photodiode 360 ​​provided in layer 310 can be formed so as to overlap with the transistor provided in layer 330. This can increase the pixel integration density, that is, improve the resolution of the imaging device.

[0597] As shown in Figures 39A1 and 39B1, the imaging device can be partially or entirely bent. Figure 39A1 shows the imaging device bent in the direction of the dotted line X1-X2 in the figure. Figure 39A2 is a cross-sectional view of the portion along the dotted line X1-X2 in Figure 39A1. Figure 39A3 is a cross-sectional view of the portion along the dotted line Y1-Y2 in Figure 39A1.

[0598] FIG39B1 shows a state where the imaging device is bent in the direction of the dot-dash line X3-X4 and in the direction of the dot-dash line Y3-Y4 in the figure. FIG39B2 is a cross-sectional view of the portion along the dot-dash line X3-X4 in FIG39B1. FIG39B3 is a cross-sectional view of the portion along the dot-dash line Y3-Y4 in FIG39B1.

[0599] Curving the imaging device can reduce curvature of field and astigmatism. This can facilitate the optical design of lenses used in conjunction with the imaging device. For example, since the number of lenses required for aberration correction can be reduced, electronic devices using the imaging device can be miniaturized or lightweight. Furthermore, the quality of captured images can be improved.

[0600] The structure described in this embodiment can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0601] Implementation Method 6 In this embodiment, an example of a CPU including a semiconductor device such as a transistor according to one embodiment of the present invention or the above-described memory device will be described.

[0602] CPU Structure FIG40 is a block diagram showing a structure of an example of a CPU part of which uses the above-mentioned transistor.

[0603] The CPU shown in Figure 40 includes, on substrate 1190, an ALU (Arithmetic Logic Unit) 1191 (ALU), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface 1198, a rewritable ROM 1199, and a ROM interface 1189. Substrate 1190 can be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. ROM 1199 and ROM interface 1189 can also be located on separate wafers. Of course, the CPU shown in Figure 40 is merely a simplified example; actual CPUs have various configurations depending on their intended use. For example, multiple cores can be configured with the CPU or arithmetic circuit shown in Figure 40 as a core and operated simultaneously. Furthermore, the number of bits that can be processed by the CPU's internal arithmetic circuit or data bus can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0604] The instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193 and decoded before being input to the ALU controller 1192 , the interrupt controller 1194 , the register controller 1197 , and the timing controller 1195 .

[0605] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on decoded instructions. Specifically, the ALU controller 1192 generates signals to control the operation of the ALU 1191. Furthermore, when executing the CPU program, the interrupt controller 1194 identifies interrupt requests from external I / O devices or peripheral circuits based on their priority or mask status and processes them. The register controller 1197 generates the address of the register 1196 and reads or writes to the register 1196 based on the CPU status.

[0606] Furthermore, the timing controller 1195 generates signals for controlling the operating timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generator that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits described above.

[0607] In the CPU shown in FIG40 , a memory unit is provided in the temporary register 1196. The aforementioned transistor or memory device can be used as the memory unit of the temporary register 1196.

[0608] In the CPU shown in Figure 40, register controller 1197 selects the retention operation in register 1196 based on instructions from ALU 1191. In other words, register controller 1197 selects whether data in the memory cells of register 1196 should be retained by flip-flops or capacitors. If data retention is selected by flip-flops, power supply voltage is supplied to the memory cells in register 1196. If data retention is selected by capacitors, data is rewritten to the capacitors, and the power supply voltage to the memory cells in register 1196 can be stopped.

[0609] FIG41 is an example of a circuit diagram of a memory element 1200 that can be used as register 1196. Memory element 1200 includes a circuit 1201 that loses stored data when the power is turned off, a circuit 1202 that does not lose stored data when the power is turned off, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a circuit 1220 with a selection function. Circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Memory element 1200 may also include other components such as diodes, resistors, or inductors, as needed.

[0610] Here, the aforementioned memory device can be used in circuit 1202. When the power supply voltage to memory element 1200 is stopped, GND (0V) or a potential that turns off transistor 1209 is continuously input to the gate of transistor 1209 in circuit 1202. For example, the gate of transistor 1209 is grounded via a load such as a resistor.

[0611] Here, an example is shown in which switch 1203 is a transistor 1213 having one conductivity type (e.g., n-channel), and switch 1204 is a transistor 1214 having the opposite conductivity type (e.g., p-channel). Here, a first terminal of switch 1203 corresponds to one of the source and drain of transistor 1213, and a second terminal of switch 1203 corresponds to the other of the source and drain of transistor 1213. Conductivity or non-conduction between the first and second terminals of switch 1203 (i.e., the on / off state of transistor 1213) is selected by a control signal RD input to the gate of transistor 1213. A first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214, a second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and conduction or non-conduction between the first terminal and the second terminal of the switch 1204 (i.e., the on state / off state of the transistor 1214) is selected by a control signal RD input into the gate of the transistor 1214.

[0612] One of the source and drain of transistor 1209 is electrically connected to one of the pair of electrodes of capacitor 1208 and the gate of transistor 1210. This connection is referred to herein as node M2. One of the source and drain of transistor 1210 is electrically connected to a wiring capable of supplying a low power supply potential (e.g., a GND line), while the other is electrically connected to the first terminal of switch 1203 (one of the source and drain of transistor 1213). The second terminal of switch 1203 (the other of the source and drain of transistor 1213) is electrically connected to the first terminal of switch 1204 (one of the source and drain of transistor 1214). The second terminal of switch 1204 (the other of the source and drain of transistor 1214) is electrically connected to a wiring capable of supplying power supply potential VDD. The second terminal of switch 1203 (the other of the source and drain of transistor 1213), the first terminal of switch 1204 (one of the source and drain of transistor 1214), the input terminal of logic element 1206, and one of the pair of electrodes of capacitor 1207 are electrically connected to one another. The connection portion is referred to herein as node M1. A fixed potential can be input to the other of the pair of electrodes of capacitor 1207. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input thereto. The other of the pair of electrodes of capacitor 1207 is electrically connected to a wiring capable of supplying a low power supply potential (such as a GND line). A fixed potential can be input to the other of the pair of electrodes of capacitor 1208. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input thereto. The other of the pair of electrodes of capacitor 1208 is electrically connected to a wiring capable of supplying a low power supply potential (such as a GND line).

[0613] Note that when parasitic capacitance of a transistor or wiring is actively utilized, capacitor 1207 and capacitor 1208 may not be provided.

[0614] A control signal WE is input to the gate of transistor 1209. The conductive state or non-conductive state between the first terminal and the second terminal of switches 1203 and 1204 is selected by a control signal RD that is different from the control signal WE. When the first terminal and the second terminal of one switch are conductive, the first terminal and the second terminal of the other switch are non-conductive.

[0615] A signal corresponding to the data held in circuit 1201 is input to the other of the source and drain of transistor 1209. FIG41 shows an example in which a signal output from circuit 1201 is input to the other of the source and drain of transistor 1209. The logic value of the signal output from the second terminal of switch 1203 (the other of the source and drain of transistor 1213) is inverted by logic element 1206 to create an inverted signal, which is then input to circuit 1201 via circuit 1220.

[0616] Furthermore, while FIG41 illustrates an example in which the signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) is input to the circuit 1201 via the logic element 1206 and the circuit 1220, the present invention is not limited thereto. The signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) may be input to the circuit 1201 without inverting its logic value. For example, if the circuit 1201 includes a node that holds a signal that inverts the logic value of a signal input from an input terminal, the signal output from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) may be input to that node.

[0617] Among the transistors used in the memory element 1200 shown in FIG41 , transistors other than the transistor 1209 may have their channels formed in a film or substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a transistor whose channel is formed in a silicon film or silicon substrate may be used. Furthermore, all transistors in the memory element 1200 may have their channels formed of an oxide semiconductor. Alternatively, the memory element 1200 may include a transistor whose channel is formed of an oxide semiconductor in addition to the transistor 1209, and transistors whose channels are formed in a film or substrate 1190 made of a semiconductor other than an oxide semiconductor may be used as the remaining transistors.

[0618] The circuit 1201 shown in FIG41 can use a flip-flop circuit, for example. Also, as the logic element 1206, an inverter or a clock inverter can be used, for example.

[0619] In the semiconductor device according to one embodiment of the present invention, while the power supply voltage is not supplied to the memory element 1200, the data stored in the circuit 1201 can be retained by the capacitor 1208 provided in the circuit 1202.

[0620] Furthermore, the off-state current of a transistor whose channel is formed in an oxide semiconductor is extremely low. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor is much lower than the off-state current of a transistor whose channel is formed in crystalline silicon. Therefore, by using this transistor as transistor 1209, the signal held by capacitor 1208 can be stored for a long period of time even when the power supply voltage is not supplied to memory element 1200. Therefore, memory element 1200 can retain stored content (data) even when the power supply voltage is not supplied.

[0621] In addition, since the memory element is precharged by using the switches 1203 and 1204, the time required for the circuit 1201 to retain the original data after the power supply voltage is restarted can be shortened.

[0622] Furthermore, in circuit 1202, the signal held by capacitor 1208 is input to the gate of transistor 1210. Therefore, after the power supply voltage to memory element 1200 is resumed,...

Claims

1. A semiconductor device comprising a first transistor, a second transistor, and a capacitor, the semiconductor device comprising: The first insulating film on the substrate; The first insulating film includes a first semiconductor layer of silicon; A second insulating film on the first semiconductor layer; A first conductive layer on the second insulating film; a third insulating film on the first conductive layer; a second semiconductor layer comprising an oxide semiconductor on the third insulating film; a fourth insulating film on the second semiconductor layer; a second conductive layer on the fourth insulating film; a third conductive layer beneath the second semiconductor layer; a fourth conductive layer contacting one of the source and drain regions in the second semiconductor layer, and a fifth conductive layer contacting the other of the source and drain regions in the second semiconductor layer; wherein the first conductive layer is configured as the gate electrode of the first transistor; wherein the second conductive layer is configured as the first gate electrode of the second transistor; wherein the third conductive layer is configured as the second gate electrode of the second transistor; wherein the second conductive layer is electrically connected to the third conductive layer; wherein the first semiconductor layer is electrically contacted with the second semiconductor layer through the fourth conductive layer; wherein the fourth conductive layer has a region disposed on the second conductive layer; wherein the fifth conductive layer is configured as the first electrode of the capacitor. The capacitor's insulator overlaps with the capacitor's first electrode and is disposed on the same layer as the fourth insulating film, and the second semiconductor layer overlaps with the first semiconductor layer in the region where the first conductive layer and the third conductive layer do not overlap with each other.

2. A semiconductor device comprising a first transistor, a second transistor, and a capacitor, the semiconductor device comprising: The first insulating film on the substrate; The first insulating film includes a first semiconductor layer of silicon; A second insulating film on the first semiconductor layer; A first conductive layer on the second insulating film; a third insulating film on the first conductive layer; a second semiconductor layer comprising an oxide semiconductor on the third insulating film; a fourth insulating film on the second semiconductor layer; a second conductive layer on the fourth insulating film; a fifth insulating film on the second conductive layer; a third conductive layer beneath the second semiconductor layer; a fourth conductive layer contacting one of the source and drain regions in the second semiconductor layer, and a fifth conductive layer contacting the other of the source and drain regions in the second semiconductor layer; wherein the first conductive layer is configured as the gate electrode of the first transistor; wherein the second conductive layer is configured as the first gate electrode of the second transistor; wherein the third conductive layer is configured as the second gate electrode of the second transistor; wherein the second conductive layer is electrically connected to the third conductive layer; wherein the first semiconductor layer is electrically contacted with the second semiconductor layer through the fourth conductive layer; wherein the fourth conductive layer has a region disposed in an opening disposed in the fifth insulating film; wherein the fifth conductive layer is configured as the first electrode of the capacitor. The capacitor's insulator overlaps with the capacitor's first electrode and is disposed on the same layer as the fourth insulating film, and the second semiconductor layer overlaps with the first semiconductor layer in the region where the first conductive layer and the third conductive layer do not overlap with each other.

3. The semiconductor device as claimed in claim 1 or 2, wherein, The second semiconductor layer comprises indium, gallium, and zinc.

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