Semiconductor deviceand methods of forming the same

Abstract

A method of forming a semiconductor device includes: epitaxially growing a first multilayer stack over a first substrate, epitaxially growing a second multilayer stack over a second substrate, and bonding the first multilayer stack to the second multilayer stack. The first substrate and the second substrate have different crystal orientations. The method further includes patterning the first and second multilayer stacks to form a fin, the fin including a plurality of lower nanostructures alternately stacked with a first dummy nanostructure and a plurality of upper nanostructures alternately stacked with a second dummy nanostructure; replacing the first dummy nanostructure with a first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second dummy nanostructure with a second gate stack surrounding each of the plurality of upper nanostructures.

Description

Channel Region in a Stacked Transistor and Method of Forming the Same Semiconductor devices are used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. The manufacture of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate and using lithography to pattern the various material layers to form circuit components and elements thereon. The semiconductor industry has been continuously increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems need to be solved. The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. For ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. According to various embodiments, a stacked transistor such as a CFET is formed. The CFET includes an n-type nanostructure FET and a p-type nanostructure FET vertically stacked together. The NFET channel region of the n-type nanostructure FET and the PFET channel region of the p-type nanostructure FET can be epitaxially grown on two different substrates, each substrate being oriented in a different crystalline plane. For example, the NFET channel region can be formed of a first semiconductor layer epitaxially grown on a silicon substrate oriented in the (100) plane, and the PFET channel region can be formed of a second semiconductor layer epitaxially grown on a silicon substrate oriented in the (110) plane. Subsequently, the two substrates are bonded together, and the CFET is formed by the bonding structure. In this way, a p-type nanostructure FET can be formed on (110)-plane-oriented silicon to increase the mobility without degrading the performance of the n-type nanostructure FET. Thus, various embodiments allow the CFET to have improved performance of the p-type nanostructure FET without affecting the performance of the n-type nanostructure FET. FIG. 1 shows an example of a schematic diagram of a CFET according to some embodiments. FIG. 1 is a three-dimensional view, and some features of the CFET are omitted for clarity. The CFET includes a plurality of vertically stacked nanostructure FETs (such as nanowire FETs, nanosheet FETs, multi bridge channel (MBC) FETs, nanoribbon FETs, gate-all-around (GAA) FETs, or the like). For example, the CFET can include a lower nanostructure FET of a first device type (such as n-type / p-type) and an upper nanostructure FET of a second device type opposite to the first device type (such as p-type / n-type). Specifically, the CFET can include a lower PMOS transistor and an upper NMOS transistor, or the CFET can include a lower NMOS transistor and an upper PMOS transistor. For simplicity, various embodiments will be described below in the context of manufacturing a CFET having a lower PMOS transistor and an upper NMOS transistor. However, it should be understood that various embodiments can also be applied to a CFET having a lower NMOS transistor and an upper PMOS transistor. Each nanoscale FET includes a semiconductor nanostructure 66 (labeled as a lower semiconductor nanostructure 66L and an upper semiconductor nanostructure 66U), where the semiconductor nanostructure 66 serves as the channel region of the nanoscale FET. The semiconductor nanostructure 66 can be a nanosheet, a nanowire, or the like. The lower semiconductor nanostructure 66L is for the lower nanoscale FET, and the upper semiconductor nanostructure 66U is for the upper nanoscale FET. A channel isolation material (not explicitly shown in FIG. 1, see FIG. 12A) can be used to separate and electrically isolate the upper semiconductor nanostructure 66U from the lower semiconductor nanostructure 66L. The gate dielectric 132 is along the top, side, and bottom surfaces of the semiconductor nanostructure 66. The gate electrode 134 (including a lower gate electrode 134L and an upper gate electrode 134U) is above the gate dielectric 132 and around the semiconductor nanostructure 66. The source / drain regions 108 (labeled as a lower source / drain region 108L and an upper source / drain region 108U) are disposed on opposite sides of the gate dielectric 132 and the gate electrode 134. Depending on the context, one or more source / drain regions 108 may refer to the source or the drain individually or collectively. Isolation features can be formed to separate the desired source / drain regions 108 and / or the desired gate electrodes 134. For example, the lower gate electrode 134L can be selectively separated from the upper gate electrode 134U. As another option, the lower gate electrode 134L can be coupled to the upper gate electrode 134U. In addition, the upper source / drain region 108U can be separated from the lower source / drain region 108L by one or more dielectric layers (not explicitly shown in FIG. 1, see FIGS. 20A - 20C). The isolation features between the channel region, the gate, and the source / drain regions allow for vertical stacking of transistors, thereby increasing device density. Due to the vertically stacked nature of the CFET, this schematic can also be referred to as a stacked transistor or a folding transistor. FIG. 1 further shows the reference cross-sections used in the subsequent figures. The cross-section A - A' is parallel to the longitudinal axis of the semiconductor nanostructure 66 of the CFET and along the direction of current flow, for example, between the source / drain regions 108 of the CFET. The cross-section B - B' is perpendicular to the cross-section A - A' and along the longitudinal axis of the gate electrode 134 of the CFET. The cross-section C - C' is parallel to the cross-section B - B' and extends through the source / drain regions 108 of the CFET. For clarity, the subsequent figures all refer to these reference cross-sections. Figures 2A - 13C are views of intermediate stages of manufacturing a CFET according to some embodiments. Figures 2A, 2B, 3A, 3B, 4A, 5, 6, 7, and 8 show three - dimensional views similar to the three - dimensional view of Figure 1. Figures 9, 10, 11, 12A, 13A, and 14 show cross - sectional views along a reference cross - section A - A' similar to that in Figure 1. Figures 12B and 13B show cross - sectional views along a reference cross - section B - B' similar to that in Figure 1. Figures 12C and 13C show cross - sectional views along a reference cross - section C - C' similar to that in Figure 1. In Figures 2A and 2B, two substrates 60L and 60U are provided respectively. Figure 2A shows substrate 60L and Figure 2B shows substrate 60U. In subsequent processes, substrate 60U can be bonded above substrate 60L (see Figure 4). Thus, substrate 60L can be referred to as the lower substrate 60L and substrate 60U can also be referred to as the upper substrate 60U. Each of substrates 60L and 60U can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor - on - insulator (SOI) substrate, or the like, which can be doped (e.g., with p - type or n - type dopants) or undoped. Substrates 60L and 60U can each be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates can also be used, such as multi - layer or gradient substrates. In some embodiments, the semiconductor material of substrates 60L and 60U can include: silicon, germanium, compound semiconductors (including carbon - doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, and / or gallium arsenide phosphide indium) or combinations thereof. In various embodiments, substrate 60L has a different crystalline orientation from substrate 60U. The crystalline orientations of substrates 60U and 60L may depend on the type of channel region to be formed by the semiconductor layers grown on each of substrates 60L and 60U. For example, substrate 60L is a (110)-oriented substrate, while substrate 60U is a (100)-oriented substrate. In another example, substrate 60L is a (100)-oriented substrate, while substrate 60U is a (110)-oriented substrate. Forming a channel region for a p-type transistor device from a semiconductor layer grown on a (110)-plane-oriented semiconductor surface has the advantage of including increased mobility, thereby improving the performance of the p-type transistor device. However, forming a channel region for an n-type device from a semiconductor layer grown on a (110)-plane-oriented semiconductor surface may reduce the performance of the n-type transistor device. By growing channel materials on two substrates with different crystalline orientations, the performance of the p-type device can be improved without reducing the performance of the n-type device. Multilayer stack 52L and multilayer stack 52U are respectively formed over substrate 60L and substrate 60U to form structures 50A, 50B respectively. Multilayer stack 52L includes alternating dummy semiconductor layers 54L and semiconductor layers 56L, and multilayer stack 52U includes alternating dummy semiconductor layers 54U and semiconductor layers 56U. After substrates 60U and 60L are subsequently bonded together, dummy semiconductor layers 54L and semiconductor layers 56L are disposed below dummy semiconductor layers 54U and semiconductor layers 56U (see FIG. 4). Thus, the layers (54L and 56L) may also be respectively referred to as lower dummy semiconductor layer 54L and lower semiconductor layer 56L, and layers 54U and 56U may also be respectively referred to as upper dummy semiconductor layer 54U and upper semiconductor layer 56U. As described in more detail subsequently, dummy semiconductor layers 54L and 54U will be removed and semiconductor layers 56L and 54U will be patterned to form the channel region of the CFET. Specifically, lower semiconductor layer 56L will be patterned to form the channel region of the lower nanostructure FET of the CFET, and upper semiconductor layer 56U will be patterned to form the channel region of the upper nanostructure FET of the CFET. The multilayer stacks 52L and 52U are each shown as including a specific number of dummy semiconductor layers 54L / 54U and semiconductor layers 56L / 56U. It should be understood that the multilayer stacks 52L and 52U can include any number of dummy semiconductor layers 54L / 54U and / or semiconductor layers 56L / 56U. Each of the multilayer stacks 52L and 52U can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE) or deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). In an embodiment where the lower nanostructure FET of the CFET is a p-type nanostructure FET and the upper nanostructure FET of the CFET is an n-type nanostructure FET, the multilayer stack 52L is grown on the (110)-plane-oriented surface of the lower substrate 60L and the multilayer stack 52U is grown on the (100)-plane-oriented surface of the upper substrate 60U. In such embodiments, the lower substrate 60L can be a (110)-plane-oriented silicon substrate and the upper substrate 60U can be a (100)-plane-oriented silicon substrate. In an embodiment where the lower nanostructure FET of the CFET is an n-type nanostructure FET and the upper nanostructure FET of the CFET is a p-type nanostructure FET, the multilayer stack 52L is grown on the (100)-plane-oriented surface of the lower substrate 60L and the multilayer stack 52U is grown on the (110)-plane-oriented surface of the upper substrate 60U. In such embodiments, the lower substrate 60L can be a (100)-plane-oriented silicon substrate and the upper substrate 60U can be a (110)-plane-oriented silicon substrate. In this way, since the p-type and n-type transistors have channel materials grown on substrates with different crystal orientations respectively, various embodiments provide p-type transistors with improved performance (such as improved mobility) without degrading the performance of the n-type transistors. The semiconductor layers of the lower multilayer stack 52L can be lattice-matched to the crystal orientation of the lower substrate 60L, and the semiconductor layers of the upper multilayer stack 52U can be lattice-matched to the crystal orientation of the upper substrate 60U. Apparently, due to the different crystal orientations of the substrates 60L and 60U, the lower multilayer stack 52L can have a different crystal orientation from that of the upper multilayer stack 52U. For example, when the multilayer stack 52L is grown on the (110)-oriented surface of the lower substrate 60L, the dummy semiconductor layer 54L and the semiconductor layer 56L can also include a crystal structure oriented along the (110) plane. In addition, when the multilayer stack 52U is grown on the (100)-oriented surface of the upper substrate 60U, the dummy semiconductor layer 54U and the semiconductor layer 56U can also include a crystal structure oriented along the (100) plane. Conversely, when the multilayer stack 52L is grown on the (100)-oriented surface of the lower substrate 60L, the dummy semiconductor layer 54L and the semiconductor layer 56L can also include a crystal structure oriented along the (100) plane. In addition, when the multilayer stack 52U is grown on the (110)-oriented surface of the upper substrate 60U, the dummy semiconductor layer 54U and the semiconductor layer 56U can also include a crystal structure oriented along the (110) plane. Therefore, when the substrates 60U and 60L are subsequently bonded together, the bonded structure includes hetero-orientation semiconductor layers. The dummy semiconductor layers 54U and 54L are formed of a first semiconductor material selected from the candidate semiconductor materials of the substrates 60U and 60L. The semiconductor layers 56U and 56L are formed of one or more second semiconductor materials. The second semiconductor material can be selected from the candidate semiconductor materials of the substrates 60U and 60L. The lower semiconductor layer 56L and the upper semiconductor layer 56U can be formed of the same semiconductor material or can be formed of different semiconductor materials. In some embodiments, both the lower semiconductor layer 56L and the upper semiconductor layer 56U are formed of a semiconductor material (such as silicon) suitable for p-type devices and n-type devices. In some embodiments, the lower semiconductor layer 56L is formed of a semiconductor material (such as germanium or silicon-germanium) suitable for p-type devices, and the upper semiconductor layer 56U is formed of a semiconductor material (such as silicon or carbon-doped silicon) suitable for n-type devices. The semiconductor materials of the semiconductor layers 56U and 56L are different from those of the dummy semiconductor layers 54U and 54L, and have a high etching selectivity relative to the semiconductor materials of the dummy semiconductor layers 54U and 54L. Therefore, in subsequent processing, the materials of the dummy semiconductor layers 54U and 54L can be removed at a faster rate than the materials of the semiconductor layers 56U and 56L. In some embodiments, the dummy semiconductor layers 54U and 54L are formed of silicon-germanium, and the semiconductor layers 56U and 56L are formed of silicon. The silicon of the semiconductor layers 56U and 56L can be undoped or lightly doped in this processing step. In FIGS. 3A and 3B, insulating bonding layers 58L and 58U are respectively deposited on multilayer stacks 52L and 52U. FIG. 3A shows a perspective view of a substrate 60L, a multilayer stack 52L (including a dummy semiconductor layer 54L and a semiconductor layer 56L), and a bonding layer 58L, and FIG. 3B shows a perspective view of a substrate 60U, a multilayer stack 52U (including a dummy semiconductor layer 54U and a semiconductor layer 56U), and a bonding layer 58U. The bonding layers 58L and 58U can be deposited by any suitable process (such as physical vapor deposition (PVD), CVD, ALD, etc.). The bonding layers 58L and 58U can facilitate bonding the lower substrate 60L to the upper substrate 60U in subsequent processes (see FIG. 4). The bonding layers 58L and 58U can each include an insulating material suitable for a dielectric-to-dielectric bonding process in subsequent processes. Example materials for the bonding layers 58L and 58U include silicon oxide (such as SiO 2 ), silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, etc. The material composition of the bonding layer 58L can be the same as or different from the material composition of the bonding layer 58U. In FIGS. 4A to 4D, an upper substrate 60U having a multilayer stack 52U disposed thereon is placed above and bonded to a lower substrate 60L having a multilayer stack 52L disposed thereon. As shown in FIG. 4A, the bonded structure includes: a lower substrate 60L; a lower multilayer stack 52L above the lower substrate 60L; bonding layers 58L and 58U above the lower multilayer stack 52L; an upper multilayer stack 52U above the bonding layers 58L and 58U; and an upper substrate 60U above the upper multilayer stack 52U. The upper substrate 60U can be bonded to the lower substrate 60L by the bonding layers 58L and 58U. Specifically, the bonding layers 58L and 58U can be bonded together using appropriate techniques (such as dielectric-to-dielectric bonding, etc.). After bonding, the lower bonding layer 58L and the upper bonding layer 58U can be collectively referred to as the bonding layer 58. The bonding layer 58 may or may not have an interface where the bonding layer 58L intersects the bonding layer 58U disposed therein. FIGS. 4B to 4D show schematic diagrams of the bonding mechanism for the bonding layers 58L and 58U when the bonding layers 58L and 58U are silicon oxide layers. In other embodiments, there may be other bonding mechanisms. In FIG. 4B, the dielectric-to-dielectric bonding process includes surface-treating one or more layers in bonding layer 58L or 58U to form hydroxyl (OH) groups at the bonding surfaces of bonding layers 58L and 58U. The surface treatment may include plasma treatment. For example, the plasma treatment may be performed at a pressure in the range of 0.2 millibar (mbar) to 0.4 mbar, with a high-frequency (e.g., in the range of 377 Hertz (Hz) to 417 Hz) power in the range of 10 watts (W) to 20 W, a low-frequency (e.g., in the range of 35 Hz to 45 Hz) power in the range of 45 W to 55 W, a duration in the range of 12 seconds to 22 seconds, and at room temperature in the range of, for example, 25°C to 26°C, nitrogen (N 2 ) plasma is applied to the exposed surfaces of bonding layers 58L and 58U. There may also be other plasma treatment parameters. After the plasma treatment, the surface treatment may further include one or more cleaning processes that can be applied to bonding layers 58L and 58U. The cleaning process may include flushing with a mixture of nitrogen (N 2 ) and water (H 2 O) at a rate of 450 revolutions per minute (rpm) to 550 rpm for a duration of 25 seconds to 35 seconds at room temperature. The flushing mixture may supply nitrogen at a rate of 60 standard liters per minute (slm) to 80 slm and water at a rate of 0.6 slm to 0.8 slm. After flushing, spin drying may be performed at a rate of 1900 rpm to 2100 rpm for a duration of 9 seconds to 13 seconds at room temperature. Thus, the surfaces of bonding layers 58L and 58U can be capped with hydroxyl groups. Other cleaning processes may also be applied in other embodiments. In FIG. 4C, bonding layer 58U may be placed above bonding layer 58L and aligned with bonding layer 58L. Then the two bonding layers 58L and 58U are pressed against each other to initiate pre-bonding of upper substrate 60U and lower substrate 60L. The pre-bonding may be performed at room temperature (e.g., in the range of 25°C to 26°C). The pre-bonding may trigger the formation of hydrogen bridge 59 at interface 61 where the lower bonding layer 58L contacts the upper bonding layer 58U. Specifically, pairs of bridging Si-OH groups from bonding layers 58L and 58U may define siloxane and water at interface 61. After pre-bonding, in FIG. 4D, an annealing process can be applied by heating the substrates 60L and 60U to a temperature in the range of 240 °C to 360 °C, for example. The annealing process can be carried out, for example, in a nitrogen environment and at a pressure of 0.99 atmospheres (atm) to 1.01 atm for a duration of 1.8 hours (h) to 4.2 h. There may also be other annealing parameters. The annealing process drives the formation of covalent bonds between the trigger bonding layers 58L and 58U. Specifically, the annealing process can diffuse away water (H2O) as a by-product and increase the formation of siloxane at the interface 61. A relatively low-temperature annealing process can be used in various embodiments because a nitric acid treatment (such as the cleaning process described above) can be applied to the bonding layers 58L and 58U, which reduces the formation of undesired water tetramers. The presence of water tetramers may force a high annealing temperature (such as greater than 590 °C or even greater than 610 °C) to decompose the tetramers. By applying a fuming nitric acid treatment to the bonding layers 58L and 58U before annealing, such water tetramers can be reduced, thus allowing a relatively low-temperature annealing to be performed in the bonding process. In FIG. 5, a thinning process is applied to reduce the thickness of the upper substrate 60U to a desired thickness. The thinning process can include a grinding process, a chemical mechanical polish, an etch-back process, a combination thereof, etc. The thinning process can reduce the thickness of the upper substrate 60U to match the thickness of each of the semiconductor layers 56U and / or 56L. In subsequent process steps, the thinned upper substrate 60U can be patterned to provide nanostructures (such as channel regions) for the upper nanostructure FETs of the CFET. In FIG. 6, a semiconductor fin 62 is formed in a lower substrate 60L. In addition, nanostructures 64, 66 (including dummy nanostructures 64, lower semiconductor nanostructures 66L, intermediate semiconductor nanostructures 66M, and upper semiconductor nanostructures 66U) are formed in an upper substrate 60U and multilayer stacks 52L and 52U, and an isolation material 100 is formed by a bonding layer 58. In some embodiments, the nanostructures 64, 66, the isolation material 100, and the semiconductor fin 62 are formed by etching trenches in the upper substrate 60U, the upper multilayer stack 52U, the bonding layer 58, the lower multilayer stack 52L, and the lower substrate 60L. The etching can be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching can be anisotropic. The formation of the nanostructures 64, 66 can define the dummy nanostructures 64 by a lower dummy semiconductor layer 54L and an upper dummy semiconductor layer 54U, the lower semiconductor nanostructures 66L by some of the lower semiconductor layer 56L, the upper semiconductor nanostructures 66U by some of the upper semiconductor layer 56U, and the intermediate semiconductor nanostructures 66M by some of the lower semiconductor layer 56L and some of the upper semiconductor layer 56U. Due to the difference in crystal orientation of the upper semiconductor layer 56U compared to the lower semiconductor layer 56L, the upper semiconductor nanostructures 66U can also have a crystal orientation different from that of the lower semiconductor nanostructures 66L. For example, the upper semiconductor nanostructures 66U can include side surfaces in the (100) crystal orientation, while the lower semiconductor nanostructures 66L can include side surfaces in the (110) crystal orientation. As another example, the upper semiconductor nanostructures 66U can include side surfaces in the (110) crystal orientation, while the lower semiconductor nanostructures 66L can include side surfaces in the (100) crystal orientation. The lower semiconductor nanostructures 66L and the upper semiconductor nanostructures 66U can also be collectively referred to as semiconductor nanostructures 66. The lower semiconductor nanostructures 66L will serve as the channel regions of the lower-nanostructure FETs of the CFET. The upper semiconductor nanostructures 66U will serve as the channel regions of the upper-nanostructure FETs of the CFET. The intermediate semiconductor nanostructures 66M are the semiconductor nanostructures 66 directly above / below (e.g., in contact with) the second dummy nanostructure 64B. Depending on the height of the subsequently formed source / drain regions, the intermediate semiconductor nanostructures 66M may or may not be adjacent to any source / drain regions and may or may not serve as the functional channel regions of the CFET. The isolation structure and the intermediate semiconductor nanostructures 66M can define the boundaries of the lower-nanostructure FETs and the upper-nanostructure FETs. The semiconductor fins 62, nanostructures 64, 66, and isolation material 100 can be patterned by any suitable method. For example, the semiconductor fins 62, nanostructures 64, 66, and isolation material 100 can be patterned using one or more lithography processes (including double patterning or multiple patterning processes). Generally, double patterning or multiple patterning processes combine optical lithography and self-alignment processes, thereby allowing the creation of patterns with pitches, for example, smaller than those obtained using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacer walls are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer walls can then be used to pattern the semiconductor fins 62, nanostructures 64, 66, and isolation material 100. In some embodiments, a mask (or other layer) can be retained over the nanostructures 64, 66. Although each of the semiconductor fins 62, nanostructures 64, 66, and isolation material 100 is shown as having a constant width, in other embodiments, the semiconductor fins 62, nanostructures 64, 66, and / or isolation material 100 can have sloped sidewalls such that the width of each of the semiconductor fins 62, nanostructures 64, 66, and / or isolation material 100 continuously increases in a direction towards the substrate 60L. In such embodiments, each of the nanostructures 64, 66, and isolation material 100 can have a different width and be trapezoidal in shape. In FIG. 7, isolation regions 70 are formed over the lower substrate 60L and between adjacent semiconductor fins 62. The isolation regions 70 can include a dielectric liner and a dielectric material over the dielectric liner. Each of the dielectric liner and the dielectric material can include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), the like, or a combination thereof. The formation of the isolation regions 70 can include depositing one or more dielectric layers and performing a planarization process (e.g., a chemical mechanical polishing (CMP) process, a mechanical polishing process, or the like) to remove excess portions of the dielectric material, e.g., portions over the nanostructures 64, 66. The deposition process can include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. In some embodiments, the isolation regions 70 include silicon oxide formed by an FCVD process followed by an annealing process. Then, one or more dielectric layers are recessed to define the isolation regions 70. The one or more dielectric layers can be recessed such that upper portions of the semiconductor fins 62, nanostructures 64, 66, and isolation material 100 extend higher than the remaining STI regions. In FIG. 8, a dummy dielectric layer 72 is formed on the semiconductor fin 62, nanostructures 64, 66, and / or isolation material 100. The dummy dielectric layer 72 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 74 is formed above the dummy dielectric layer 72, and a capping layer 76 is formed above the dummy gate layer 74. The dummy gate layer 74 can be deposited above the dummy dielectric layer 72 and then planarized, for example, by chemical mechanical polishing. The capping layer 76 can be deposited above the dummy gate layer 74. The dummy gate layer 74 can be a conductive or non-conductive material and can be selected from amorphous silicon, polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal, etc. The dummy gate layer 74 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 74 can be made of other materials that have a high etch selectivity with respect to the etching of the isolation regions. The capping layer 76 can include, for example, silicon nitride, silicon oxynitride, or the like. In the illustrated embodiment, the dummy dielectric layer 72 covers the isolation region 70 such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the isolation region 70. In another embodiment, the dummy dielectric layer 72 only covers the semiconductor fin 62, nanostructures 64, 66, and / or isolation material 100. In FIG. 9, the capping layer 76 can be patterned using acceptable photolithography and etching techniques to form a capping mask 86. Then the pattern of the capping mask 86 can be transferred to the dummy gate layer 74 and the dummy dielectric layer 72 to form a dummy gate 84 and a dummy dielectric 82, respectively. The dummy gate 84 covers the channel regions of the nanostructures 64, 66, respectively. The pattern of the capping mask 86 can be used to physically separate each of the dummy gate 84 and the adjacent dummy gates 84 from each other. The dummy gate 84 can also have a length direction that is generally perpendicular to the length direction of the corresponding semiconductor fin 62. After patterning, the capping mask 86 can be selectively removed, for example, by any acceptable etching technique. In FIG. 10, the gate spacer 90 is formed over the nanostructures 64, 66 and on the exposed sidewalls of the capping layer 86 (if present), dummy gate 84, and dummy dielectric 82. The gate spacer 90 can be formed by conformally depositing one or more dielectric materials and then etching the dielectric materials. Acceptable dielectric materials can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or the like, which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Other dielectric materials formed by any acceptable process can be used. Any acceptable etching process (e.g., dry etching, wet etching, etc. or a combination thereof) can be performed to pattern the dielectric materials. The etching can be anisotropic. During etching, one or more dielectric materials leave portions on the sidewalls of the dummy gate 84 (thereby forming the gate spacer 90). In some embodiments, during etching, the dielectric materials can also leave portions on the sidewalls of the semiconductor fin 62 and / or nanostructures 64, 66. It should be noted that the previous disclosure generally describes the process of forming the spacer. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different sequences of steps can be used, additional spacers can be formed and removed, etc. Source / drain recesses 94 are formed in the semiconductor fin 62, nanostructures 64, 66, isolation material 100, and substrate 60L. Epitaxial source / drain regions will subsequently be formed in the source / drain recesses 94. The source / drain recesses 94 can extend through the nanostructures 64, 66, through the isolation material 100 and into the substrate 60L. The semiconductor fin 62 can be etched such that the bottom surface of the source / drain recess 94 is disposed above, below, or flush with the top surface of the isolation region 70. The source / drain recesses 94 can be formed by etching the semiconductor fin 62, nanostructures 64, 66, isolation material 100, and substrate 60L using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process for forming the source / drain recesses 94, the gate spacers 90 and dummy gate 84 shield portions of the semiconductor fin 62, nanostructures 64, 66, isolation material 100, and substrate 60L. A single etching process or multiple etching processes can be used to etch each layer in the nanostructures 64, 66, isolation material 100, and / or semiconductor fin 62. A timed etching process can be used to stop etching of the source / drain recesses 94 after the source / drain recesses 94 reach the desired depth. In FIG. 11, an inner spacer wall 98 is formed on the sidewalls of the dummy nanostructure 64 and the isolation material 100. To form the inner spacer wall 98, multiple portions of the sidewalls of the dummy nanostructure 64 and the isolation material 100 that are exposed by the source / drain recess 94 are recessed to form sidewall recesses. The sidewall recesses can be formed by recessing the sidewalls of the dummy nanostructure 64 and the isolation material 100 using any acceptable etching process. The etching is selective for the material of the dummy nanostructure 64 (e.g., etching the material of the dummy nanostructure 64 at a faster rate than the material of the semiconductor nanostructure 66). The etching can also be selective for the material of the first isolation material 100 (e.g., selectively etching the material of the first isolation material 100 at a faster rate than the material of the semiconductor nanostructure 66). The etching can be isotropic. Although the sidewalls of the dummy nanostructure 64 and the isolation material 100 are shown as straight after etching, the sidewalls can be concave or convex. In some embodiments, the same etching process is used to recess the sidewalls of the dummy nanostructure 64 and the isolation material 100. Specifically, the etching process can selectively etch the material of the dummy nanostructure 64 at a faster rate (e.g., as shown in FIG. 11), the same rate, or a slower rate than the isolation material 100. The etching rate results in relatively different dimensions on the sidewalls of the dummy nanostructure 64 compared to the isolation material 100. The relative etching rates of the dummy nanostructure 64 and the isolation material 100 can be achieved, for example, by adjusting the etching parameters of the etching process. Then, an inner spacer wall 98 is formed in the sidewall recesses of the dummy nanostructure 64 and the isolation material 100. As described in more detail subsequently, source / drain regions will then be formed in the source / drain recess 94, and the dummy nanostructure 64 will be replaced by corresponding gate structures. The inner spacer wall 98 serves as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structures. In addition, the inner spacer wall 98 can be used to prevent the subsequently formed source / drain regions from being damaged by subsequent etching processes (e.g., the etching process used to form the gate structures). The inner spacer wall 98 can be formed by conformally forming an insulating material in the source / drain recess 94 and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon carbide, silicon nitride, etc. Other low dielectric constant (low-k) materials with a dielectric constant value less than about 3.5 can be used. The insulating material can be formed by a deposition process (e.g., ALD, CVD, etc.). The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. When etching, there are remaining portions of the insulating material in the sidewall recesses 96A and 96B (thus forming the inner spacer wall 98). Although the outer sidewall of the inner spacer wall 98 is shown flush with the sidewall of the semiconductor nanostructure 66, the outer sidewall of the inner spacer wall 98 may extend beyond the sidewall of the semiconductor nanostructure 66 or be recessed from the sidewall of the semiconductor nanostructure 66. In other words, the inner spacer wall 98 may partially fill, fully fill, or overfill the sidewall recesses 96A and 96B. Additionally, although the sidewalls of the inner spacer wall 98 are shown as straight, those sidewalls may be concave or convex. Due to the dimensional differences between the dummy nanostructure 64 and the sidewall recesses on the isolation material 100, the inner spacer wall 98 on the isolation material 100 may also have a different dimension (e.g., width) from the inner spacer wall 98 on the dummy semiconductor nanostructure 64. For example, in the illustrated embodiment, the width of the inner spacer wall 98 on the isolation material 100 is less than the width of the inner spacer wall 98 on the dummy semiconductor nanostructure 64. In other embodiments, the inner spacer wall 98 on the isolation material 100 may be wider or have the same width as the inner spacer wall 98 on the dummy semiconductor nanostructure 64. In FIGS. 12A to 12C, lower and upper epitaxial source / drain regions 108L and 108U are formed. The lower epitaxial source / drain region 108L is formed in the lower portion of the source / drain recess 94. The lower epitaxial source / drain region 108L contacts the lower semiconductor nanostructure 66L and does not contact the upper semiconductor nanostructure 66U. The inner spacer wall 98 electrically insulates the lower epitaxial source / drain region 108L from the dummy nanostructure 64, which will be replaced by a gate in a subsequent process. The lower epitaxial source / drain region 108L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 108L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon, which is doped with an n-type dopant such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 108L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium, which is doped with a p-type dopant such as boron, indium, etc. The lower epitaxial source / drain region 108L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopant. During the epitaxial growth of the lower epitaxial source / drain region 108L, the upper semiconductor nanostructure 66U may be masked to prevent unwanted epitaxial growth on the upper semiconductor nanostructure 66U. After growing the lower epitaxial source / drain region 108L, the mask on the upper semiconductor nanostructure 66U may be removed. As a result of the epitaxial process for forming the lower epitaxial source / drain region 108L, the upper surface of the lower epitaxial source / drain region 108L has facets that laterally extend outward beyond the sidewalls of the multilayer stack. In some embodiments (see FIG. 12C), after the epitaxial process is completed, adjacent lower epitaxial source / drain regions 108L remain separated. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 108L of the same FET to merge. A first contact etch stop layer (CESL) 112 and a first ILD 114 are formed over the lower epitaxial source / drain region 108L. The first CESL 112 can be formed of a dielectric material (such as silicon nitride, silicon oxide, silicon oxynitride, or the like) that has a high etch selectivity relative to the etch of the first ILD 114, and it can be formed by any suitable deposition process (such as CVD, ALD, or the like). The first ILD 114 can be formed of a dielectric material, and it can be deposited by any appropriate method (such as CVD, plasma-enhanced CVD (PECVD), or FCVD). Suitable dielectric materials for the first ILD 68 can include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), silicon oxide, and the like. The formation process can include depositing a conformal CESL layer, depositing the material for the first ILD 114, followed by a planarization process and then an etch-back process. In some embodiments, the first ILD 114 is etched first, while the first CESL 112 is not etched. Then an anisotropic etch process is performed to remove the portion of the first CESL 112 that is above the recessed first ILD 114. After the recess, the sidewalls of the upper semiconductor nanostructure 66U are exposed. Then, an upper epitaxial source / drain region 108U is formed in the upper portion of the source / drain recess 94. The upper epitaxial source / drain region 108U can be epitaxially grown on the exposed surface of the upper semiconductor nanostructure 66U. Depending on the desired conductivity type of the upper epitaxial source / drain region 108U, the material of the upper epitaxial source / drain region 108U can be selected from the same candidate group of materials as those used to form the lower source / drain region 108L. The conductivity type of the upper epitaxial source / drain region 108U can be opposite to that of the lower epitaxial source / drain region 108L. For example, the upper epitaxial source / drain region 108U can be doped oppositely to the lower epitaxial source / drain region 108L. The upper epitaxial source / drain region 108U can be in-situ doped and / or implantable with n-type or p-type dopants. Adjacent upper source / drain regions 108U can remain separated (see FIG. 12C) or can be merged after the epitaxial process. After forming the epitaxial source / drain region 108U, a second CESL 122 and a second ILD 124 are formed. The materials and formation methods can be respectively similar to those of the first CESL 112 and the first ILD 114, which will not be discussed in detail herein. The formation process can include depositing layers of the CESL 122 and the ILD 124 and performing a planarization process to remove the excess portions of the corresponding layers. After the planarization process, the top surface of the second ILD 124, the top surface of the gate spacer walls 90, and the top surface of the dummy gate stack are coplanar within the process variation range. The planarization process can remove the mask 86 or can retain the hard mask 86 without removing it. FIGS. 13A to 13C illustrate a replacement gate process of replacing the dummy gate stack 82 / 84 and the dummy nanostructure 64 with a gate stack 136. The replacement gate process includes first removing the remaining portions of the dummy gate stack 82 / 84 and the dummy nanostructure 64. The hard mask 86 (if present) can also be removed. The dummy gate stack 82 / 84 is removed in one or more etching processes such that a recess is defined between the gate spacer walls 90 and the semiconductor nanostructure 66 / the dummy nanostructure 64 is exposed. Then, the remaining portion of the dummy nanostructure 64 is removed by etching such that the recess extends between the semiconductor nanostructures 66. In the etching process, the dummy nanostructure 64 is etched at a faster etching rate than the semiconductor nanostructures 66, the isolation material 100, and the inner spacer wall 98. The etching can be isotropic. For example, when the dummy nanostructure 64 is formed of silicon germanium and the semiconductor nanostructures 66 are formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), etc. Then, the gate dielectric 130 is deposited in the recess between the gate spacer walls 90 and on the exposed semiconductor nanostructures 66. The gate dielectric 130 conformally forms on the exposed surfaces of the recess (the removed gate stack 82 / 84 and the dummy nanostructures 64), which includes the semiconductor nanostructures 66, the isolation material 100, and the gate spacer walls 90. In some embodiments, the gate dielectric 130 surrounds all (e.g., four) sides of the semiconductor nanostructures 66 and the isolation material 100. Specifically, the gate dielectric 130 can be formed on the top surface of the fin 62, on the top surfaces, sidewalls, and bottom surfaces of the semiconductor nanostructures 66U, 66L, on the exposed side surfaces and sidewalls of the semiconductor nanostructure 66M, on the sidewalls of the isolation material 100, and on the sidewalls of the gate spacer walls 90. The gate dielectric 130 can include an oxide (e.g., silicon oxide) or a metal oxide, a silicate (e.g., a metal silicate), a combination thereof, a multilayer thereof, or the like. The gate dielectric 130 can include a high-k (high dielectric constant) material having a dielectric constant value greater than about 7.0, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The method of forming the gate dielectric 130 can include molecular-beam deposition (MBD), ALD, PECVD, etc. Although a single layer of the gate dielectric 130 is shown, the gate dielectric 130 can include multiple layers, such as an interface layer and an upper high-k dielectric layer. The lower gate electrode 134L is formed on the gate dielectric 130 surrounding the lower semiconductor nanostructure 66L. For example, the lower gate electrode 134L surrounds the lower semiconductor nanostructure 66L. The lower gate electrode 134L can be formed of a metal-containing material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. Although a single-layer gate electrode is shown, the lower gate electrode 134L can include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filling materials. The lower gate electrode 134L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 134L may include one or more work function adjustment layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 134L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 134L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or alternatively, the lower gate electrode 134L may include a dipole-inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof. The lower gate electrode 134L can be formed by conformally depositing one or more gate electrode layers and recessing the gate electrode layers. Any acceptable etching process (e.g., dry etching, wet etching, the like, or a combination thereof) can be performed to recess the lower gate electrode 134L to a desired level (e.g., at or below the level of the isolation material 100). The etching can be isotropic. Etching the lower gate electrode 134L can expose the upper semiconductor nanostructure 66U. In some embodiments, an isolation layer (not explicitly shown) can be selectively formed on the lower gate electrode 134L. The isolation layer serves as an isolation feature between the lower gate electrode 134L and the subsequently formed upper gate electrode 134U. The isolation layer can be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, combinations thereof, or the like) and then recessing the dielectric material to expose the upper semiconductor nanostructure 66U. Then, the upper gate electrode 134U is formed on the above-described isolation layer (if present) or on the lower gate electrode 134L. The upper gate electrode 134U is disposed between the upper semiconductor nanostructures 66U. In some embodiments, the upper gate electrode 134U surrounds the upper semiconductor nanostructures 66U. The upper gate electrode 134U can be formed of the same candidate materials and candidate processes used to form the lower gate electrode 134L. The upper gate electrode 134U is formed of a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 134U may include one or more work function adjustment layers formed of a material suitable for the device type of the upper nanostructure FET. Although a single layer of the gate electrode 134U is shown, the upper gate electrode 134U may include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filling materials. Additionally, one or more removal processes are performed to make the top surfaces of the upper gate electrode 134U and the gate dielectric 130 flush with the second ILD 124. The removal process used to form the gate dielectric 130 can be the same removal process as that used to form the upper gate electrode 134U. In some embodiments, a planarization process (such as chemical mechanical polishing (CMP), etch-back process, a combination thereof, or the like) can be used. After the planarization process, the top surfaces of the upper gate electrode 134U, the gate dielectric 130, the second ILD 124, and the gate sidewall spacers 90 are substantially coplanar within the process variation range. Each pair of the gate dielectric 130 and the gate electrode 134 (including the upper gate electrode 134U and / or the lower gate electrode 134L) can be collectively referred to as a "gate stack" 136 (including the upper gate stack 136U and the lower gate stack 136L). Each gate stack 136 extends along three sides (such as the top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 66 (see FIG. 1). The lower gate structure 90L can also extend along the sidewalls and / or the top surface of the semiconductor fin 62. As also shown in FIGS. 13A to 13C, a gate capping layer 138 is formed over the gate stack 136. The formation process can include recessing the gate stack 136, filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, etc., and performing a planarization process to remove the excess dielectric material above the second ILD 124. In FIG. 14, the silicide regions 142 and the source / drain contact plugs 144 are formed through the second ILD 124 to be electrically coupled to the upper epitaxial source / drain regions 108U and / or the lower epitaxial source / drain regions 108L. As an example of forming the source / drain contact 144, openings are formed through the second ILD 124 and the second CESL 122 using acceptable photolithography and etching techniques. A liner (not shown separately; such as a diffusion barrier layer, an adhesion layer, or the like) and a conductive material are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A removal process can be performed to remove the excess material from the top surfaces of the gate sidewall spacers 90 and the second ILD 124. The remaining liner and conductive material form the source / drain contact 144 in the openings. In some embodiments, a planarization process, such as chemical mechanical polishing, etch-back process, a combination thereof, or the like, is used. After the planarization process, the top surfaces of the gate sidewall spacers 90, the second ILD 124, and the source / drain contact 144 are substantially coplanar within the process variation range. A metal-semiconductor alloy region 142 is optionally formed at the interface between the source / drain region 108 and the source / drain contact 144. The metal-semiconductor alloy region 142 can be a silicide region formed by a metal silicide (such as titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed by a metal germanide (such as titanium germanide, cobalt germanide, nickel germanide, etc.), a silicogermanide region formed by both a metal silicide and a metal germanide, or the like. By depositing a metal in the opening of the source / drain contact 144 and then performing a thermal annealing process, the metal-semiconductor alloy region 142 can be formed prior to the material of the source / drain contact 144. The metal can be any metal (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or their alloys) that can react with the semiconductor material (such as silicon, silicon germanium, germanium, etc.) of the source / drain region 108 to form a low-resistance metal-semiconductor alloy. The metal can be deposited by a deposition process (such as ALD, CVD, PVD, etc.). After the thermal annealing process, a cleaning process (such as wet cleaning) can be performed to remove any residual metal from the opening of the source / drain contact 144 (such as from the surface of the metal-semiconductor alloy region 142). Then, one or more materials of the source / drain contact 144 can be formed on the metal-semiconductor alloy region 142. Then, an etch stop layer (ESL) 152 and a third ILD 154 are formed. In some embodiments, the ESL 152 can include a dielectric material having a high etch selectivity with respect to the etching of the third ILD 154, such as aluminum oxide, aluminum nitride, silicon oxycarbide, etc. The third ILD 154 can be formed using flowable CVD, ALD, or the like, and the material can include PSG, BSG, BPSG, USG, or the like, which can be deposited by any suitable method (such as CVD, PECVD, etc.). Subsequently, gate contact plugs 156 and source / drain vias 158 are formed to contact the upper gate stack 136U and the source / drain contact plugs 144, respectively. As an example of forming the gate contacts 156 and the source / drain vias 158, openings for the gate contacts 156 and the source / drain vias 158 are formed through the third ILD 154, the ESL 152, and the gate capping layer 138. Acceptable photolithography and etching techniques can be used to form the openings. A liner (not shown separately; such as a diffusion barrier layer, an adhesion layer, or the like) and a conductive material are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A planarization process (such as chemical mechanical polishing) can be performed to remove the excess material from the top surface of the third ILD 154. The remaining liner and conductive material form the gate contact plugs 156 and the source / drain vias 158 in the openings. The gate contact plugs 156 and the source / drain vias 158 can be formed in different processes or can be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact plugs 156 and the source / drain vias 158 can be formed in a different cross-section, which can avoid short-circuiting of the contacts. The active devices shown are collectively referred to as the device layer 170. In some embodiments, contacts to the lower gate stack 136L and the lower source / drain regions 108L can be formed through the backside of the device layer 170 (e.g., the side opposite the source / drain contact plugs 144). According to various embodiments, a CFET includes an n-type nanostructure FET and a p-type nanostructure FET vertically stacked together. The NFET channel region of the n-type nanostructure FET and the PFET channel region of the p-type nanostructure FET can be epitaxially grown on two different substrates, each with a different crystal orientation. For example, the NFET channel region can be formed by a first semiconductor layer epitaxially grown on a silicon substrate with a (100) plane orientation, and the PFET channel region can be formed by a second semiconductor layer epitaxially grown on a silicon substrate with a (110) plane orientation. Subsequently, the two substrates are bonded together and a CFET is formed by the bonding structure. In this way, a p-type nanostructure FET can be formed on (110)-plane-oriented silicon to increase the mobility without degrading the performance of the n-type nanostructure FET. Thus, various embodiments allow the CFET to have improved performance of the p-type nanostructure FET without affecting the performance of the n-type nanostructure FET. In some embodiments, a method includes: epitaxially growing a first multilayer stack above a first substrate; epitaxially growing a second multilayer stack above a second substrate, wherein the first substrate and the second substrate have different crystal orientations; bonding the first multilayer stack to the second multilayer stack; patterning the first multilayer stack and the second multilayer stack to form fins, the fins including a plurality of lower nanostructures alternately stacked with a first dummy nanostructure and a plurality of upper nanostructures above the lower nanostructures, the upper nanostructures being alternately stacked with a second dummy nanostructure; replacing the first dummy nanostructure with a first gate stack surrounding each of the lower nanostructures; and replacing the second dummy nanostructure with a second gate stack surrounding each of the upper nanostructures. In some embodiments, bonding the first multilayer stack to the second multilayer stack includes: depositing a first bonding layer above the first multilayer stack; depositing a second bonding layer above the second multilayer stack; and directly bonding the first bonding layer to the second bonding layer by dielectric-to-dielectric bonding. In some embodiments, forming the fins further includes patterning the first bonding layer and the second bonding layer. In some embodiments, the method further includes: patterning source / drain recesses in the fins; forming a first source / drain region in the source / drain recesses, the lower nanostructures extending between the first source / drain regions; depositing an insulating layer in the source / drain recesses over the first source / drain regions; and forming a second source / drain region in the source / drain recesses above the insulating layer, the upper nanostructures extending between the second source / drain regions. In some embodiments, the first substrate is a substrate with a (110) crystal orientation, wherein the second substrate is a substrate with a (100) crystal orientation. In some embodiments, replacing the first dummy nanostructure with the first gate stack defines a channel region of a p-type transistor from the lower nanostructures. In some embodiments, replacing the second dummy nanostructure with the second gate stack defines a channel region of an n-type transistor from the upper nanostructures. In some embodiments, the first substrate is a substrate with a (100) crystal orientation, wherein the second substrate is a substrate with a (110) crystal orientation. In some embodiments, the method further includes depositing an isolation layer above the first gate stack, wherein the second gate stack is deposited above the isolation layer, and wherein the isolation layer extends between the lower nanostructures and the upper nanostructures. In some embodiments, a method includes: epitaxially growing a first semiconductor layer and a second semiconductor layer over a first semiconductor substrate; epitaxially growing a third semiconductor layer and a fourth semiconductor layer over a second semiconductor substrate, the first semiconductor substrate having a crystal orientation different from that of the second semiconductor substrate; depositing a first bonding layer over the second semiconductor layer; depositing a second bonding layer over the fourth semiconductor layer; directly bonding the first bonding layer to the second bonding layer to form a bonding layer; performing a dummy patterning on the second semiconductor substrate, the third semiconductor layer, the fourth semiconductor layer, the bonding layer, the second semiconductor layer, and the first semiconductor layer to define fins extending upward from the first semiconductor substrate; patterning source / drain recesses in the fins; forming a first source / drain in the source / drain recesses; depositing a first isolation layer over the first source / drain; and forming a second source / drain in the source / drain recesses over the first isolation layer. In some embodiments, defining the fins includes: defining a lower nanostructure by the first semiconductor layer, wherein forming the first source / drain includes forming the first source / drain adjacent to the lower nanostructure; defining an upper nanostructure by the third semiconductor layer, wherein forming the second source / drain includes forming the second first source / drain adjacent to the upper nanostructure; defining a first dummy nanostructure by the second semiconductor layer; defining a second dummy nanostructure by the fourth semiconductor layer; and defining an isolation material by the bonding layer. In some embodiments, the method further includes replacing the first dummy nanostructure with a lower gate stack disposed around the lower nanostructure; and replacing the second dummy nanostructure with an upper gate stack disposed around the upper nanostructure. In some embodiments, the method further includes replacing the isolation material with a second isolation layer disposed between the lower nanostructure and the upper nanostructure, wherein the second isolation layer is deposited over the lower gate stack, and wherein the upper gate stack is deposited over the second isolation layer. In some embodiments, directly bonding the first bonding layer to the second bonding layer includes a dielectric-to-dielectric bonding process, the bonding process including: capping a first surface of the first bonding layer or a second surface of the second bonding layer with a hydroxyl group; bringing the first surface of the first bonding layer into contact with the second surface of the second bonding layer; and annealing the first bonding layer and the second bonding layer after bringing the first surface of the first bonding layer into contact with the second surface of the second bonding layer to form a covalent bond at an interface between the first bonding layer and the second bonding layer. In some embodiments, the method further includes thinning the second semiconductor substrate before patterning the second semiconductor substrate. In some embodiments, the first semiconductor substrate is a (110)-oriented crystalline substrate, and the second semiconductor substrate is a (100)-oriented crystalline substrate.In some embodiments, epitaxially growing a first semiconductor layer and a second semiconductor layer over a first semiconductor substrate includes epitaxially growing the first semiconductor layer and the second semiconductor layer according to the crystal orientation of the first semiconductor substrate, and wherein epitaxially growing a third semiconductor layer and a fourth semiconductor layer over a second semiconductor substrate includes epitaxially growing the third semiconductor layer and the fourth semiconductor layer according to the crystal orientation of the second semiconductor substrate. In some embodiments, a device includes: an upper nanostructure over a lower nanostructure, the upper nanostructure having a crystal orientation different from that of the lower nanostructure; an isolation material between the upper nanostructure and the lower nanostructure; a lower gate structure around the lower nanostructure; an upper gate structure around the upper nanostructure; a lower source / drain region, the lower nanostructure extending between the lower source / drain regions; a first insulating layer over the lower source / drain region; and an upper source / drain region over the first insulating layer, the upper nanostructure extending between the upper source / drain regions. In some embodiments, the lower nanostructure, the lower source / drain region, and the lower gate structure provide a p-type transistor, wherein the upper nanostructure, the upper source / drain region, and the upper gate structure provide an n-type transistor, wherein the lower nanostructure has a (110) plane crystal orientation, and wherein the upper nanostructure has a (100) plane crystal orientation. In some embodiments, the lower source / drain region and the lower gate structure provide an n-type transistor, wherein the upper nanostructure, the upper source / drain region, and the upper gate structure provide a p-type transistor, wherein the lower nanostructure has a (100) plane crystal orientation, and wherein the upper nanostructure has a (110) crystal orientation. The features of several embodiments are outlined above so that those skilled in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 50A, 50B: Structure 52L: Multilayer Stack / Lower Multilayer Stack 52U: Multilayer Stack / Upper Multilayer Stack 54L:Dummy Semiconductor Layer / Lower Dummy Semiconductor Layer 54U: Dummy Semiconductor Layer / Upper Dummy Semiconductor Layer 56L: Semiconductor Layer / Lower Semiconductor Layer 56U: Semiconductor Layer / Upper Semiconductor Layer 58: Bonding Layer 58L: Bonding Layer / Lower Bonding Layer 58U: Bonding Layer / Upper Bonding Layer 59: Hydrogen Bridge 60L: Substrate / Lower Substrate 60U: Substrate / Upper Substrate 61: Interface 62: Semiconductor Fin 64: Nanostructure / Dummy Nanostructure 64B: Second Dummy Nanostructure 66: Nanostructure / Semiconductor Nanostructure 66L: Lower Semiconductor Nanostructure 66M: Middle Semiconductor Nanostructure 66U: Upper Semiconductor Nanostructure 70: Isolation Region 72: Dummy Dielectric Layer 74: Dummy Gate Layer 76: Capping Layer 82: Dummy Dielectric 84: Dummy Gate 86: Capping 90: Gate Spacer 90L: Lower Gate Structure 94: Source / Drain Recess 96A, 96B: Sidewall Recess 98: Inner Spacer 100: Isolation Material 108: Source / Drain Region 108L: Lower Source / Drain Region / Lower Epitaxial Source / Drain Region 108U: Upper Source / Drain Region / Upper Epitaxial Source / Drain Region 112: First Contact Etch Stop Layer (CESL) / CESL 114: ILD / First ILD 122: CESL / Second CESL 124: ILD / Second ILD 130, 132: Gate Dielectric 134: Gate Electrode 134L: Lower Gate Electrode 134U: Upper Gate Electrode 136: Gate Stack 136L: Lower Gate Stack 136U: Upper Gate Stack 138: Gate Capping 142: Silicide Region / Metal-Semiconductor Alloy Region 144: Source / Drain Contact Plug 152: Etch Stop Layer / ESL 154: Third ILD 156: Gate Contact Plug / Gate Contact 158: Source / Drain Via 170: Device Layer A-A’, B-B’, C-C’: Cross Section The present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to standard practice in the industry, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 shows an exemplary schematic diagram of a stacked transistor, such as a complementary field-effect transistor (CFET), according to some embodiments in a three-dimensional view. FIGS. 2A, 2B, 3A, 3B, 4A, 4B, 4C, 4D, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 12C, 13A, 13B, 13C, and 14 show different views of intermediate stages of manufacturing a CFET according to some embodiments. 60L: Substrate / Lower Substrate 62: Semiconductor Fin 66L: Lower Semiconductor Nanostructure 66M: Intermediate Semiconductor Nanostructure 66U: Upper Semiconductor Nanostructure 90: Gate Spacer 98: Inner Spacer 100: Isolation Material 108L: Lower Source / Drain Region / Lower Epitaxial Source / Drain Region 108U: Upper Source / Drain Region / Upper Epitaxial Source / Drain Region 114: ILD / First ILD 130: Gate Dielectric 134L: Lower Gate Electrode 134U: Upper Gate Electrode 136: Gate Stack 136L: Lower Gate Stack 136U: Upper Gate Stack 138: Gate Capping 142: Silicide Region / Metal-Semiconductor Alloy Region 144: Source / Drain Contact Plug 152: Etch Stop Layer / ESL 154: Third ILD 156: Gate Contact Plug / Gate Contact 158: Source / Drain Via

Claims

1. A method for forming a semiconductor device, comprising: The first multilayer stack is epitaxially grown on the first substrate; A second multilayer stack is epitaxially grown over a second substrate, wherein the first substrate and the second substrate have different crystal orientations; the first multilayer stack is bonded to the second multilayer stack; the first multilayer stack and the second multilayer stack are patterned to form fins, the fins comprising a plurality of lower nanostructures alternately stacked with a first dummy nanostructure and a plurality of upper nanostructures above the lower nanostructures, the upper nanostructures being alternately stacked with a second dummy nanostructure; the first dummy nanostructure is replaced with a first gate stack surrounding each of the lower nanostructures; and the second dummy nanostructure is replaced with a second gate stack surrounding each of the upper nanostructures.

2. The method of forming a semiconductor device as claimed in claim 1, wherein bonding the first multilayer stack to the second multilayer stack comprises: A first bonding layer is deposited over the first multilayer stack; A second bonding layer is deposited over the second multilayer stack; And the first bonding layer is directly bonded to the second bonding layer by dielectric-to-dielectric bonding.

3. The method for forming the semiconductor device as claimed in claim 1, further comprising: The source / drain recesses are patterned in the fin; A first source / drain region is formed in the source / drain recess, and the lower nanostructure extends between the first source / drain regions; an insulating layer is deposited in the source / drain recess above the first source / drain regions; A second source / drain region is formed in the source / drain recess above the insulating layer, and the upper nanostructure extends between the second source / drain regions.

4. The method for forming the semiconductor device as claimed in claim 1, further comprising: An isolation layer is deposited above the first gate stack, wherein a second gate stack is deposited above the isolation layer, and wherein the isolation layer extends between the lower nanostructure and the upper nanostructure.

5. A method for forming a semiconductor device, comprising: A first semiconductor layer and a second semiconductor layer are epitaxially grown over a first semiconductor substrate; A third semiconductor layer and a fourth semiconductor layer are epitaxially grown over a second semiconductor substrate, wherein the first semiconductor substrate has a different crystal orientation than the second semiconductor substrate; a first bonding layer is deposited over the second semiconductor layer; A second bonding layer is deposited over the fourth semiconductor layer; the first bonding layer is directly bonded to the second bonding layer to form a bonding layer; the second semiconductor substrate, the third semiconductor layer, the fourth semiconductor layer, the bonding layer, the second semiconductor layer, and the first semiconductor layer are patterned to define fins extending upward from the first semiconductor substrate; The source / drain recesses are patterned in the fin; a first source / drain is formed in the source / drain recesses; a first isolation layer is deposited above the first source / drain; and a second source / drain is formed in the source / drain recess above the first isolation layer.

6. A method of forming a semiconductor device as claimed in claim 5, wherein the fin is defined as comprising: A lower nanostructure is defined by the first semiconductor layer, wherein forming the first source / drain includes forming a first source / drain adjacent to the lower nanostructure; an upper nanostructure is defined by the third semiconductor layer, wherein forming the second source / drain includes forming a second source / drain adjacent to the upper nanostructure; a first dummy nanostructure is defined by the second semiconductor layer; a second dummy nanostructure is defined by the fourth semiconductor layer; and an isolation material is defined by the bonding layer.

7. A method of forming a semiconductor device as claimed in claim 5, wherein directly bonding the first bonding layer to the second bonding layer includes a dielectric-to-dielectric bonding process, the dielectric-to-dielectric bonding process comprising: The first surface of the first bonding layer or the second surface of the second bonding layer is capped with hydroxyl groups; The first surface of the first bonding layer is brought into contact with the second surface of the second bonding layer; And after bringing the first surface of the first bonding layer into contact with the second surface of the second bonding layer, the first bonding layer and the second bonding layer are annealed to form covalent bonds at the interface between the first bonding layer and the second bonding layer.

8. A method for forming a semiconductor device, comprising: A first epitaxial stack is bonded to a second epitaxial stack, wherein the first epitaxial stack is formed from a first semiconductor substrate having a first crystal orientation, and the second epitaxial stack is formed from a second semiconductor substrate having a second crystal orientation different from the first crystal orientation; a fin is formed by patterning the first epitaxial stack and the second epitaxial stack, the fin including a plurality of lower nanostructures and a plurality of upper nanostructures above the lower nanostructures; a source / drain recess is patterned in the fin; a lower source / drain region, an isolation layer, and an upper source / drain region are sequentially formed in the source / drain recess; and a lower gate structure and an upper gate structure are formed around each of the lower nanostructures.

9. A method of forming a semiconductor device as claimed in claim 8, wherein the lower nanostructure, the lower source / drain region, and the lower gate structure provide a p-type transistor, wherein the upper nanostructure, the upper source / drain region, and the upper gate structure provide an n-type transistor, wherein the lower nanostructure has a (110) crystal orientation, and wherein the upper nanostructure has a (100) crystal orientation.

10. A method of forming a semiconductor device as claimed in claim 8, wherein the lower nanostructure, the lower source / drain region, and the lower gate structure provide an n-type transistor, wherein the upper nanostructure, the upper source / drain region, and the upper gate structure provide a p-type transistor, wherein the lower nanostructure has a (100) crystal orientation, and wherein the upper nanostructure has a (110) crystal orientation.

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