Memory system

Abstract

A memory system includes a computing unit and a memory device. The memory device includes a plurality of first connection ports, a second connection port, a high-speed computing connection switch, and a processor. The high-speed computing connection switch is connected to the plurality of first connection ports. The processor is connected to the second connection port and the high-speed computing connection switch, and is configured to obtain the current configuration of the plurality of first connection ports from the computing unit through the second connection port to update the original configuration stored in the processor, wherein the current configuration indicates the electronic device connected to each of the plurality of first connection ports.

Description

Technical Field

[0001] The invention relates to a memory system. Prior Art

[0002] In existing servers, it is common to use various switches to configure the server architecture. However, since these architectures are usually large, the space and cost of the overall equipment are very high, and the transmission efficiency is reduced. In addition, these architectures are all fixed, which causes application limitations. In addition, since multiple signals need to be transmitted in the server, and some signals need to be transmitted over a long distance, it is easy to cause signal loss and may affect the stability of the signal. Take the dual in-line memory module (DIMM) in the server as an example. In order to maintain the reading speed and computing speed required by the processor, the distance between the dual in-line memory module and the central processing unit cannot be too far, so direct memory access (DMA) is developed. For the dual in-line memory modules in the current server, a central processing unit is roughly equipped with 12 dual in-line memory modules, but when the server is actually operating, the utilization rate of the dual in-line memory modules is probably less than 80%. Summary of the invention

[0003] In view of the above, the present invention provides a memory system that solves the above problems.

[0004] A memory system according to an embodiment of the present invention comprises: a computing device and a memory device. The memory device comprises a plurality of first connection ports, a second connection port, a computing high-speed connection switch and a processor. The computing high-speed connection switch is connected to the plurality of first connection ports. The processor is connected to the second connection port and the computing high-speed connection switch and is used to obtain the current configuration of the plurality of first connection ports from the computing device through the second connection port to update the original configuration stored in the processor, wherein the current configuration indicates the electronic devices connected to each of the plurality of first connection ports.

[0005] According to a memory system including a memory device and a computing device according to one or more embodiments of the present invention, the computing device and the processor can determine the latest configuration of the memory device, thereby avoiding operational problems of the computing device and the processor due to unupdated configuration.

[0006] The above description of the disclosed contents and the following description of the implementation methods are used to demonstrate and explain the spirit and principle of the present invention, and to provide a further explanation of the scope of the patent application of the present invention. Simple diagram description

[0007] FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention. FIG. 2 is a block diagram of a computing high-speed link switch and a plurality of connection ports according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a memory module according to an embodiment of the present invention. FIG. 4 is a block diagram of a memory device according to another embodiment of the present invention. FIG. 5 is a schematic diagram of a connection module according to an embodiment of the present invention. FIG. 6 is a block diagram of a memory system according to an embodiment of the present invention. FIG. 7 is a block diagram of a memory system according to another embodiment of the present invention. FIG. 8 is a block diagram of a memory system according to yet another embodiment of the present invention. Implementation

[0008] The following detailed features and advantages of the present invention are described in detail in the embodiments, and the contents are sufficient to enable anyone skilled in the relevant art to understand the technical content of the present invention and implement it accordingly. According to the contents disclosed in this specification, the scope of the patent application and the drawings, anyone skilled in the relevant art can easily understand the relevant purposes and advantages of the present invention. The following examples are to further illustrate the viewpoints of the present invention in detail, but are not intended to limit the scope of the present invention in any way.

[0009] Please refer to FIG1, which is a block diagram of a memory device according to an embodiment of the present invention. As shown in FIG1, the memory device 1 includes a housing 10, a computing high-speed connection switch 11, a plurality of connection ports 12 and a memory module 13.

[0010] The computing high-speed connection switch 11, the connection port 12 and the memory module 13 are all disposed in the housing 10. Further, the computing high-speed connection switch 11, the connection port 12 and the memory module 13 can be disposed on the same substrate, and the substrate is disposed in the housing 10. The computing high-speed connection switch 11 can be an open high-speed interconnect communication protocol (compute express link, CXL) switch. The connection port 12 can be a slot of a peripheral component interconnect express (PCIe), and can be a pluggable connection port.

[0011] The memory module 13 may be a dual in-line memory module (DIMM). The memory module 13 is connected to the computing high-speed connection switch 11 through one of the plurality of connection ports 12. In other words, the number of the connection ports 12 may be equal to or greater than the number of the memory modules 13. By arranging the computing high-speed connection switch 11 and the memory module 13 together in the housing 10, the transmission efficiency may be improved, and the space and cost occupied by the overall device may be reduced.

[0012] It should be noted that FIG. 1 exemplarily shows two connection ports 12 and one memory module 13 , but the memory device 1 may also have, for example, 16 connection ports 12 and 8 memory modules 13 , and the present invention does not limit the number of connection ports 12 and memory modules 13 .

[0013] Please refer to FIG. 1 and FIG. 2 together, wherein FIG. 2 is a block diagram of a computing high-speed connection switch and a plurality of connection ports according to an embodiment of the present invention. As shown in FIG. 2, the memory device 1 may further include a substrate 14, on which the computing high-speed connection switch 11 and the connection port 12 are disposed. In addition, the memory device 1 may further include another substrate 15 disposed on the substrate 14, and a central processing unit 16 disposed on the substrate 15. Please refer to FIG. 1 and FIG. 3 together, wherein FIG. 3 is a schematic diagram of a memory module according to an embodiment of the present invention. The memory module shown in FIG. 3 may be the memory module 13 of FIG. 1. As shown in FIG. 3, the memory module 13 includes a substrate 130, a first sub-connection port 131a, a plurality of second sub-connection ports 131b, a plurality of memories 132, and a chip 133. The first sub-connection port 131a and the second sub-connection port 131b are located on the substrate 130. The first sub-connection port 131a may be connected to the computing high-speed connection switch 11. The first sub-connection port 131a can be a connection port for quickly interconnecting peripheral components. The memory 132 can be a dual in-line memory module (DIMM for short).

[0014] The chip 133 may be a control chip on the dual-line memory module. The chip 133 is connected to the second sub-connection port 131b and is used to convert the signal format. Further, the chip 133 may convert the signal from the computing high-speed connection switch 11 from a format based on the fast peripheral component interconnection to a format accessible to the memory 132, or convert the signal from the memory 132 to a format based on the fast peripheral component interconnection.

[0015] Please refer to FIG4, which is a block diagram of a memory device according to another embodiment of the present invention. As shown in FIG4, the memory device 2 includes a housing 20, a computing high-speed connection switch 21, a plurality of connection ports 22, a memory module 23 and a connection module 24.

[0016] The computing high-speed connection switch 21, the connection port 22, the memory module 23, and the connection module 24 are all disposed in the housing 20. Further, the computing high-speed connection switch 21, the connection port 22, the memory module 23, and the connection module 24 can be disposed on the same substrate, and the substrate is disposed in the housing 20. The housing 20, the computing high-speed connection switch 21, the connection port 22, and the memory module 23 of the memory device 2 can be implemented in the same manner as the housing 10, the computing high-speed connection switch 11, the connection port 12, and the memory module 13 of the memory device 1 of FIG. 1, and will not be described in detail here.

[0017] The memory module 23 is connected to the computing high-speed connection switch 21 through one of the connection ports 22, and the connection module 24 is connected to the computing high-speed connection switch 21 through another of the connection ports 22. Specifically, as described above, the connection port 22 can be a pluggable connection port. Therefore, each connection port 22 in the memory device 2 can be used to plug in the memory module 23 or the connection module 24. In addition, as shown in FIG. 4, the connection module 24 can be used to connect the computing device A1, and the memory module 23 is connected to the computing device A1 through the computing high-speed connection switch 21 and the connection module 24. For example, the computing device A1 can be a server, and the connection module 24 can be implemented by a connection card (port card) provided with a server connection port.

[0018] The number of memory modules 23 and connection modules 24 in FIG. 4 is only an example, and the ratio between the memory modules 23 and the connection modules 24 is adjustable. A composable memory device can be realized through the architecture of FIG. 4 . Therefore, the memory device can be further connected to other devices by adjusting the number and / or position of the memory modules and connection modules inserted in the memory device, thereby expanding the memory architecture.

[0019] Please refer to FIG. 4 and FIG. 5 , where FIG. 5 is a schematic diagram of a connection module according to an embodiment of the present invention. The connection module shown in FIG. 5 may be the connection module 24 of FIG. 4 . As shown in FIG. 5 , the connection module 24 includes a substrate 240, a first connector 241, and a second connector 242. The first connector 241 and the second connector 242 are disposed on the substrate 240. The first connector 241 may include a CDFP connector. The second connector 242 may be a quick peripheral component interconnect connector. The second connector 242 is used for connecting the connection module 24 to the connection port 22.

[0020] The first connector 241 can be used to connect to the server. The first connector 241 can be used to receive a platform reset signal generated by the server, and further send the platform reset signal to the connection port 22 of the memory device 2 through the second connector 242. The server and the memory system 100 are electrically connected through the CDFP connector.

[0021] Please refer to Figure 6, which is a block diagram of a memory system according to an embodiment of the present invention. As shown in Figure 6, the memory system 100 includes a plurality of memory devices 3A, 3B and 3C.

[0022] The memory device 3A includes a housing 30a, a computing high-speed connection switch 31a, a connection port 32a, a memory module 33a, and a connection module 34a; the memory device 3B includes a housing 30b, a computing high-speed connection switch 31b, a connection port 32b, a memory module 33b, and a connection module 34b; and the memory device 3C includes a housing 30c, a computing high-speed connection switch 31c, a connection port 32c, a memory module 33c, and a connection module 34c. The implementation of each of the memory devices 3A, 3B, and 3C may be the same as the memory device of one or more embodiments described above with reference to FIGS. 1 to 5, so the details of the memory devices 3A, 3B, and 3C are not repeated here.

[0023] The memory module of each of the memory devices 3A, 3B and 3C is connected to the computing high-speed connection switch through one of the connection ports, the connection module of each of the memory devices 3A, 3B and 3C is connected to the computing high-speed connection switch through another of the connection ports; and the connection module of one of the memory devices 3A, 3B and 3C is connected to the connection module of another of the memory devices 3A, 3B and 3C.

[0024] Taking the memory device 3A as an example, the memory module 33a of the memory device 3A is connected to the computing high-speed connection switch 31a through one of the connection ports 32a, and the connection module 34a of the memory device 3A is connected to the computing high-speed connection switch 31a through another connection port 32a. Moreover, one connection module 34a of the memory device 3A is connected to the connection module 34b of the memory device 3B. In addition, another connection module 34a of the memory device 3A can be connected to the connection module 34c of the memory device 3C.

[0025] Each of the memory devices 3A, 3B and 3C may include one or more memory modules and at least one connection module. In other words, the memory module of each of the memory devices 3A, 3B and 3C may be replaced by a connection module, and the connection module of each of the memory devices 3A, 3B and 3C may also be replaced by a memory module. The connection method shown in FIG6 is only an example, and the number of memory devices and the number of connection modules and memory modules of each memory device shown in FIG6 are only examples.

[0026] In addition, as shown in FIG6 , the memory system 100 may further include a computing device 4, wherein the computing device 4 may be a server. The computing device 4 is a selectively arranged element. The computing device 4 is connected to a connection module of at least one of the memory devices 3A, 3B, and 3C. For example, as shown in FIG6 , the computing device 4 may be connected to a connection module 34b of the memory device 3B. According to FIG6 , each of the memory devices 3A, 3B, and 3C may include two connection modules, wherein one connection module is used to connect to another memory device, and the other connection module is used to connect to other devices (e.g., the computing device A1).

[0027] According to one or more embodiments of the present invention, the memory system can expand the memory pool according to demand, and is more flexible in use.

[0028] Please refer to FIG7, which is a block diagram of a memory system according to another embodiment of the present invention. As shown in FIG7, the memory system 200 includes a memory device 5 and a computing device 6.

[0029] The memory device 5 includes a computing high-speed connection switch 51, a plurality of memory modules 52, and a first signal corrector 53. The computing high-speed connection switch 51 and the memory module 52 may be implemented in the same manner as the computing high-speed connection switch and the memory module of one or more embodiments described above with reference to FIGS. 1 to 6, and the memory module 52 may be connected to the high-speed connection switch 51 via a connection port of one or more embodiments described above with reference to FIGS. 1 to 6. Further, the memory device 5 may be connected to the computing device 6 via a connection port and a connection module of one or more embodiments described above with reference to FIGS. 4 and 5. Further, the first signal corrector 53 may be disposed between the computing high-speed connection switch and the connection port, or may be disposed in the connection module.

[0030] The computing device 6 includes a second signal corrector 61 and a computing element 62. The second signal corrector 61 is connected to the first signal corrector 53 and the computing element 62. The computing device 6 can be a server. The computing element 62 is, for example, a central processing unit, a graphics processor, etc.

[0031] The first signal corrector 53 and the second signal corrector 61 can be used to correct at least one of the error and loss of the initial signal generated by the memory module 52. The computing element 62 of the computing device 6 can receive the signal generated by one of the first signal corrector 53 and the second signal corrector 61.

[0032] In one embodiment, the first signal corrector 53 and the second signal corrector 61 can each be a redriver. The first signal corrector 53 is used to correct the loss of the initial signal output by the high-speed link switch 51 to output a first correction signal to the second signal corrector 61, and the second signal corrector 61 is used to correct the loss of the first correction signal to output a second correction signal to the operation element 62. In other words, the first signal corrector 53 can amplify the initial signal to generate a first correction signal, and the second signal corrector 61 can amplify the first correction signal to generate a second correction signal.

[0033] In another embodiment, the first signal corrector 53 is a retimer, and the second signal corrector 61 is a redriver. The first signal corrector 53 is used to correct the error of the initial signal to output a first correction signal to the second signal corrector 61, and the second signal corrector 61 is used to correct the loss of the first correction signal to output a second correction signal to the operation element 62. In other words, the first signal corrector 53 can repair the jittered initial signal to generate a first correction signal, and the second signal corrector 61 can amplify the first correction signal to generate a second correction signal.

[0034] In another embodiment, the first signal corrector 53 is a re-driver, and the second signal corrector 61 is a re-timer. The first signal corrector 53 is used to correct the loss of the initial signal to output the first correction signal to the second signal corrector 61, and the second signal corrector 61 is used to correct the error of the first correction signal to output the second correction signal to the operation element 62. In other words, the first signal corrector 53 can amplify the initial signal to generate the first correction signal, and the second signal corrector 61 can repair the jittered first correction signal to generate the second correction signal.

[0035] Through the memory system of one or more of the above embodiments, by implementing the signal corrector with a re-driver, the signal can be transmitted over a longer distance. Furthermore, by implementing the signal corrector with a re-timer, a clean and stable signal can be generated.

[0036] Please refer to FIG8, which is a block diagram of a memory system according to another embodiment of the present invention. As shown in FIG8, the memory system 300 includes a memory device 7 and a computing device 8.

[0037] The memory device 7 includes a computing high-speed connection switch 71, a plurality of first connection ports 72a and a second connection port 72b. The computing high-speed connection switch 71 may be an open high-speed interconnection communication protocol switch. The first connection port 72a and the second connection port 72b may be slots for quick peripheral component interconnection, and may be pluggable connection ports. The processor 74 may be a central processing unit, such as the central processing unit 16 shown in FIG. 2. The computing device 8 may be a server.

[0038] The first connection ports 72a are each connected to an electronic device 73. For example, the first connection port 72a may be a connection port of one or more embodiments described above with reference to FIG. 1 to FIG. 6, and the electronic device 73 may be a memory module or a connection module of one or more embodiments described above with reference to FIG. 1 to FIG. 7.

[0039] The processor 74 is connected to the second connection port 72b and the computing high-speed connection switch 71, and the second connection port 72b is further connected to the computing device 8, wherein the second connection port 72b can be connected to the computing device 8 in a wired or wireless manner. The processor 74 is used to obtain the current configuration of the first connection port 72a from the computing device 8 through the second connection port 72b to update the original configuration stored in the processor 74. The current configuration indicates the electronic device 73 connected to each of the first connection ports 72a. The current configuration can be implemented by a quick peripheral component interconnection enumeration.

[0040] Furthermore, the memory device 7 may further include a housing 70 , and the high-speed connection switch 71 , the first connection port 72 a , the second connection port 72 b , the electronic device 73 and the processor 74 are disposed in the housing 70 .

[0041] The computing device 8 can transmit a reset signal to the processor 74 through the second connection port 72b, and the processor 74 is further used to control the computing high-speed connection switch 71 to respectively connect the first connection ports 72a and the computing device 8 according to the reset signal to generate the current configuration of the first connection ports 72a. The computing device 8 can scan the first connection ports 72a respectively through the computing high-speed connection switch 71 to generate the current configuration. The reset signal can be a platform environment reset signal. Specifically, as described above, the electronic device 73 can be a memory module and a connection module, and the memory module and the connection module can be provided with respective control chips, and the computing device 8 can obtain the current configuration of the first connection ports 72a by reading the control chip.

[0042] Specifically, after the computing device 8 transmits the reset signal to the processor 74, the processor 74 may first connect one of the first connection ports 72a to the computing device 8, and the computing device 8 reads the configuration data of the first connection port 72a. Then, the processor 74 may connect another first connection port 72a to the computing device 8, so that the computing device 8 reads the configuration data of the other first connection port 72a. Accordingly, the computing device 8 may use the read configuration data as the current configuration. The configuration data may indicate one or more of the serial number of the first connection port 72a, the name of the first connection port 72a, the brand of the first connection port 72a, the serial number of the electronic device 73 connected to the first connection port 72a, the name of the electronic device 73, and the brand of the electronic device 73.

[0043] In addition, the computing device 8 can also set the current configuration according to the user's command. For example, the user's command can indicate one or more of the serial number, name and brand of each first connection port 72a, and the user's command can further indicate one or more of the serial number, name and brand of the electronic device 73 connected to each first connection port 72a. The computing device 8 can use the configuration data indicated by the user's command as the current configuration.

[0044] After obtaining the current configuration, the computing device 8 may output the current configuration to the processor 74 to update the original configuration stored in the processor 74. The computing device 8 may include a basic input / output system (BIOS), which may be used to generate the aforementioned reset signal.

[0045] According to the memory system of one or more of the above embodiments, the computing device and the processor can determine the latest configuration of the memory device, thereby avoiding operational problems of the computing device and the processor due to unupdated configuration.

[0046] In this embodiment, the server of the present invention can be used for artificial intelligence (AI) computing, edge computing, and can also be used as a 5G server, a cloud server, or an Internet of Vehicles server.

[0047] In summary, according to one or more embodiments of the present invention, the memory device can improve the transmission efficiency and reduce the space and cost occupied by the overall device by setting the computing high-speed connection switch, multiple connection ports and multiple memory modules in the housing. According to one or more embodiments of the present invention, the memory device can be further connected to other devices by adjusting the number and / or position of the memory modules and connection modules inserted in the memory device, thereby expanding the memory architecture. According to one or more embodiments of the present invention, the memory system including multiple memory devices can expand the memory pool according to demand, which is more flexible in use. According to one or more embodiments of the present invention, the memory system including the signal corrector can enable the computing device to obtain a better quality signal. In addition, by implementing the signal corrector with a re-driver, the signal can be transmitted over a longer distance; and by implementing the signal corrector with a re-timer, a clean and stable signal can be generated. According to a memory system including a memory device and a computing device according to one or more embodiments of the present invention, the computing device and the processor can determine the latest configuration of the memory device, thereby avoiding operational problems of the computing device and the processor due to unupdated configuration.

[0048] Although the present invention is disclosed in the above embodiments, it is not intended to limit the present invention. Any changes and modifications made without departing from the spirit and scope of the present invention are within the scope of patent protection of the present invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

[0049] 1,2,3A,3B,3C,5,7: Memory devices 10,20,30a,30b,30c,70: Shell 11,21,31a,31b,31c,51,71: Calculate high-speed link switches 12,22,32a,32b,32c:Ports 13,23,33a,33b,33c,52: ​​Memory module 24,34a,34b,34c: Connection module 14,15,130,240:Substrate 16:CPU 131a: First sub-port 131b: Second sub-port 132: Memory 133: Chip 241: First connector 242: Second connector 53: First signal corrector 6,8: Computing device 61: Second signal corrector 62: Operational element 100,200,300:Memory system 4,8,A1: Computing device 72a: First connection port 72b: Second port 73: Electronic devices 74: Processor

Claims

1. A memory system comprising: a computing device; and a memory device including: a plurality of first connection ports; a second connection port; a computing high-speed connection switch connected to the first connection ports; and a processor connected to the second connection port and the computing high-speed connection switch, and configured to obtain a current configuration of the first connection ports from the computing device through the second connection port to update an original configuration stored in the processor, wherein the current configuration indicates an electronic device connected to each of the first connection ports.

2. The memory system as claimed in claim 1, wherein the computing device is configured to transmit a reset signal to the processor via the second connection port, and the processor is further configured to control the computing high-speed connection switch to connect the first connection ports and the computing device respectively according to the reset signal to generate the current configuration of the first connection ports.

3. The memory system as claimed in claim 2, wherein the computing device generates the current configuration by scanning the first ports respectively through the computing high-speed connection switch.

4. The memory system as claimed in claim 2, wherein the computing device includes a basic input / output system for generating the reset signal.

5. The memory system as claimed in claim 1, wherein the computing device is configured to set the current configuration according to a user instruction.

6. The memory system as claimed in claim 1, wherein the first connection ports are pluggable connection ports.

7. The memory system as described in claim 1, wherein the current configuration is implemented by a quick peripheral component interconnection list.

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