Semiconductor structure and method for manufacturing the same

Abstract

A semiconductor structure and a method for manufacturing the same are provided. The method includes forming a first channel structure and a second channel structure, forming a first type source / drain structure attached to both sides of the first channel structure, and forming a second type source / drain structure attached to both sides of the second channel structure. The method further includes forming a first gate dielectric layer having a first portion covering the first channel structure and a second portion covering the second channel structure, and includes driving a first metal element into the first portion of the first gate dielectric layer. The method further includes forming a capping layer over both the first and second portions of the first gate dielectric layer, and includes performing an annealing process on the first gate dielectric layer below the capping layer.

Description

Semiconductor structure and manufacturing method The present invention relates to semiconductor structures, and more particularly to semiconductor structures having a treated gate dielectric layer. The electronics industry has experienced a growing demand for smaller and faster electronic devices that can support increasingly complex and sophisticated functionality. Therefore, there has been a persistent trend in the semiconductor industry towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by miniaturizing semiconductor ICs (e.g., minimum component size), thereby improving production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of semiconductor manufacturing processes. Therefore, continued progress in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies. Recently, multi-gate devices have been introduced to attempt to improve gate control by increasing gate channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). However, the integrated fabrication of multi-gate devices remains challenging. This invention provides a method for manufacturing a semiconductor structure, comprising: forming a first channel structure in a first region and forming a second channel structure in a second region; forming a first type of source / drain structure attached to both sides of the first channel structure and forming a second type of source / drain structure attached to both sides of the second channel structure; forming a first gate dielectric layer having a first portion covering the first channel structure and a second portion covering the second channel structure; driving a first metal element into the first portion of the first gate dielectric layer; after driving the first metal element into the first portion of the first gate dielectric layer, forming a capping layer over both the first and second portions of the first gate dielectric layer; performing an annealing process on the first gate dielectric layer below the capping layer; and forming a work function metal layer, the work function metal layer extending continuously from the first region to the second region and covering the first and second channel structures. This invention provides a method for manufacturing a semiconductor structure, comprising: forming a first type of source / drain structure and a second type of source / drain structure above a substrate; forming a plurality of first channel structures vertically suspended above the substrate and sandwiched between the first type of source / drain structures; forming a plurality of second channel structures vertically suspended above the substrate and sandwiched between the second type of source / drain structures; forming a first gate dielectric layer having a first portion surrounding the first channel structure and a second portion surrounding the second channel structure; forming a first dipole layer, the first dipole layer being in solid contact with the first portion of the first gate dielectric layer and separated from the second portion of the first gate dielectric layer; forming a second gate dielectric layer above the first gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are formed of the same material; forming a capping layer surrounding the first channel structure and the second channel structure above the second gate dielectric layer; and annealing the first gate dielectric layer and the second gate dielectric layer after forming the capping layer. This invention provides a semiconductor structure comprising a first type of source / drain structure formed in a first region above a substrate, and a second type of source / drain structure formed in a second region above the substrate; a plurality of first channel structures separated from each other along a first direction and interspersed between the first type of source / drain structures along a second direction different from the first direction; a plurality of second channel structures separated from each other along the first direction and interspersed between the second type of source / drain structures along the second direction; a gate dielectric layer having a first portion surrounding the first channel structure in the first region and a second portion surrounding the second channel structure in the second region, wherein the first portion of the gate dielectric layer is doped with a first metal element, and the concentration of the first metal element in the lower part of the first portion of the gate dielectric layer is greater than the concentration of the first metal element in the upper part of the first portion of the gate dielectric layer; and a work function metal layer formed above both the first portion and the second portion of the gate dielectric layer. The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of the invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed. Some variations of the embodiments are described. In the various schematic and illustrative embodiments, similar reference numerals are used to indicate similar elements. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be substituted or eliminated for other embodiments of the method. The nanostructured transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nano-ribbon field-effect transistors (FETs), and gate-all-around (GAA) transistors) can be patterned using any suitable method. For example, structures can be patterned using one or more optical lithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine lithography with self-alignment processes to create patterns with, for example, smaller pitches than those obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as masks to pattern the nanostructure. This disclosure provides embodiments of semiconductor structures and methods for forming the same. The semiconductor structure may include a first type (e.g., n-type) transistor formed in a first region and a second type (e.g., p-type) transistor formed in a second region adjacent to the first region. Both the first and second type transistors may include a channel structure, such as a nanostructure, formed over a substrate, and a gate structure formed over the channel structure. Furthermore, forming the gate structure may include forming a dielectric material in both the first and second regions, and treating the dielectric material with an additional metal element in the first region but not in the second region. After treating the dielectric material, a single work function metal layer (e.g., a p-type work function metal layer) may be formed over the dielectric material in both the first and second regions. The dielectric material can be used as the gate dielectric layer in both type I and type II transistors, and the threshold voltages of the type I and type II transistors can be different. That is, although the same work function metal layer is formed in both type I and type II transistors, they can still have different threshold voltages due to the treatment of additional metal elements in the dielectric material of the first region. Therefore, by treating the gate dielectric layer with additional metal elements, the threshold voltage of the transistor can be adjusted without requiring an additional work function metal layer. Thus, there will be no material boundary of work function metal material between type I and type II transistors, and the performance and reliability of the formed transistors can be improved. Figures 1A, 1B, and 1C are perspective views illustrating intermediate stages of manufacturing the semiconductor structure 100 according to some embodiments. Figures 2A-1 to 2J-1, 2A-2 to 2J-2, and 2A-3 to 2J-3 are illustrations, according to some embodiments, showing intermediate stages of manufacturing the semiconductor structure 100 along section line Y in Figure 1C. SD -Y SD '(That is, in the Y direction), section line Y' MG -Y MG The figures are cross-sectional views along line X-X (i.e., in direction Y) and line X-X (i.e., in direction X). More specifically, Figures 2A-1, 2A-2, and 2A-3 illustrate cross-sectional views of an intermediate stage of the semiconductor structure 100 shown in Figure 1C, while Figures 2B-1 to 2J-1, 2B-2 to 2J-2, and 2B-3 to 2J-3 illustrate cross-sectional views after an intermediate stage of manufacturing the semiconductor structure 100, according to some embodiments. Semiconductor structure 100 may include multi-gate devices and may be included in a microprocessor, memory, or other IC device. For example, semiconductor structure 100 may be part of an IC chip, which includes various passive and / or active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. According to some embodiments, a substrate 102 comprising a first region 10 and a second region 20 is formed, and a semiconductor stack comprising a first semiconductor material layer 106 and a second semiconductor material layer 108 is formed on the first region 10 and the second region 20 of the substrate 102, as illustrated in Figure 1A. The substrate 102 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 102 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In some embodiments, a first semiconductor material layer 106 and a second semiconductor material layer 108 are alternately stacked on top of a substrate 102 to form a semiconductor stack. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are formed of different semiconductor materials. In some embodiments, the material of the first semiconductor material layer 106 is SiGe, and the material of the second semiconductor material layer 108 is silicon. It is worth noting that although four first semiconductor material layers 106 and three second semiconductor material layers 108 are shown in Figure 1A, the semiconductor stack may contain fewer or more alternately stacked first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor stack may contain two to five layers of first semiconductor material layers 106 and two to five layers of second semiconductor material layers 108. The first semiconductor material layer 106 and the second semiconductor material layer 108 can be formed using low-pressure chemical vapor deposition (LPCVD), epitaxial growth processes, other suitable methods, or combinations thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE). In some embodiments, after forming a first semiconductor material layer 106 and a second semiconductor material layer 108 as a semiconductor stack above the substrate 102, the semiconductor stack is patterned to form fin structures 104-1 in the first region 10 and fin structures 104-2 in the second region 20, as illustrated in Figure 1B. Fin structures 104-1 and 104-2 may extend longitudinally in the X direction. In some embodiments, the patterning process includes forming a mask structure 110 above the semiconductor material stack and etching the semiconductor material stack and the substrate 102 below it through the mask structure 110. In some embodiments, the mask structure 110 is a multi-layer structure including a pad oxide layer and a nitride layer formed above the pad oxide layer. The pad oxide layer can be formed of silicon oxide through thermal oxidation or chemical vapor deposition, while the nitride layer can be formed of silicon nitride through chemical vapor deposition, such as low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, fin structures 104-1 and 104-2 include a substrate fin structure 104B and a semiconductor stack formed on the substrate fin structure 104B, including a first semiconductor material layer 106 and a second semiconductor material layer 108. After forming fin structures 104-1 and 104-2, an isolation structure 116 is formed around fin structures 104-1 and 104-2, as illustrated in Figures 1C, 2A-1, 2A-2, and 2A-3. According to some embodiments, the isolation structure 116 is configured to electrically isolate the active regions of the semiconductor structure (e.g., fin structures 104-1 and 104-2) and is also referred to as a shallow trench isolation (STI) component. More specifically, an insulating layer may be formed around and covering the fin structures 104-1 and 104-2, and the insulating layer may be etched to form an isolation structure 116, wherein the fin structures 104-1 and 104-2 protrude from the top surface of the isolation structure 116. In some embodiments, the insulating layer is formed of silicon oxide, silicon nitride, silicon oxynitride (SiON), other suitable insulating materials, or combinations thereof. Furthermore, a liner layer (not shown) may be formed prior to the formation of the insulating layer, and the liner layer may also be etched together with the insulating layer to form the isolation structure 116. In some embodiments, the liner layer comprises multiple dielectric material layers. Subsequently, according to some embodiments, a dummy gate structure 130 is formed across fin structures 104-1 and 104-2, as illustrated in Figures 2B-1, 2B-2, and 2B-3. The dummy gate structure 130 can be used to define the channel region of the formed semiconductor structure 100. In some embodiments, the dummy gate structure 130 includes a dummy gate dielectric layer 132 and a dummy gate electrode layer 134. In some embodiments, the dummy gate dielectric layer 132 is formed of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), and HfO. 2. HfZrO, HfSiO, HfTiO, HfAlO, or a combination thereof. In some embodiments, the dummy gate dielectric layer 132 is formed using thermal oxidation, chemical vapor deposition, atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable methods, or a combination thereof. In some embodiments, the dummy gate electrode layer 134 is formed of a conductive material, such as polysilicon (poly-Si), polysilicon-germanium (poly-SiGe), or a combination thereof. In some embodiments, the dummy gate electrode layer 134 is formed using CVD, PVD, or a combination thereof. In some embodiments, a hard masking layer 136 is formed over the dummy gate electrode layer 134. In some embodiments, the hard masking layer 136 comprises multiple layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide and the nitride layer is silicon nitride. The formation of the dummy gate structure 130 may include conformally forming a dielectric material as a dummy gate dielectric layer 132. Then, a conductive material may be formed above the dielectric material as a dummy gate electrode layer 134, and a hard masking layer 136 may be formed above the conductive material. Next, the dielectric and conductive materials may be patterned through the hard masking layer 136 to form the dummy gate structure 130. According to some embodiments, after forming the dummy gate structure 130, a spacer layer 138 is formed to cover the top surface and sidewalls of the dummy gate structure 130 and the fin structures 104-1 and 104-2, as illustrated in Figures 2C-1, 2C-2, and 2C-3. In some embodiments, the spacer layer 138 is formed of one or more dielectric materials. The dielectric material may comprise silicon oxide (SiO2). 2) Silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), and / or combinations thereof. According to some embodiments, after the spacer layer 138 is formed, an etching process is performed to form a gate spacer 140 and a fin spacer 142 together with the spacer layer 138, and to form source / drain grooves 144 in the fin structures 104-1 and 104-2, as illustrated in Figures 2D-1, 2D-2 and 2D-3. The gate spacer 140 may be configured to separate the source / drain structure (which is subsequently formed) from the dummy gate structure 130, and the fin spacer 142 may be configured to restrict the growth of the source / drain structure therein. More specifically, according to some embodiments, the spacer layer 138 is etched to form gate spacers 140 on both sidewalls of the dummy gate structure 130, and fin spacers 142 covering the sidewalls of fin structures 104-1 and 104-2. Furthermore, according to some embodiments, multiple portions of fin structures 104-1 and 104-2 not covered by the dummy gate structure 130 and gate spacers 140 are etched during the etching process to form source / drain recesses 144. The etching process can be anisotropic, such as dry plasma etching, and the dummy gate structure 130 and gate spacers 140 can be used as etching masks during the etching process. In some embodiments, the isolation structure 116 is also lightly etched during the etching process. According to some embodiments, after forming the source / drain recess 144, the first semiconductor material layer 106 exposed by the source / drain recess 144 is laterally etched to form notches 146, as illustrated in Figures 2E-1, 2E-2, and 2E-3. In some embodiments, an etching process is performed to laterally etch the first semiconductor material layer 106 of the fin structures 104-1 and 104-2 from the source / drain recess 144. In some embodiments, during the etching process, the first semiconductor material layer 106 has a greater etching rate (or etching amount) than the second semiconductor material layer 108, thereby forming notches 146 between adjacent second semiconductor material layers 108. In some embodiments, the second semiconductor material layer 108 is also slightly etched during the etching process, such that the portion of the second semiconductor material layer 108 exposed by the notches 146 becomes thinner than the other portions. In some embodiments, the etching process is isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, other suitable techniques, and / or combinations thereof. Next, according to some embodiments, an inner spacer 148 is formed in a recess 146 between the second semiconductor material layers 108, as illustrated in Figures 2F-1, 2F-2, and 2F-3. The inner spacer 148 can be configured to separate the source / drain structure and the gate structure formed in subsequent manufacturing processes. As described above, according to some embodiments, since the second semiconductor material layer 108 is also partially etched when the recess 146 is formed, the thickness of the inner spacer 148 formed in the recess 146 is greater than the thickness of the first semiconductor material layer 106. Furthermore, according to some embodiments, the inner spacer 148 has curved sidewalls. In some embodiments, the inner spacer 148 is formed of a dielectric material, such as silicon oxide (SiO2). 2) Silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), or a combination thereof. According to some embodiments, after forming the inner spacer 148, source / drain structures 150-1 and 150-2 are formed in the source / drain grooves 144 of the fin structures 104-1 and 104-2, respectively, as illustrated in Figures 2G-1, 2G-2, and 2G-3. The source / drain structures described in this disclosure may refer to the source or drain individually or collectively, depending on the context. In some embodiments, source / drain structures 150-1 and 150-2 are formed using separate epitaxial growth processes, such as MBE, MOCVD, VPE, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, source / drain structures 150-1 and 150-2 are formed from any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or combinations thereof. In some embodiments, source / drain structures 150-1 and 150-2 are in-situ doped during the epitaxial growth process. In some embodiments, source / drain structures 150-1 and 150-2 are doped in one or more implantation processes after the epitaxial growth process. In some embodiments, source / drain structures 150-1 and 150-2 are formed of materials with different conductivity types. In some embodiments, source / drain structure 150-1 is an n-type source / drain structure, while source / drain structure 150-2 is a p-type source / drain structure. For example, source / drain structure 150-1 can be epitaxially grown Si, doped with carbon to form a silicon:carbon (Si:C) source / drain component, doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain component, or doped with both carbon and phosphorus to form a silicon-carbon-phosphorus (SiCP) source / drain component. For example, source / drain structure 150-2 can be epitaxially grown SiGe, doped with boron (B). According to some embodiments, after the source / drain structures 150-1 and 150-2 are formed, a contact etch stop layer (CESL) 160 is compliantly formed to cover the source / drain structures 150-1 and 150-2, and an interlayer dielectric (ILD) 162 is formed above the contact etch stop layer 160, as illustrated in Figures 2H-1, 2H-2 and 2H-3. In some embodiments, the contact etch stop layer 160 is formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The dielectric material for the contact etch stop layer 160 can be compliantly deposited over the semiconductor structure by performing CVD, ALD, other application methods, or combinations thereof. The interlayer dielectric layer 162 may comprise a multilayer film formed of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other suitable low-k (dielectric constant) dielectric materials. The interlayer dielectric layer 162 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. According to some embodiments, after depositing the contact etch stop layer 160 and the interlayer dielectric layer 162, a planarization process such as chemical mechanical polishing (CMP) or etch-back is performed until the dummy gate electrode layer 134 is exposed, as illustrated in Figures 2H-2 and 2H-3. Next, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form a gate trench 166, as illustrated in Figures 2I-1, 2I-2, and 2I-3. More specifically, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form channel structures (e.g., nanostructures) 108'-1 and 108'-2, respectively, with the second semiconductor material layers 108 of the fin structures 104-1 and 104-2. As illustrated in Figure 2I-3, according to some embodiments, the channel structures 108'-1 and 108'-2 are vertically suspended above the substrate and spaced apart from each other in the Z direction. Furthermore, according to some embodiments, channel structures 108'-1 and 108'-2 extend laterally in the X direction between and intersect with source / drain structures 105-1 and 150-2, respectively. Although not clearly shown in the figures, channel structures 108'-1 and 108'-2 and the base fin structure 104B may have rounded corners. The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 134 can be formed of polysilicon, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode layer 134. Subsequently, plasma dry etching, dry chemical etching, and / or wet etching can be used to remove the dummy gate dielectric layer 132. The first semiconductor material layer 106 can be removed by performing a selective wet etching process, such as an ammonium and hydrogen peroxide mixture (APM) etching process. For example, a wet etching process using ammonium hydroxide (NH4OH) solution... Etching agents including 4OH, TMAH, ethylenediamine pyrocatechol (EDP), and / or potassium hydroxide (KOH) solution. According to some embodiments, after forming the gate trench 166, a gate structure 168 is formed in the gate trench 166, as illustrated in Figures 2J-1, 2J-2, and 2J-3. Figures 3A to 3H illustrate, according to some embodiments, an intermediate stage in the formation of the gate structure 168 of the semiconductor structure 100 (i.e., the block BK illustrated in Figure 2J-2). 2I An enlarged cross-sectional schematic diagram of the area in the diagram. More specifically, according to some embodiments, after forming channel structures 108'-1 and 108'-2, an interface layer 170, a gate dielectric layer 172, and a dipole layer 174 are formed to wrap the channel structures 108'-1 and 108'-2, and to cover the exposed top of the base fin structure 104B of the fin structures 104-1 and 104-2, as illustrated in Figure 3A. Interface layer 170 can be used to improve the interface between channel structures 108'-1 and 108'-2 and the subsequently formed dielectric layer. Furthermore, interface layer 170 can help suppress the mobility degradation of charge carriers in channel structures 108'-1 and 108'-2, which serve as channel regions for transistors. In some embodiments, interface layer 170 is an oxide layer formed by performing a thermal process. In some embodiments, the thickness of interface layer 170 ranges from about 0.5 nm to about 1.5 nm. According to some embodiments, after the interface layer 170 is formed, a gate dielectric layer 172 is compliantly formed to cover the interface layer 170 and the bottom surface and sidewalls of the gate trench 166. In some embodiments, the gate dielectric layer 172 includes a first portion 172-1 wrapping around the channel structure 108'-1 and a second portion 172-2 wrapping around the channel structure 108'-2. In some embodiments, the gate dielectric layer 172 is formed of a dielectric material, such as HfO. 2. HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Zirconia, Alumina, Titanium oxide, Hafnium dioxide-alumina (HfO) 2-Al 2O 3) Alloys, La 2O 3-Al 2O 3. Or LaO, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 172 is formed using CVD, ALD, other suitable methods, or combinations thereof. In some embodiments, the thickness of the gate dielectric layer 172 ranges from about 1 nm to about 2 nm. According to some embodiments, after forming the gate dielectric layer 172, a dipole layer 174 is formed above and in physical contact with the top surface of the gate dielectric layer 172 in both the first region 10 and the second region 20. The dipole layer 174 is configured to adjust the gate dielectric layer 172 to increase or decrease the effect of the voltage applied to the gate electrode on the conduction or cutoff of the formed transistor. That is, the threshold voltage of the formed transistor can be adjusted. In some embodiments, the dipole layer 174 comprises a metallic element such as La, Y, Al, Sr, Er, Zn, Sc, Ti, Nb, or the like. In some embodiments, the thickness of the dipole layer 174 ranges from about 0.5 nm to about 2.5 nm. According to some embodiments, after forming an interface layer 170, a gate dielectric layer 172, and a dipole layer 174 to surround channel structures 108'-1 and 108'-2, a hard mask layer 176 is formed to cover channel structures 108'-1 and 108'-2 in both the first region 10 and the second region 20, as illustrated in Figure 3A. In some embodiments, the spaces between adjacent stacked channel structures 108'-1 and between adjacent stacked channel structures 108'-2 are completely filled by the hard mask layer 176. In some embodiments, the hard mask layer 176 is formed of an oxide or nitride, such as SiO2. x AlO x ZrO 2. SiN, TiN, or the like. In some embodiments, the thickness of the hard masking layer 176 ranges from about 1 nm to about 5 nm. Next, according to some embodiments, a photoresist layer 178 is formed to cover the structure in the first region 10, and the hard mask layer 176 and dipole layer 174 not covered by the photoresist layer 178 in the second region 20 are removed, as illustrated in Figure 3B. According to some embodiments, after removing the dipole layer 174 in the second region 20, the photoresist layer 178 in the first region 10 is also removed, and a processing step 180 is performed to form an adjusted first portion 172'-1 of the gate dielectric layer 172 in the first region 10, as illustrated in Figure 3C. More specifically, the metal elements of the dipole layer 174 are driven (e.g., diffused) into the first portion 172-1 of the gate dielectric layer 172 in the first region 10 to form the adjusted first portion 172'-1. The metal elements driven into the first portion 172-1 of the gate dielectric layer 172 cause a dipole effect, which increases or decreases the effect of the voltage applied to the gate electrode on the transistor formed in the first region 10, thus turning it on or off. In other words, it modulates the effective work function of the formed transistor, thereby increasing or decreasing the critical voltage of the transistor formed in the first region 10. In some embodiments, by treating the first portion 172-1 of the gate dielectric layer 172 with the metal elements of the dipole layer 174 in the first region 10, the critical voltage of the transistor formed in the first region 10 will be different from the critical voltage of the transistor formed in the second region 20. Meanwhile, according to some embodiments, since the dipole layer 174 in the second region 20 has been removed before the processing step 180, the second portion 172-2 of the gate dielectric layer 172 in the second region 20 has not been processed (e.g., adjusted), and therefore the critical voltage of the transistor in the second region 20 is different from the critical voltage of the transistor in the first region 10. In some embodiments, process 180 is an annealing process. In some embodiments, the annealing process is performed at a temperature ranging from about 400°C to about 1000°C. In some embodiments, the annealing process is performed for about 0.5 seconds to about 30 seconds. According to some embodiments, after processing 180 is performed, the dipole layer 174 in the first region 10 is removed, as illustrated in the 3D figure. The dipole layer 174 can be removed by performing an etching process, such as a dry etching process or a wet etching process. Next, according to some embodiments, an additional gate dielectric layer 182 is formed over the adjusted first portion 172'-1 of the gate dielectric layer 172 in the first region 10 and over the second portion 172-2 of the gate dielectric layer 172 in the second region 20, as illustrated in Figure 3E. As previously described, according to some embodiments, the first portion 172-1 of the gate dielectric layer 172 is processed to adjust the critical voltage of the formed transistor. However, if the gate dielectric layer 172 is too thick, adjusting the first portion 172-1 of the gate dielectric layer 172 may be challenging. On the other hand, if the gate dielectric layer in the gate structure is not thick enough, the risk of leakage current may increase. Therefore, a relatively thin gate dielectric layer 172 (i.e., tightly attached to the channel structure 108'-1) is formed and first processed to form an adjusted first portion 172'-1 of the gate dielectric layer 172, while an additional gate dielectric layer 182 is formed on top of the gate dielectric layer 172 so that the combination of the gate dielectric layers 172 and 182 can achieve the required thickness. In some embodiments, the sum of the thicknesses of the gate dielectric layer 172 and the gate dielectric layer 182 ranges from about 1 nm to about 5 nm. In some embodiments, the thickness of the gate dielectric layer 182 is less than the thickness of the gate dielectric layer 172. In some embodiments, the gate dielectric layer 182 is formed of the same dielectric material as the gate dielectric layer 172, but the gate dielectric layer 182 does not contain the metal elements of the dipole layer 174. In some embodiments, the gate dielectric layer 182 is formed of a dielectric material, such as HfO. 2. HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Zirconia, Alumina, Titanium oxide, Hafnium dioxide-alumina (HfO) 2-Al 2O 3) Alloys, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, CVD, ALD, other suitable methods, or combinations thereof are used to form the gate dielectric layer 182. According to some embodiments, after forming the gate dielectric layer 182, a capping layer 184 is formed over the gate dielectric layer 182, and a post-deposition annealing process 186 is performed, as illustrated in Figure 3F. Since the gate dielectric layers 182 and 172 are covered by the capping layer 184 during the post-deposition annealing process 186, the gate dielectric layers 182 and 172 can be densified during the post-deposition annealing process 186. In some embodiments, the gate dielectric layers 172 and 182 are formed of the same dielectric material, therefore, no interface is shown between the gate dielectric layers 172 and 182 after performing the post-deposition annealing process 186. That is, gate dielectric layer 172 and gate dielectric layer 182 can form a gate dielectric structure having a first portion surrounding channel structure 108'-1 and a second portion surrounding channel structure 108'-2. Furthermore, according to some embodiments, the lower portion of the first portion of the gate dielectric structure (i.e., the adjusted first portion 172'-1 of gate dielectric layer 172) contains the metal element of dipole layer 174, while the upper portion of the first portion and the entire second portion of the gate dielectric structure (i.e., the second portion 172-1 of gate dielectric layer 172 and gate dielectric layer 182) do not contain the metal element of dipole layer 174. In some embodiments, the concentration of the first metal element in the lower portion of the first portion of the gate dielectric layer is greater than the concentration of the first metal element in the upper portion of the first portion of the gate dielectric layer. In some embodiments, the capping layer 184 is formed of a metallic material, comprising metals such as Ti, Ta, or the like. In some embodiments, the metallic material further comprises N and / or Si. In some embodiments, the capping layer 184 is formed of TiN. In some embodiments, the thickness of the capping layer 184 ranges from about 1 nm to about 3 nm. In some embodiments, the post-deposition annealing process 186 is performed at a temperature ranging from about 800°C to about 1000°C. Furthermore, since the critical voltage of the transistor formed in the first region 10 can be achieved by adjusting the gate dielectric layer 172, the capping layer 184 does not need to be removed after the post-deposition annealing process 186. Therefore, the gate dielectric layer 182 beneath the capping layer 184 is not damaged by the removal of the capping layer 184. In addition, the capping layer 184 helps to trap oxygen in the interface layer 170, and therefore the thickness of the interface layer 170 can be made thinner. According to some embodiments, after performing the post-deposition annealing process 186, a work function metal layer 190 is formed over the capping layer 184 in both the first region 10 and the second region 20, as illustrated in Figure 3G. More specifically, according to some embodiments, both the channel structure 108'-1 in the first region 10 and the channel structure 108'-2 in the second region 20 are surrounded by the work function metal layer 190. In some embodiments, the work function metal layer 190 is a p-type work function metal layer. In some embodiments, the work function metal layer 190 is formed of titanium nitride, tantalum nitride, tungsten nitride, tantalum, or the like. As described above, since the critical voltage of the transistor formed in the first region 10 can be modified by adjusting the gate dielectric layer 172, the transistors formed in the first region 10 and the second region 20 can have different critical voltages without the need to form an additional work function metal layer (e.g., an additional n-type work function metal layer). According to some embodiments, after forming the functional metal layer 190, a gate fill layer 192 is formed to completely fill the gate trench 166, and a polishing process is performed until the interlayer dielectric layer 162 is exposed, as illustrated in Figures 3H, 2J-1, 2J-2, 2J-3, 2J-4 and 2J-5. In some embodiments, a gate filler layer 192 is formed over a work function metal layer 190. In some embodiments, the gate filler layer 192 is formed of a conductive material, such as tungsten, titanium, tantalum, cobalt, copper, or the like. In some embodiments, the gate filler layer 192 is formed using CVD, ALD, electroplating, other suitable methods, or a combination thereof. In some embodiments, the polishing process is a CMP process. In some embodiments, the gate filler layer 192 comprises tungsten and fluorine. In some embodiments, the fluorine in the gate filler layer 192 diffuses into the work function metal layer 190 and the gate dielectric layers 182 and 172. Due to the fluorine diffused therein, the risk of leakage current in the gate dielectric layers 182 and 172 can be reduced. Figure 2J-4 illustrates, according to some embodiments, the block BK shown in Figure 2J-2. 2J An enlarged cross-sectional view of the semiconductor structure 100 is shown in Figures 2J-5. Figures 2J-5 are top views illustrating the semiconductor structure 100 according to some embodiments. For clarity, Figures 2J-5 have been simplified to better understand the inventive concept disclosed herein. Additional components may be included in the semiconductor structure 100, and some components described below may be replaced, modified, or eliminated. As illustrated in Figures 2J-5, according to some embodiments, the semiconductor structure 100 includes a transistor T-1 in the first region 10 and a transistor T-2 in the second region 20. Furthermore, according to some embodiments, a gate structure 168 extends over the channel structure 108'-1 of the fin structure 104-1 in the first region 10 and the channel structure 108'-2 of the fin structure 104-2 in the second region 20, and the gate structure 168 is oriented longitudinally along the Y direction. In some embodiments, transistor T-1 is an n-type transistor and transistor T-2 is a p-type transistor. In some embodiments, transistor T-1 includes channel structures 108'-1 spaced apart from each other along direction Z, source / drain structures 150-1 (e.g., n-type source / drain structures) attached to both sides of channel structure 108'-1, and a first portion 168-1 of gate structure 168 surrounding channel structure 108'-1. Similarly, transistor T-2 includes channel structure 108'-2, source / drain structures 150-2 (e.g., p-type source / drain structures) attached to both sides of channel structure 108'-2, and a second portion 168-2 of gate structure 168 surrounding channel structure 108'-2. As previously described, according to some embodiments, although transistors T-1 and T-2 have different conductivity types and different threshold voltages, both the first portion 168-1 and the second portion 168-2 of the gate structure 168 have the same and single work function metal layer 190 (e.g., a p-type work function metal layer) and the same gate fill layer 192. In some embodiments, the distance in the Z direction between the gate fill layer 192 and the top surface of the topmost structure of the channel structure 108'-1 is substantially equal to the distance in the Z direction between the gate fill layer 192 and the top surface of the topmost structure of the channel structure 108'-2. In some embodiments, the work function metal layer 190 and the gate fill layer 192 extend continuously from transistor T-1 in the first region 10 to transistor T-2 in the second region 20. That is, according to some embodiments, there are no stacked work function metal layers of different types at the boundary between transistors T-1 and T-2, nor is there a boundary between two types of work function metal layers. Therefore, boundary effects caused by metal diffusion in different types of work function metal layers can be prevented. Furthermore, by forming the adjusted first portion 172'-1 of the gate dielectric layer 172, the critical voltages of transistors T-1 and T-2 can be different from each other. In some embodiments, the gate dielectric layer 172 is an oxide layer, so that metal elements therein do not easily diffuse. That is, although there is a boundary between the adjusted first portion 172'-1 of the gate dielectric layer 172 in the first region 10 and the second portion 172-2 of the gate dielectric layer 172 in the second region 20, as illustrated in Figures 2J-5, the boundary effect may not occur or may not be too severe. Furthermore, since the critical voltages of transistors T-1 and T-2 are adjusted by processing the first portion 172-1 of the gate dielectric layer 172, it is no longer necessary to form multiple work function metal layers. In other words, more space can be used to form the gate fill layer 192, thereby improving the performance of transistors T-1 and T-2. Figures 2J'-2 and 2J'-3 illustrate, according to some embodiments, the semiconductor structure 100' along section line Y. MG -Y MG Figure 3H' is a cross-sectional view of the semiconductor structure 100' (i.e., in the Y direction) and the section line X-X' (i.e., in the X direction). Figure 3H' is an enlarged cross-sectional view of the semiconductor structure 100' according to some embodiments. According to some embodiments, the semiconductor structure 100' may be similar to the previously described semiconductor structure 100, but the difference is that the capping layer 184 between channel structures 108'-1 and 108'-2 is merged. That is, according to some embodiments, the work function metal layer 190 does not extend between channel structures 108'-1 and 108'-2. In some embodiments, the thickness of the capping layer 184 in the semiconductor structure 100' is greater than about 3 nm. The process and materials for forming the semiconductor structure 100' may be similar to or the same as those for forming the semiconductor structure 100 described above, and will not be repeated here. Figures 4A and 4B are enlarged cross-sectional schematic diagrams illustrating intermediate stages of manufacturing the semiconductor structure 100a according to some embodiments. According to some embodiments, the semiconductor structure 100a may be similar to the previously described semiconductor structure 100, except that the capping layer 184 is removed. The processes and materials used to form the semiconductor structure 100a may be similar to or the same as those used to form the semiconductor structure 100, and will not be repeated here. For example, according to some embodiments, other elements of the semiconductor structure 100a not shown in Figure 4B may be similar to or the same as the elements shown in Figures 2J-1, 2J-2, 2J-3, 2J-4, and 2J-5 previously described. More specifically, the processes illustrated in Figures 2A-1 to 2I-1, 2A-2 to 2I-2, 2A-3 to 2I-3, and 3A to 3F can be performed. According to some embodiments, after performing the post-deposition annealing process 186 (not shown in Figure 4A, see Figure 3F), the capping layer 184 (not shown in Figure 4A, see Figure 3F), as illustrated in Figure 4A, is removed. After removing the capping layer 184, the processes illustrated in Figures 3G and 3H are performed to form a semiconductor structure 100a comprising transistors Ta-1 and Ta-2. Since the gate dielectric layer 172 is covered by the additional gate dielectric layer 182, the gate dielectric layer 172 is not damaged by the removal of the capping layer 184. Furthermore, the space for forming the power function metal layer 190 and the gate fill layer 192 can be increased. Figures 5A to 5G are enlarged cross-sectional schematic diagrams illustrating intermediate stages of manufacturing the semiconductor structure 100b according to some embodiments. The processes and materials used to form the semiconductor structure 100b may be similar to or the same as those used to form the semiconductor structure 100 described above, and will not be repeated here. According to some embodiments, other elements of the semiconductor structure 100b not shown in Figure 5G may also be similar to or the same as those shown in Figures 2J-1, 2J-2, 2J-3, 2J-4, and 2J-5 previously described. More specifically, according to some embodiments, channel structures 108'b-1, 108'b-2, 108'b-3, and 108'b-4 are formed in regions 10b, 20b, 30b, and 40b, respectively, as illustrated in Figure 5A. According to some embodiments, after forming channel structures 108'b-1, 108'b-2, 108'b-3, and 108'b-4, an interface layer 170, a gate dielectric layer 172b, a dipole layer 174b, and a hard mask layer 174b are formed to cover channel structures 108'b-1, 108'b-2, 108'b-3, and 108'b-4 in regions 10b, 20b, 30b, and 40b, as illustrated in Figure 5A. In addition, the gate dielectric layer 172b includes multiple portions 172b-1, 172b-2, 172b-3, and 172b-4 that respectively surround the channel structures 108'b-1, 108'b-2, 108'b-3, and 108'b-4. Next, according to some embodiments, a photoresist layer 178b is formed in regions 10b and 20b, while regions 30b and 40b are exposed. Subsequently, according to some embodiments, portions of the hard mask layer 176 and the dipole layer 174b located in regions 30b and 40b are removed, as illustrated in Figure 5B. According to some embodiments, after removing portions of the dipole layer 174b in regions 30b and 40b, portions of the photoresist layer 178b and the hard mask layer 176 in regions 10b and 20b are also removed. Subsequently, a processing step (e.g., the previously described processing step 180) is performed to form adjusted portions 172'b-1 and 172b'-2 in regions 10b and 20b, while during the processing step, portions 172b-3 and 172b-4 remain unadjusted because the remaining portions of the dipole layer 174b are spaced apart from portions 172b-3 and 172b-4. In some embodiments, a first metal element in the dipole layer 174b is driven into portions 172b-1 and 172b-2 of the gate dielectric layer 172b. According to some embodiments, after performing the processing step, portions of the dipole layer 174b in regions 10b and 20b are removed, as illustrated in Figure 5C. Next, according to some embodiments, another dipole layer 274b and another hard mask layer 276b are formed over regions 10b, 20b, 30b, and 40b, as illustrated in Figure 5D. The dipole layer 274b is configured to adjust the gate dielectric layer 272b. In some embodiments, the dipole layer 274b contains a second metal element, such as La, Y, Al, Sr, Er, Zn, Sc, Ti, Nb, or the like. In some embodiments, the thickness of the dipole layer 274b ranges from about 0.5 nm to about 2.5 nm. In some embodiments, the dipole layers 174b and 274b contain different metal elements. Subsequently, according to some embodiments, a photoresist layer 278b is formed over regions 10b and 30b, exposing regions 20b and 40b, and portions of the hard mask layer 276b and the dipole layer 274b located in regions 20b and 40b are removed, as illustrated in Figure 5E. According to some embodiments, after removing portions of the dipole layer 274b located in regions 20b and 40b, the photoresist layer 278b and portions of the hard mask layer 276b are removed, and a processing step (e.g., the aforementioned processing step 180) is performed to form adjusted portions 172''b-1 and 172'b-3 in regions 10b and 30b, as illustrated in Figure 5F. In some embodiments, a second metal element in the dipole layer 274b is driven into portions 172'b-1 and 172b-3 to form adjusted portions 172''b-1 and 172'b-3. In some embodiments, the second metal element in the dipole layer 274b is different from the first metal element in the dipole layer 174b. Next, according to some embodiments, the processes previously described in Figures 3E to 3H are performed to form a gate structure 168b of the semiconductor structure 100b, as illustrated in Figure 5G. In some embodiments, the gate structure 168b includes a portion 168b-1 surrounding channel structure 108'b-1, a portion 168b-2 surrounding channel structure 108'b-2, a portion 168b-3 surrounding channel structure 108'b-3, and a portion 168b-4 surrounding channel structure 108'b-4. Furthermore, according to some embodiments, all portions 168b-1, 168b-2, 168b-3, and 168b-4 include the same and a single work function metal layer 190. In some embodiments, the semiconductor structure 100b includes transistors Tb-1, Tb-2, Tb-3, and Tb-4 respectively located in regions 10b, 20b, 30b, and 40b. As described above, according to some embodiments, two processing steps are performed, thus processing a portion 172b-1 of the gate dielectric layer 172b in region 10b using both the first metal element in dipole layer 174b and the second metal element in dipole layer 274b. Furthermore, according to some embodiments, a portion 172b-2 of the gate dielectric layer 172b in region 20b is processed using the first metal element in dipole layer 174b. According to some embodiments, a portion 172b-3 of the gate dielectric layer 172b in region 30b is processed using the second metal element in dipole layer 274b, while a portion 172b-4 of the gate dielectric layer 172b in region 40b is not processed. In other words, the adjusted portion 172''b-1 contains both the first metal element and the second metal element, the adjusted portion 172'b-2 contains the first metal element but not the second metal element, the adjusted portion 172'b-3 contains the second metal element but not the first metal element, and the portion 172b-4 contains neither the first nor the second metal element. In some embodiments, the critical voltage of transistor Tb-1 is less than the critical voltage of transistor Tb-2. In some embodiments, the critical voltage of transistor Tb-3 is greater than the critical voltage of transistor Tb-4. The fabrication processes and materials used to form channel structures 108'b-1, 108'b-2, 108'b-3, and 108'b-4, gate dielectric layer 172b, dipole layers 174b and 274b, photoresist layers 178b and 278b, hard mask layer 276, and gate structure 168b can be similar to or the same as those used to form channel structures 108'-1 and 108'-2, gate dielectric layer 172, dipole layer 174, photoresist layer 178, hard mask layer 176, and gate structure 168, and will not be described in detail here. Furthermore, in some other embodiments, similar to the previously described semiconductor structure 100a, the capping layer 184 of semiconductor structure 100b can be removed. Figures 6A-1 to 6J-1, 6A-2 to 6J-2, and 6A-3 to 6J-3 are schematic cross-sectional views illustrating intermediate stages of manufacturing the semiconductor structure 100c according to some embodiments. Figure 6J-4 illustrates, according to some embodiments, the block BK shown in Figure 6J-2. 6J An enlarged cross-sectional view of the semiconductor structure 100c is shown in Figure 6J-5. Figure 6J-5 is a top view of the semiconductor structure 100c according to some embodiments. For clarity, Figure 6J-5 has been simplified to better understand the inventive concept disclosed herein. More specifically, Figures 6A-1 to 6J-1, 6A-2 to 6J-2, and 6A-3 to 6J-3, according to some embodiments, respectively illustrate intermediate stages of manufacturing the semiconductor structure 100c along section line Y in Figure 6J-5. SD6 -Y SD6 '(That is, in the Y direction), section line Y' MG6 -Y MG6 '(that is, in the Y direction), and section line X 6-X A cross-sectional view at 6' (i.e., in the direction X). According to some embodiments, semiconductor structure 100c may be similar to the previously described semiconductor structure 100, but the difference lies in the formation of a dielectric wall structure. Some processes and materials used to form semiconductor structure 100c may be similar to or the same as those used to form semiconductor structure 100, and will not be described again here. First, according to some embodiments, the processes described in Figures 1A and 1B are performed to form a semiconductor stack over the substrate 102, and the semiconductor stack is patterned using a mask structure 110 to form a fin structure 104c-1 in the first region 10c and a fin structure 104c-2 in the second region 10c, as illustrated in Figures 6A-1, 6A-2 and 6A-3. According to some embodiments, after forming fin structures 104c-1 and 104c-2, a dielectric layer 620 is formed to cover fin structures 104c-1 and 104c-2, as illustrated in Figures 6B-1, 6B-2, and 6B-3. As illustrated in Figures 6B-1 and 6B-2, according to some embodiments, the lateral space between fin structures 104c-1 and 104c-2 is completely filled by the dielectric layer 620. In some embodiments, the dielectric layer 620 comprises one or more dielectric materials, such as SiO2. 2. SiN, SiCN, SiOC, SiOCN, HfO 2. ZrO 2. HfAlO x HfSiO x Al 2O 3. Or similar methods. The dielectric material can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition (HDPCVD), metal-organic chemical vapor deposition, remote plasma chemical vapor deposition (RPCVD), plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition (ALCVD), atmospheric pressure chemical vapor deposition (APCVD), other suitable methods, or combinations thereof. In some embodiments, the dielectric layer 620 comprises a high-k shell layer and a low-k core layer formed above the high-k shell layer. Next, according to some embodiments, an etching process is performed to form a dielectric wall structure 626 interposed between fin structures 104c-1 and 104c-2, as illustrated in Figures 6C-1, 6C-2, and 6C-3. In some embodiments, multiple portions of the dielectric layer 620 outside the space between fin structures 104c-1 and 104c-2 are removed during the etching process. In some embodiments, the etching process is performed without using a masking structure. More specifically, because the space between fin structures 104c-1 and 104c-2 is completely filled by the dielectric layer 620, the removal of the dielectric layer 620 in this space may be much slower than the removal of the dielectric layer 620 in other spaces. In other words, removing the dielectric layer 620 in other spaces is easier and faster than removing the dielectric layer 620 in the space between fin structures 104c-1 and 104c-2, because the top and sidewall surfaces of the dielectric layer 620 are largely exposed in other areas. Therefore, the dielectric layer 620 formed in the wider spaces can be completely removed, while the dielectric layer 620 formed in the space between fin structures 104c-1 and 104c-2 is only partially removed during the etching process. In some embodiments, the masking structure 110 formed above the fin structures 104c-1 and 104c-2 is also partially etched during the etching process. According to some embodiments, after forming the dielectric wall structure 626, an isolation structure 116 is formed around the fin structures 104c-1 and 104c-2, as illustrated in Figures 6D-1, 6D-2, and 6D-3. Subsequently, according to some embodiments, a dummy gate structure 130 is formed across the fin structures 104c-1 and 104c-2 and the dielectric wall structure 626, as illustrated in Figures 6E-1, 6E-2, and 6E-3. According to some embodiments, after forming the dummy gate structure 130, a spacer layer 138 is formed to cover the top surface and sidewalls of the dummy gate structure 130 and the fin structures 104c-1 and 104c-2, as well as the top surface of the dielectric wall structure 626, as illustrated in Figures 6E-1, 6E-2, and 6E-3. According to some embodiments, after the spacer layer 138 is formed, an etching process is performed to form the gate spacer 140 and the fin spacer 142 together with the spacer layer 138, and to form source / drain recesses 144 in the fin structures 104c-1 and 104c-2, as illustrated in Figures 6F-1, 6F-2 and 6F-3. In some embodiments, during the etching process that forms the source / drain recesses 144, the dielectric wall structure 626 of the source / drain region is also slightly etched. According to some embodiments, after forming the source / drain recess 144, inner spacers 148 are formed between the second semiconductor material layers 108, and source / drain structures 150c-1 and 150c-2 are formed in the source / drain recess 144, as illustrated in Figures 6G-1, 6G-2, and 6G-3. The source / drain structures described in this disclosure may refer to the source or drain individually or collectively, depending on the context. In some embodiments, source / drain structures 150c-1 and 150c-2 have different shapes from source / drain structures 150-1 and 150-2. More specifically, according to some embodiments, source / drain structures 150c-1 and 150c-2 are sandwiched between a fin spacer 122 and a dielectric wall structure 626, wherein the dielectric wall structure 126 is higher than the fin spacer 142. Therefore, according to some embodiments, source / drain structures 150c-1 and 150c-2 have an asymmetrical shape in a cross-sectional view along the Y direction. According to some embodiments, source / drain structure 150c-1 has a first side and a second side opposite to the first side, and has a substantially vertical sidewall on the second side. According to some embodiments, the substantially vertical sidewall of source / drain structure 150c-1 is in direct contact with the first sidewall of dielectric wall structure 626. Meanwhile, according to some embodiments, the source / drain structure 150c-1 extends laterally from the sidewall of the first side to the sidewall of the fin structure 104c-1, and further to the sidewall of the fin spacer 142. Similarly, the source / drain structure 150c-2 has a first side and a second side opposite to the first side. In some embodiments, according to certain examples, the substantially vertical sidewall of the source / drain structure 150c-2 on the first side is in direct contact with the second sidewall of the dielectric wall structure 626. Meanwhile, according to certain embodiments, the sidewall of the source / drain structure 150c-2 on the second side extends laterally beyond the sidewall of the fin structure 104c-2, and further beyond the sidewall of the fin spacer 142. In some embodiments, the top surface of the dielectric wall structure 626 is higher than the topmost part of the source / drain structures 150c-1 and 150c-2. In some embodiments, the source / drain structures 150c-1 and 150c-2 are formed of different types of source / drain materials. In some embodiments, the source / drain structure 150c-1 is formed of an n-type epitaxial material, and the source / drain structure 150c-2 is formed of a p-type epitaxial material. According to some embodiments, after forming the source / drain structures 150c-1 and 150c-2, a contact etch stop layer (CESL) 160 is compliantly formed to cover the source / drain structures 150c-1 and 150c-2 and the interlayer dielectric layer 162 (ILD) formed above the contact etch stop layer 160, as illustrated in Figures 6H-1, 6H-2, and 6H-3. In some embodiments, the contact etch stop layer 160 is in direct contact with the sidewalls of the dielectric wall structure 626. According to some embodiments, after depositing the contact etch stop layer 160 and the interlayer dielectric layer 162, a planarization process such as CMP or etch-back is performed until the dummy gate electrode layer 134 is exposed. Next, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form gate trenches 166c-1 and 166c-2, as illustrated in Figures 6I-1, 6I-2, and 6I-3. More specifically, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form channel structures (e.g., nanostructures) 108'c-1 and 108'c-2 with the second semiconductor material layer 108 of the fin structures 104c-1 and 104c-2. Although not clearly illustrated in the figures, the channel structures 108'c-1 and 108'c-2 and the substrate fin structure 104B may have rounded corners. As illustrated in Figure 6I-2, according to some embodiments, the top and bottom surfaces of each channel structure 108'c-1 and 108'c-2 are exposed by gate trenches 166c-1 and 166c-2, but not all lateral sidewalls of the channel structures 108'c-1 and 108'c-2 are exposed by gate trenches 166c-1 and 166c-2. That is, one sidewall of each channel structure 108'c-1 and 108'c-2 is attached to the dielectric wall structure 626 and is not exposed by gate trenches 166c-1 and 166c-2, while the other three lateral sidewalls of each channel structure 108'c-1 and 108'c-2 are exposed by gate trenches 166c-1 and 166c-2. According to some embodiments, in a cross-sectional view along the Y direction, each channel structure 108'c-1 and 108'c-2 has only one sidewall exposed by the gate trenches 166c-1 and 166c-2. Furthermore, according to some embodiments, the first sidewall of the dielectric wall structure 626 is not attached to multiple portions of the channel structure 108'c-1, which are exposed by the gate trench 166c-1, and the second sidewall of the dielectric wall structure 626 is not attached to multiple portions of the channel structure 108'c-2, which are exposed by the gate trench 166c-2. Next, according to some embodiments, a gate structure 168c is formed in gate trenches 166c-1 and 166c-2, as illustrated in Figures 6J-1, 6J-2, 6J-3, 6J-4, and 6J-5. More specifically, the processes illustrated in Figures 3A to 3H can be performed to form the gate structure 168c. In some embodiments, an interface layer 170c is formed over the exposed portions of channel structures 108'c-1 and 108'c-2 and the substrate fin structure 104B. Subsequently, according to some embodiments, a gate dielectric layer 172c is formed over the interface layer 170c and over the dielectric wall structure 262. Furthermore, according to some embodiments, the gate dielectric layer 172c includes an adjusted portion 172'c-1 surrounding the channel structure 108'c-1 in the first region 10c and a portion 172c-2 surrounding the channel structure 108'c-2 in the second region 20c. In some embodiments, the adjusted portion 172'c-1 of the gate dielectric layer 172c partially covers and is in direct contact with the first sidewall and top surface of the dielectric wall structure 626. On the other hand, according to some embodiments, a portion 172c-2 of the gate dielectric layer 172c partially covers and is in direct contact with the second sidewall and top surface of the dielectric wall structure 626. As illustrated in Figures 6J-4, according to some embodiments, the boundary between the adjusted portion 172'c-1 and portion 172c-2 is located above the top surface of the dielectric wall structure 626. The modified portion 172'c-1 treated with metallic elements can be formed by performing the processes shown in Figures 3A to 3D previously described, which will not be repeated here. After forming the adjusted portion 172'c-1, the processes illustrated in Figures 3E to 3H can be performed to form the gate structure 168c. That is, according to some embodiments, a gate dielectric layer 182c, a capping layer 184c, a work function metal layer 190c, and a gate fill layer 192c are formed. Furthermore, according to some embodiments, each of the gate dielectric layer 182c, the capping layer 184c, the work function metal layer 190c, and the gate fill layer 192c extends continuously from the channel structure 108'c-1 to the channel structure 108'c-2 and passes through the top surface of the dielectric wall structure 626. In some embodiments, the semiconductor structure 100c includes transistor Tc-1 and transistor Tc-2. Transistor Tc-1 includes a portion 168c-1 of gate structure 168c formed around channel structure 108'c-1, and transistor Tc-2 includes a portion 168c-2 of gate structure 168c formed around channel structure 108'c-2. As illustrated in Figure 6J-2, according to some embodiments, the dielectric wall structure 626 is interposed between the channel structures 108'c-1 and 108'c-2. Furthermore, according to some embodiments, the dielectric wall structure 626 is substantially parallel to the fin structures 104c-1 and 104c-2 and oriented longitudinally along direction X, as illustrated in Figure 6J-5. The processes and materials used to form the fin structures 104c-1 and 104c-2, source / drain structures 150c-1 and 150c-2, gate trenches 166c-1 and 166c-2, channel structures 108'c-1 and 108'c-2, gate structure 168c, interface layer 170c, gate dielectric layer 172c, gate dielectric layer 182c, capping layer 184c, work function metal layer 190c, and gate fill layer 192c can be compared with those used in the fabrication of the fin structures 104c-1 and 104c-2, source / drain structures 150c-1 and 150c-2, gate trenches 166c-1 and 166c-2, channel structures 108'c-1 and 108'c-2, gate structure 168c, interface layer 170c, gate dielectric layer 172c, capping layer 184c, work function metal layer 190c, and gate fill layer 192c. The processes and materials used to form the fin structures 104-1 and 104-2, source / drain structures 150-1 and 150-2, gate trenches 166-1 and 166-2, channel structures 108'-1 and 108'-2, gate structure 168, interface layer 170, gate dielectric layer 172, gate dielectric layer 182, capping layer 184, work function metal layer 190, and gate fill layer 192 described previously are similar or the same, and will not be repeated here. Furthermore, in some other embodiments, similar to the previously described semiconductor structure 100a, the capping layer 184c of the semiconductor structure 100c can be removed. Additionally, according to some embodiments, the gate dielectric layer 172 can be processed according to the process illustrated in Figures 5A to 5G. For example, a portion 172c-1 of the gate dielectric layer 172 can be adjusted twice to be approximately or identical to a portion 172b''-1 of the semiconductor structure 100b. For example, a portion 172c-2 of the gate dielectric layer 172 can also be processed approximately or identically to portions 172''b-1 or 172'b-3 of the semiconductor structure 100b. Figures 6J'-2 and 6J'-3 are schematic cross-sectional views illustrating semiconductor structure 100c' according to some embodiments. According to some embodiments, semiconductor structure 100c' may be similar to the previously described semiconductor structure 100c, but the difference lies in that the capping layer 184 between channel structures 108'c-1 and 108'c-2 is merged. That is, according to some embodiments, the work function metal layer 190c does not extend between channel structures 108'c-1 and 108'c-2. In some embodiments, the thickness of the capping layer 184c in semiconductor structure 100c' is greater than about 3 nm. The processes and materials used to form semiconductor structure 100c' may be similar to or the same as those previously described for forming semiconductor structure 100c, and will not be repeated here. Figures 7A-1 to 7Q-1, 7A-2 to 7Q-2, and 7A-3 to 7Q-3 are schematic cross-sectional views illustrating intermediate stages of manufacturing a semiconductor structure 100d according to some embodiments. Figure 7Q-4 illustrates, according to some embodiments, the block BK shown in Figure 7Q-3. 7Q An enlarged cross-sectional view of the semiconductor structure 100d is shown in Figure 7Q-5. Figure 7Q-5 is a top view schematic diagram of the semiconductor structure 100d according to some embodiments. For clarity, Figure 7Q-5 has been simplified to better understand the inventive concept disclosed herein. More specifically, Figures 7A-1 to 7Q-1, 7A-2 to 7Q-2, and 7A-3 to 7Q-3, according to some embodiments, respectively illustrate intermediate stages of manufacturing the semiconductor structure 100d along section line Y in Figure 7Q-5. SD7 -Y SD7 '(That is, in the Y direction), section line Y' MG7 -Y MG7 '(that is, in the Y direction), and section line X 7-X 7' (i.e., in direction X) is a cross-sectional schematic diagram. Some of the processes and materials used to form the semiconductor structure 100d may be similar to or the same as those previously described for forming the semiconductor structure 100, and will not be repeated here. First, according to some embodiments, a first semiconductor stack and a second semiconductor stack are formed in a first region 10d and a second region 20d above a substrate 102, and a masking structure 110d is used to pattern the first semiconductor stack, the second semiconductor stack, and the substrate 102 to form a fin structure 104d, as illustrated in Figures 7A-1, 7A-2, and 7A-3. According to some embodiments, as illustrated in Figure 7A-1, the fin structure 104d includes a first portion 104d-1 containing the first semiconductor stack formed in the first region 10d, a second portion 104d-2 containing the second semiconductor stack formed in the second region 20d, and a base fin structure 104Bd. Furthermore, according to some embodiments, the first portion 104d-1 and the second portion 104d-2 of the fin structure 104d overlap vertically. In some embodiments, both the first semiconductor stack and the second semiconductor stack include alternately stacked first semiconductor material layers 106 and second semiconductor material layers 108. Furthermore, according to some embodiments, an intermediate layer 109 is formed over the first semiconductor stack and over the second semiconductor stack. In some embodiments, the intermediate layer 109 is formed of the same material as the first semiconductor material layer 106. In some embodiments, the intermediate layer 109 is formed of SiGe. According to some embodiments, after forming the fin structure 104d, the mask structure 110d is removed, and an isolation structure 116 is formed around the fin structure 104d, as illustrated in Figures 7B-1, 7B-2, and 7B-3. Subsequently, a dummy gate structure 130 is formed across the fin structure 104d, as illustrated in Figures 7C-1, 7C-2, and 7C-3. According to some embodiments, after forming the dummy gate structure 130, a spacer layer is formed, and an etching process is performed to form a gate spacer 140 and a source / drain groove 144d, as illustrated in Figures 7D-1, 7D-2, and 7D-3. According to some embodiments, after forming the source / drain recess 144d, the first semiconductor material layer 106 and the intermediate layer 109 in both the first region 10d and the second region 20d are laterally etched to form a notch, and an inner spacer 148d is formed between the second semiconductor material layer 108 in both the first region 10d and the second region 20d, and an intermediate spacer 149 is formed in the notch between the first region 10d and the second region 20d, as illustrated in Figures 7E-1, 7E-2 and 7E-3. In some embodiments, the intermediate spacer 149 and the inner spacer 148d are formed of the same material. According to some embodiments, after forming the inner spacer 148d and the intermediate spacer 149, a source / drain structure 150d-1 is formed in the bottom region of the source / drain recess 144d, as illustrated in Figures 7E-1, 7E-2, and 7E-3. As illustrated in Figure 7E-3, according to some embodiments, the source / drain structure 150d-1 is attached to both sides of the second semiconductor material layer 108 in the first portion 104d-1 of the fin structure 104d in the first region 10d. Next, according to some embodiments, a contact etch stop layer (CESL) 160d-1 and an interlayer dielectric layer (ILD) 162d-1 are formed above the source / drain structure 150d-1 in the middle portion of the source / drain recess 144d, as illustrated in Figures 7F-1, 7F-2, and 7F-3. In some embodiments, the contact etch stop layer 160d-1 covers the sidewalls of the intermediate spacer 149 and is in direct contact with the sidewalls of the intermediate spacer 149. In some embodiments, the contact etch stop layer 160d-1 and the interlayer dielectric layer 162-1 are laterally sandwiched between the intermediate spacers 149. According to some embodiments, after forming the contact etch stop layer 160d-1 and the interlayer dielectric layer 162d-1, a source / drain structure 150d-2 is formed in the upper part of the source / drain recess 144d, as illustrated in Figures 7F-1, 7F-2, and 7F-3. As illustrated in Figure 7F-3, according to some embodiments, the source / drain structure 150d-2 is attached to both sides of the second semiconductor material layer 108 in the second portion 104d-2 of the fin structure 104d in the second region 20d. In some embodiments, the source / drain structures 150d-1 and 150d-2 are source / drain structures of different types. In some embodiments, the source / drain structure 150d-1 is formed of an n-type epitaxial material, and the source / drain structure 150d-2 is formed of a p-type epitaxial material. Next, according to some embodiments, a contact etch stop layer 160d-2 and an interlayer dielectric layer 162d-2 are formed above the source / drain structure 150d-2 in the upper part of the source / drain groove 144d, and a polishing process is performed until the dummy gate electrode 130 is exposed, as shown in Figures 7G-1, 7G-2 and 7G-3. Next, according to some embodiments, the first semiconductor material layer 106 and the intermediate layer 109 of both the dummy gate structure 130, the first region 10d, and the second region 20d are removed to form a gate trench 166d including a first portion 166d-1 and a second portion 166d-2, as illustrated in Figures 7H-1, 7H-2, and 7H-3. More specifically, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form channel structures (e.g., nanostructures) 108'd-1 and 108'd-2 with the second semiconductor material layer 108 of the first portion 104d-1 and the second portion 104d-2 of the fin structure 104d. Although not clearly illustrated in the figures, the channel structures 108'd-1 and 108'd-2 and the substrate fin structure 104Bd may have rounded corners. As illustrated in Figures 7H-2 and 7H-3, according to some embodiments, channel structure 108'd-2 and channel structure 108'd-1 are vertically overlapped and aligned. In some embodiments, the vertical distance between the bottommost structure of channel structure 108'd-2 and the topmost structure of channel structure 108'd-1 is greater than the vertical distance between adjacent channel structures 108'd-1 and greater than the vertical distance between adjacent channel structures 108'd-2. According to some embodiments, after forming channel structures 108'd-1 and 108'-2, an interface layer 170d (comprising 170d-1 and 170d-2), a gate dielectric layer 172d (comprising 172d-1 and 172d-2), a dipole layer 174d (comprising 174d-1 and 174d-2), and a hard mask layer 176d (comprising 176d-1 and 176d-2) are formed, as illustrated in Figures 7I-1, 7I-2, and 7I-3. More specifically, according to some embodiments, an interface layer 170d-1, a gate dielectric layer 172d-1, a dipole layer 174d-1, and a hard masking layer 176d-1 are formed to surround the channel structure 108'd-1 and cover the substrate fin structure 104Bd, and an interface layer 170d-2, a gate dielectric layer 172d-2, a dipole layer 174d-2, and a hard masking layer 176d-2 are formed to surround the channel structure 108'd-2. In some embodiments, interface layers 170d-1 and 170d-2 are formed from the same material and using the same deposition process. In some embodiments, gate dielectric layers 172d-1 and 172d-2 are formed from the same material and using the same deposition process. In some embodiments, dipole layers 174d-1 and 174d-2 are formed from the same material and using the same deposition process. Subsequently, according to some embodiments, a photoresist layer 178d is formed in the first region 10d to cover the hard mask layer 176d-1, and the hard mask layer 176d-2 and the dipole layer 174d-2 are removed, as illustrated in Figures 7J-1, 7J-2, and 7J-3. According to some embodiments, after removing the dipole layer 174d-2, the photoresist layer 178d and the hard mask layer 176d-1 in the first region 10d are also removed, and a processing step 180 is performed to adjust the gate dielectric layer 172d-1 in the first region 10d, as illustrated in Figures 7K-1, 7K-2, and 7K-3. More specifically, according to some embodiments, metal elements in the dipole layer 174d-1 are driven into the gate dielectric layer 172d-1 to form an adjusted gate dielectric layer 172'd-1. According to some embodiments, after performing processing step 180, the dipole layer 174d-1 is removed, as illustrated in Figures 7L-1, 7L-2, and 7L-3. Next, according to some embodiments, an additional hard mask layer 176d (comprising 276d-1 and 276d-2) is formed over the adjusted gate dielectric layer 172'd-1 and gate dielectric layer 172d-2, as illustrated in Figures 7M-1, 7M-2, and 7M-3. Subsequently, according to some embodiments, an additional photoresist layer 278d is formed in the first region 10d to cover the hard mask layer 276d-1 in the first region 10d, and the hard mask layer 276d-2 exposed by the photoresist layer 278d is removed, as illustrated in Figures 7N-1, 7N-2, and 7N-3. According to some embodiments, after removing the hard mask layer 276d-2, a dipole layer 274d-1 is formed around the channel structure 108'd-1 in the first region 10d, and a dipole layer 274d-2 is formed to surround the channel structure 108'd-1 in the second region 20d, as illustrated in Figures 7O-1, 7O-2, and 7O-3. In some embodiments, the dipole layers 274d-1 and 274d-2 are formed from the same material and using the same deposition process. According to some embodiments, as illustrated in Figure 70-2, the dipole layer 274d-1 is separated from the gate dielectric layer 172'd-1 surrounding the channel structure 108'd-1 by a hard mask layer 276d-1, while the dipole layer 274d-2 is in direct contact with the gate dielectric layer 172d-2 surrounding the channel structure 108'd-2. According to some embodiments, after forming dipole layers 274d-1 and 274d-2, a processing step 180 is performed to adjust the gate dielectric layer 172d-2 in the second region 20d, thereby forming an adjusted gate dielectric layer 172'd-2, as illustrated in Figures 7O-1, 7O-2, and 7O-3. As described above, during processing step 180, dipole layer 274d-1 is separated from the adjusted gate dielectric layer 172'd-1. Therefore, according to some embodiments, during processing step 180, a second metal element in dipole layer 274d-2 is driven into gate dielectric layer 172d-2 to form the adjusted gate dielectric layer 172'd-2. On the other hand, according to some embodiments, a second metal element in dipole layer 274d-1 is not driven into gate dielectric layer 172'd-1. In some embodiments, the second metal element in the dipole layer 274d-2 is driven into the hard mask layer 276d-1 during the processing step 180 illustrated in Figure 7O-2. Next, according to some embodiments, dipole layers 274d-1 and 274d-2 and hard masking layer 276d-1 are removed, as illustrated in Figures 7P-1, 7P-2, and 7P-3. Subsequently, according to some embodiments, the processes shown in Figures 3E to 3H are performed to form gate structure 168d, as illustrated in Figures 7Q-1, 7Q-2, 7Q-3, and 7Q-4. More specifically, according to some embodiments, a gate dielectric layer 182 (comprising 182-1 and 182-2), a capping layer 184 (comprising 184d-1 and 184d-2), a work function metal layer 190d (comprising 190d-1 and 190d-2), and a gate fill layer 192d are formed in gate trenches 166d-1 and 166d-2. In some embodiments, gate dielectric layers 182-1 and 182-2 are formed from the same material and using the same deposition process. In some embodiments, capping layers 184d-1 and 184d-2 are formed from the same material and using the same deposition process. In some embodiments, work function metal layers 190d-1 and 190d-2 are formed from the same material and using the same deposition process. As illustrated in Figure 7Q-2, according to some embodiments, semiconductor structure 100d includes transistor Td-1 in a first region 10d and transistor Td-2 in a second region 20d. Furthermore, according to some embodiments, transistor Td-2 overlaps transistor Td-1 perpendicularly. In some embodiments, transistor Td-1 includes channel structure 108'd-1, source / drain structures 150d-1 attached to both sides of channel structure 108'd-1, and a gate structure 168d surrounding a portion 168d-1 of channel structure 108'd-1. Similarly, according to some embodiments, transistor Td-2 includes channel structure 108'd-2, source / drain structures 150d-2 attached to both sides of channel structure 108'd-2, and a gate structure 168d surrounding a portion 168d-2 of channel structure 108'd-2. In some embodiments, even if the work function metal layers 190d-1 and 190d-2 are formed of the same material with the same thickness, the critical voltage of transistor Td-1 is different from that of transistor Td-2. In some embodiments, the thickness of work function metal layer 190d-1 above the top structure of channel structure 108'd-1 (e.g., the distance between the top surface of gate dielectric layer 182d-1 and the surface of gate fill layer 192d, which contacts work function metal layer 190d-1 above the top structure of channel structure 108'd-1 in direction Z) is substantially equal to the thickness of work function metal layer 190d-2 above the top structure of channel structure 108'd-2 (e.g., the distance between the top surface of gate dielectric layer 182d-2 and the surface of gate fill layer 192d, which contacts work function metal layer 190d-2 above the top structure of channel structure 108'd-1 in direction Z). In some embodiments, the gate filling layer 192d is continuously formed around the channel structures 108'd-1 and 108'd-2, and a portion of the gate filling layer is vertically sandwiched between the top structure of the channel structure 108'd-1 and the bottom structure of the channel structure 108'd-2. In some embodiments, the adjusted gate dielectric layer 172'd-1 is doped with a first metal element but does not contain a second metal element, while the adjusted gate dielectric layer 172'd-2 is doped with a second metal element but does not contain a first metal element. Furthermore, according to some embodiments, the adjusted gate dielectric layer 172'd-2 overlaps the adjusted gate dielectric layer 172'd-1 perpendicularly. In some embodiments, the adjusted gate dielectric layer 172'd-1 covers and directly contacts the lower portion of the intermediate spacer 149, and the adjusted gate dielectric layer 172'd-2 covers and directly contacts the upper portion of the intermediate spacer 149, as illustrated in Figure 7Q-4. In some embodiments, a portion of the intermediate spacer 149 is sandwiched between the contact etch stop layer 160d-1 and the adjusted gate dielectric layer 172'd-1. In some embodiments, a portion of the intermediate spacer 149 is sandwiched between the contact etch stop layer 160d-1 and the adjusted gate dielectric layer 172'd-2. In some embodiments, a portion of the intermediate spacer 149 is sandwiched between the source / drain structure 150d-2 and the adjusted gate dielectric layer 172'd-2. The following components are used to form the mask structure 110d, inner spacer 148d, source / drain structures 150d-1 and 150d-2, contact etch stop layers 160d-1 and 160d-2, interlayer dielectric layers 162d-1 and 162d-2, gate trench 166d, channel structures 108'd-1 and 108'd-2, interface layers 170d-1 and 170d-2, gate dielectric layers 172d-1 and 172d-2, dipole layers 174d-1, 174d-2, 274d-1 and 274d-2, hard mask layers 176d-1, 176d-2, 276d-1 and 276d-2, photoresist layers 178d and 278d, and gate dielectric layers 182-1 and 182-2. The fabrication process and materials of the capping layer 184d, the work function metal layers 190d-1 and 190d-2, and the gate fill layer 192d, which include capping layers 184d-1 and 184d-2, can be similar to or the same as those previously described for forming the mask structure 110, the inner spacer 148, the source / drain structures 150-1 and 150-2, the contact etch stop layer 160, the interlayer dielectric layer 162, the gate trench 166, the channel structures 108'-1 and 108'-2, the interface layer 170, the gate dielectric layer 172, the dipole layer 174, the hard mask layer 176, the photoresist layer 178, the gate dielectric layer 182, the capping layer 184, the work function metal layer 190, and the gate fill layer 192, and will not be described again here. Furthermore, in some other embodiments, similar to the previously described semiconductor structure 100a, the capping layers 184d-1 and 184d-2 of the semiconductor structure 100d can be removed. Additionally, according to some embodiments, the gate dielectric layers 172d-1 and 172d-2 can be processed according to the processes illustrated in Figures 5A to 5G. For example, the gate dielectric layers 172d-1 and / or 172d-2 can be adjusted twice to be approximately the same as or identical to a portion 172b''-1 of the semiconductor structure 100b. Figures 7Q'-2 and 7Q'-3 are schematic cross-sectional views illustrating semiconductor structure 100d' according to some embodiments. According to some embodiments, semiconductor structure 100d' may be approximately the same as the previously described semiconductor structure 100d, but the difference lies in that the capping layer 184d between channel structures 108'd-1 and 108'd-2 is merged. That is, according to some embodiments, the work function metal layer 190d does not extend between channel structures 108'd-1 and 108'd-2. In some embodiments, the thickness of the capping layer 184d in semiconductor structure 100d' is greater than about 3 nm. The processes and materials used to form semiconductor structure 100d may be similar to or the same as those previously described for forming semiconductor structure 100, and will not be repeated here. Figures 8-1, 8-2, and 8-3 are schematic cross-sectional views of the semiconductor structure 100e according to some embodiments. Figure 8-4 is a view of the block BK shown in Figure 8-3 according to some embodiments. 8. Enlarged cross-sectional schematic diagram of semiconductor structure 100e. According to some embodiments, semiconductor structure 100e may be similar to the previously described semiconductor structure 100d, but the difference is that no gate filling layer is formed. Some processes and materials used to form semiconductor structure 100e may be similar to or the same as those used to form semiconductor structure 100d, and will not be described again here. More specifically, the processes illustrated in Figures 7A-1 to 7P-1, 7A-2 to 7P-2, 7A-3 to 7P-3, and 3E to 3F can be performed. According to some embodiments, after forming capping layers 184d-1 and 184d-2, the gate trenches (e.g., gate trenches 166d-1 and 166d-2) are completely filled with work function metal layers 190e to form a semiconductor structure 100e, as illustrated in Figures 8-1, 8-2, and 8-3. As illustrated in Figure 8-2, according to some embodiments, semiconductor structure 100e includes transistor Te-1 and transistor Te-2. Furthermore, according to some embodiments, transistor Te-2 is perpendicularly overlapped with transistor Te-1. In some embodiments, transistor Te-1 includes channel structure 108'd-1, source / drain structures 150d-1 attached to both sides of channel structure 108'd-1, and a gate structure 168e surrounding a portion 168e-1 of channel structure 108'd-1. Similarly, according to some embodiments, transistor Te-2 includes channel structure 108'd-2, source / drain structures 150d-2 attached to both sides of channel structure 108'd-2, and a gate structure 168e surrounding a portion 168e-2 of channel structure 108'd-2. In some embodiments, the critical voltage of transistor Te-1 is different from the critical voltage of transistor Te-2. In some embodiments, a work function metal layer 190e is continuously formed around channel structures 108'd-1 and 108'd-2, and a portion of the work function metal layer 190e is vertically sandwiched between the top structure of channel structure 108'd-1 and the bottom structure of channel structure 108'd-2. The process and materials used to form the power function metal layer 190e can be similar to or the same as those previously described for forming the power function metal layer 190, and will not be repeated here. Furthermore, in some other embodiments, similar to the previously described semiconductor structure 100a, the capping layers 184d-1 and 184d-2 of the semiconductor structure 100d can be removed. Figures 9-1, 9-2, and 9-3 are schematic cross-sectional views of the semiconductor structure 100f according to some embodiments. Figure 9-4 is a top view of the semiconductor structure 100f according to some embodiments. For clarity, Figure 9-4 has been simplified to better understand the inventive concept disclosed herein. More specifically, Figures 9-1, 9-2, and 9-3, according to some embodiments, respectively illustrate intermediate stages of manufacturing the semiconductor structure 100f along section line Y in Figure 9-4. SD9 -Y SD9 '(That is, in the Y direction), section line Y' MG9 -Y MG9 '(that is, in the Y direction), and section line X 9-X A cross-sectional view at 9' (i.e., in the direction X). According to some embodiments, the semiconductor structure 100f may be similar to the previously described semiconductor structure 100, but the difference lies in that the fabrication process is applied to the fin field effect transistor (FinFET) structure. Some of the processes and materials used to form the semiconductor structure 100f may be similar to or the same as those used to form the semiconductor structure 100 previously described, and will not be repeated here. More specifically, fin structures 104f-1 and 104f-2 are formed using a patterned substrate 102. The fin structures can be patterned using any suitable method. For example, one or more optical lithography processes can be used to pattern the fin structures, including dual or multiple patterning processes. Generally, dual or multiple patterning processes combine lithography with self-alignment processes to create, for example, patterns with smaller pitches than those obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as masks to pattern the fin structures. According to some embodiments, after forming fin structures 104f-1 and 104f-2, the processes illustrated in Figures 2A-1 to 2H-1, 2A-2 to 2H-2, and 2A-3 to 2H-3 can be performed. Next, a dummy gate structure (e.g., dummy gate structure 130) is removed, and the processes illustrated in Figures 3A to 3H are performed to form a gate structure 168f spanning fin structures 104f-1 and 104f-2, as illustrated in Figures 9-2 and 9-3. As illustrated in Figure 9-2, according to some embodiments, semiconductor structure 100f includes transistor Tf-1 and transistor Tf-2. In some embodiments, transistor Tf-1 includes fin structure 104f-1, a portion 168f-1 of gate structure 168f formed across fin structure 104f-1, and source / drain structures 150-1 adjacent to both sides of the portion 168f-1 of gate structure 168f. Similarly, according to some embodiments, transistor Tf-2 includes fin structure 104f-2, a portion 168f-2 of gate structure 168f formed across fin structure 104f-2, and source / drain structures 150-2 adjacent to both sides of the portion 168f-2 of gate structure 168f. In some embodiments, the gate structure 168f includes an interface layer 170f, a gate dielectric layer 172f having portions 172f-1 and 172f-2, a gate dielectric layer 182f, a capping layer 184f, a work function metal layer 190f, and a gate fill layer 192f. In some embodiments, portion 172f-1 includes a first metal element, while portion 172f-2 does not include a first metal element, so that the critical voltage of transistor Tf-1 is different from the critical voltage of transistor Tf-2. The processes and materials used to form the interface layer 170f, gate dielectric layer 172f, gate dielectric layer 182f, capping layer 184f, work function metal layer 190f, and gate fill layer 192f can be similar to or the same as those previously described for forming the interface layer 170, gate dielectric layer 172, gate dielectric layer 182, capping layer 184, work function metal layer 190, and gate fill layer 192, and will not be repeated here. Furthermore, in some other embodiments, similar to the previously described semiconductor structure 100a, the capping layer 184f of the semiconductor structure 100f can be removed. Additionally, according to some embodiments, the gate dielectric layer 172f can be processed according to the processes illustrated in Figures 5A to 5G. Generally, multiple work function metal layers can be formed in a gate structure to allow the resulting transistor to have different threshold voltages. For example, more than one work function metal layer can be formed in a gate structure. However, as the size of semiconductor devices continues to shrink, the space used to form the gate structure may be primarily occupied by the work function metal layers. In other words, there may not be enough space to form a gate fill layer. Furthermore, during the patterning process of forming different work function metal layers in different regions, multiple etching processes may be required, and completely removing the metal layer without damaging the components exposed during the etching process can be challenging. On the other hand, different types of work function metal layers can be formed in a single metal gate structure. For example, a p-type transistor can contain both an n-type and a p-type work function metal layer. Therefore, the difference in critical voltage between p-type and n-type transistors is reduced, and reliability is also decreased. In addition, metal elements in one type of work function metal layer can diffuse into other types of work function metal layers. That is, at the interface between two types of work function metal layers, metal in the p-type work function metal layer may diffuse into the n-type work function metal layer, and vice versa, and therefore the critical voltage may not meet the design requirements, and the performance of the formed transistor may be compromised. Therefore, in the above embodiments, at least a portion of the gate dielectric layer (e.g., gate dielectric layer 172) is doped with a metal element from the dipole layer (e.g., dipole layer 174) to allow the transistor's critical voltage to be adjusted. That is, although only a single type of work function metal layer (e.g., work function metal layer 190) is used, according to some embodiments, the transistor can still have different critical voltages. Furthermore, sufficient space can still be provided in the gate trench for forming the gate fill layer (e.g., gate fill layer 192). Therefore, the reliability and performance of the formed transistor can be improved. In some embodiments, the gate dielectric layer of the n-type transistor (e.g., transistor T-1) is treated with a metallic element, and thus both the n-type transistor and the adjacent p-type transistor (e.g., transistor T-2) contain a p-type work function metal layer but not an n-type work function metal layer. Since no n-type work function metal layer is formed, the critical voltage of the p-type transistor is not affected by the normally formed n-type work function metal layer, and therefore can have a lower critical voltage. Furthermore, the absence of an n-type work function metal layer (e.g., containing an Al layer) on top of the gate dielectric layer can result in improved reliability. Furthermore, there will be no interface between the two types of work function metal layers. Meanwhile, the doping of metal elements in the gate dielectric layer (such as an oxide layer) may be relatively slow, and the diffusion of metal elements in the oxide layer may be relatively slow. Therefore, there will be no boundary effects caused by metal element diffusion between the different types of work function metal layers. Thus, performance can be improved. Furthermore, according to some embodiments, a capping layer (e.g., capping layer 184) is formed over the gate dielectric layer, and an annealing process (e.g., post-deposition annealing process 186) is performed to densify the gate dielectric layer (e.g., gate dielectric layers 172 and 182) to improve the quality of the gate dielectric layer. Additionally, the capping layer can be retained within the gate structure, so the gate dielectric layer is not damaged by the removal of the capping layer. It should be understood that the elements depicted in semiconductor structures 100, 100a, 100b, 100c, 100d, 100e, and 100f can be combined and / or interchanged. For example, a semiconductor structure may include at least one of the modified portions 172''b-1, 172'b-2, 172'b-3, and 172b-4. Furthermore, it is worth noting that the same elements in Figures 1A to 9-3 can be represented by the same reference numerals, and may contain the same or similar materials and can be formed by the same or similar processes; therefore, these redundant details have been omitted for brevity. Moreover, although structures related to the method are described in Figures 1A to 9-3, it should be understood that the structures revealed in Figures 1A to 9-3 are not limited to this method, but can exist independently of this method. Similarly, the methods shown in Figures 1A to 9-3 are not limited to the revealed structures, but can exist independently of these structures. Furthermore, according to some embodiments, the channel structure (e.g., nanostructure) described above may include nanowires, nanosheets, or other suitable nanostructures. Furthermore, although the disclosed methods are illustrated and described below as a series of actions or events, it should be understood that the order of the illustrated actions or events may be changed in some other embodiments. For example, some actions may occur in a different order and / or simultaneously with other actions or events other than those illustrated and / or described above. Additionally, not all illustrated actions may be required to implement one or more of the above aspects or embodiments. Furthermore, one or more of the above actions may be performed in one or more separate actions and / or stages. Furthermore, the terms "approximately," "generally," "roughly," and "about" used above indicate minor variations that can occur in different technologies and have a range of deviations understood by one of ordinary skill in the art. For example, when used in conjunction with an event or situation, these terms can refer to instances where the event or situation occurred precisely or instances that were very close to the occurrence of the event or situation. An embodiment for forming a semiconductor structure can be provided. The semiconductor structure may include a gate dielectric layer formed in a first region and a second region, and a gate dielectric layer tuned with a first metal element in the first region but not in the second region. A capping layer can then be formed over the tuned gate dielectric layer to densify it, thereby improving the quality of the gate dielectric layer. Next, a work function metal layer can be formed in both the first and second regions. Since the gate dielectric layer in the first region is doped with the first metal element, the first transistor and the second transistor can have different threshold voltages. In some embodiments, a method for manufacturing a semiconductor structure is provided. The method includes forming a first channel structure in a first region and forming a second channel structure in a second region; forming a first type source / drain structure attached to both sides of the first channel structure and forming a second type source / drain structure attached to both sides of the second channel structure; forming a first gate dielectric layer having a first portion covering the first channel structure and a second portion covering the second channel structure; driving a first metal element into the first portion of the first gate dielectric layer; after driving the first metal element into the first portion of the first gate dielectric layer, forming a capping layer over both the first and second portions of the first gate dielectric layer; performing an annealing process on the first gate dielectric layer below the capping layer; and forming a work function metal layer that extends continuously from the first region to the second region and covers the first and second channel structures. In some embodiments, the method further includes forming a second gate dielectric layer over both the first and second portions of the first gate dielectric layer after driving a first metal element into a first portion of the first gate dielectric layer. In some embodiments, the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer. In some embodiments, the second gate dielectric layer and the first gate dielectric layer are formed of the same material. In some embodiments, the first channel structure and the second channel structure are suspended above the substrate and separated from each other. In some embodiments, the method further includes driving a second metal element into a second portion of the first gate dielectric layer in a second region, wherein the first metal element is different from the second metal element. In some embodiments, the first region and the second region overlap vertically. In some embodiments, the work function metal layer is formed of a p-type work function metal. In some embodiments, a method for manufacturing a semiconductor structure is provided. The method includes forming a first type of source / drain structure and a second type of source / drain structure above a substrate; forming a plurality of first channel structures vertically suspended above the substrate and sandwiched between the first type of source / drain structures; forming a plurality of second channel structures vertically suspended above the substrate and sandwiched between the second type of source / drain structures; forming a first gate dielectric layer having a first portion surrounding the first channel structure and a second portion surrounding the second channel structure; forming a first dipole layer, the first dipole layer being in solid contact with the first portion of the first gate dielectric layer and separated from the second portion of the first gate dielectric layer; forming a second gate dielectric layer above the first gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are formed of the same material; forming a capping layer surrounding the first channel structure and the second channel structure above the second gate dielectric layer; and annealing the first gate dielectric layer and the second gate dielectric layer after forming the capping layer. In some embodiments, the method further includes forming a direct contact between the top surface of the work function metal layer and the capping layer; and forming a direct contact between the top surface of the gate fill layer and the top surface of the work function metal layer, wherein the first work function metal layer is formed vertically above the topmost structure of the first channel structure in a first portion having a first thickness, and the first work function metal layer is formed vertically above the topmost structure of the second channel structure in a second portion having a second thickness, the first thickness and the second thickness being substantially equal. In some embodiments, the method further includes driving a first metal element of the first dipole layer into a first portion of the first gate dielectric layer; and removing the first dipole layer before forming the second gate dielectric layer. In some embodiments, the method further includes forming a physical contact between the second dipole layer and a second portion of the first gate dielectric layer; and driving a second metal element of the second dipole layer into a second portion of the first gate dielectric layer. In some embodiments, the method further includes forming a dielectric wall structure laterally intersecting between the first channel structure and the second channel structure, wherein a first portion of the first gate dielectric layer is in direct contact with a first sidewall of the dielectric wall structure, and a second portion of the first gate dielectric layer is in direct contact with a second sidewall of the dielectric wall structure relative to the first sidewall. In some embodiments, the method further includes forming a first semiconductor stack over a substrate and forming a second semiconductor stack over the first semiconductor stack, wherein each of the first semiconductor stack and the second semiconductor stack includes alternatingly stacked plurality of first semiconductor material layers and plurality of second semiconductor material layers; patterning the first semiconductor stack and the second semiconductor stack to form a fin structure; removing the first semiconductor material layer of the first semiconductor stack to form a first channel structure having a second semiconductor material layer of the first semiconductor stack; and removing the first semiconductor material layer of the second semiconductor stack to form a second channel structure having a second semiconductor material layer of the second semiconductor stack, wherein a first portion of the first gate dielectric layer and a second portion of the first gate dielectric layer vertically overlap. In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first type of source / drain structure formed in a first region above a substrate, and a second type of source / drain structure formed in a second region above the substrate; a plurality of first channel structures spaced apart from each other along a first direction and interspersed between the first type of source / drain structures along a second direction different from the first direction; a plurality of second channel structures spaced apart from each other along the first direction and interspersed between the second type of source / drain structures along the second direction; a gate dielectric layer having a first portion in the first region surrounding the first channel structure and a second portion in the second region surrounding the second channel structure, wherein the first portion of the gate dielectric layer is doped with a first metal element, and the concentration of the first metal element in the lower part of the first portion of the gate dielectric layer is greater than the concentration of the first metal element in the upper part of the first portion of the gate dielectric layer; and a work function metal layer formed above both the first portion and the second portion of the gate dielectric layer. In some embodiments, the semiconductor structure further includes a gate filling layer extending continuously from the first region to the second region and oriented longitudinally along a third direction different from the first and second directions, wherein the distance between the gate filling layer and the top surface of the topmost structure of the first channel structure in the first direction is substantially equal to the distance between the gate filling layer and the top surface of the topmost structure of the second channel structure in the first direction. In some embodiments, a second portion of the gate dielectric layer is doped with a second metal element, the second portion of the gate dielectric layer does not contain the first metal element, and the first portion of the gate dielectric layer does not contain the second metal element. In some embodiments, the semiconductor structure further includes a dielectric wall structure sandwiched between the first channel structure and the second channel structure and oriented longitudinally along the second direction, wherein both the first and second portions of the gate dielectric layer partially cover the top surface of the dielectric wall structure. In some embodiments, a portion of the work function metal layer is vertically sandwiched between the topmost structure of the first channel structure and the bottommost structure of the second channel structure. In some embodiments, the semiconductor structure further includes a gate filling layer surrounding the first channel structure and the second channel structure, wherein a portion of the gate filling layer is vertically sandwiched between the topmost structure of the first channel structure and the bottommost structure of the second channel structure. The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. 10: First region 10b: Region 10c: First region 10d: First region 20: Second region 20b: Region 20c: Second region 20d: Second region 30b: Region 40b: Region 100: Semiconductor structure 100': Semiconductor structure 100a: Semiconductor structure 100b: Semiconductor structure 100c: Semiconductor structure 100c': Semiconductor structure 100d: Semiconductor structure 100d': Semiconductor structure 100e: Semiconductor structure 100f: Semiconductor structure 102: Substrate 104-1: Fin structure 104-2: Fin structure 104B: Substrate fin structure 104Bd: Substrate fin structure 104c-1, 104c-2: Fin structure 104d: Fin structure 104d-1: First part 104d-2: Second part 104f-1, 104f-2: Fin structure; 106: First semiconductor material layer; 108: Second semiconductor material layer; 108'-1: Channel structure; 108'-2: Channel structure; 108'b-1, 108'b-2, 108'b-3, 108'b-4: Channel structure; 108'c-1, 108'c-2: Channel structure; 108'd-1, 108'd-2: Channel structure; 109: Intermediate layer; 110: Mask structure; 110d: Mask structure; 116: Isolation structure; 130: Virtual gate structure; 132: Virtual gate dielectric layer; 134: Virtual gate electrode layer; 136: Hard mask layer; 138: Spacer layer; 140: Gate spacer; 142: Fin spacer; 144: Source / drain groove; 144d: Source / drain groove; 146: Notch; 148: Inner spacer; 148d: Inner spacer; 149: Intermediate spacer; 150-1: Source / drain structure; 150-2: Source / drain structure; 150c-1, 150c-2: Source / drain structure; 150d-1, 150d-2: Source / drain structure; 160: Contact etch stop layer; 160d-1, 160d-2: Contact etch stop layer; 162: Interlayer dielectric layer; 162d-1, 162d-2: Interlayer dielectric layer; 166: Gate trench; 166d: Gate trench; 166d-1: First part; 166d-2: Second part; 166c-1, 166c-2: Gate trench; 168: Gate structure; 168-1: First part; 168-2: Second part; 168b: Gate structure; 168c: Gate structure; 168c-1, 168c-2: Partial; 168d: Gate structure; 168e: Gate structure; 168e-1, 168e-2: Partial; 168f: Gate structure; 168f-1, 168f-2: Partial; 170: Interface layer; 170c: Interface layer; 170d: Interface layer; 170d-1,170d-2: Interface layer; 170f: Interface layer; 172: Gate dielectric layer; 172-1: First part; 172-2: Second part; 172'-1: Adjusted first part; 172b: Gate dielectric layer; 172b-1, 172b-2, 172b-3, 172b-4: Parts; 172'b-1, 172'b-2, 172'b-3: Adjusted parts; 172''b-1: Adjusted part; 172c: Gate dielectric layer; 172c-1, 172c-2: Parts; 172'c-1: Adjusted part; 172d: Gate dielectric layer; 172d-1, 172d-2: Gate dielectric layer; 172'd-1, 172'd-2: Adjusted gate dielectric layer; 172f: Gate dielectric layer; 172f-1, 172f-2: Partial; 174: Dipole layer; 174b: Dipole layer; 174d: Dipole layer; 174d-1, 174d-2: Dipole layer; 176: Hard masking layer; 176d: Hard masking layer; 176d-1, 176d-2: Hard masking layer; 178: Photoresist layer; 178b: Photoresist layer; 178d: Photoresist layer; 180: Processing; 182: Gate dielectric layer; 182-1, 182-2: Gate dielectric layer; 182c: Gate dielectric layer; 182f: Gate dielectric layer; 184: Cap layer; 184c: Cap layer; 184d-1, 184d-2: Cap layer; 184f: Cap layer; 186: Post-deposition annealing process; 190: Work function metal layer; 190c: Work function metal layer; 190d: Work function metal layer; 190d-1, 190d-2: Work function metal layer; 190e: Work function metal layer; 190f: Work function metal layer; 192: Gate fill layer; 192c: Gate fill layer; 192d: Gate fill layer; 192f: Gate fill layer; 274b: Dipole layer; 274d-1, 274d-2: Dipole layer; 276b: Hard mask layer; 276d-1, 276d-2: Hard mask layer; 278b: Photoresist layer; 278d: Photoresist layer; 620: Dielectric layer; 626: Dielectric wall structure BK. 2I: Box BK 2J :box BK 6J :box BK 7Q :box BK 8: Box T-1: Transistor T-2: Transistor Ta-1: Transistor Ta-2: Transistor Tb-1, Tb-2, Tb-3, Tb-4: Transistor Tc-1, Tc-2: Transistor Td-1, Td-2: Transistor Te-1, Te-2: Transistor Tf-1, Tf-2: Transistor X: Direction X-X': Section X 6-X 6': Section X 7-X 7': Section X 9-X 9': Section line Y: Direction Y MG -Y MG ':Section Y MG6 -Y MG6 ':Section Y MG7 -Y MG7 ':Section Y MG9 -Y MG9 ' : Section Y SD -Y SD ':Section Y SD6 -Y SD6 ':Section Y SD7 -Y SD7 ':Section Y SD9 -Y SD9 ' :Section line Z:Direction The embodiments of the present invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention. Figures 1A, 1B, and 1C are perspective schematic diagrams illustrating intermediate stages of manufacturing a semiconductor structure according to some embodiments. Figures 2A-1 to 2J-1, 2A-2 to 2J-2, and 2A-3 to 2J-3 are drawings illustrating intermediate stages of manufacturing a semiconductor structure along section line Y in Figure 1C, according to some embodiments. SD -Y SD '(That is, in the Y direction), section line Y' MG -Y MG A cross-sectional view of the section line '(i.e., in direction Y) and section line X-X' (i.e., in direction X). Figures 2J-4 illustrate, according to some embodiments, the block BK shown in Figure 2J-2. 2J Figures 2J-5 are enlarged cross-sectional views of the semiconductor structure, illustrating some embodiments from above. Figures 2J'-2 and 2J'-3 illustrate the semiconductor structure along section line Y in Figure 1C, according to some embodiments. MG -Y MG 'And a cross-sectional view along section X-X'. Figures 3A to 3H illustrate, according to some embodiments, the gate structure for manufacturing a semiconductor structure (i.e., the box BK shown in Figures 2I-2). 2I Figure 3H' is an enlarged cross-sectional view of an intermediate stage in the fabrication of a semiconductor structure according to some embodiments. Figures 4A and 4B are enlarged cross-sectional views of intermediate stages in the fabrication of a semiconductor structure according to some embodiments. Figures 5A to 5G are enlarged cross-sectional views of intermediate stages in the fabrication of a semiconductor structure according to some embodiments. Figures 6A-1 to 6J-1, 6A-2 to 6J-2, and 6A-3 to 6J-3 are cross-sectional views of intermediate stages in the fabrication of a semiconductor structure according to some embodiments. Figure 6J-4 shows the block BK shown in Figure 6I-2 according to some embodiments. 6JThe figures are enlarged cross-sectional views of the semiconductor structure. Figure 6J-5 is a top view of the semiconductor structure according to some embodiments. Figures 6J'-2 and 6J'-3 are cross-sectional views of the semiconductor structure according to some embodiments. Figures 7A-1 to 7Q-1, 7A-2 to 7Q-2, and 7A-3 to 7Q-3 are cross-sectional views of intermediate stages in the fabrication of the semiconductor structure according to some embodiments. Figure 7Q-4 shows the block BK shown in Figure 7Q-3 according to some embodiments. 7Q Figure 7Q-5 is a top view schematic diagram of the semiconductor structure according to some embodiments. Figures 7Q'-2 and 7Q'-3 are cross-sectional schematic diagrams of the semiconductor structure according to some embodiments. Figures 8-1, 8-2, and 8-3 are cross-sectional schematic diagrams of the semiconductor structure according to some embodiments. Figure 8-4 illustrates the block BK shown in Figure 8-3 according to some embodiments. Figure 8 is an enlarged cross-sectional view of the semiconductor structure. Figures 9-1, 9-2, and 9-3 are cross-sectional views of the semiconductor structure according to some embodiments. Figure 9-4 is a top view of the semiconductor structure according to some embodiments. 10: Zone 1 20: Second District 100: Semiconductor Structure 104-1: Fin Structure 104-2: Fin Structure 104B: Base fin structure 108'-1: Channel Structure 108'-2: Channel Structure 116: Isolation Structure 168: Gate Structure 168-1: Part One 168-2: Part Two 170: Interface Layer 172-2: Part Two 172'-1: The first part after adjustment 182: Gate dielectric layer 184: Cap layer 190: Work function metal layer 192: Gate filler layer BK 2J : box

Claims

1. A method for manufacturing a semiconductor structure, comprising: A first channel structure is formed in a first area and a second channel structure is formed in a second area; A first type source / drain structure is formed and attached to both sides of the first channel structure, and a second type source / drain structure is formed and attached to both sides of the second channel structure; a first gate dielectric layer is formed, the first gate dielectric layer having a first portion covering the first channel structure and a second portion covering the second channel structure; a first metal element is driven into the first portion of the first gate dielectric layer; after driving the first metal element into the first portion of the first gate dielectric layer, a second gate dielectric layer is formed above both the first portion and the second portion of the first gate dielectric layer, wherein the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer; after driving the first metal element into the first portion of the first gate dielectric layer and forming the second gate dielectric layer, a capping layer is formed above both the first portion and the second portion of the first gate dielectric layer; an annealing process is performed on the first gate dielectric layer below the capping layer; A work function metal layer is formed, which extends continuously from the first region to the second region and covers the first channel structure and the second channel structure. The second portion of the first gate dielectric layer is driven in with a second metal element. The second portion of the first gate dielectric layer does not contain the first metal element, and the first portion of the first gate dielectric layer does not contain the second metal element. The first metal element includes Sr, Er, Zn, or Sc.

2. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the second gate dielectric layer and the first gate dielectric layer are formed of the same material.

3. A method for manufacturing a semiconductor structure as claimed in claim 1 or claim 2, wherein the first channel structure and the second channel structure are suspended above a substrate and separated from each other.

4. A method for manufacturing a semiconductor structure as claimed in claim 1 or claim 2, wherein the first metal element is different from the second metal element.

5. A method for manufacturing a semiconductor structure, comprising: A first type of source / drain structure and a second type of source / drain structure are formed on a substrate; Multiple first channel structures are formed, vertically suspended above the substrate and sandwiched between the first type of source / drain structures; multiple second channel structures are formed, vertically suspended above the substrate and sandwiched between the second type of source / drain structures; a first gate dielectric layer is formed, the first gate dielectric layer having a first portion wrapping around the first channel structures and a second portion wrapping around the second channel structures; a first dipole layer is formed, the first dipole layer being in physical contact with the first portion of the first gate dielectric layer and separated from the second portion of the first gate dielectric layer; a second gate dielectric layer is formed above the first gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are formed of the same material, wherein the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer; a capping layer is formed to surround the first channel structures and the second channel structures above the second gate dielectric layer; After the capping layer is formed, the first gate dielectric layer and the second gate dielectric layer are annealed, wherein the first portion of the first gate dielectric layer is driven in with a first metal element, the second portion of the first gate dielectric layer is driven in with a second metal element, the second portion of the first gate dielectric layer does not contain the first metal element, and the first portion of the first gate dielectric layer does not contain the second metal element, wherein the first metal element includes Sr, Er, Zn, or Sc; and a work function metal layer is formed on a top surface of the capping layer.

6. The method for manufacturing the semiconductor structure as described in claim 5 further includes: A gate fill layer is formed in direct contact with a top surface of the work function metal layer, wherein a first portion of the work function metal layer is formed vertically above a top structure of the first channel structures and has a first thickness, and a second portion of the work function metal layer is formed vertically above a top structure of the second channel structures and has a second thickness, wherein the first thickness and the second thickness are substantially equal.

7. The method for manufacturing the semiconductor structure as described in claim 5 further includes: The first metal element of the first dipole layer is driven into the first portion of the first gate dielectric layer; Before forming the second gate dielectric layer, the first dipole layer is removed; a second dipole layer is formed to make physical contact with the second portion of the first gate dielectric layer; and the second metal element of the second dipole layer is driven into the second portion of the first gate dielectric layer.

8. The method for manufacturing the semiconductor structure as described in claim 5 further includes: A dielectric wall structure is formed and transversely interspersed between the first channel structures and the second channel structures, wherein the first portion of the first gate dielectric layer is in direct contact with a first sidewall of the dielectric wall structure, and the second portion of the first gate dielectric layer is in direct contact with a second sidewall of the dielectric wall structure relative to the first sidewall.

9. The method for manufacturing the semiconductor structure as described in claim 5 further includes: A first semiconductor stack is formed over the substrate and a second semiconductor stack is formed over the first semiconductor stack, wherein each of the first semiconductor stack and the second semiconductor stack includes a plurality of alternately stacked first semiconductor material layers and a plurality of second semiconductor material layers; the first semiconductor stack and the second semiconductor stack are patterned to form a fin structure; the first semiconductor material layers of the first semiconductor stack are removed to form first channel structures having the second semiconductor material layers of the first semiconductor stack; And remove the first semiconductor material layers of the second semiconductor stack to form the second channel structures having the second semiconductor material layers of the second semiconductor stack, wherein the first portion of the first gate dielectric layer overlaps perpendicularly with the second portion of the first gate dielectric layer.

10. A semiconductor structure comprising: A first type source / drain structure is formed in a first region above a substrate, and a second type source / drain structure is formed in a second region above the substrate; a plurality of first channel structures are separated from each other along a first direction and interspersed between the first type source / drain structures along a second direction different from the first direction; a plurality of second channel structures are separated from each other along the first direction and interspersed between the second type source / drain structures along the second direction; a first gate dielectric layer has a first portion located in the first region surrounding the first channel structures and a second portion located in the second region surrounding the second channel structures, wherein the first portion of the first gate dielectric layer is doped with a first metal element, and the concentration of the first metal element in the lower part of the first portion of the first gate dielectric layer is greater than the concentration of the first metal element in the upper part of the first portion of the first gate dielectric layer, wherein the first metal element includes Sr, Er, Zn, or Sc; A second gate dielectric layer is formed above both the first portion and the second portion of the first gate dielectric layer, wherein the thickness of the second gate dielectric layer is less than the thickness of the first gate dielectric layer; And a work function metal layer is formed on both the first portion and the second portion of the first gate dielectric layer, wherein the second portion of the first gate dielectric layer is doped with a second metal element, the second portion of the first gate dielectric layer does not contain the first metal element, and the first portion of the first gate dielectric layer does not contain the second metal element.

11. The semiconductor structure of claim 10 further includes: A gate filling layer extends continuously from the first region to the second region and is longitudinally oriented along a third direction different from the first and second directions, wherein the distance between the gate filling layer and the top surface of the topmost structure of the first channel structures in the first direction is substantially equal to the distance between the gate filling layer and the top surface of the topmost structure of the second channel structures in the first direction.

12. The semiconductor structure of claim 10 further includes: A dielectric wall structure is sandwiched between the first channel structures and the second channel structures and is oriented longitudinally along the second direction, wherein both the first portion and the second portion of the first gate dielectric layer partially cover the top surface of the dielectric wall structure.

13. The semiconductor structure of claim 10, wherein a portion of the work function metal layer is vertically sandwiched between a top structure of the first channel structure and a bottom structure of the second channel structure.

14. The semiconductor structure of claim 10 further includes: A gate filler layer surrounds the first channel structures and the second channel structures, wherein a portion of the gate filler layer is vertically sandwiched between a top structure of the first channel structures and a bottom structure of the second channel structures.

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